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W9968CF jpeg usb dual mode camera chip publication release date: may 1999 - 1 - revision a2 W9968CF jpeg usb dual mode camera chip
W9968CF - 2 - revision history revision issue date comments a1 april, 1998 formal release. a2 may, 1999 supports usb spec. rev. 1.1. changed bcdusb and bcddevice values from 0x0100 to 0x0110. added cr39_4 for jpeg clock enable. copyright by winbond electronics corp., all rights reserved. the information in this document has been carefully checked and is believed to be correct as of the date of publication. winbond electronics corp. reserves the right to make changes in the product or specification, or both, presented in this publication at any time without notice. winbond assumes no responsibility or liability arising from the specification listed herein. winbond makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patents, trademark, copyright, or rights of third parties. no license is granted by implication or other under any patent or patent rights of winbond electronics corp. all other trademarks and registered trademarks are the property of their respective holders.
W9968CF publication release date: may 1999 - 3 - revision a2 table of contents 1 general description ................................ ................................ ................................ .............. 7 2 features ................................ ................................ ................................ ................................ ....... 8 3 pin configuration ................................ ................................ ................................ .................. 10 4 pin description ................................ ................................ ................................ ........................ 11 4.1 p in d efinition ................................ ................................ ................................ ................................ .. 11 4.2 p in l ist ................................ ................................ ................................ ................................ ............. 16 4.3 p ower - on r eset i nitialization ................................ ................................ ................................ ..... 17 5 system diagram ................................ ................................ ................................ ....................... 18 6 block diagram ................................ ................................ ................................ ......................... 19 7 functional description ................................ ................................ ................................ ...... 20 7.1 v ideo i nput i nterface ................................ ................................ ................................ .................... 20 7.1.1 camera control serial bus ................................ ................................ ................................ ...... 20 7.1.2 input video data format ................................ ................................ ................................ .......... 20 7.1.3 cropping ................................ ................................ ................................ ................................ .... 21 7.1.4 scaling ................................ ................................ ................................ ................................ ....... 21 7.1.5 filtering ................................ ................................ ................................ ................................ ...... 22 7.1.6 captured video data format ................................ ................................ ................................ ... 22 7.2 dram c ontrol and i nterface ................................ ................................ ................................ ..... 23 7.2.1 dram access arbitration ................................ ................................ ................................ ........ 23 7.2.2 dram interface ................................ ................................ ................................ ........................ 23 7.3 jpeg c ompression ................................ ................................ ................................ ........................ 25 7.3.1 level shift and forward dct ................................ ................................ ................................ .. 25 7.3.2 quantization ................................ ................................ ................................ .............................. 25 7.3.3 huffman encoding ................................ ................................ ................................ .................... 26 7.3.4 jpeg encoding order ................................ ................................ ................................ .............. 26 7.4 usb i nterface and d evice c ontrol ................................ ................................ ............................ 27 7.4.1 endpoints ................................ ................................ ................................ ................................ ..... 27 7.4.1.1 default endpoint (endpoint 0) ................................ ................................ ................................ ............ 27 7.4.1.2 video data-in endpoint (endpoint 1) ................................ ................................ ................................ . 27 7.4.2 usb device requests ................................ ................................ ................................ .............. 27 7.4.2.1 standard device requests ................................ ................................ ................................ ................ 27 7.4.2.2 video camera class-specific requests ................................ ................................ ........................... 29 7.4.2.3 vendor-specific requests ................................ ................................ ................................ ................. 29 7.4.3 descriptors ................................ ................................ ................................ ................................ 30 7.4.3.1 device descriptors ................................ ................................ ................................ ............................. 30 7.4.3.2 configuration descriptors ................................ ................................ ................................ .................. 31 7.4.3.3 string descriptors ................................ ................................ ................................ ............................... 33 7.5 v ideo /s till i mage d ata t ransfer ................................ ................................ ................................ . 34
W9968CF - 4 - 7.5.1 output video data format ................................ ................................ ................................ ....... 34 7.5.2 video frame synchronization ................................ ................................ ................................ . 34 7.5.3 bandwidth management ................................ ................................ ................................ .......... 34 7.6 p ower m anagement ................................ ................................ ................................ ....................... 35 7.6.1 W9968CF reset ................................ ................................ ................................ ....................... 35 7.6.2 before configured ................................ ................................ ................................ .................... 35 7.6.3 after configured ................................ ................................ ................................ ....................... 35 7.6.4 suspend ................................ ................................ ................................ ................................ .... 35 7.6.5 resume ................................ ................................ ................................ ................................ ..... 36 7.7 s erial eeprom i nterface ................................ ................................ ................................ ........... 37 7.7.1 eeprom data structure ................................ ................................ ................................ ............ 37 7.7.2 eeprom operations ................................ ................................ ................................ ............... 37 7.8 m icrocontroller i nterface ................................ ................................ ................................ ........ 39 7.8.1 base address setup ................................ ................................ ................................ ................... 39 7.8.2 W9968CF register access ................................ ................................ ................................ ........ 39 7.8.3 microcontroller interrupt ................................ ................................ ................................ .............. 39 7.8.4 dram access ................................ ................................ ................................ ............................. 39 7.8.5 ihv-specific information ................................ ................................ ................................ ............. 40 8 control and status registers ................................ ................................ ...................... 41 8.1 g eneral c ontrol r egisters ................................ ................................ ................................ ........ 43 8.2 v ideo i nput c ontrol r egisters ................................ ................................ ................................ ... 52 8.3 jpeg e ncoder c ontrol r egisters ................................ ................................ ............................ 63 9 electrical characteristics ................................ ................................ ............................ 70 9.1 a bsolute m aximum r atings ................................ ................................ ................................ .......... 70 9.2 dc c haracteristics ................................ ................................ ................................ ...................... 70 9.2.1 usb transceiver dc characteristics ................................ ................................ ...................... 70 9.2.2 digital dc characteristics ................................ ................................ ................................ ........ 70 9.3 ac c haracteristics ................................ ................................ ................................ ...................... 71 9.3.1 usb transceiver ac characteristics ................................ ................................ ...................... 71 9.3.2 reset timing ac characteristics ................................ ................................ .......................... 72 9.3.3 clock ac characteristics ................................ ................................ ................................ ......... 73 9.3.4 input video ac characteristics ................................ ................................ ............................... 73 9.3.5 dram interface ac characteristics ................................ ................................ ........................ 74 9.3.6 eeprom interface ac characteristics ................................ ................................ .................. 75 9.3.7 microcontroller interface ac characteristics ................................ ................................ .......... 76 10 package spec. ................................ ................................ ................................ ........................ 77 11 ordering information ................................ ................................ ................................ ....... 78
W9968CF publication release date: may 1999 - 5 - revision a2 list of figures f igure 3.1 W9968CF p in c onfiguration ................................ ................................ ................................ .. 10 f igure 5.1 W9968CF-b ased usb d igital v ideo c amera s ystem d iagram ................................ ........... 18 f igure 6.1 W9968CF b lock d iagram ................................ ................................ ................................ ....... 19 f igure 7.1 i nput v ideo d ata f ormats ................................ ................................ ................................ ..... 21 f igure 7.2 jpeg e ncoding o rder ................................ ................................ ................................ ............. 26 f igure 7.3 d evice c onfiguration ................................ ................................ ................................ ............ 27 f igure 7.4 eeprom t iming d iagram ................................ ................................ ................................ ....... 38 f igure 9.1 d ata s ignal r ise and f all t ime ................................ ................................ ............................ 71 f igure 9.2 d ifferential d ata j itter ................................ ................................ ................................ ........ 71 f igure 9.3 d ifferential to eop t ransition s kew and eop w idth ................................ ....................... 71 f igure 9.4 r eceiver j itter t olerance ................................ ................................ ................................ ..... 72 f igure 9.5 reset t iming ................................ ................................ ................................ .......................... 72 f igure 9.6 c lock w aveform ................................ ................................ ................................ .................... 73 f igure 9.7 i nput v ideo t iming ................................ ................................ ................................ .................. 73 f igure 9.8 dram i nterface i nput t iming ................................ ................................ ............................... 74 f igure 9.9 dram i nterface o utput t iming ................................ ................................ ............................ 74 f igure 9.10 eeprom i nterface t iming ................................ ................................ ................................ ... 75 f igure 9.11 m icrocontroller i nterface t iming ................................ ................................ .................... 76 f igure 10.1 128l qfp (14 x 20 x 2.75 mm footprint 3.2 mm ) d imensions ................................ ....................... 77
W9968CF - 6 - list of tables t able 4.1 W9968CF p in l ist ................................ ................................ ................................ .................... 16 t able 4.2 p ower - on r eset c onfiguration d efinitions ................................ ................................ ...... 17 t able 7.1 c aptured v ideo d ata f ormat ................................ ................................ ............................... 22 t able 7.2 sdram and edo dram i nterface s ignals ................................ ................................ ........ 23 t able 7.3 s tandard d evice r equests ................................ ................................ ................................ ... 28 t able 7.4 W9968CF v endor -s pecific r equests ................................ ................................ .................. 29 t able 7.5 W9968CF d evice d escriptor ................................ ................................ ................................ 30 t able 7.6 W9968CF c onfiguration d escriptor ................................ ................................ .................. 31 t able 7.7 W9968CF v ideo i nterface d escriptor ................................ ................................ ............... 31 t able 7.8 W9968CF d ata -i n e ndpoint d escriptor ................................ ................................ ............. 32 t able 7.9 W9968CF v ideo i nterface a lternate s etting 1-16 i nterface d escriptor ................... 32 t able 7.10 W9968CF a lternate s etting 1-16 d ata -i n e ndpoint d escriptor ................................ . 32 t able 7.11 t he m aximum d ata p ayload s ize in b ytes for a lternate s ettings ............................... 33 t able 7.12 W9968CF d efault s tream d escriptors ................................ ................................ ........... 33 t able 7.13 o utput v ideo d ata f ormat ................................ ................................ ................................ . 34 t able 7.14 eeprom d ata s tructure ................................ ................................ ................................ ..... 37 t able 8.1 W9968CF c ontrol r egister m ap ................................ ................................ ........................... 41 t able 9.1 a bsolute m aximum r atings ................................ ................................ ................................ ...... 70 t able 9.2 usb t ransceiver dc c haracteristics ................................ ................................ .................. 70 t able 9.3 d igital dc c haracteristics ................................ ................................ ................................ ..... 70 t able 9.4 usb t ransceiver ac c haracteristics ................................ ................................ ................... 72 t able 9.5 reset t iming ................................ ................................ ................................ ............................. 73 t able 9.6 c lock ac c haracteristics ................................ ................................ ................................ ...... 73 t able 9.7 i nput v ideo ac c haracteristics ................................ ................................ ............................. 74 t able 9.8 dram i nterface ac c haracteristics ................................ ................................ .................... 74 t able 9.9 eeprom i nterface ac c haracteristics ................................ ................................ ............... 75 t able 9.10 m icrocontroller i nterface ac c haracteristics ................................ .............................. 76
W9968CF publication release date: may 1999 - 7 - revision a2 1 general description the W9968CF is a digital video processing chip offered by winbond to facilitate adapterless connection between digital video camera and personal computer for video and still image capturing and editing, video e-mail, and video conferencing applications. low-cost, high-performance, and high-quality digital video camera can be realized by using winbond s W9968CF, which includes universal serial bus (usb) technology and the international standard jpeg compression. the digital video camera is becoming the next great input device for the pc. usb is now a common pc standard for connecting peripheral products, which features low cost, hot-attachable plug and play, adequate 12 mb/s full speed bandwidth, and simultaneous attachment of multiple devices. the W9968CF has built-in full speed usb controller which benefits from using the isochronous data transfer mode of the usb bus, and which is compliant with the full power management requirements of the usb specification, including startup, operating, and suspend modes. to prevent saturation of the usb bus, the W9968CF uses no more than 8 mb/s of available bandwidth to ensure the continued operation of other low bandwidth devices such as usb mice and keyboards. although usb provides a low-cost solution for low to medium speed peripherals, its 12 mb/s bandwidth is not enough for high-quality and high-performance digital video camera. high-quality and low-cost compression is necessary to boost frame rate for a high-performance digital video camera. the W9968CF has built-in the baseline jpeg compression, which corresponds to the iso/iec international standard 10918-1, with ycbcr4:2:2 or ycbcr4:2:0 components in non-interleaved scan. the baseline jpeg implementation in the W9968CF includes discrete cosine transform (dct), quantization, zig- zag scan, and huffman encoder. with jpeg compression, the W9968CF can easily achieve good quality 30 frames per second (fps) in cif resolution (352 288) and 10~15 fps in vga resolution (640 480) by consuming no more than 8 mb/s usb bandwidth. the W9968CF can accept ntsc, pal, or vga video in 8- or 16-bit ycbcr4:2:2 format, square or rectangular pixels, and converts to sub-qcif (128 96), qcif (176 144), cif (128 96), sif (352 240), 320 240, or vga (640 480) format. built-in cropping window control and arbitrary scaling in both the horizontal and vertical directions can serve as the digital pan and zoom over a user-specified region for camera control. in addition to usb interface, the W9968CF also supports an 8-bit microcontroller interface for portable pc camera applications. up to 24 still images in 640 480 vga format can be captured, jpeg compressed, and stored into an external 2 mbytes flash memory when in the portable mode. an on-chip dram controller is used to interface to sdram or edo dram through a 16-bit data bus. an external serial e 2 prom is also supported if ihv-specific vendor id and product id are needed. the ihv-specific information can be also provided by an external microcontroller if present to save the cost of an e 2 prom. the W9968CF is a 3.3 v device with ttl-compatible 3.3 v or 5.0 v i/o, and is packaged in a 128l qfp.
W9968CF - 8 - 2 features q usb interface fully compliant with usb specification revision 1.1 supports for full speed devices with maximum 12 mb/s usb bandwidth uses no more than 8 mb/s usb bandwidth to prevent saturation of the usb bus provides multiple alternate settings for various isochronous bandwidth consumptions does not use isochronous bandwidth for default alternate setting 0 complies with usb power management requirements usb control and isochronous transfers on-chip usb full speed transceivers bus-powered high power devices q video compression fully compliant with iso/iec 10918-1 international jpeg standard on-chip dct, quantization, zig-zag scan, and huffman encoder contains two ac and two dc huffman code tables, and two programmable quantization tables supports baseline sequential mode in ycbcr4:2:2 or ycbcr4:2:0 non-interleaved scan encodes in sub-qcif (128x96), qcif (176x144), cif (352x288), sif (352x240), 320x240, or vga (640x480) picture format encodes sub-qcif/qcif/cif/sif/320x240 format at 30 frames per second (fps), vga format at 10~15 fps q video pre-processing direct connect to digital camera through an 8- or 16-bit data bus glueless interface to ntsc/pal tv decoder input video format compliant with ycbcr 4:2:2 ccir 601 standard built-in cropping, arbitrary scaling, and filtering functions for digital pan and zoom camera control
W9968CF publication release date: may 1999 - 9 - revision a2 q video output video output can be either compressed bit stream or original video compressed bit stream is fully compliant with iso baseline jpeg standard in ycbcr4:2:2 or ycbcr4:2:0 non-interleaved scan original video output can be in ycbcr4:2:2 or ycbcr4:2:0 packed format q dram interface supports sdram or 1-cycle edo dram supports sdram self refresh supports 16-bit dram interface in 0.5, 1, 2 or 4 mbytes configuration q serial eeprom interface supports optional 1k (128 8) serial eeprom for ihv-specific vendor id and product id q supports hardware and software snap shot q supports 8-bit microcontroller interface for portable pc camera applications q built-in pll (phase-locked loops) clock synthesizer q operating frequency is 48 mhz with video input frequency of 13.5 mhz (typical) q 3.3 v device with ttl-compatible 3.3 v or 5.0 v i/o q 128l qfp package
W9968CF - 10 - 3 pin configuration the W9968CF is packaged in a 128l qfp. the pin configuration is shown in figure 3.1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 45 46 47 48 49 50 39 40 (top view) W9968CF dp dm usbvdd vssi vssi vssp 25 26 27 28 29 30 41 42 43 44 vddi vddi vssp vddp md6 md8 md7 vddp cas1#/dqm1 cas0#/dqm0 oe#/cke we# scas# sras# ras0#/cs0# smclk vssp ba ma10 ma9 ma8 ma7 ma6 ma1 ma5 ma2 ma4 ma3 md13 md14 md15 uv0 uv1 uv2 uv3 uv4 uv5 uv6 uv7 vddp usbvss vssp xin xout vddp ma0 vssp ras1#/cs1# vddp vssp md2 sde#/sds md1 md0 sclk vssp rstin# rstout suspnd pwrdwn vddp sda/eeprom pwrdwn# scl md9 sdata intxtr 31 32 33 34 65 51 52 53 103 35 36 37 38 54 55 56 57 58 59 60 61 62 63 64 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 vssi vssp md4 md10 md5 md11 md3 vs hs y0 y1 y2 y3 y4 y5 y6 y7 vddp rd# wr# ale ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 int# clk24m test# rcv vpo vssp viclk md12 vdd5v vddi a8/gpio0 vmo toe# vp vm avdd avss a9/gpio1 a10/gpio2 a11/gpio3 a12/gpio4 a13/gpio5 a14/gpio6 a15/gpio7 extmcu cs#/snap# figure 3.1 W9968CF pin configuration
W9968CF publication release date: may 1999 - 11 - revision a2 4 pin description the following signal types are used in these descriptions. i input pin iu input pin with internal pull-up resistor b bi-directional input/output pin o output pin aio analog input/output pin p power supply pin g ground pin # active low 4.1 pin definition usb and external transceiver interface (8 pins) pin name pin number type description dm 50 aio data minus line of differential usb upstream port. dp 51 aio data plus line of differential usb upstream port. note: provide an external 1.5 k w pull-up resistor at dp so the device indicates to the host that it is a full-speed device. vm 53 iu single-ended receiver input of the data minus line. vp 54 iu single-ended receiver input of the data plus line. rcv 55 iu differential receiver input. toe# 57 o output enable for external transceiver. vmo 58 o data minus output to the differential driver. vpo 59 o data plus output to the differential driver. dram interface (37 pins) pin name pin number type description md[15:0] 92-95, 97-106, 109-110 b data bus. ma[10:0] 65-68, 70, 72- 77 o address bus. note: for sdram, ma[10:0] are sampled during the active
W9968CF - 12 - command (row address ma[10:0]) and read/write command (column address ma[7:0], with ma10 defining auto precharge) to select one location out of the 521k available in the respective bank. ma10 is sampled during a precharge command to determine if all banks are to be precharged (ma10 high). ba 78 o edo dram: not used. sdram: bank address input. ba defines to which internal bank the active, read, write or precharge command is being applied. ba is also used to program the 12th bit of the mode register. ras[1:0]# cs[1:0]# 80, 81 o edo dram: row address strobes. sdram: chip select. cs# enables the command decoder for the sdram. cas[1:0]# dqm[1:0] 89, 90 o edo dram: column address strobes. sdram: input/output mask. dqm[1:0] are input mask signals for write accesses and output enable signals for read accesses. dqm0 corresponds to md[7:0]; dqm1 corresponds to md[15:8]. oe# cke 84 o edo dram: output enable. sdram: clock enable. cke activates the smclk signal. the sdram enters precharge power-down to deactivate the input and output buffers, excluding cke, for maximum power saving when cke is low coincident with a nop. we# 88 o edo dram: write enable. sdram: command input. sras#, scas#, and we# (along with cs#) define the command being entered. sras# 82 o edo dram: not used. sdram: command input. sras#, scas#, and we# (along with cs#) define the command being entered. scas# 85 o edo dram: not used. sdram: command input. sras#, scas#, and we# (along with cs#) define the command being entered. smclk 86 o edo dram: not used. sdram: clock. input video interface (22 pins) pin name pin number type description y[7:0] 117-120, 122- 125 i digital y (luminance) inputs in 16-bit mode, or digital yuv inputs in 8-bit mode.
W9968CF publication release date: may 1999 - 13 - revision a2 uv[7:0] 2-9 i digital uv (chrominance) inputs in 16-bit mode, or not used in 8-bit mode. hs 116 i horizontal sync input. programmable polarity. vs 115 i vertical sync input. programmable polarity. viclk 127 i input video clock. sde#/sds 112 o serial data enable/serial data strobe. sclk 113 b serial interface clock. sdata 114 b serial interface data. micro controller interface (21 pins) pin name pin number type description ad[7:0] 21-24, 26-29 b multiplexed address/data bus. a[15:8] gpio[7:0] 31-38 i b extmcu = 1: high-order address bus. extmcu = 0: general purpose i/os. ale 18 i address latch enable. ale is used to enable the address latch that separates the address from the data on ad bus. rd# 15 iu data read strobe. wr# 16 iu data write strobe. cs# sanp# 17 iu extmcu = 1: chip select. extmcu = 0: snap shot input. int# 14 o interrupt output, level-triggered. serial e 2 prom interface (2 pins) pin name pin number type description scl 62 o serial clock. sda/eepro m 63 b serial data/serial e 2 prom detection. during a reset operation, the W9968CF samples this signal to see if an external e 2 prom exists. a 10k ohm pull-up resistor should be used if an external e 2 prom is used; otherwise it should be tied to vss. miscellaneous (11 pins) pin name pin number type description
W9968CF - 14 - xin 11 i reference frequency input from a crystal or a clock source. it should be 48 mhz if pll is off (pllsel = 0) or 12 mhz if pll is on (pllsel = 1) for full-speed device. xout 12 o oscillator output to a crystal. this pin is left unconnected if an external clock source is employed. clk24m 20 o 24 mhz clock output. extmcu 39 i external micro controller (mcu). 0: no; 1: yes. test# 40 iu test input. intxtr 44 i internal usb transceiver select. 0: off; 1: on. rstin# 45 iu system reset input. pwrdwn# 46 o low-active power down control. this pin is active upon reset, suspended, or when the camera power-on control register (cr00_4) is 0. once active, it remains active until the cr00_4 is set to 1. pwrdwn 47 o high-active power down control. this pin is active upon reset, suspended, or when the camera power-on control register (cr00_4) is 0. once active, it remains active until the cr00_4 is set to 1. suspnd 48 o usb suspend mode. this pin is active when the W9968CF is in the suspend mode. it is cleared to 0 when the W9968CF is resumed, or reset by rstin# pin or a usb reset command. rstout 56 o reset output. this pin is active when rstin# pin is active, or a usb reset command is received. power and ground (27 pins) pin name pin number type description vdd5v 128 p 5v buffer power supply. provide 5v power to the i/o buffers for 5v input tolerance. +4.4 v ~ +5.25 v. vddp 1, 13, 30, 61, 71, 91, 107 p buffer power supply. provide isolated power to the i/o buffers for improved noise immunity. +3.3 v 0.3 v. vssp 10, 25, 64, 69, 79, 87, 96, 111, 126 g buffer ground. usbvdd 52 p usb transceiver power supply. +3.3 v 0.3 v. usbvss 49 g usb transceiver ground. avdd 42 p pll power supply. +3.3 v 0.3 v. avss 43 g pll ground. vddi 19, 60, 108 p core logic power supply. +3.3 v 0.3 v.
W9968CF publication release date: may 1999 - 15 - revision a2 vssi 41, 83, 121 g core logic ground.
W9968CF - 16 - 4.2 pin list table 4.1 W9968CF pin list pin name pin name pin name pin name 1 vddp 33 a10/gpio2 65 ma3 97 md5 2 uv0 34 a11/gpio3 66 ma4 98 md10 3 uv1 35 a12/gpio4 67 ma2 99 md4 4 uv2 36 a13/gpio5 68 ma5 100 md11 5 uv3 37 a14/gpio6 69 vssp 101 md3 6 uv4 38 a15/gpio7 70 ma1 102 md12 7 uv5 39 extmcu 71 vddp 103 md2 8 uv6 40 test# 72 ma6 104 md13 9 uv7 41 vssi 73 ma0 105 md1 10 vssp 42 avdd 74 ma7 106 md14 11 xin 43 avss 75 ma10 107 vddp 12 xout 44 intxtr 76 ma8 108 vddi 13 vddp 45 rstin# 77 ma9 109 md0 14 int# 46 pwrdwn# 78 ba 110 md15 15 rd# 47 pwrdwn 79 vssp 111 vssp 16 wr# 48 suspnd 80 ras0#/cs0# 112 sde#/sds 17 cs#/snap# 49 usbvss 81 ras1#/cs1# 113 sclk 18 ale 50 dm 82 sras# 114 sdata 19 vddi 51 dp 83 vssi 115 vs 20 clk24m 52 usbvdd 84 oe#/cke 116 hs 21 ad0 53 vm 85 scas# 117 y0 22 ad1 54 vp 86 smclk 118 y1 23 ad2 55 rcv 87 vssp 119 y2 24 ad3 56 rstout 88 we# 120 y3 25 vssp 57 toe# 89 cas0#/dqm0 121 vssi 26 ad4 58 vmo 90 cas1#/dqm1 122 y4 27 ad5 59 vpo 91 vddp 123 y5 28 ad6 60 vddi 92 md7 124 y6 29 ad7 61 vddp 93 md8 125 y7 30 vddp 62 scl 94 md6 126 vssp 31 a8/gpio0 63 sda/eeprom 95 md9 127 viclk 32 a9/gpio1 64 vssp 96 vssp 128 vdd5v note 1. all output and bi-directional pins, except xout pin, are tri-stated during reset.
W9968CF publication release date: may 1999 - 17 - revision a2 4.3 power-on reset initialization during power-on reset, states of the memory data lines md[7:0] are latched into the W9968CF s internal configuration registers as device configuration information. since each pin of md[7:0] is internally pulled up on its i/o buffer, no external pull-up resistor is required. for pull-down, a 4.7k ohm resistor is recommended. table 4.2 describes the power-on reset configuration definitions. table 4.2 power-on reset configuration definitions md bit value definition conf reg md7 0 1 normal operation force suspend mode if suspend mode is enabled cr00_15 md6 0 1 suspend mode is disabled suspend mode is enabled cr00_14 md5 0 1 isochronous handshake phase is enabled isochronous handshake phase is disabled cr00_13 md4 0 1 internal rcv comes from sie internal rcv comes from usb transceiver cr00_12 md3 0 1 pll disable pll enable cr00_11 md2 0 1 low power, bus-powered devices high power, bus-powered devices cr00_10 md1 0 1 edo dram sdram cr00_9 md0 0 1 256kx dram 1mx dram cr00_8
W9968CF - 18 - 5 system diagram W9968CF jpeg or original video usb video memory 1mx16 sdram ycbcr 4:2:2 sensor dsp ccd/cmos sensor serial e 2 prom 128x8 8-bit uc optional optional figure 5.1 W9968CF-based usb digital video camera system diagram
W9968CF publication release date: may 1999 - 19 - revision a2 6 block diagram video in ycbcr 4:2:2 vpre dram controller video memory d+ serial e 2 prom W9968CF dct quantization zig-zag vle device controller usb sie usb xcvrs d- 8-bit uc pll xin xout figure 6.1 W9968CF block diagram
W9968CF - 20 - 7 functional description 7.1 video input interface video input data is cropped, down-scaled, and filtered in the video pre-processing (vpre) block, then is stored into the dram as captured video for the following jpeg compression and transfer. 7.1.1 camera control serial bus a dedicated programmable serial bus is supported for camera control. the serial bus includes sclk, sdata, and sde#/sds signals. during serial bus read, these signals are controlled by the host via bits 4-0 of the serial bus control register (cr01_4-0). there are two serial bus write modes which are controlled by bit 5 of the serial bus control register (cr01_5).: normal serial bus write mode (cr01_5 = 0) and fast serial bus write mode (cr01_5 = 1). normal serial bus write mode (cr01_5 = 0): sdata and sclk signals are output from cr01_1-0 directly. fast serial bus write mode (cr01_5 = 1): sdata and sclk signals are output from cr06-cr09 in about 400 khz bit frequency. 7.1.2 input video data format the W9968CF accepts video data in yuv 4:2:2 format through a 16-bit (y[7:0] and uv[7:0]) or 8-bit (y[7:0]) data bus. many yuv ordering formats are supported which are selected by bits 9-8 of the video capture control register (cr26) as shown in figure 7.1. video data can be latched by the W9968CF by using either rising-edge or falling-edge of the viclk clock signal. in the 8-bit modes the viclk frequency is twice the pixel rate, only y[7:0] pins are used for video data input and uv[7:0] pins are not used.
W9968CF publication release date: may 1999 - 21 - revision a2 viclk 16-bit uv mode (cr26_10-8=00x) y0 y1 y2 y3 y4 y5 y6 u0 v0 u2 v2 u4 v4 u6 y[7:0] uv[7:0] 16-bit vu mode (cr26_10-8=01x) y0 y1 y2 y3 y4 y5 y6 v0 u0 v2 u2 v4 u4 v6 y[7:0] uv[7:0] 8-bit yuyv mode (cr26_10-8=100) y0 u0 y1 v0 y2 u2 y3 y[7:0] 8-bit uyvy mode (cr26_10-8=101) u0 y0 v0 y1 u2 y2 v2 y[7:0] 8-bit yvyu mode (cr26_10-8=110) y0 v0 y1 u0 y2 v2 y3 y[7:0] 8-bit vyuy mode (cr26_10-8=111) v0 y0 u0 y1 v2 y2 u2 y[7:0] figure 7.1 input video data formats 7.1.3 cropping a cropping rectangle (or window) is supported for cropping or clipping the incoming video data. only interested video data located inside the cropping rectangle is processed and sent to the host system. the cropping rectangle can be moved within the input rectangle by programming the cropping window start x and cropping window start y registers. cropping is performed based on the vs signal for vertical cropping and hs signal for horizontal cropping. both vs and hs are programmable polarity for maximum flexibility. 7.1.4 scaling the cropped video can be down-scaled horizontally and/or vertically. the horizontal down-scaling and vertical down-scaling are performed independently by using two ddas (digital differential accumulator) with horizontal down - scaling fa ctor captured v ideo width cropping w indow end x cropping w indow star t x and vertical d own - scaling fa ctor captured v ideo heigh t cropping w indow end y cropping w indow star t y . = - ? ? ? ? = - ? ? ? ? the W9968CF does not perform up-scaling during video pre-processing. to produce cif format from 240-line video for the jpeg compression, a special vertical up-scaling can be performed by the jpeg
W9968CF - 22 - encoder. for the original video transfer, the cif format from 240-line video can be produced by the software driver. 7.1.5 filtering a 3-tap or 5-tap fir filter is used to reduce noise and aliasing artifacts produced by the ccd or cmos sensor, and the scaling process. 7.1.6 captured video data format after cropped, down-scaled, and filtered in the video pre-processing (vpre) block, the input video is stored into the dram as captured video. four different formats are supported for the captured video: yuv4:2:2 packed, yuv4:2:0 packed, yuv4:2:2 planar, and yuv4:2:0 planar modes, which are selected by bits 1-0 of the video capture control register (cr26) as described in table 7.1. yuv4:2:2 and yuv4:2:0 packed modes are used for original video transfer, while yuv4:2:2 and yuv4:2:0 planar modes are used for jpeg compression video transfer. table 7.1 captured video data format cr26_1-0 captured video data format 00 yuv4:2:2 packed mode for original video transfer 01 yuv4:2:0 packed mode for original video transfer 10 yuv4:2:2 planar mode for jpeg compression video transfer 11 yuv4:2:0 planar mode for jpeg compression video transfer
W9968CF publication release date: may 1999 - 23 - revision a2 7.2 dram control and interface the W9968CF supports 256k 16 and 1m 16 sdram or edo dram in a 0.5 ~ 4 mbytes configuration with 16-bit data bus. a single 1m 16, -15 or above, sdram is recommended for better cost/performance. 7.2.1 dram access arbitration the dram arbiter helps to maximize performance by orchestrating memory access requests from internal engines. two priority levels are defined for these requests: first priority: dram refresh request and sdram mode register write request second priority: capture fifo write request, dct read request, vle read request, vle fifo write request, usb fifo read request, and usb control read/write request programmable fifo status are provided by the capture fifo, vle fifo, and usb fifo such that the dram controller arbitrates according to these fifo status to prevent any video data loss and to achieve the best performance. 7.2.2 dram interface the dram controller provides many programmable controls for the dram operations which include: dram type: supports sdram and edo dram dram address: programmable 9-bit (256k edo dram), 10-bit (1m edo dram or 256k sdram), and 12-bit (1m sdram) address dram timing: adjustable trp, trcd, tras, and tcas timings dram refresh: 1 ~ 8 refresh cycles per scan line sdram read latency: 1 ~ 3 clocks sdram burst type: sequential or interleaved sdram burst length: 1, 2, 4, 8, or full page sdram self refresh table 7.2 shows the interface signals for sdram and edo dram. table 7.2 sdram and edo dram interface signals pin name 256k edo dram 1m edo dram 256k sdram 1m sdram md[15:0] md[15:0] md[15:0] md[15:0] md[15:0] ma[10:0] ma[8:0] ma[9:0] ma[8:0] ma[10:0] ba ba ba ras[1:0]#/cs[1:0]# ras[1:0]# ras[1:0]# cs[1:0]# cs[1:0]#
W9968CF - 24 - cas[1:0]#/dqm[1:0] cas[1:0]# cas[1:0]# dqm[1:0] dqm[1:0] oe#/cke oe# oe# cke cke we# we# we# we# we# sras# sras# sras# scas# scas# scas# smclk smclk smclk
W9968CF publication release date: may 1999 - 25 - revision a2 7.3 jpeg compression the W9968CF supports jpeg baseline sequential process for video data compression. for the sequential dct-based mode, 8 8 sample blocks are typically input block by block from left to right, and block-row by block-row from top to bottom. each block is transformed by the forward dct (fdct) into a set of 64 values referred to as dct coefficients. each of the 64 coefficients is then quantized using one of 64 corresponding values from a quantization table. after quantization, the dc coefficients and the 63 ac coefficients are converted into a one-dimensional zig-zag sequence, then are passed to a huffman encoder for entropy encoding procedure which compresses the data further. 7.3.1 level shift and forward dct prior to computing the fdct the input data are level shifted to a signed two s complement representation. for 8-bit precision the level shift is achieved by subtracting 128. the following equation specifies the mathematical definition of the fdct. ( ) ( ) s c c s x u y v vu u v yx y x = + + = = ? ? 1 4 2 1 16 2 1 16 0 7 0 7 cos cos p p where c c c c u v u v , , = = 1 2 1 for u, v = 0 otherwise 7.3.2 quantization after the fdct is computed for a block, each of the 64 resulting dct coefficients is quantized by a uniform quantizer. the uniform quantizer is defined by the following equation. rounding is to the nearest integer: sq round s q vu vu vu = ? ? ? ? the quantizer step size for each coefficient s vu is the value of the corresponding element q vu from the quantization table. the W9968CF supports two programmable quantization tables, luminance quantization table and chrominance quantization table, which are made by two internal 64 8 srams, and which should be loaded by the host via the usb bus before start of the jpeg compression. the quantized dct coefficient values are signed, two s complement integers with 11-bit precision for 8-bit input precision.
W9968CF - 26 - 7.3.3 huffman encoding after quantization, the quantized coefficients are converted to the zig-zag sequence for huffman encoding. the dc coefficients are coded differently from the ac coefficients. the value that should be encoded is the difference (diff) between the quantized dc coefficient of the current block (dc i which is also designated as sq 00 ) and that of the previous block of the same component (pred): diff dc pred i = - at the beginning of the scan and at the beginning of each restart interval, the prediction for the dc coefficient prediction is initialized to 0. for the ac coefficient encoding, since many ac coefficients are zero, runs of zeros are identified and coded efficiently. in addition, if the remaining coefficients in the zig-zag sequence order are all zero, this is coded explicitly as an end-of-block (eob). the W9968CF huffman encoder employs two dc and two ac huffman tables within one scan for luminance and chrominance components. 7.3.4 jpeg encoding order the W9968CF jpeg encoder supports two non-interleaved encoding orders shown in figure 7.2: yuv4:2:2 non-interleaved encoding order yuv4:2:0 non-interleaved encoding order y 1 , y 2 , ...y n scan 1 yuv4:2:2 non-interleaved encoding order y 1 y 2 y n u 1 u 2 u n/2 v 1 v 2 v n/2 y 1 y 2 y n u 1 u 2 u n/4 v 1 v 2 v n/4 u 1 , u 2 , ...u n/2 scan 2 v 1 , v 2 , ...v n/2 scan 3 u 3 v 3 y 3 y 4 y 3 y 4 y 1 , y 2 , ...y n scan 1 yuv4:2:0 non-interleaved encoding order u 1 , u 2 , ...u n/4 scan 2 v 1 , v 2 , ...v n/4 scan 3 figure 7.2 jpeg encoding order
W9968CF publication release date: may 1999 - 27 - revision a2 7.4 usb interface and device control the W9968CF contains two endpoints: default and video data-in endpoints. figure 7.3 shows the device configuration for the W9968CF-based usb digital video camera. host device default pipe data-in pipe w9967cf-based figure 7.3 device configuration 7.4.1 endpoints 7.4.1.1 default endpoint (endpoint 0) the default endpoint uses control transfers as defined in the usb specification. the default endpoint provides access to the W9968CF-based device s configuration, status, and control information by sending standard, class, and vendor-specific requests to the device, an interface, or an endpoint. 7.4.1.2 video data-in endpoint (endpoint 1) the video data-in endpoint is used to receive video image data from the device intended for delivery to a video capture application on the host. the video data-in endpoint uses isochronous transfers. the direction is always in. the maximum packet size can be varied for different alternate settings for limited usb bandwidth. 7.4.2 usb device requests the W9968CF responds to requests from the host on the default pipe. the W9968CF supports standard, class, and vendor-specific usb device requests. 7.4.2.1 standard device requests the W9968CF supports the standard usb device requests as shown in table 7.3 and described below. it responds to standard device requests whether it has been assigned a non-default address or is currently configured. if any unrecognized or unsupported standard request is received, it returns stall.
W9968CF - 28 - table 7.3 standard device requests bmrequesttype brequest wvalue windex wlength data 00000010b clear_feature (1) feature selector (0) endpoint zero none 10000000b get_configuration (8) zero zero one configurati- on value 10000000b get_descriptor (6) descriptor type and descriptor index zero or language id descriptor length descriptor 10000001b get_interface (10) zero interface (0) one alternate setting 10000000b 10000001b 10000010b get_status (0) zero zero interface endpoint two device, interface, or endpoint status 00000000b set_address (5) device address zero zero none 00000000b set_configuration (9) configura -tion value zero zero none 00000000b set_descriptor (7) (not supported) 00000010b set_feature (3) feature selector (0) endpoint zero none 00000001b set_interface (11) alternate setting interface (0) zero none 00000010b synch_frame (12) (not supported) clear feature the W9968CF supports the following clear feature request: when directed to an endpoint recipient for endpoint_stall the W9968CF returns stall if any unrecognized or unsupported clear feature request is received. get configuration the W9968CF returns zero if it is unconfigured or the bconfiguration value defined in the configuration descriptor is configured. get descriptor the W9968CF supports get descriptor requests for standard descriptors (device, configuration, and string). the W9968CF returns stall if a get descriptor request is received for a class-specific descriptor or a vendor-specific descriptor, is unrecognized or unsupported.
W9968CF publication release date: may 1999 - 29 - revision a2 get interface the W9968CF supports a get interface request for interface 0 by returning the selected alternate setting. the default alternate setting is zero. the W9968CF returns stall for a get interface request for any other interface or any get interface request before the device is configured. get status the W9968CF supports a get status directed at the device, interface 0, or any defined endpoint (default or video data-in). the W9968CF returns stall if a get status request is received for interface 0 or any defined endpoint before the device is configured, or if a get status request is received for any unrecognized or unsupported recipient. set address the W9968CF supports a set address request to change the device address from the default address (zero) to a unique address. set configuration the W9968CF supports set configuration requests to set the device configuration to zero (unconfigured) or the bconfiguration value defined in the configuration descriptor. the W9968CF returns stall if a set configuration request is received with any other value. set descriptor the W9968CF does not support update for any defined descriptor (device, configuration, interface, endpoint, or string). it returns stall for any set descriptor request. clear feature the W9968CF supports the following set feature request: when directed to an endpoint recipient for endpoint_stall the W9968CF returns stall if any unrecognized or unsupported set feature request is received. set interface when configured, the W9968CF supports a set interface request to interface 0 for defined alternate settings. this request allows the host to select the desired alternate setting. the W9968CF returns stall for any other set interface request. synch frame the W9968CF returns stall for any synch frame request. 7.4.2.2 video camera class-specific requests currently, there is no class-specific request is defined for the video camera devices. the W9968CF returns stall for any class-specific request. 7.4.2.3 vendor-specific requests the W9968CF supports two vendor-specific requests for the control registers in/out transfers on the default pipe (endpoint 0): get W9968CF control and set W9968CF control. the vendor-specific requests defined for the W9968CF are shown in table 7.4. the W9968CF returns stall if an unrecognized or unsupported vendor-specific request is received. table 7.4 W9968CF vendor-specific requests bmrequesttype brequest wvalue windex wlength data 11000000b get_W9968CF_control (1) zero index 1 length 2 data 01000000b set_W9968CF_control (0) data0 3 index 1 length 2 data note 1. index specifies the starting index of the control registers to be accessed. an index counter,
W9968CF - 30 - loaded with the index value, will be incremented by one after every two bytes of data transferred. note 2. length specifies number of data bytes transferred during the second phase of the control transfer. it should be an even number value. if this field is zero, there is no data transfer phase. note 3. data0 is a word-sized data to be programmed into the control register indexed by the index field, no matter the length field is zero or not. the internal index counter will be incremented by one once data0 is transferred. get W9968CF control the W9968CF supports a get W9968CF control request for W9968CF control registers in transfer. length field should be an even number value. the W9968CF returns stall for any unrecognized or unsupported get W9968CF control request. set W9968CF control the W9968CF supports a set W9968CF control request for W9968CF control registers out transfer. length field should be an even number value. if the length field is zero, only data0 is transferred with no data transfer phase. the W9968CF returns stall for any unrecognized or unsupported set W9968CF control request. 7.4.3 descriptors the W9968CF supports the standard usb descriptors as described below. the W9968CF returns stall if a request is received for any unrecognized or unsupported standard descriptor. 7.4.3.1 device descriptors the W9968CF returns a device descriptor with the values shown in table 7.5. table 7.5 W9968CF device descriptor offset field size value description 0 blength 1 0x12 size of this descriptor in bytes 1 bdescriptortype 1 0x01 device descriptor type 2 bcdusb 2 0x0110 usb specification release number in bcd 4 bdeviceclass 1 0x00 class code 5 bdevicesubclass 1 0x00 subclass code 6 bdeviceprotocol 1 0x00 protocol code 7 bmaxpacketsize0 1 0x08 maximum packet size for endpoint zero 8 idvendor 2 0x1046 vendor id 10 idproduct 2 0x9967 product id 12 bcddevice 2 0x0110 device release number in bcd 14 imanufacturer 1 0x01 index of string descriptor describing manufacturer 15 iproduct 1 0x02 index of string descriptor describing product 16 iserialnumber 1 0x00 index of string descriptor describing the device s serial number
W9968CF publication release date: may 1999 - 31 - revision a2 17 bnumconfigurations 1 0x01 number of possible configurations note 1. vendor id and product id will be replaced with bytes 0-3 of an external serial e 2 prom or uc if present. 7.4.3.2 configuration descriptors the W9968CF returns a configuration descriptor and other configuration related descriptors as described below. when the host requests the configuration descriptor, all related interface and endpoint descriptors are returned. table 7.6 W9968CF configuration descriptor offset field size value description 0 blength 1 0x09 size of this descriptor in bytes 1 bdescriptortype 1 0x02 configuration descriptor type 2 wtotallength 2 0x0119 total length of data returned for this configuration. includes the combined length of all descriptors returned for this configuration. 4 bnumberinterfaces 1 0x01 number of interfaces supported by this configuration 5 bconfigurationvalue 1 0x01 value used as an argument to set configuration to select this configuration 6 iconfiguration 1 0x00 no configuration string 7 bmattributes 1 0x80 configuration characteristics 8 maxpower 1 0xfa or 0x32 (note 1) maximum power consumption from the bus when the device is fully operational. expressed in 2 ma units. note 1. value of this field is 0xfa (500 ma) for high power devices (cr00_10 = 1), or 0x32 (100 ma) for low power devices (cr00_10 = 0). table 7.7 W9968CF video interface descriptor offset field size value description 0 blength 1 0x09 size of this descriptor in bytes 1 bdescriptortype 1 0x04 interface descriptor type 2 binterfacenumber 1 0x00 number of interface 3 balternatesetting 1 0x00 default alternate setting zero 4 bnumendpoints 1 0x01 number of endpoints used by this interface 5 binterfaceclass 1 0x00 image interface class code 6 binterfacesubclass 1 0x00 digital video camera subclass code 7 binterfaceprotocol 1 0x00 protocol code. no class specific protocol.
W9968CF - 32 - 8 iinterface 1 0x00 no interface string table 7.8 W9968CF data-in endpoint descriptor offset field size value description 0 blength 1 0x07 size of this descriptor in bytes 1 bdescriptortype 1 0x05 endpoint descriptor type 2 bendpointaddress 1 0x81 endpoint number. direction is set to in. 3 bmattributes 1 0x01 isochronous transfer type 4 wmaxpacketsize 2 0x00 default zero bandwidth 6 binterval 1 0x01 interval in milliseconds for polling endpoint for data transfers the W9968CF video interface includes 16 alternate settings that allow the data-in endpoint bandwidth to be varied decreasingly from 8 mbps down to 0.5 mbps in descending 0.5 mbps steps such that the device driver can request subsequently smaller bandwidth quantities. a separate interface descriptor and its associated endpoint are included for each setting. when the host requests the configuration descriptor, all 16 pairs of interface and endpoint descriptors for alternate setting should follow the interface and endpoint descriptors for the default alternate setting zero. the W9968CF supports the get interface and set interface requests to report or select a specific alternate setting for the video interface. table 7.9 W9968CF video interface alternate setting 1-16 interface descriptor offset field size value description 0 blength 1 0x09 size of this descriptor in bytes 1 bdescriptortype 1 0x04 interface descriptor type 2 binterfacenumber 1 0x00 number of interface 3 balternatesetting 1 1-16 (note 1) alternate setting 1-16 for this interface 4 bnumendpoints 1 0x01 number of endpoints used by this interface 5 binterfaceclass 1 0x00 image interface class code 6 binterfacesubclass 1 0x00 digital video camera subclass code 7 binterfaceprotocol 1 0x00 protocol code. no class specific protocol. 8 iinterface 1 0x00 no interface string note 1. refer to table 7.11. table 7.10 W9968CF alternate setting 1-16 data-in endpoint descriptor offset field size value description
W9968CF publication release date: may 1999 - 33 - revision a2 0 blength 1 0x07 size of this descriptor in bytes 1 bdescriptortype 1 0x05 endpoint descriptor type 2 bendpointaddress 1 0x81 endpoint number. direction is set to in. 3 bmattributes 1 0x01 isochronous transfer type 4 wmaxpacketsize 2 note 1 maximum packet size of this alternate setting 6 binterval 1 0x01 interval in milliseconds for polling endpoint for data transfers note 1. refer to table 7.11. table 7.11 shows balternatesetting fields and wmaxpacketsize fields for these alternate settings. table 7.11 the maximum data payload size in bytes for alternate settings alternate setting 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 balternatesetting 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 wmaxpacketsize 1023 959 895 831 767 703 639 575 511 447 383 319 255 191 127 63 7.4.3.3 string descriptors the W9968CF includes strings describing the manufacturer and product as shown in table 7.12. table 7.12 W9968CF default stream descriptors offset field size value description 0 blength 1 0x04 length of string descriptor in bytes 1 bdescriptortype 1 0x03 string descriptor type 2 bstring 2 0x0409 array of two-byte langid codes (english american) 4 blength 1 0x10 length of string descriptor in bytes 5 bdescriptortype 1 0x03 string descriptor type 6 bstring 14 winbond manufacturer 20 blength 1 0x10 length of string descriptor in bytes 21 bdescriptortype 1 0x03 string descriptor type 22 bstring 14 W9968CF product
W9968CF - 34 - 7.5 video/still image data transfer video or still image data from the device is delivered to the host system through an isochronous pipe (endpoint 1). the maximum packet size can be varied for different alternate settings for limited usb bandwidth for other usb devices. 7.5.1 output video data format the W9968CF supports two video transfer modes: original video transfer mode and jpeg compression video transfer mode. the captured video stored in the dram will be compressed by the jpeg encoder and then transferred to the host if jpeg compression video transfer mode is selected, or will be directly transferred to the host if original video transfer mode is selected. four different formats are supported for the output video which are selected by bits 1-0 of the video capture control register (cr26) and bits 1 of the jpeg encoder control register (cr39) as described in table 7.13. table 7.13 output video data format cr39_1 cr26_1-0 output video data format 0 00 original yuv4:2:2 packed mode 0 01 original yuv4:2:0 packed mode 1 0x reserved 1 10 jpeg yuv4:2:2 non-interleaved scan mode 1 11 jpeg yuv4:2:0 non-interleaved scan mode 7.5.2 video frame synchronization a single video frame typically requires multiple usb packets. one or more zero length isochronous data packets are used to mark the end of a video frame. the first non-zero data packet is the start of the next video frame. if an error is encountered during the reception of a usb packet, the host may discard the entire video frame. processing begins again with the next video frame as indicated by the first non-zero length isochronous data packet after one or more zero-length packet. 7.5.3 bandwidth management the W9968CF provides for varying the bandwidth required by providing a zero-bandwidth interface (alternate setting zero) and 16 alternate settings interfaces with 8 mbps down to 0.5 mbps bandwidth in descending 0.5 mbps steps. the default alternate setting zero (with zero bandwidth) selected by a set configuration request allows a video camera to be initially configured even on a highly utilized usb bus. before the device begins streaming video data, the host software must select an alternate setting with the appropriate amount of bandwidth by using the set interface request.
W9968CF publication release date: may 1999 - 35 - revision a2 7.6 power management the W9968CF provides three output pins as described below for the video camera power management to meet the usb specification requirements. pwrdwn/pwrdwn# : these pins, when active, are used to turn off the usb 5v power supply to the video source circuits (ccd/cmos sensor device, adc, dsp, video decoder, etc.). suspnd : this pin, when active, is used to turn off the 3.3v power supply to the W9968CF (excluding usbvdd pin, the power supply for the transceiver), dram, and e 2 prom. bit 10 of the miscellaneous control register (cr00) determines whether the W9968CF-based device is a high power device or a low power device as described below: cr00_10 = 1 : high power, bus-powered devices. they must draw no more than 100 ma upon power up and may draw up to 500 ma after being configured. cr00_10 = 0 : low power, bus-powered devices. may draw up to 100 ma from their upstream connection to allow the interface to function when the remainder of the hub is powered down. 7.6.1 W9968CF reset the W9968CF has two reset sources: system reset from the input rstin# pin, and the usb reset detected by seeing a single-ended zero (se0) for more than 2.5 us. all reset sources are joined inside the W9968CF into a single reset signal which initializes the W9968CF and is also output via the rstout pin to initialize other external circuits. reset can wake the W9968CF from the suspended mode (suspnd is inactive low) and turn off the usb 5v power supply to the video source circuits (pwrdwn is active high and pwrdwn# is active low). 7.6.2 before configured before configured, the W9968CF should be reset and keep pwrdwn and pwrdwn# to be active (cr00_4 = 0) such that the W9968CF-based devices will not draw more than 100 ma from the usb bus power supply. it is required that an external power-on reset should be applied to the rstin# pin before any usb transaction is sent to the W9968CF by the host. 7.6.3 after configured after configured, pwrdwn and pwrdwn# pins should be inactive by programming the camera power-on control register to one (cr00_4 = 1) to enable device functions. the W9968CF-based devices must draw less than 100 ma (cr00_10 = 0) or 500 ma (cr00_10 = 1) from the bus during normal operation. the sof (start of frame) packet is guaranteed to occur once a frame to keep full speed devices awake during normal bus operation. 7.6.4 suspend the W9968CF goes into the suspend mode from any powered state when it sees a constant idle state
W9968CF - 36 - on the usb bus lines for more than 3.0 ms. when suspended, both suspnd and pwrdwn are active high, pwrdwn# is active low, and the camera power-on control register is cleared to zero (cr00_4 = 0). the W9968CF-based devices must draw less than 500 ua from the bus when suspended. 7.6.5 resume once the W9968CF is in the suspended state, it can be resumed by receiving non-idle signaling on the bus. suspnd will be inactive low when resumed. pwrdwn and pwrdwn# will remain active until the camera power-on control register is set to one (cr00_4 = 1) by the host.
W9968CF publication release date: may 1999 - 37 - revision a2 7.7 serial eeprom interface the W9968CF supports an external 1k (128 8) serial e 2 prom as an optional source for ihv-specific vendor id and product id. the external e 2 prom data, in stead of the default data, will be used when a high is sampled at sda pin (pin 49) during a reset operation. 7.7.1 eeprom data structure the e 2 prom contains ihv-specific vendor id and product id as described in table 7.14. table 7.14 eeprom data structure address field size value description 0x00 2 tl total length of e 2 prom data to be returned 0x02 idvendor 2 vendor id 0x04 idproduct 2 product id 7.7.2 eeprom operations the external e 2 prom will be only read right after a reset operation. tl (defined in address 0x00) bytes of data will be read by using a sequential read operation. start condition: a high-to-low transition of sda with scl high is a start condition which must proceed any other command. stop condition: a low-to-high transition of sda with scl high is a stop condition which terminates all communications. after a read sequence, the stop command will place the e 2 prom in a standby power mode. acknowledge: all addresses and data words are serially transmitted to and from the e 2 prom in 8-bit words. the e 2 prom will acknowledge by pulling sda low after receiving each address. the W9968CF will likewise acknowledge by pulling sda low after receiving each data word. this must happen during the ninth clock cycle after each word received and after all other devices have freed the sda bus. refer to figure 7.4, a sequential read is initiated by the W9968CF with a start condition followed by a 7-bit data word address (always 0) and a high read bit. the e 2 prom will respond with an acknowledge and then serially output 8 data bits. after the W9968CF receives an 8-bit data word, it responds with an acknowledge. as long as the e 2 prom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. the sequential read operation is terminated when the memory address limit (tl) is reached and the W9968CF does not respond with an acknowledge but does generate a following stop condition.
W9968CF - 38 - sda scl start stop acknowledge 1 8 9 start scl sda in sda out start msb lsb word address (0) r/w ack data 0 ack data 1 ack data 127 no ack stop sda sequential read figure 7.4 eeprom timing diagram
W9968CF publication release date: may 1999 - 39 - revision a2 7.8 microcontroller interface the W9968CF supports an external 8-bit microcontroller to access dram and W9968CF internal registers for portable pc camera applications. 7.8.1 base address setup the W9968CF internal registers occupy 256-byte microcontroller address space. a special base address (ba) setup mechanism, described as followed, is designed for the microcontroller to configure base address for the W9968CF internal register access: 1 assert hardware reset. 2 write the key, 2 ! 2 2 ! 2 2 w 2 2 9 2 2 9 2 2 6 2 2 7 2 2 ! 2 in ascii code, to the port xx00h. 3 the port address, xx00h, then will be used as base address (ba) for the microcontroller access. the setup procedure must be executed right after the hardware reset. once the procedure is finished, the xx00h address will be used as the base address until another hardware reset is asserted. 7.8.2 W9968CF register access since all internal registers are 16-bit wide, it takes two cycles for the microcontroller to access one 16- bit register through the 8-bit data bus. the two microcontroller access cycles should be in low-byte then high-byte order. for example, to write cr00 register, the microcontroller must write to ba + 00h address at first, then write to ba + 01h address to complete this 16-bit register access. 7.8.3 microcontroller interrupt the W9968CF interrupts the microcontroller by forcing int# pin to low when it completes a still image capture (original video mode) or jpeg compression of this image (jpeg compression mode). once interrupt is acknowledged by the microcontroller, it must write one to bit 5 of the miscellaneous control register (cr00_5) to clear the interrupt. interrupt can also be disabled by writing zero to bit 6 of the miscellaneous control register (cr00_6). 7.8.4 dram access the external microcontroller can read/write access dram through W9968CF by using the following registers: uc access dram start address register (ba + 18h ~ 1ah): specifies the 21-bit starting word address of the dram to be accessed. uc access dram mode select (bit 8 of ba + 1bh): specifies read or write access mode. uc access dram data port register (ba + 1ch ~ 1dh): 16-bit data port which stores data read from dram in read mode, or data to be written into dram in write mode. read access (uc reads data from dram)
W9968CF - 40 - 1 dram start address setup. program the 21-bit word address to ba + 18h (bits 7-0), ba + 19h (bits 15-8), then ba + 1ah (bits 20-16). 2 read access mode setup. program 0 to bit 0 of ba + 1bh to select read mode. W9968CF then starts accessing 16-bit dram data into the internal latches, and the internal dram address will be increased by 1 automatically after the access. 3 read low-byte dram data. read low-byte dram data from ba + 1ch location. 4 read high-byte dram data. read high-byte dram data from ba + 1dh location. the W9968CF starts accessing the next-address dram data and the internal dram address will be increased by 1 automatically after the access. 5 read contiguous dram data. repeat steps 3 and 4 for contiguous dram data accesses. write access (uc writes data to dram) 1 dram start address setup. program the 21-bit word address to ba + 18h (bits 7-0), ba + 19h (bits 15-8), then ba + 1ah (bits 20-16). 2 write access mode setup. program 1 to bit 0 of ba + 1bh to select write mode. 3 write low-byte dram data. write low-byte dram data into ba + 1ch location. 4 write high-byte dram data. write high-byte dram data into ba + 1dh location. the W9968CF then starts writing the 16-bit data into dram and the internal dram address will be increased by 1 automatically after the access. 5 write contiguous dram data. repeat steps 3 and 4 for contiguous dram data accesses. 7.8.5 ihv-specific information the microcontroller can provide ihv-specific information including vendor id, product id, device release number, and string descriptors of manufacturer, product, and device s serial number as that of e 2 prom to save the cost of an e 2 prom. maximum 128 bytes information can be provided and data structure is the same as that of e 2 prom shown in table 7.14. all ihv-specific information must be written to the W9968CF via the vendor string data port register (cr0f) in word-aligned sequence right after hardware reset and base address is set up.
W9968CF publication release date: may 1999 - 41 - revision a2 8 control and status registers the internal W9968CF control registers can be accessed by performing one of the two vendor-specific requests on the default pipe (endpoint 0): get W9968CF control for read access and set W9968CF control for write access. all W9968CF control registers are 16-bit wide and can be accessed in word only. table 8.1 shows the control register map. table 8.1 W9968CF control register map index uc address symbol description 0000h ba + 00h - 01h cr00 miscellaneous control register 0001h ba + 02h - 03h cr01 serial bus control register 0002h ba + 04h - 05h cr02 general i/o port control register 0003h ba + 06h - 07h cr03 dram timing control register 0004h ba + 08h - 09h cr04 sdram control register 0005h ba + 0ah - 0bh cr05 memory controller test mode control register 0006h ba + 0ch - 0dh cr06 fast serial bus write register 0 0007h ba + 0eh - 0fh cr07 fast serial bus write register 1 0008h ba + 10h - 11h cr08 fast serial bus write register 2 0009h ba + 12h - 13h cr09 fast serial bus write register 3 000ch ba + 18h - 19h cr0c uc access dram start address low register 000dh ba + 1ah - 1bh cr0d uc access dram start address high register 000eh ba + 1ch - 1dh cr0e uc access dram data port register 000fh ba + 1eh - 1fh cr0f vendor string register 0010h ba + 20h - 21h cr10 cropping window start x register 0011h ba + 22h - 23h cr11 cropping window start y register 0012h ba + 24h - 25h cr12 cropping window end x register 0013h ba + 26h - 27h cr13 cropping window end y register 0014h ba + 28h - 29h cr14 captured video width register 0015h ba + 2ah - 2bh cr15 captured video height register 0016h ba + 2ch - 2dh cr16 video capture control register 0017h ba + 2eh - 2fh cr17 video capture test mode control register 0018h ba + 30h - 31h cr18 capture test data register 0020h ba + 40h - 41h cr20 capture y frame buffer 0 start address low register 0021h ba + 42h - 43h cr21 capture y frame buffer 0 start address high register
W9968CF - 42 - 0022h ba + 44h - 45h cr22 capture y frame buffer 1 start address low register 0023h ba + 46h - 47h cr23 capture y frame buffer 1 start address high register 0024h ba + 48h - 49h cr24 capture u frame buffer 0 start address low register 0025h ba + 4ah - 4bh cr25 capture u frame buffer 0 start address high register 0026h ba + 4ch - 4dh cr26 capture u frame buffer 1 start address low register 0027h ba + 4eh - 4fh cr27 capture u frame buffer 1 start address high register 0028h ba + 50h - 51h cr28 capture v frame buffer 0 start address low register 0029h ba + 52h - 53h cr29 capture v frame buffer 0 start address high register 002ah ba + 54h - 55h cr2a capture v frame buffer 1 start address low register 002bh ba + 56h - 57h cr2b capture v frame buffer 1 start address high register 002ch ba + 58h - 59h cr2c capture y frame buffer stride register 002dh ba + 5ah - 5bh cr2d capture uv frame buffer stride register 002eh ba + 5ch - 5dh cr2e video capture y fifo threshold register 002fh ba + 5eh - 5fh cr2f video capture uv fifo threshold register 0030h ba + 60h - 61h cr30 image maximum width register 0031h ba + 62h - 63h cr31 image maximum height register 0032h ba + 64h - 65h cr32 compressed bitstream buffer 0 start address low register 0033h ba + 66h - 67h cr33 compressed bitstream buffer 0 start address high register 0034h ba + 68h - 69h cr34 compressed bitstream buffer 1 start address low register 0035h ba + 6ah - 6bh cr35 compressed bitstream buffer 1 start address high register 0036h ba + 6ch - 6dh cr36 restart interval register 0037h ba + 6eh - 6fh cr37 vle fifo threshold register 0038h ba + 70h - 71h cr38 vertical up-scaling control register 0039h ba + 72h - 73h cr39 jpeg encoder control register 003ah ba + 74h - 75h cr3a jpeg image size low register 003bh ba + 76h - 77h cr3b jpeg image size high register 003ch ba + 78h - 79h cr3c usb fifo enable and threshold register 003dh ba + 7ah - 7bh cr3d usb isochronous transfer size low register 003eh ba + 7ch - 7dh cr3e usb isochronous transfer size high register 003fh ba + 7eh - 7fh cr3f jpeg/mctl test data register 0040h-5fh ba + 80h - bfh cr40-5f jpeg luminance quantization table registers 0060h-7fh ba + c0h - ffh cr60-7f jpeg chrominance quantization table registers
W9968CF publication release date: may 1999 - 43 - revision a2 8.1 general control registers miscellaneous control register (cr00) read/write index: 0000h uc address: 00h - 01h power-on default: ff00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fs sus iso rcv pll bp type ms 24m inte intc pwr r jr ur mr bit 15 force suspend mode (it reflects status of the md7 pin upon reset) 0 = force suspend mode when suspend mode is enabled (cr00_14 = 1) 1 = normal operation bit 14 suspend mode enable (it reflects status of the md6 pin upon reset) 0 = disable 1 = enable bit 13 isochronous handshake phase support (it reflects status of the md5 pi n upon reset) 0 = enable 1 = disable bit 12 differential rcv source (it reflects status of the md4 pin upon reset) 0 = generated by the sie 1 = generated by the usb transceiver bit 11 pll enable (it reflects status of the md3 pin upon reset) 0 = disable 1 = enable bit 10 high power device (it reflects status of the md2 pin upon reset) 0 = low power device 1 = high power device bit 9 dram type (it reflects status of the md1 pin upon reset) 0 = edo dram 1 = sdram bit 8 dram size (it reflects status of the m d0 pin upon reset) 0 = 256k dram
W9968CF - 44 - 1 = 1m dram bit 7 clk24m output enable 0 = disable, clk24m pin is forced to low 1 = enable bit 6 interrupt enable 0 = disable, int# is forced to inactive high 1 = enable bit 5 interrupt clear 0 = normal operation 1 = clear interrupt, int# will be cleared to high if enabled. bit 4 camera power-on control 0 = power-down 1 = power-on note. this register will be cleared to zero when suspended. bit 3 reserved bit 2 jpeg encoder reset 0 = normal operation 1 = reset jpeg encoder bit 1 usb fifo reset 0 = normal operation 1 = reset usb fifo bit 0 md bus reset 0 = normal operation 1 = reset md bus (tri-stated) serial bus control register (cr01) read/write index: 0001h uc address: 02h - 03h power-on default: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved eep mcu xtr reserved fsb sde sdr scr sdw scw bits 15-11 reserved
W9968CF publication release date: may 1999 - 45 - revision a2 bit 10 external eeprom enable (read-only, it reflects status of the sda pin upon reset) 0 = disable 1 = enable bit 9 external microcontroller enable (read-only, it reflects status of the extmcu pin) 0 = disable 1 = enable bit 8 usb transceiver (it reflects status of the intxtr pin upon reset) 0 = external transceiver 1 = internal transceiver bits 7-6 reserved bit 5 fast serial bus write enable 0 = disable, serial bus outputs (sdata and sclk) are controlled by cr01_1-0 1 = enable, serial bus outputs (sdata and sclk) are controlled by cr06 - cr09. once cr09 is programmed, all 32-bit data for sdata and 32-bit data for sclk from cr06 - cr09 will be serially output in 400 khz bit frequency (2.5 us bit time). bit 4 serial data enable/serial data strobe 0 = sde#/sds pin is driven low 1 = sde#/sds pin is driven high bit 3 serial interface data read (read only) 0 = sdata is low 1 = sdata is high bit 2 seria l interface clock read (read only) 0 = sclk is low 1 = sclk is high bit 1 serial interface data write 0 = sdata pin is driven low 1 = sdata pin is tri-stated bit 0 serial interface clock write 0 = sclk pin is driven low 1 = sclk pin is tri-state general i/o port control register (cr02) read/write index: 0002h uc address: 04h - 05h
W9968CF - 46 - power-on default: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p7w p6w p5w p4w p3w p2w p1w p0w p7d p6d p5d p4d p3d p2d p1d p0d bits 15-8 gpio[7:0] direction 0 = input 1 = output bits 7-0 gpio[7:0] data 0 = low 1 = high note. gpio[7:0] pins are used as a[15:8] to the external microcontroller if used (extmcu = 1). this register does not control on the gpio[7:0] pins if an external microcontroller is used. dram timing control register (cr03) read/write index: 0003h uc address: 06h - 07h power-on default: 405dh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r refresh cycles dct t_rp ras t_rcd t_ras re t_cas bit 15 reserved bits 14-12 refresh cycles 000 = 1 refresh cycle per horizontal scan line 001 = 2 refresh cycles per horizontal scan line 010 = 3 refresh cycles per horizontal scan line 011 = 4 refresh cycles per horizontal scan line 100 = 5 refresh cycles per horizontal scan line 101 = 6 refresh cycles per horizontal scan line 110 = 7 refresh cycles per horizontal scan line 111 = 8 refresh cycles per horizontal scan line bit 11 dct dram data access 0 = dct dram data access can be interrupted by mctl when other dram request is active. 1 = dct dram data access cannot be interrupted by mctl.
W9968CF publication release date: may 1999 - 47 - revision a2 bits 10-9 ras# precharge time control 00 = 2 mclks 01 = 3 mclks 10 = 4 mclks 11 = 5 mclks bit 8 ras# precharge time shrink 0 = not shrink 1 = shrink by 0.5 mclk over that specified by bits 10-9 of this register bits 7-6 ras# low to cas# low time control 00 = 1 mclk 01 = 2 mclks 10 = 3 mclks 11 = 4 mclks bits 5-3 refresh cycle ras# low pulse width control 000 ~ 111 = 1 ~ 8 mclk cycles bit 2 ras# low extend 0 = not extend 1 = extend 1 mclk bits 1-0 cas# low stretch control 00 = not stretch 01 = stretch approximately 1 ns 10 = stretch approximately 2 ns 11 = stretch approximately 3 ns sdram control register (cr04) read/write index: 0004h uc address: 08h - 09h power-on default: 0030h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved read latency btyp burst length bits 15-7 reserved bits 6-4 read latency
W9968CF - 48 - 000 = reserved 001 = 1 clock 010 = 2 clocks 011 = 3 clocks 100 ~ 111 = reserved bit 3 burst type 0 = sequential 1 = interleaved bits 2-0 burst length burst length bits 2-0 sequential (bit 3 =0) interleaved (bit 3 = 1) 000 1 1 001 2 2 010 4 4 011 8 8 100 reserved reserved 101 reserved reserved 110 reserved reserved 111 full page reserved memory controller test mode control register (cr05) read/write index: 0005h uc address: 0ah - 0bh power-on default: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ten hd sr test r mts bits 15-8 reserved bit 7 memory controller test mode enable 0 = disable 1 = enable bit 6 dram controller hold control 0 = normal operation 1 = hold dram controller operation bit 5 sdram self refresh 0 = disable 1 = enable
W9968CF publication release date: may 1999 - 49 - revision a2 bit 4 sdram delay test (used for test mode only) bit 3 reserved bits 2-0 memory controller test mode select fast serial bus write registers 0~3 (cr06~cr09) read/write index: 0006h - 0009h u c address: 0ch - 13h power-on default: 0000h cr06 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 c7 d7 c6 d6 c5 d5 c4 d4 c3 d3 c2 d2 c1 d1 c0 d0 cr07 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 c15 d15 c14 d14 c13 d13 c12 d12 c11 d11 c10 d10 c9 d9 c8 d8 cr08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 c23 d23 c22 d22 c21 d21 c20 d20 c19 d19 c18 d18 c17 d17 c16 d16 cr09 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 c31 d31 c30 d30 c29 d29 c28 d28 c27 d27 c26 d26 c25 d25 c24 d24 d[31:0] 32-bit data for sdata output. when fast s erial bus is enabled (cr01_5 = 1), d[31:0] will be output serially from lsb to msb once cr09 is programmed. c[31:0] 32-bit data for sclk output. when fast serial bus is enabled (cr01_5 = 1), c[31:0] will be output serially from lsb to msb once cr09 is programmed. uc access dram start address low register (cr0c) read/write index: 000ch uc address: 18h - 19h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 uca[15:0] bits 15-0 uc access dram start address low
W9968CF - 50 - a 21-bit value specifies the word offset from the start of the frame buffer for the external microcontroller access. this register contains 16 lower-order bits of the value. bits 20-16 are located at cr0d_4-0. uc access dram start address high register (cr0d) read/write index: 000dh uc address: 1ah - 1bh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved r/w reserved uca[20:16] bits 15-9 reserved bit 8 uc access dram mode 0 = read mode. uc reads data from dram. 1 = write mode. uc writes data to dram. bits 7-5 reserved bits 4-0 uca[20:16] uc access dram data port register (cr0e) read/write index: 000eh uc address: 1ch - 1dh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 high byte data low byte data bits 15-8 high byte data bits 7-0 low byte data vendor string data port register (cr0f) write -only index: 000fh uc address: 1eh - 1fh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vendor string data port
W9968CF publication release date: may 1999 - 51 - revision a2 bits 15-0 vendor string data port maximum 128 bytes ihv-specific information can be provided by the microcontroller through this data port. this data port can be written by the microcontroller only and is prohibted from the usb interface accessing.
W9968CF - 52 - 8.2 video input control registers cropping window start x register (cr10) read/write index: 0010h uc address: 20h - 21h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cropping window start x bits 15-10 reserved bits 11-0 cropping window start x a 12-bit value specifies the number of pixels between the inactive edge of hs and the first cropped video pixel. cropping window start y register (cr11) read/write index: 0011h uc address: 22h - 23h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cropping window start y bits 15-11 reserved bits 10-0 cropping window start y an 11-bit value specifies the number of lines between the inactive edge of vs and the first cropped video data line. cropping window end x register (cr12) read/write index: 0012h uc address: 24h - 25h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cropping window end x
W9968CF publication release date: may 1999 - 53 - revision a2 bits 15-12 reserved bits 10-1 cropping window end x a 12-bit value specifies the number of pixels between the inactive edge of hs and the last cropped video pixel. cropping window end y register (cr13) read/write index: 0013h uc address: 26h - 27h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved cropping window end y bits 15-11 reserved bits 10-0 cropping window end y an 11-bit value specifies the number of lines between the inactive edge of vs and the last cropped video data line. captured video width register (cr14) read/write index: 0014h uc address: 28h - 29h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved captured video width bits 15-11 reserved bits 10-0 captured video width an 11-bit value specifies the width in pixel of the captured video which is down-scaled (or not) from the cropped video. cr14 cr12 - cr10. down-scaling is automatically done by an internal dda (digital differential accumulator). captured video height register (cr15) read/write index: 0015h uc address: 2ah - 2bh power-on default: xxxxh
W9968CF - 54 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved captured video height bits 15-11 reserved bits 10-0 captured video height an 11-bit value specifies the height in line of the captured video which is down-scaled (or not) from the cropped video. cr15 cr13 - cr11. down-scaling is automatically done by an internal dda (digital differential accumulator). video capture control register (cr16) read/write index: 0016h uc address: 2ch - 2dh power-on default: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vce capctl vsp hsp vim vi format dbe dbs clm ckf fte ftm vc format bit 15 video capture enable 0 = disable 1 = enable bits 14-13 video capture control 00 = capture all received fields/frames video data 01 = capture every other received fields/frames video data 10 = capture and hold after one frame/field (non-interlaced/interlaced mode) 11 = reserved bit 12 vs input pin polarity 0 = negative sync pulse 1 = positive sync pulse bit 11 hs input pin polarity 0 = negative sync pulse 1 = positive sync pulse bit 10 input video mode 0 = 16-bit mode 1 = 8-bit mode bits 9-8 input video data format
W9968CF publication release date: may 1999 - 55 - revision a2 yuv input video data format bits 9-8 8-bit mode (y[7:0]) 16-bit mode (uv[7:0]) 00 y, u, y, v, ? u, v, u, v, ? 01 u, y, v, y, ? u, v, u, v, ? 10 y, v, y, u, ? v, u, v, u, ? 11 v, y, u, y, ? v, u, v, u, ? bit 7 double buffering enable 0 = disable 1 = enable bit 6 doubl e buffering status (read-only) 0 = buffer 0 active 1 = buffer 1 active bit 5 video data clamping enable (clamped to ccir-601 format) 0 = disable 1 = enable (y is clamped to 16 - 235, uv is clamped to 16 - 240) bit 4 viclk falling edge latch 0 = input video data and signals are latched by rising edge of viclk 1 = input video data and signals are latched by falling edge of viclk bit 3 filter enable 0 = disable 1 = enable bit 2 filter type 0 = 1-2-1 filter 1 = 2-3-6-3-2 filter bits 1-0 captured video data format 00 = yuv4:2:2 packed mode 01 = yuv4:2:0 packed mode 10 = yuv4:2:2 planar mode 11 = yuv4:2:0 planar mode video capture test mode control register (cr17) read/write index: 0017h uc address: 2eh - 2fh power-on default: 0000h
W9968CF - 56 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ten reserved video test selection bits 15-8 reserved bit 7 video capture test mode enable 0 = normal operation 1 = test mode enable bits 6-5 reserved bits 4-0 video capture test mode selection capture test data register (cr18) read/write index: 0018h uc address: 30h - 31h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 capture test data bits 15-0 capture test data (used for test mode only) capture y frame buffer 0 start address low register (cr20) read/write index: 0020h uc address: 40h - 41h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 capysa0[15:0] bits 15-0 capture y frame buffer 0 start address low a 21-bit value specifies the word offset from the start of the frame buffer for buffer 0 (packed mode), or y components (planar mode) of the captured video. buffer 0 is always used, no matter double buffering is enabled or disabled. this register contains 16 lower- order bits of the value. bits 20-16 are located at cr17_4-0. capture y frame buffer 0 start address high register (cr21)
W9968CF publication release date: may 1999 - 57 - revision a2 read/write index: 0021h uc address: 42h - 43h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved capysa0[20:16] bits 15-5 reserved bits 4-0 capysa0[20:16] capture y frame buffer 1 start address low register (cr22) read/write index: 0022h uc address: 44h - 45h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 capysa1[15:0] bits 15-0 capture y frame buffer 1 start address low a 21-bit value specifies the word offset from the start of the frame buffer for buffer 1 (packed mode), or y components (planar mode) of the captured video. buffer 1 is not used if double buffering is disabled. this register contains 16 lower-order bits of the value. bits 20-16 are located at cr19_4-0. capture y frame buffer 1 start address high register (cr23) read/write index: 0023h uc address: 46h - 47h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved capysa1[20:16] bits 15-5 reserved bits 4-0 capysa1[20:16] capture u frame buffer 0 start address low register (cr24) read/write index: 0024h uc address: 48h - 49h
W9968CF - 58 - power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 capusa0[15:0] bits 15-0 capture u frame buffer 0 start address low a 21-bit value specifies the word offset from the start of the frame buffer for u components (planar mode) of the captured video. it is not used if the captured video is in packed mode. buffer 0 is always used, no matter double buffering is enabled or disabled. this register contains 16 lower-order bits of the value. bits 20-16 are located at cr1b_4-0. capture u frame buffer 0 start address high register (cr25) read/write index: 0025h uc address: 4ah - 4bh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved capusa0[20:16] bits 15-5 reserved bits 4-0 capusa0[20:16] capture u frame buffer 1 start address low register (cr26) read/write index: 0026h uc address: 4ch - 4dh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 capusa1[15:0] bits 15-0 capture u frame buffer 1 start address low a 21-bit value specifies the word offset from the start of the frame buffer for u components (planar mode) of the captured video. it is not used if the captured video is in packed mode. buffer 1 is not used if double buffering is disabled. this register contains 16 lower-order bits of the value. bits 20-16 are located at cr1d_4-0. capture u frame buffer 1 start address high register (cr27) read/write index: 0027h uc address: 4eh - 4fh
W9968CF publication release date: may 1999 - 59 - revision a2 power-on default: xx xxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved capusa1[20:16] bits 15-5 reserved bits 4-0 capusa1[20:16] capture v frame buffer 0 start address low register (cr28) read/write index: 0028h uc address: 50h - 51h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 capvsa0[15:0] bits 15-0 capture v frame buffer 0 start address low a 21-bit value specifies the word offset from the start of the frame buffer for v components (planar mode) of the captured video. it is not used if the captured video is in packed mode. buffer 0 is always used, no matter double buffering is enabled or disabled. this register contains 16 lower-order bits of the value. bits 20-16 are located at cr1f_4-0. capture v frame buffer 0 start address high register (cr29) read/write index: 0029h uc address: 52h - 53h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved capvsa0[20:16] bits 15-5 reserved bits 4-0 capvsa0[20:16] capture v frame buffer 1 start address low register (cr2a) read/write ind ex: 002ah uc address: 54h - 55h power-on default: xxxxh
W9968CF - 60 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 capvsa1[15:0] bits 15-0 capture v frame buffer 1 start address low a 21-bit value specifies the word offset from the start of the frame buffer for v components (planar mode) of the captured video. it is not used if the captured video is in packed mode. buffer 1 is not used if double buffering is disabled. this register contains 16 lower-order bits of the value. bits 20-16 are located at cr21_4-0. capture v frame buffer 1 start address high register (cr2b) read/write index: 002bh uc address: 56h - 57h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved capvsa1[20:16] bits 15-5 reserved bits 4-0 capvsa1[20:16] capture y frame buffer stride register (cr2c) read/write index: 002ch uc address: 58h - 59h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved capys[10:0] bits 15-11 reserved bits 10-0 capture y frame buffer stride this register specifies the word offset of vertically adjacent pixels (packed mode), or vertically adjacent y components of the captured video. it is used for both buffer 0 and buffer 1. capture uv frame buffer stride register (cr2d) read/write index: 002dh uc address: 5ah - 5bh
W9968CF publication release date: may 1999 - 61 - revision a2 power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved capys[9:0] bits 15-10 reserved bits 9-0 capture uv frame buffer stride this register specifies the word offset of vertically adjacent u or v components of the captured video which is in planar mode. it is used for both buffer 0 and buffer 1. it is not used if the captured video is in packed mode. video capture y fifo threshold register (cr2e) read/write index: 002eh uc address: 5ch - 5dh power-on default: 0804h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved vcapy_ht[4:0] reserved vcapy_lt[4:0] bits 15-13 reserved bits 12-8 video capture y fifo high threshold when video capture fifo (packed mode), or y fifo (planar mode) is filled to this threshold, a request is generated to the dram controller for dram access. initial value is 08h. bits 7-5 reserved bits 4-0 video capture y fifo low threshold when video capture fifo (packed mode), or y fifo (planar mode) is fetched to this threshold by dram controller, the fifo is ready to release dram access to other pending requests. initial value is 04h. video capture uv fifo threshold register (cr2f) read/write index: 002fh uc address: 5eh - 5fh power-on default: 8484h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vcapu_ht[3:0] vcapu_lt[3:0] vcapv_ht[3:0] vcapv_lt[3:0]
W9968CF - 62 - bits 15-12 video capture u fifo high threshold when video capture u fifo (planar mode) is filled to this threshold, a request is generated to the dram controller for dram access. it is not used if the captured video is in packed mode. initial value is 08h. bits 11-8 video capture u fifo low threshold when video capture u fifo (planar mode) is fetched to this threshold by dram controller, the fifo is ready to release dram access to other pending requests. it is not used if the captured video is in packed mode. initial value is 04h. bits 7-4 video capture v fifo high threshold when video capture v fifo (planar mode) is filled to this threshold, a request is generated to the dram controller for dram access. it is not used if the captured video is in packed mode. initial value is 08h. bits 3-0 video capture v fifo low threshold when video capture v fifo (planar mode) is fetched to this threshold by dram controller, the fifo is ready to release dram access to other pending requests. it is not used if the captured video is in packed mode. initial value is 04h.
W9968CF publication release date: may 1999 - 63 - revision a2 8.3 jpeg encoder control registers image maximum width register (cr30) read/write index: 0030h uc address: 60h - 61h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved maxw[10:0] bits 15-11 reserved bits 10-0 image maximum width image maximum height register (cr31) read/write index: 0031h uc address: 62h - 63h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved maxh[10:0] bits 15-11 reserved bits 10-0 image maximum height compressed bitstream buffer 0 start address low register (cr32) read/write index: 0032h uc address: 64h - 65h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bssa0[15:0] bits 15-0 compressed bitstream buff er 0 start address low a 21-bit value specifies the word offset from the start of the frame buffer for the compressed bitstream buffer 0. bits 20-16 are located at cr33_4-0.
W9968CF - 64 - compressed bitstream buffer 0 start address high register (cr33) read/write index : 0033h uc address: 66h - 67h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved bssa0[20:16] bits 15-5 reserved bits 4-0 bssa0[20:16] compressed bitstream buffer 1 start address low register (cr34) read/write index: 0034h uc a ddress: 68h - 69h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bssa1[15:0] bits 15-0 compressed bitstream buffer 1 start address low a 21-bit value specifies the word offset from the start of the frame buffer for the compressed bitstream buffer 1. bits 20-16 are located at cr35_4-0. compressed bitstream buffer 1 start address high register (cr35) read/write index: 0035h uc address: 6ah - 6bh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved bssa1[20:16] bits 15-5 reserved bits 4-0 bssa1[20:16] restart interval register (cr36) read/write index: 0036h uc address: 6ch - 6dh
W9968CF publication release date: may 1999 - 65 - revision a2 power-on default: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 restart interval bits 15-0 restart interval specifies the number of mcu (minimum coded unit) in the restart interval. restart interval processing is disabled if this value is 0. vle fifo threshold register (cr37) read/write index: 0037h uc address: 6eh - 6fh power-on default: 0804h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved vle_ht[3:0] reserved vle_lt[3:0] bits 15-12 reserved bits 11-8 vle fifo high threshold when vle fifo is filled with jpeg coded bitstream to this threshold, a request is generated to the dram controller for dram access. initial value is 08h. bits 7-4 reserved bits 3-0 vle fifo low threshold when vle fifo is fetched to this threshold by dram controller, the fifo is ready to release dram access to other pending requests. initial value is 04h. vertical up-scaling control register (cr38) read/write ind ex: 0038h uc address: 70h - 71h power-on default: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en reserved vertical up-scaling factor bit 15 vertical up-scaling enable 0 = disable 1 = enable
W9968CF - 66 - bits 14-6 reserved bits 5-0 vertical up-scaling factor up-scaling ratio (scaled height/original height) = 1.x, where x = vertical up-scaling factor/64. the maximum 2 up-scaling will be done if 0 is programmed. jpeg encoder control register (cr39) read/write index: 0039h uc address: 72h - 73h power-on default: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved qrd reserved jclk test ten jen r bits 15-9 reserved bit 8 jpeg quantization table registers (cr40 ~ cr7f) read enable 0 = disable 1 = enable bits 7-5 reserved bit 4 jpeg clock enable (must be enable d before jpeg q-table access or encoding) 0 = disable 1 = enable bit 3 jpeg test (used for test mode only) bit 2 jpeg test mode enable 0 = disable 1 = enable bit 1 jpeg encoder enable 0 = disable 1 = enable bit 0 reserved jpeg image size low register (cr3a) read-only index: 003ah uc address: 74h - 75h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W9968CF publication release date: may 1999 - 67 - revision a2 jimg_size[15:0] bits 15-0 jpeg image size low a 21-bit value specifies the jpeg compressed image size in word. it is used by the microcontroller to determine starting address for the next still image. this register contains the 16 lower-order bits of the value. bits 20-16 are located at cr3b_4-0. jpeg image size high register (cr3b) read-only index: 003bh uc address: 76h - 77h power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved jimg_size _size[20:16] bits 15-5 reserved bits 4-0 jpeg image size high this register contains the 4 high-order bits of the jpeg image size. usb fifo enable and threshold register (cr3c) read/write index: 003ch uc address: 78h - 79h power-on default: 0a05h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 uen reserved usb_ht[3:0] reserved usb_lt[3:0] bit 15 usb isochronous pipe transfer enable 0 = disable 1 = enable bits 14-12 reserved bits 11-8 usb fifo high threshold bits 7-4 reserved bits 3-0 usb fifo low threshold
W9968CF - 68 - usb isochronous transfer size low register (cr3d) read/write index: 003dh uc address: 7ah - 7bh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iso_size[15:0] bits 15-0 usb isochronous transfer size low a 21-bit value specifies the usb isochronous transfer size in word for the original video transfer or the still image transfer. it is not used for the jpeg compression video transfer mode (cr39_1 = 1). this register contains the 16 lower-order bits of the value. bits 20-16 are located at cr3e_4-0. usb isochronous transfer size high register (cr3e) read/write index: 003eh uc address: 7ch - 7dh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved iso_size[20:16] bits 15-5 reserved bits 4-0 usb isochronous transfer size high this register contains the 4 high-order bits of the usb isochronous transfer size. it is not used for the jpeg compression video transfer mode (cr39_1 = 1). jpeg/mctl test data register (cr3f) read/write index: 003fh uc address: 7eh - 7fh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 jpeg/mctl test data bits 15-0 jpeg/mctl test data (used for test mode only) jpeg luminance quantization table registers (cr40 -- cr5f)
W9968CF publication release date: may 1999 - 69 - revision a2 read/write index: 0040h - 005fh uc address: 80h - bfh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 jpeg luminance quantization table bits 15-0 jpeg luminance quantization table note. these registers can be read only when cr39 bit 8 is enabled (cr39_8 = 1). jpeg chrominance quantization table registers (cr60 -- cr7f) read/write index: 0060h - 007fh uc address: c0h - ffh power-on default: xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 jpeg chrominance quantization table bits 15-0 jpeg chrominance quantization table note. these registers can be read only when cr39 bit 8 is enabled (cr39_8 = 1).
W9968CF - 70 - 9 electrical characteristics 9.1 absolute maximum ratings table 9.1 absolute maximum ratings ambient temperature 0 c to 70 c storage temperature -40 c to 125 c dc supply voltage -0.5v to 7v i/o pin voltage with respect to vss -0.5v to vdd + 0.5v 9.2 dc characteristics 9.2.1 usb transceiver dc characteristics table 9.2 usb transceiver dc characteristics symbol parameter conditions min. max. unit v di differential input sensitivity ? dp - dm 0.2 v v cm differential common mode range includes v di range 0.8 2.5 v v se single ended receiver threshold 0.8 2.0 v v ol static output low voltage rl of 1.5 k w to 3.6 v 0.3 v v oh static output high voltage rl of 15 k w to vss 2.8 3.6 v v crs output signal crossover voltage 1.3 2.0 v z drv driver output resistance steady state drive 28 43 w c in pin capacitance 20 pf 9.2.2 digital dc characteristics table 9.3 digital dc characteristics symbol parameter conditions min. max. unit vdd5v 5v power supply 4.40 5.25 v vdd 3.3v power supply 3.0 3.6 v v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v v ol output low voltage vss+0.4 v v oh output high voltage 2.4 v
W9968CF publication release date: may 1999 - 71 - revision a2 i il input low leakage current v in = 0.4v +70 m a i ih input high leakage current v in = 2.4v -70 m a i up pull-up current v in = 0v -133.2 -400.6 m a c io pin capacitance 10 pf i pd powerdown current usb suspend 200 m a i dd active current f clk = 12 mhz 120 ma 9.3 ac characteristics 9.3.1 usb transceiver ac characteristics low speed: 75ns at c l = 50pf, 300ns at c l = 350pf full speed: 4 to 20ns at c l = 50pf differential data lines 10% rise time 90% fall time t f t r 10% 90% c l c l figure 9.1 data signal rise and fall time t period differential data lines crossover points paired transitions n * t period + t xjr2 consecutive transitions n * t period + t xjr1 figure 9.2 differential data jitter t period differential data lines crossover point crossover point extended source eop width: t eopt receiver eop width: t eopr1 , t eopr2 diff. data to se0 skew n * t period + t deop figure 9.3 differential to eop transition skew and eop width
W9968CF - 72 - differential data lines paired transitions n * t period + t jr2 t period consecutive transitions n * t period + t jr1 t jr t jr1 t jr2 figure 9.4 receiver jitter tolerance table 9.4 usb transceiver ac characteristics symbol parameter conditions min. max. unit t r rise time cl = 50 pf 4 20 ns t f fall time cl = 50 pf 4 20 ns t rfm rise/fall time matching 90 110 % t drate full speed data rate average bit rate (12 mb/s 0.25%) 11.97 12.03 mbps t dj1 t dj2 source differential driver jitter to next transition for paired transitions -3.5 -4.0 3.5 4.0 ns ns t eopt source eop width 160 175 ns t deop differential to eop transition skew -2 5 ns t jr1 t jr2 receiver data jitter tolerance to next transition for paired transitions -18.5 -9 18.5 9 ns ns t eopr1 t eopr2 eop width at receiver must reject as eop must accept as eop 40 82 ns ns 9.3.2 reset timing ac characteristics rstin# t rst figure 9.5 reset timing
W9968CF publication release date: may 1999 - 73 - revision a2 table 9.5 reset timing symbol parameter conditions min. max. unit t rst reset pulse width 100 ns 9.3.3 clock ac characteristics t high t low t cyc 0.8 v 1.5 v 2.0 v figure 9.6 clock waveform table 9.6 clock ac characteristics symbol parameter conditions min. max. unit 1/t cyc oscillator frequency viclk frequency smclk frequency 11.988 5 47.88 12.012 30 48.12 mhz mhz mhz t h igh oscillator clock high time viclk clock high time smclk clock high time 33 5 8.3 50 12.5 ns ns ns t low oscillator clock low time viclk clock low time smclk clock low time 33 5 8.3 50 12.5 ns ns ns 9.3.4 input video ac characteristics viclk y[7:0], uv[7:0] hs, vs t su t h 1.5 v 1.5 v 1.5 v input valid figure 9.7 input video timing
W9968CF - 74 - table 9.7 input video ac characteristics symbol parameter conditions min. max. unit t su y[7:0], uv[7:0], hs, vs setup time 6 ns t h y[7:0], uv[7:0], hs, vs hold time 4 ns 9.3.5 dram interface ac characteristics smclk md[15:0] t su t h 1.5 v 1.5 v 1.5 v input valid figure 9.8 dram interface input timing smclk output delay t val 1.5 v 1.5 v figure 9.9 dram interface output timing table 9.8 dram interface ac characteristics symbol parameter conditions min. max. unit t su md[15:0] setup time 0 ns t h md[15:0] hold time 7 ns t h md[15:0], ma[10:0], ba, ras[1:0]#/cs[1:0]#, cas[1:0]#/dqm[1:0], oe#/cke, we#, sras#, scas# 2 7 ns
W9968CF publication release date: may 1999 - 75 - revision a2 9.3.6 eeprom interface ac characteristics scl sda in t su.sta t low t hd.sta t high t aa t dh t hd.dat t su.dat sda out t buf t su.sto figure 9.10 eeprom interface timing table 9.9 eeprom interface ac characteristics symbol parameter conditions min. max. unit f scl scl clock frequency 100 khz t low clock pulse width low 4.7 m s t high clock pulse width high 4.0 m s t aa clock low to data out valid 0.1 4.5 m s t buf time the bus must be free before a new transmission can start 4.7 m s t hd.sta start hold time 4.0 m s t su.sta start set-up time 4.7 m s t hd.dat data in hold time 0 m s t su.dat data in set-up time 200 ns t r inputs rise time 1.0 m s t f inputs fall time 300 ns t su.sto stop set-up time 4.7 m s t dh data out hold time 100 ns
W9968CF - 76 - 9.3.7 microcontroller interface ac characteristics ale a[15:8] ad[7:0] rd# ad[7:0] wr# a[7:0] d[7:0] a[7:0] d[7:0] t as t ah t dar t dda t rdh t rd t daw t wdh t wr figure 9.11 microcontroller interface timing table 9.10 microcontroller interface ac characteristics symbol parameter conditions min. max. unit t as address set-up time 5 ns t ah address hold time 5 ns t dar ale low to rd# low 10 ns t dda rd# low to data valid t mclk + 5 ns t rdh read data hold time 3 ns t rd rd# pulse width 2 t mclk ns t daw ale low to wr# low 10 ns t wdh write data hold time 5 ns t wr wr# pulse width 2 t mclk ns
W9968CF publication release date: may 1999 - 77 - revision a2 10 package spec. 0.10 0 12 0 0.004 1.60 1.00 17.40 0.80 17.20 0.60 17.00 0.063 0.039 0.685 0.031 0.677 0.023 0.669 0.50 14.10 0.25 0.25 2.87 3.40 14.00 2.72 13.90 0.10 0.15 2.57 0.10 0.555 0.010 0.010 0.113 0.134 0.551 0.107 0.020 0.547 0.004 0.006 0.101 0.004 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 12 0.783 0.787 0.791 19.90 20.00 20.10 0.905 0.913 0.921 23.00 23.20 23.40 0.055 0.071 1.40 1.80 103 128 102 65 64 39 38 1 c detail f see detail f 1 l l seating plane 1 a a y e h e d d h b e a 2 figure 10.1 128l qfp (14x20x2.75mm footprint 3.2mm) dimensions
W9968CF - 78 - 11 ordering information part number package W9968CF 128l qfp h e a d q u a r t e r s n o . 4 , c r e a t i o n r d . i i i , s c i e n c e - b a s e d i n d u s t r i a l p a r k , h s i n c h u , t a i w a n t e l : 8 8 6 - 3 - 5 7 7 0 0 6 6 f a x : 8 8 6 - 3 - 5 7 9 2 6 4 7 h t t p : / / w w w . w i n b o n d . c o m . t w / v o i c e & f a x - o n - d e m a n d : 8 8 6 - 2 - 7 1 9 7 0 0 6 t a i p e i o f f i c e 1 1 f , n o . 1 1 5 , s e c . 3 , m i n - s h e n g e a s t r d . , t a i p e i , t a i w a n t e l : 8 8 6 - 2 - 7 1 9 0 5 0 5 f a x : 8 8 6 - 2 - 7 1 9 7 5 0 2 w i n b o n d e l e c t r o n i c s ( h . k . ) l t d . r m . 8 0 3 , w o r l d t r a d e s q u a r e , t o w e r i i , 1 2 3 h o i b u n r d . , k w u n t o n g , k o w l o o n , h o n g k o n g t e l : 8 5 2 - 2 7 5 1 3 1 0 0 f a x : 8 5 2 - 2 7 5 5 2 0 6 4 w i n b o n d e l e c t r o n i c s n o r t h a m e r i c a c o r p . w i n b o n d m e m o r y l a b . w i n b o n d m i c r o e l e c t r o n i c s c o r p . w i n b o n d s y s t e m s l a b . 2 7 3 0 o r c h a r d p a r k w a y , s a n j o s e , c a 9 5 1 3 4 , u . s . a . t e l : 1 - 4 0 8 - 9 4 3 6 6 6 6 f a x : 1 - 4 0 8 - 9 4 3 6 6 6 8 n o t e : a l l d a t a a n d s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e .

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