ucc3588 preliminary description the ucc3588 synchronous step-down (buck) regulator provides accurate high efficiency power conversion. using few external components, the ucc1588 converts 5 v t o a n adjustable output ranging from 3.5vdc to 2.1vdc in 100mv steps and 2.05vdc to 1.3vdc in 50mv steps with 1% dc system accuracy. a high level of integration and novel design allow this 16-pin controller to provide a complete control solution for today?s demanding microcontroller power requirements. typical applications include on board or vrm based power conversion for intel pentium ii microprocessors, a s well as other processors from a variety of manufacturers. high efficiency is obtained through the use of synchronous rectification. the softstart function provides a controlled ramp up of the system output voltage. o vercurrent circuitry detects a hard (or soft) short o n the system output voltage and invokes a timed softstart/shutdown cycle to reduce the pwm controller on time to 5%. the oscillator frequency is externally programmed with rt and operates over a range of 50khz to 800khz. the gate drivers are low impedance to- tem pole output stages capable of driving large external mosfets. cross conduction is eliminated by fixed delay times between turn off and turn o n of the external high side and synchronous mosfets. the chip includes undervoltage lockout circuitry which assures the correct logic states at the outputs during power up and power down. (continued) 5-bit programmable output bicmos power supply controller features ? 5-bit digital-to-analog converter (dac) supports intel pentium ii ? microprocessor vid codes ? compatible with 5v or 12v systems ? 1% output voltage accuracy guaranteed ? drives 2 n-channel mosfets ? programmable frequency to 800khz ? power good ov / uv / ovp voltage monitor ? undervoltage lockout and softstart functions ? short circuit protection ? low impedance mosfet drivers ? chip disable sl us 31 1 - ju ly 19 99 4 11 15 5 6 7 8 3 16 12 9 10 1 2 14 13 ucc3588 vcc drvhi pwrgood d0 d1 d2 d3 d4 ss/enbl gnd comp vfb vsense isns drvlo rt r2 47k c5 33nf c16 10 f r1 10k c4 c3 c2 c1 ++ ++ rtn d0 d1 d2 d3 d4 r3 200k c6 220pf c7 22pf r7 15k c13 1nf r8 20k r4 3 ? r5 3 ? r6 0.003 ? c15 150 f c12 c11 c10 c8 + + rtn vout l1 1.6 h q2 irl3103 q1 irl3103 d2d1 12v in 5v in c8-c12 1500 f +++ c1-c4 1500 f + c14 150 f c9 + application diagram udg-98158
2 ucc3588 dip-16, soic-16, tssop-16 (top view) n, j, d and pw packages absolute maximum ratings supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15v gate drive current, 50% duty cycle. . . . . . . . . . . . . . . . . . 1a input voltage, v sense ,v fb , ss, command, comp . . . . . 5v input voltage, d0, d1, d2, d3, d4 . . . . . . . . . . . . . . . . . . . 6v input current, rt, comp . . . . . . . . . . . . . . . . . . . . . . . . . 5ma currents are positive into, negative out of the specified termi - nal. consult packaging section of databook for thermal limita - tions and considerations of packages. all voltages are referenced to gnd. thermal data plastic dip package thermal resistance junction to leads, jc . . . . . . . . 45c/w thermal resistance junction to ambient, ja . . . . . . 90c/w ceramic dip package thermal resistance junction to leads, jc . . . . . . . . 28c/w thermal resistance junction to ambient, ja . . . . . 120c/w standard surface mount package thermal resistance junction to leads, jc . . . . . . . . 35c/w thermal resistance junction to ambient, ja . . . . . 120c/w note: the above numbers for ja and jc are maximums for the limiting thermal resistance of the package in a standard mounting configuration. the ja numbers are meant to be guidelines for the thermal performance of the device and pc-board system. all of the above numbers assume no ambi- ent airflow, see the packaging section of unitrode product data handbook for more details. rt 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 vcc drvlo drvhi gnd pwrgood vfb comp vsense isns ss/enbl d0 d1 d2 d3 d4 connection diagrams electrical characteristics: unless otherwise stated, these specifications hold for t a = 0c to 70c. t a =t j . v cc = 12v, rt = 49k. parameter test conditions min typ max units supply current section supply current, on v cc = 12v, v rt = 2v 4.5 5.5 ma uvlo section vcc uvlo turn-on threshold 10.05 10.50 10.85 v uvlo threshold hysteresis 350 450 550 mv voltage error amplifier section input bias current v cm = 2.0v ?0.025 ?0.050 a open loop gain (note 5) 77 db output voltage high i comp = ?500 a 3.5 3.6 v output voltage low i comp = +500 a 0.2 0.5 v output source current v vfb = 2v, v command =v comp = 2.5v ?400 ?500 a output sink current v vfb = 3v, v command =v comp = 2.5v 5 10 ma this device is available in 16- pin surface mount, plastic and ceramic dip, tssop packages, and 20 pin surface mount. the ucc3588 is specified for operation from 0c to +70c. description (cont.) pvcc vcc rt drvlo drvhi gnd pgnd pwrgood isns vsense n/c d1 d2 ss/enbl n/c d0 d4 d3 vfb 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 comp soic-20 (top view) dw package
3 ucc3588 electrical characteristics: unless otherwise stated, these specifications hold for t a = 0c to 70c. t a =t j . v cc = 12v, rt = 49k. parameter test conditions min typ max units oscillator/pwm section initial accuracy 0c 4 ucc3588 electrical characteristics: unless otherwise stated, these specifications hold for t a = 0c to 70c. t a =t j . v cc = 12v, rt = 49k. parameter test conditions min typ max units gate drivers (drvhi, drvlo) section output high voltage i gate = 100ma, v cc = 12v 10.8 11.5 v output low voltage i gate =? 100ma, v cc = 12v 0.5 0.8 v driver non-overlap time (drvhi? to drvlo+) (note 3) 90 120 150 ns driver non-overlap time (drvlo? to drvhi+) (note 3) 50 80 120 ns driver rise time 3nf capacitive load 80 100 ns driver fall time 3nf capacitive load 80 100 ns current limit section start of quick charge to shutdown threshold v isns =v sense + 75mv, c ss = 10nf, (note 4) (note 5) 50 s current limit threshold voltage v threshold =v isns ?v vsense 40 54 70 mv isns input bias current ?8 ?12 ?16 a note 1: this percentage is measured with respect to the ideal command voltage programmed by the v id (d0,....,d4) pins and ap - plies to all dac codes from 1.3 to 3.5v. note 2: reference and error amplifier offset trimmed while the voltage amp is set in unity gain mode. note 3: deadtime delay is measured from the 50% point of drvhi falling to the 50% point of drvlo rising, and vice-verse. note 4: this time is dependent on the value of c ss . note 5: guaranteed by design. not 100% tested in production. 10 8 7 6 5 4 3 dac ovp ov/uv + ? 9 1 softstart current limit block over- current 2 11 osc 16 r s q vref 15 12 turn on delay turn on delay anti cross- conduction 13 14 v cc uvlo 10.5v vbias voltage amplifier comp vfb d4 d3 d2 d1 d0 ss/enbl isns vsense pwrgood rt gnd vcc drvhi drvlo command ?3% command +3% vsense duty=1 duty=0 shutdown pwm comp. command shutdown to vref shutdown + + ?+ ? block diagram udg-98152
5 ucc3588 comp: (voltage amplifier output) the system voltage compensation network is applied between comp and vfb. d0, d1, d2, d3, d4: these are the digital input control codes for the dac. the dac is comprised of two ranges set by d4, with d0 representing the least significant bit (lsb) and d3, the most significant bit (msb). a bit is set low by being connected the pin to gnd; a bit is set high by floating the pin. each control pin is pulled up to ap - proximately 6v by an internal pull-up. if one of the low voltage codes is commanded on the dac inputs, the out - puts will be disabled. the outputs will also be disabled for all 1?s, the no cpu command. drvhi: (pwm output, mosfet driver) this output pro - vides a low impedance totem pole driver. use a series resistor between this pin and the gate of the external mosfet to prevent excessive overshoot. minimize cir - cuit trace length to prevent drvhi from ringing below gnd. drvhi is disabled during uvlo conditions. drvhi has a typical output impedance of 5 ? for a v cc voltage of 12v. drvlo: (synchronous rectifier output, mosfet driver) this output provides a low impedance totem pole driver to drive the low-side synchronous external mosfet. use a series resistor between this pin and the gate of the external mosfet to prevent excessive overshoot. mini- mize circuit trace length to prevent drvlo from ringing below gnd. drvlo is disabled during uvlo conditions. drvlo has a typical output impedance of 5 ? for a v cc voltage of 12v. gnd: (ground) all voltages measured with respect to ground. vcc should be bypassed directly to gnd with a 0.1f or larger ceramic capacitor. the timing capacitor discharge current also returns to this pin, so the lead from the oscillator timing to gnd should be as short and direct as possible. isns: (current limit sense input) a resistance con - nected between this sense connection and vsense sets up the current limit threshold (54mv typical voltage threshold). pwrgood: this pin is an open drain output which is driven low to reset the microprocessor when vsns rises above or falls below its nominal value by 8.5%(typ). the on resistance of the open-drain switch is no higher than 470 ? . this output should be pulled up to a logic level voltage and should be programmed to sink 1ma or less. rt: (oscillator charging current) this pin is a low im - pedance voltage source set at ~1.25v. a resistor from rt to gnd is used to program the internal pwm oscilla - tor frequency. the equation for r t follows: () r fpf t = ? ? ? ? ? ? ? ? ? ? 1 67 2 800 . (1) ss/enbl: (soft start/shut down) a low leakage capaci - tor connected between ss and gnd will provide a softstart function for the converter. the voltage on this capacitor will slowly charge on start-up via an internal current source (10 a typ.) and ultimately clamp at ap - proximately 3.7v. the output of the voltage error ampli - fier (comp) tracks this voltage thereby limiting the controller duty ratio. if a short circuit is detected, the clamp is released and the cap on ss charges with a 100 a (typ) current source. if the ss voltage exceeds 4.2v, the converter shuts down, and the 100 a current source is switched off. the ss cap will then be dis- charged with a 2.5 a (typ) current sink. when the volt- age on ss falls below 0.5v, a new ss cycle is started. the equation for softstart time follows: t c a ss ss = ? ? ? ? ? ? 37 10 . . (2) shutdown is accomplished by pulling ss/sd below 0.5v. vcc: (positive supply voltage) this pin is normally con - nected to a 12v 10% system voltage. the ucc1588 will commence normal operation when the voltage on vcc exceeds 10.5v (typ). bypass vcc directly to gnd with a 0.1f (minimum) ceramic capacitor to supply current spikes required to charge external mosfet gate capaci - tances. vfb: (voltage amplifier inverting input) this is normally connected to a compensation network and to the power converter output through a divider network. vsense: (direct output voltage connection) this pin is a direct kelvin connection to the output voltage used for over voltage, under voltage, and current sensing. pin description
6 ucc3588 figure 1 shows a synchronous regulator using the ucc3588. it accepts +5v and +12v as input, and deliv - ers a regulated dc output voltage. the value of the out - put voltage is programmable via a 5-bit dac code to a value between 1.3v and 3.5v. the example given here is for a 12a regulator, running from a 10% tolerance source, and operating at 300khz. the design of the power stage is straightforward buck regulator design. assuming an output noise requirement of 50mv, and an output ripple current of 20% of full load, the value of the output inductor should be calculated at the highest input voltage and lowest output voltage that the regulator is likely to see. this insures that the ripple current will decrease as the input voltage and output volt - age differential decreases. the minimum duty cycle, min , should also be calculated under this condition. 1) the current sense resistor is chosen to allow current limit to occur at 1.4 times the full load current. () r v i mv a m trip out 6 14 50 16 8 3 = ? == . . ? (3) 2) to properly approximate the full load duty cycle oper - ating range, assumptions are made regarding the mosfets? rds on , and the output inductor?s dc resis - tance. q1 and q2 are irf3103s, each with an rds on of 0.014 ? . the output inductor is allowed to dissipate one watt under full load, giving a dc resistance of 6.9m ? , and r6 is 3m ? . the resulting duty cycle at the operating extremes is then: () () () () min .. . = +?+ + = +? = virrdsr v out lo out on in hi 6 1 8 12 0 024 55 0 379 . (4) () () () () max .. . = +?+ + = +? = virrdsr v out hi out on in lo 6 3 5 12 0 024 45 0 842 . (5) 3) the value of the output inductor is chosen at the worst case ripple current point. application information 4 11 15 5 6 7 8 3 16 12 9 10 1 2 14 13 ucc3588 vcc drvhi pwrgood d0 d1 d2 d3 d4 ss/enbl gnd comp vfb vsense isns drvlo rt r2 47k c5 33nf c16 10 f r1 10k c4 c3 c2 c1 ++ ++ rtn d0 d1 d2 d3 d4 r3 200k c6 220pf c7 22pf r7 15k c13 1nf r8 20k r4 3 ? r5 3 ? r6 0.003 ? c15 150 f c12 c11 c10 c8 + + rtn vout l1 1.6 h q2 irl3103 q1 irl3103 d2 d1 12v in 5v in c8-c12 1500 f +++ c1-c4 1500 f + c14 150 f c9 + application diagram udg-98158
7 ucc3588 () () () () l vv t i in hi out lo s out = ?? = ?? ? min .. . . . ? 5 5 1 8 0 379 3 333 24 = 19 . h (6) four turns of #16 on a micrometals t51-52c core has an inductance of 1.9 h, has a dc resistance of 6.6m ? , and will dissipate about 1w under full load conditions. with an output inductor value of 1.9 h, the ripple current will be 1750ma under the low-input-high-output condition. 4) to meet the output noise voltage requirement, the out - put capacitor(s) must be chosen so that the ripple volt - age induced across the esr of the capacitors by the output ripple current is less than 50mv. esr mv i m out <= 50 42 ? ? (7) additionally, to meet output load transient response re- quirements, the capacitors? esl and esr must be low enough to avoid excessive voltage transient spikes. (see application note u-157 for a discussion of how to deter- mine the amount and type of load capacitance.) for this example, four sanyo mv-gx 1500 f, 6.3v capacitors will be used. the esr of each capacitor is approximately 44m ? so the parallel combination of four results in an equivalent esr of 11m ? . 5) q1 and q2 are chosen to be irf3103 n-channel mosfets. each mosfet has an rds on of approxi - mately 0.014 ? , a gate charge requirement of 50nc, and a turn off time of approximately 54ns. to calculate the losses in the upper mosfet, q1, first calculate the rms current it will be conducting. () iq i i rms out out 1 12 2 2 =+ ? ? ? ? ? ? ? (8) notice that with a higher output voltage, the duty cycle in - creases, and therefore so does the rms current. any heat sink design should take into account the worst case power dissipation the device will experience. with the highest programmable output voltage of 3.5 volts and the lowest possible input voltage of 4.5v, the rms current q1 will conduct is 10.5 amps, and the con - duction loss is () pqi rds w con q rms on 115 1 2 =?= . (9) next, the gate drive losses are found. () pqqv f w gate g in hi s 1008 =? ?= . (10) and the turn off losses are estimated as () () () pqv i tff w toff inhi dpk s 1056 1 2 =???= . (11) the total loss in q1is the sum of the three components, or about 2.1 watts. the gate drive losses in q2 will be the same as in q1, but the turn off losses will be associated with the re - verse recovery of the body diode, instead of the turn off of the channel. this is due to the ucc3588?s delay built into the switching of the upper and lower mosfet?s drive. for example, when q1 is turned off, the turn on of q2 is delayed for about 100ns, insuring that the circuit has time to commutate and that current has begun to flow in the body diode of q2. when q2 is turned off, current is diverted from the channel of q2 into the body diode of q2, resulting in virtually no power dissipation. when q1 is turned on 100ns later however, the circuit is forced to commutate again. this time causing reverse re - covery loss in the body diode of q2 as its polarity is re- versed. the loss in the diode is expressed as: pq q v f w rr rr in hi s 2026 1 2 =? ? ? = () . (12) where q rr , the reverse recovery of the body diode, is 310nc. 100ns before the turn on of q2, and 100ns after the turn off of q2, current flows through q2?s intrinsic body di- ode. the power dissipation during this interval is: pq iv ns s w com diode out diode 2 200 333 12 1 4 0 06 1 = ?? =??= . .. (13) during the on period of q2, current flows through the rds on of the device. where the highest rms current in q1 was at the low-input-and-high-output condition, the highest rms current in q2 is found when the input is at its highest, and the output is at its lowest. the equation for the rms current in q2 is: () iq ns s i i rms out out 2 1 200 333 12 2 2 = ?? ? ? ? ? ? ? ?+ ? ? ? ? min . ? ? ? = 87 . a (14) () pqiq rds w con rms on 22 106 2 =?= . (15) the worst case loss in q2 comes to about 2.4 watts. 6) repeating the preceding procedure for various input and output voltage combinations yields a table of operat - ing conditions. application information (cont.)
8 ucc3588 7) assuming the converter?s input current is dc, the re - maining switching current drawn by q1 must come from the input capacitors. the next step then, is to find the worst case rms current the capacitors will experience. (equation 16). where i in (avg) is the average input cur- rent. repeating the above calculation over the operating range of the regulator (see table 2.) reveals that the worst case capacitor ripple current is found at low input, and at low output voltage. a sanyo mv-gx, 1500 f, 6.3v capacitor is rated to handle 1.25 amps at 105c. derating the de - sign to 70c allows the use of four capacitors, each one experiencing one fourth of the total ripple current. 8) the voltage feedback loop is next. the gain and fre - quency response of the pwm and lc filter is shown in equation 17. to compensate the loop with as high a bandwidth as practical, additional gain is added to the loop with the voltage error amplifier. application information (cont.) v in = 4.5 5.0 5.5 v out =3.5 pd q1 pd q2 pd l pd total average input duty cycle 2.2 1.5 0.95 5.1 10.50 0.84 2.1 1.6 0.95 5.2 9.5 0.76 2 1.8 0.95 5.4 8.70 0.69 v out =1.8 pd q1 pd q2 pd l pd total average input duty cycle 1.5 2.3 0.95 5.2 6.00 0.46 1.4 2.4 0.95 5.3 5.40 0.42 1.4 2.5 0.95 5.4 4.96 0.38 table 1. regulator operating conditions v in = 4.5 5.0 5.5 v out = 3.5 total input cap rms current total input cap power dissipation total power dissipation power train efficiency 4.4 0.21 5.1 0.89 5.2 0.29 5.3 0.88 5.6 0.34 5.4 0.87 v out =1.8 total input cap rms current total input cap power dissipation total power dissipation power train efficiency 6 0.39 5.2 0.81 5.9 0.39 5.3 0.8 5.8 0.37 5.4 0.8 table 2. regulator operating conditions -60 -50 -40 -30 -20 -10 0 10 20 0.1 1 10 100 1000 frequency (khz) gain (db) vin = 4.5v vin = 5.5v -180 -90 0 90 180 0.1 1 10 100 1000 frequency (khz) phase () figure 1. modulator frequency response () () () iii i i cap out in avg out in avg rms =?+ ? ? ? ? ? ? +? ? ? 2 2 2 12 1 ? (16) () () kf v v fr c flc rr pwm in ramp esr out out == +? ? ??? ++ 12 14 6 2 2 () +?+ ? ? ? ? ? ? rc l r esr out load (17)
9 ucc3588 the equation for the gain of the voltage amplifier in this configuration is: () () () () () () () () () k scrf sc r r rsccrf sc c scr ea i i = +?+ + ++?+ 11 13 2 12 1 2 1 3 2 2 (18) for good transient response, select the r f -c1 zero at 5khz. add additional phase margin by placing the r i -c3 zero also at 5khz. to roll off the gain at high frequency, selece the r2-c3 pole to be at 10khz, and the final c2- r f pole at 40khz. results are r i =20k, r f =200k, r2=15k, c1=220pf, c2=20pf, c3=1000pf. the gain- phase plots of the voltage error amplifier and the overall loop are plotted below. 9) the value of rt is given by: rt fpf k s = ? ? ? ? ? ? ? ?= 1 67 2 800 48 . ? (19) 10) the value of the soft start capacitor is given by: c t v ss ss =? 10 37 . (20) where t ss is the desired soft start time. to insure that soft start is long enough so that the con - verter does not enter current limit during startup, the minimum value of soft start may be determined by: c ci v r i v v ss out ch lim sense out in ramp ? ? ? ? ? ? ? ? ? (21) where c out is the output capacitance, ich is the soft start charging current (10 a typ), v lim is the current limit trip voltage (54mv typ), i out is the load current, v in is the 5v supply, and v ramp is the internal oscillator ramp voltage (1.85v typ). for this example, c ss must be greater than 35nf, and the resulting soft start time will be 13ms. 11) the output of the regulator is adjustable by program- ming the following codes into the d0 - d4 pins according to the table below. to program a logic zero, ground the pin. to program a logic 1, then leave the pin floating. do not tie the pin to an external voltage source. 12) a series resistor should be placed in series with the gate of each mosfet to prevent excessive ringing due to parasitic effects. a value of 3 ? to 5 ? is usually suffi- cient in most cases. additionally, to prevent pins 13 and 14 from ringing more than 0.5v below ground, a clamp schottky rectifier placed as close as possible to the ic is also recommended. application information (cont.) + ? c1 c2 c3 r2 r i r f v in v ref v out figure 3. voltage error amplifier configuration. -40 -20 0 20 40 60 0.1 1 10 100 1000 frequency (khz) gain (db) error amp vin = 4.5v vin = 5.5v figure 4. error amplifier and loop frequency response. 0 20 40 60 80 100 120 140 160 180 0.1 1 10 100 1000 frequency (khz) phase (deg) error amp vin = 4.5v vin = 5.5v figure 5. error amplifier and loop frequency response.
10 ucc3588 unitrode corporation 7 continental blvd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 application information (cont.) d4 d3 d2 d1 d0 v out 011111.3 01110 1.35 011011.4 01100 1.45 010111.5 01010 1.55 010011.6 01000 1.65 001111.7 00110 1.75 001011.8 00100 1.85 000111.9 00010 1.95 000012 00000 2.05 11111no outputs 111102.1 111012.2 111002.3 110112.4 110102.5 110012.6 110002.7 101112.8 101102.9 101013 101003.1 100113.2 100103.3 100013.4 100003.5 table 3. vid codes and resulting regulator output voltage
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