pi74lpt16501 18-bit registered transceivers 1 ps2071a 01/16/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74lpt16501 fast cmos 18-bit registered transceivers product features ? compatible with lcx? and lvt? families of products ? supports 5v tolerant mixed signal mode operation ? input can be 3v or 5v ? output can be 3v or connected to 5v bus ? advanced low power cmos operation ? excellent output drive capability: balanced drives (24 ma sink and source) ? pin compatible with industry standard double-density pinouts ? low ground bounce outputs ? hysteresis on all inputs ? industrial operating temperature range: ?40c to +85c ? multiple center pins and distributed vcc/gnd pins minimize switching noise ? packages available: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 300 mil wide plastic ssop (v) product description pericom semiconductor?s pi74lpt series of logic circuits are produced using the company?s advanced 0.6 micron cmos technology, achieving industry leading speed grades. the pi74lpt16501 is an 18-bit registered bus transceiver designed with d-type latches and flip-flops to allow data flow in transparent, latched, and clocked modes. the output enable (oeab and oeba, latch enable (leab and leba) and clock (clkab and clkba) inputs control the data flow in each direction. when leab is high, the device operates in transparent mode for a-to- b data flow. when leab is low, the a data is latched if clkab is held at a high or low logic level. the a bus data is stored in the latch/flip-flop on the low-to-high transition of clkab, if leab is low. oeab performs the output enable function on the b port. data flow from b port to a port is similar using oeba, leba and clkba. this high-speed, low power device offers a flow-through organization for ease of board layout. the pi74lpt16501 can be driven from either 3.3v or 5.0v devices allowing this device to be used as a translator in a mixed 3.3v/5.0v system. logic block diagram leab clkab oeba leba clkba oeab d c d c a 1 d c d c b 1 to 17 other channels
pi74lpt16501 18-bit registered transceivers 2 ps2071a 01/16/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product pin description pin name description oeab a-to-b output enable input oeba b-to-a output enable input (active low) leab a-to-b latch enable input leba b-to-a latch enable input clkab a-to-b clock input clkba b-to-a clock input ax a-to-b data inputs or b-to-a 3-state outputs bx b-to-a data inputs or a-to-b 3-state outputs gnd ground v cc power inputs outputs oeab leab clkab ax bx lxxx z hhxl l hhxh h hl - ll hl - hh hllx b (2) hlhx b (3) truth table (1,4) notes: 1. a-to-b data flow is shown. b-to-a data flow is similar but uses oeba, leba, and clkba. 2. output level before the indicated steady-state input condi- tions were established. 3. output level before the indicated steady-state input condi- tions were established, provided that clkab was high before leab went low. 4. h = high voltage level l = low voltage level z = high impedance - = low-to-high transition oeab leab a 0 gnd a 1 a 2 v cc a 3 a 4 a 5 gnd a 6 a 7 a 8 a 9 a 10 a 11 gnd a 12 a 13 a 14 v cc a 15 a 16 gnd a 17 oeba leba gnd clkab b 0 gnd b 1 b 2 v cc b 3 b 4 b 5 gnd b 6 b 7 b 8 b 9 b 10 b 11 gnd b 12 b 13 b 14 v cc b 15 b 16 gnd b 17 clkba gnd product pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 56-pin v56 a56
pi74lpt16501 18-bit registered transceivers 3 ps2071a 01/16/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 2.7v to 3.6v) parameters description test conditions (1) min. typ (2) max. units v ih input high voltage (input pins) guaranteed logic high level 2.2 ? 5.5 v input high voltage (i/o pins) 2.0 ? 5.5 v v il input low voltage guaranteed logic low level ?0.5 ? 0.8 v (input and i/o pins) i ih input high current (input pins) v cc = max. v in = 5.5v ? ? 1 a input high current (i/o pins) v cc = max. v in = v cc ??1a i il input low current (input pins) v cc = max. v in = gnd ? ? 1 a input low current (i/o pins) v cc = max. v in = gnd ? ? 1 a i ozh high impedance output current v cc = max. v out = 5.5v ? ? 1 a i ozl (3-state output pins) v cc = max. v out = gnd ? ? 1 a v ik clamp diode voltage v cc = min., i in = ?18 ma ? ?0.7 ?1.2 v i odh output high current v cc = 3.3v, v in = v ih or v il , v o = 1.5v (3) ?36 ?60 ?110 ma i odl output low current v cc = 3.3v, v in = v ih or v il , v o = 1.5v (3) 50 90 200 ma v oh output high voltage v cc = min. i oh = ?0.1 ma vcc-0.2 ? ? v v in = v ih or v il i oh = ?3 ma 2.4 3.0 ? v v cc = 3.0v, i oh = ?8 ma 2.4 (5) 3.0 ? v v in = v ih or v il i oh = ?24 ma 2.0 ? ? v ol output low voltage v cc = min. i ol = 0.1 ma ? ? 0.2 v v in = v ih or v il i ol = 16 ma ? 0.2 0.4 v i ol = 24 ma ? 0.3 0.5 v i os short circuit current (4) v cc = max. (3) , v out = gnd ?60 ?85 ?240 ma i off power down disable v cc = 0v, v in or v out 4.5v ? ? 100 a v h input hysteresis ? 150 ? mv maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) note: stresses greater than those listed under maximum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type . 2. typical values are at vcc = 3.3v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is guaranteed but not tested. 5. v oh = v cc ? 0.6v at rated current. storage temperature ............................................................. ?55c to +125c ambient temperature with power applied ............................ ?40c to +85c supply voltage to ground potential (inputs & vcc only) ...... ?0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) .. ?0.5v to +7.0v dc input voltage .................................................................... ?0.5v to +7.0v dc output current .............................................................................. 120 ma power dissipation .................................................................................... 1.0w
pi74lpt16501 18-bit registered transceivers 4 ps2071a 01/16/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power supply current v cc = max. v in = gnd or v cc 0.1 10 a d i cc quiescent power supply current v cc = max. v in = v cc ? 0.6v (3) 2.0 30 a ttl inputs high i ccd dynamic power supply (4) v cc = max., v in = v cc 50 75 a/ outputs open v in = gnd mhz x oe = gnd one bit toggling 50% duty cycle i c total power supply v cc = max., v in = v cc ? 0.6v 0.6 2.3 ma current (6) outputs open v in = gnd f i = 10 mh z 50% duty cycle x oe = gnd one bit toggling v cc = max., v in = v cc ? 0.6v 2.1 4.7 (5) outputs open v in = gnd f i = 2.5 mh z 50% duty cycle x oe = gnd 16 bits toggling notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device. 2. typical values are at vcc = 3.3v, +25c ambient. 3. per ttl driven input; all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current (i ccl , i cch and i ccz ) d i cc = power supply current for a ttl high input d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
pi74lpt16501 18-bit registered transceivers 5 ps2071a 01/16/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lpt16501 lpt16501a lpt16501c com. com. com. preliminary parameters description conditions (2) min (3) max min (3) max min (3) max unit t max clkab or clkba frequency c l = 50 pf ? 100 ? 150 ? 150 mhz t plh propagation delay r l = 500 w 1.5 6.5 1.5 5.1 1.5 4.6 ns t phl a x to b x or a x to b x t plh propagation delay 1.5 7.5 1.5 5.6 1.5 5.3 ns t phl leba to a x , leab to b x t plh propagation delay 1.5 8.0 1.5 5.6 1.5 5.3 ns t phl clkba to a x , clkab to b x t pzh output enable time 1.5 8.0 1.5 6.0 1.5 5.6 ns t pzl oeba to a x , oeab to b x t phz output disable time (4) 1.5 7.5 1.5 5.6 1.5 5.2 ns t plz oeba to a x , oeab to b x t su setup time high or low 4.0 ? 3.0 ? 3.0 ? ns ax to clkab, bx to clkba t h hold time high or low 0 ? 0 ? 0 ? ns ax to clkab, bx to clkba t su setup time clock high 4.0 ? 3.0 ? 3.0 ? ns high or low ax to leab, clock low 1.5 ? 1.5 ? 1.5 ? ns bx to leba t h hold time high or low 1.5 ? 1.5 ? 1.5 ? ns ax to leab, bx to leba t w leab or leba pulse width 3.0 ? 3.0 ? 3.0 ? ns high (4) t w clkab or clkba pulse width 3.0 ? 3.0 ? 3.0 ? ns high or low (4) t sk ( o ) output skew (5) ? 0.5 ? 0.5 ? 0.5 ns notes: 1. propagation delays and enable/disable times are with vcc = 3.3v 0.3v, normal range. for vcc = 2.7v, extended range, all propagation delays and enable/disable times should be degraded by 20%. 2. see test circuit and waveforms. 3. minimum limits are guaranteed but not tested on propagation delays. 4. this parameter is guaranteed but not production tested. 5. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. pi74lpt16501 switching characteristics over operating range (1) note: 1. this parameter is determined by device characterization but is not production tested. capacitance (t a = 25c, f = 1 mhz) parameters (1) description test conditions typ. max. units c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
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