unisonic technologies co., ltd m1725 cmos ic www.unisonic.com.tw 1 of 10 copyright ? 2010 unisonic technologies co., ltd qw-r502-427.a 16-bit,96khz stereo audio d/a converter ? description the utc m1725 is a complete stereo digital-to-analog output system including a 16-bit d/a conversion, a 5-level 3rd-order ? modulator, a digital interpolation f ilter, and an analog output amplifier in a small 14-pin package. the utc m1725 can be operating with from a single 5v power supply and requires minimal support circuitry. these features are ideal for set-top boxes, dvd pl ayers and a/v receivers, etc. ? features * complete stereo dac system: inte rpolation, d/a, output analog filtering * 16-bit conversion * 95db dynamic range * single +5v power supply * 16khz to 96khz multiple sampling frequencies * 8x oversampling digital filter * 256 f s /384 f s system clock * normal or i 2 s data input formats sop-14 ? ordering information ordering number package packing M1725G-S14-R sop-14 tape reel
m1725 cmos ic unisonic technologies co., ltd 2 of 10 www.unisonic.com.tw qw-r502-427.a ? pin configurations 4 3 2 1 11 12 13 14 lrcin din bckin nc nc format scki dm 7 6 5 8 9 10 cap v out r gnd v cc nc v out l ? pin description pin no pin name pin type pin description 1 lrcin i left/right clock input 2 din i serial audio data input 3 bckin i bit clock input for audio data 4 nc -- no connection 5 cap i/o common pin of analog output amp 6 v out r o right-channel analog output 7 gnd i/o ground 8 v cc i/o power supply 9 v out l o left-channel analog output 10 nc -- no connection 11 nc -- no connection 12 dm i de-emphasis control high: de-emphasis off low: de-emphasis on(44.1khz) 13 format i audio data format select high: i 2 s data format low: standard data format 14 scki i system clock input (256 f s or 384 f s )
m1725 cmos ic unisonic technologies co., ltd 3 of 10 www.unisonic.com.tw qw-r502-427.a ? block diagram serial input interface de- emphasis normal or i 2 s data input format 8x oversampling digital filter 5-level 3rd-order ? modulator 5-level 3rd-order ? modulator dac dac analog low-pass filter analog low-pass filter 256f s /384f s power supply bckin lrcin din dm format scki v cc gnd v out l v out r cap
m1725 cmos ic unisonic technologies co., ltd 4 of 10 www.unisonic.com.tw qw-r502-427.a ? absolute maximum rating ( ta=25c, unless otherwise specified) parameter symbol ratings unit power supply voltage v cc +6.5 v + v cc to+ v dd difference v d 0.1 v input logic voltage v lgc -0.3v to (v dd +0.3v) w power dissipation p d 300 mw operating temperature range t opr -25 ~ +85 c storage temperature t stg -55 ~ +125 c note: absolute maximum ratings are those values beyo nd which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? recommended operating conditions parameter symbol ratings unit power supply voltage v cc 4.5 ~ 5.5 v junction temperature t j -25 ~ +85 c storage temperature t stg -55 ~ +100 c ? thermal data parameter symbol ratings unit junction to ambient ja 70 c/w ? electrical characteristics (ta=25c, v cc =+5v, f s =44.1khz, cap=10uf, 16-bit input data, scki=384 f s , unless otherwise specified) parameter symbol test conditions min typ max unit data format data bit length 16 bits input sample rate f s 16 96 khz internal system clock frequency scki 256/384 f s digital input/output logic level ttl v ih 2 v input logic level (note1) v il 0.8 v input logic current (note1) i in 0.8 ua dynamic performance (note2) thd+n at fs (0db) f=991khz -83 -78 db thd+n at -60db f=991khz -32 db dynamic range dr f=991khz,a-weighted 90 95 db signal-to-noise ratio snr f=991khz,a-weighted 90 97 db channel separation cs f=991khz 88 95 db dc accuracy gain arror 1.0 5.0 % of fsr gain mis-match(channel-to-channel) 1.0 5.0 % of fsr bipolar zero error bze v out =v cc /2 at bpz 20 50 mv analog output output voltage v o full scale(0db) 0.62*v cc v p-p center voltage v c v cc /2 v load impedance r l ac load 10 k ? 1. pins 1, 2, 3, 12, 13: lrcin, din, bckin, dm, format (schmi tt trigger input); pin 14: scki. note: 2. dynamic performance specs are tested with 20khz lo w pass filter and thd+n specs are tested with 30khz lpf, 400hz hpf, average-mode.
m1725 cmos ic unisonic technologies co., ltd 5 of 10 www.unisonic.com.tw qw-r502-427.a ? electrical characteristics (cont.) parameter symbol test conditions min typ max unit digital filter performance passband 0.445 f s stopband 0.555 f s passband ripple 0.17 db stopband attenuation -35 db delay time t d 11.125/ f s sec internal analog filter -3db bandwidth 100 khz passband response f=20khz -0.16 db power supply requirements voltage range v cc 4.5 5 5.5 v supply current i q 13 18 ma power dissipation p d 65 90 mw
m1725 cmos ic unisonic technologies co., ltd 6 of 10 www.unisonic.com.tw qw-r502-427.a ? typical applications circuit
m1725 cmos ic unisonic technologies co., ltd 7 of 10 www.unisonic.com.tw qw-r502-427.a ? timing diagrams 1.4v 1.4v 1.4v lrckin bckin din t bckh t cy t bckl t bl t lb t dh t ds t cy bckin pulse cycle time 100ns t bckh bckin pulse width high 50ns t bckl bckin pulse width low 50ns t bl bckin rising edge to lrcin edge 30ns t lb lrcin edge to bckin rising edge 30ns t ds din set up time 30ns t dh din hold time 30ns figure 1.audio data input timing figure 2.normal data input timing
m1725 cmos ic unisonic technologies co., ltd 8 of 10 www.unisonic.com.tw qw-r502-427.a ? timing diagrams (cont.) left right msb lsb 0 1 2 13 14 15 1/f s lrcin bckin din msb lsb 0 1 2 13 14 15 14 15 figure 3. i 2 s data input timing 2.0v 0.8v t sckil t sckih scki t sckih system clock pulse width high 13ns t sckil system clock pulse width low 13ns figure 4. system clock timing
m1725 cmos ic unisonic technologies co., ltd 9 of 10 www.unisonic.com.tw qw-r502-427.a ? functional description system clock the system clock (scki) must be either 256 f s or 384 f s , where f s is the audio sampling frequency (lrcin),typically 32khz, 44.1khz or 48khz. the system clock is used to operate the digital filter and the noise shaper. timing conditions for scki are shown in figure4 . m1725 includes a system clock detection circuit which auto-matically detects the frequency, either 256 f s or 384 f s . the system clock should be synchronized with lrcin,but m1725 can compensate for phase differences. if the phase difference between lrcin and system clock is greater than 6 bit clocks (bckin), the synchronization is performed automatically. the analog outputs are forced to a bipolar zero state (vcc/2) during the synchronization function. the typical system clock fr equency inputs vs sampling rate for the m1725 is shown below. system clock frequency(mhz) sampling rate(lrcin)(khz) 256 f s 384 f s 32 8.192 12.288 44.1 11.2896 16.934 48 12.288 18.432 input data format m1725 can accept input data in either normal (msb-first, right-justified) or i 2 s format by applying low or high voltage level on format-pin. format input data format selected low normal format (msb-first, right-justified) high i2s format (philips serial data protocol) de-emphasis control dm-pin enables m1725 ?s de-emphasis function. de-emphasis operates only at 44.1khz. dm de-emphasis function selected low de-emphasis on (44.1khz) high de-emphasis off reset m1725 includes an internal power-on reset circuit. the power-on reset initializes and has an initialization period equal to 1024 system clock periods after v cc >2.2v. during the initialization period, the dac outputs are invalid, and the analog outputs are forced to vcc/2.
m1725 cmos ic unisonic technologies co., ltd 10 of 10 www.unisonic.com.tw qw-r502-427.a utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
|
