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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2004 analog devices, inc. all rights reserved. adp3415 dual mosfet driver with bootstrapping features all-in-one synchronous buck driver one pwm signal generates both drives anticross conduction protection circuitry programmable transition delay zero-crossing synchronous drive control synchronous override control undervoltage lockout shutdown quiescent current <100 a applications mobile computing cpu core power converters multiphase desktop cpu supplies single-supply synchronous buck converters standard-to-synchronous converter adaptations functional block diagram vcc bst drvh sw dly gnd drvl adp3415 sd drvlsd in overlap protection circuit uvlo vcc general description the adp3415 is a dual mosfet driver optimized for driving two n-channel fets that are the two switches in the nonisolated synchronous buck power converter topology. each driver size is optimized for performance in notebook pc regulators for cpus in the 20 a range. the high-side driver can be boots trapped atop the switched node of the buck converter as needed to drive the upper switch and is designed to accommo date the high voltage slew rate associated with high performance, high frequency switching. the adp3415 features an overlapping protection circuit (opc); undervoltage lockout ( uvlo) that holds the switches off until the driver is assured of having sufficient voltage for proper operation; a programmable transition delay; and a synchronous drive disable pin. the quiescent current, when the device is disabled, is less than 100 a. the adp3415 is specified over the extended commercial tem perature range of 0 c to 100 c and is available in a 10- lead msop package. bst drvh sw sd in drvlsd dly gnd drvl adp3415 v dcin v out 5v from system enable control from duty ratio modulator from system state logic vcc figure 1. typical application circuit
rev. b e2e adp3415especifications 1 (t a = 0 c to 100 c, v cc = 5 v, v bst e v sw = 5 v, sd d d s s s sd sd s d sddsd drvlsd v v v vl v l v d drvlsd s drvlsd sd sd v v v vl v l v v v v vl v l v rlsdsd sd sd sd sd sddrvrdrv rdrv C C C C C C C C C C C
rev. b adp3415 e3e absolute maximum ratings * vcc to gnd . . . . . . . . . . . . . . . . . . . . . . . . . C C C C sd drvlsd d C ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 c/w jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c/w storage temperature range . . . . . . . . . . . . C sd sdrvdrvl drvlsd dls drvlsd drvl drvlsd drvl dl sd v sd drvl srd d s s
rev. b e4e adp3415 bias en bias v uvloth uvlo therm sd vtok thsd clr s r q drvh t on dly set s r q vcc dly r dly in sd drvlsd adp3415 bst drvh + d bst c bst vcc vcc v dcin q1 drvl t on dly sw drvl gnd q2 figure 2. functional block diagram in drvl tpdl drvlsd tpdh drvlsd d rvlsd figure 3. drvlsd d
rev. b adp3415 e5e in drvl drvh-sw tpdl drvl tf drvl tpdh drvh tr drvh tr drvl tf drvh tpdl drvh tpdh drvl figure 4. switching timing diagram (propagation delay referenced to 50%, rise and fall time to 10% and 90% points) in drvl sw drvh t swto crowbar act ion figure 5. switching waveformsesw node failure modeedrvl timeout
rev. b e6e adp3415etypical performance characteristics drvh drvl in vcc = 5v c load = 3nf v sw = 0v time e ns 20ns/div 2v/div tpc 1. drvh fall and drvl rise times drvl drvh in vcc = 5v c load = 3nf r dly = 40k time e ns 20ns/div 2v/div tpc 2. drvl fall and drvh rise times input voltage e v peak current e a 80 30 05 1234 70 50 0 10 vcc = 5v t a = 25 c c load = 3nf 100 90 60 40 20 high-to-low transition low-to-high transition tpc 3. input voltage vs. input current junction temperature e c time e ns 35 27 0 125 25 50 75 100 31 29 33 21 25 23 vcc = 5v c load = 3nf fa ll time 37 rise time tpc 4. drvl rise and fall times vs. temperature junction temperature e c time e ns 0 125 25 50 16 30 18 vcc = 5v c load = 3nf rise time fa ll time 75 100 28 26 24 22 20 tpc 5. drvh rise and fall times vs. temperature load capacitance e nf time e ns 40 110 3579 60 50 70 10 30 20 vcc = 5v drvh drvl 2468 t a = 25 c tpc 6. drvh and drvl rise time vs. load capacitance
rev. b adp3415 e7e junction temperature e c time e ns 52 42 22 0 125 25 50 75 100 32 27 37 47 7 17 12 vcc = 5v c load = 3nf 2 tpdl drvh tpdl drvl tpc 7. drvh and drvl propagation delay vs. temperature load capacitance e nf time e ns 52 42 22 110 3568 32 27 37 47 7 17 12 vcc = 5v t a = 25 c 24 79 drvl drvh tpc 8. drvh and drvl fall time vs. load capacitance junction temperature e c time e ns 182 142 62 0 125 25 50 75 100 102 82 122 162 2 42 22 vcc = 5v f in = 200khz open delay pin shorted to ground c load = 3nf tpc 9. tpdh drvh vs. temperature in frequency e khz supply current e ma 45 35 15 200 1200 400 600 800 1000 25 20 30 40 0 10 5 vcc = 5v t a = 25 c c load = 3nf tpc 10. supply current vs. frequency junction temperature e c supply current e ma 10.5 9.5 7.5 0 125 25 50 75 100 8.5 8.0 9.0 10.0 6.0 7.0 6.5 vcc = 5v f in = 250khz c load = 3nf tpc 11. supply current vs. temperature
rev. b e8e adp3415 theory of operation the adp3415 is a dual mosfet driver optimized for driving two n-channel fets in a synchronous buck converter topology. a single duty ratio modulation signal is all that is required to command the proper drive signal for the high-side and the low- side fets. a more detailed description of the adp3415 and its features follows. refer to the functional block diagram (figure 2). drive state input the drive state input, in, should be connected to the duty ratio modulation signal of a switch-mode controller. in can be driven by 2.5 v to 5.0 v logic. the fets will be driven so that the sw node follows the polarity of in. low-side driver the supply rails for the low-side driver, drvl, are vcc and gnd. in its conventional application, it drives the gate of the synchronous rectifier fet. when the driver is enabled, the driver drvlsd drvlsd drvlsd drvlsd drvlsd lsd drv drv drvl s drv s d drvl ss drvl s v d v d
rev. b adp3415 e9e shutdown for optimal system power management, when the output voltage is not needed, the adp3415 can be shut down to conserve power. when the sd d sd drvdrvl v l vl vvl vvl v v s d lr ss vd l d l sr rv v s sds v c q v bst gate bst = (1) where q gate is the total gate charge of the high-side fet, and v bst is the voltage droop allowed on the high-side fet drive. for example, the irfr8503 has a total gate charge of about 15 nc. for an allowed droop of 150 mv, the required bootstrap capacitance is 100 nf. use an mlc capacitor. a schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side fet. the bootstrap diode must also be able to withstand the maximum battery voltage plus 5 v. the average forward current can be estimated by iqf f avg gate max () (2) where f max is the maximum switching frequency of the controller. delay resistor selection the delay resistor, r dly , is used to add an additional delay when the low-side fet drive turns off and when the high-side drive starts to turn on. the delay resistor programs a specified additional delay besides the 20 ns of fixed delay. printed circuit board layout considerations use the following general guidelines when designing printed circuit boards: 1. trace out the high current paths and use short, wide traces to make these connections. 2. locate the vcc bypass capacitor as close as possible to the vcc and gnd pins.
rev. b e10e adp3415 outline dimensions 10-lead micro small outline package [msop] (rm-10) dimensions shown in millimeters 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba
rev. b adp3415 e11e revision history location page 1/04?data sheet changed from rev. a to rev. b. updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1/03?data sheet changed from rev. 0 to rev. a. edits to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
c01681e0e1/04(b) e12e

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