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| 5-1 key features programmable peripheral zpsd4xx family field-programmable microcontroller peripherals o complete family of field programmable microcontroller peripherals enables the user to efficiently implement a highly integrated embedded control system in a short time. the zpsd4xx family has a variety of functions such as zplds , i/o ports, power management, eprom and sram. o ?o glue-logic?user programmable interface to 8 or 16 bit microcontroller multiplexed and non-multiplexed bus. the bus control logic can directly decode control signals generated by 8031, 80196, 80186, 68hc11, 68hc16, 683xx, 16000, z80, and z8 architecture. extended address capability up to 24 bits of address. o a range of zpld (zero power pld) architectures have up to 24 macrocells, 59 inputs and 126 output product terms. the zpsd4xx includes 2 functional zplds which enable the user to efficiently implement a variety of state machines, logic functions, address decoding and control of the internal zpsd4xx functional blocks . o the zplds use a zero power cmos technology that reduces the device standby current to 5 ua typical. unused product terms are disabled to reduce operating power. o 40 i/o ports that can be individually configured by the user as standard mcu i/o ports, pld i/o, latched address outputs and special function i/o. two eight bit i/o ports can be configured as open drain outputs. o the zpsd4xx family contains eprom densities of 256 kbit, 512 kbit and 1 mbit that can be configured as 8 or 16 bit data width. the eprom is divided into 4 equal blocks that can be mapped to different address spaces. access time is 70 ns which includes address latching and decoding pld. the eprom has a low power mode that is controlled by the cmiser-bit. o the zpsd4xx family contains a 16 kbit scratch pad sram that can be configured as 8 or 16 bit data width. access time is 70 ns which includes address latching and decoding pld. the sram can be used as standby storage if standby power is supplied to the vstdby pin. switching between v cc and vstdby occurs automatically. o page logic is connected to the zplds and enables address space expansion of microcontrollers with limited address space capability. up to 16 pages are available. o a security bit prevents reading the zpsd4xx configuration, zpld and eprom contents. this inhibits copying the device on a programmer. o port a can be used as a buffered microcontroller data bus ( peripheral i/o mode) of the microcontroller bus. this provides easy access to sub-systems that require more drive on the data bus or accessing a resource that is shared by another mcu or dma controller.
zpsd4xx family 5-2 key features (cont.) o zpsd4xx standard versions are ideal for general purpose applications o zpsd4xxv versions (2.7.0 to 5.5 volt operation) are excellent for very low power applications o zpsd4xxm mask-programmable versions are ideal for code-stable, high-volume low cost applications. o low power operation of the zpsd4xxv versions is achieved by using a power management unit (pmu) that enables automatic stand-by modes in the eprom, sram, and zplds. it also disables the clock to the zpld. also available is an automatic power down mode using the ale signal. a sleep mode is also available that consumes only 1 ? standby power consumption. o package choices include 68 pin plastic (j) and ceramic (l) chip carriers. o the zpsd4xx family is supported with pc based psdsoft ms-windows compatible development tools. offering abel as a design entry method (psdabel ), an efficient fitter, address translator, magicpro programmer and a full chip simulator (silos iii from simucad ) (psdsim ) are included. portable and battery powered systems have recently become major embedded control application segments. as a result, the demand for electronic components having extremely low power consumption has increased dramatically. recognizing this need, wsi, inc. has developed a new zpsd (zero power psd) technology. zpsd products virtually eliminate the dc component of power consumption reducing it to standby levels. eliminating the dc component is the basis for the words ?ero power?in the zpsd name. zpsd products also minimize the ac power component when the chip is changing states. the result is a programmable microcontroller peripheral family that replaces at least six discrete circuit functions while drawing much less power than a single eprom. zpsd background zpsd4xx family 5-3 upon each address or logic input change to the zpsd, the device powers up from low power standby for a short time. then the zpsd consumes only the necessary power to deliver new logic or memory data to its outputs as a response to the input change. after the new outputs are stable, the zpsd latches them and automatically reverts back to standby mode. the i cc current flowing during standby mode and during dc operation is identical and is only a few microamperes. the zpsd automatically reduces its dc current drain to these low levels and does not require controlling by the csi (chip select) input. disabling the csi pin unconditionally forces the zpsd to standby mode independent of other input transitions. the only significant power consumption in the zpsd occurs during ac operation. the zpsd contains the first architecture to apply zero power techniques to memory circuit blocks as well as logic. figure 1 compares zpsd zero power operation to the operation of a discrete solution. a standard microcontroller (mcu) bus cycle usually starts with an ale (or as) pulse and the generation of an address. the zpsd detects the address transition and powers up for a short time. the zpsd then latches the outputs of the pad, eprom and sram to the new values. after finishing these operations, the zpsd shuts off its internal power, entering standby mode. the time taken for the entire cycle is less than the zpsd s ?ccess time. the zpsd will stay in standby mode if the address does not change between bus cycles (for example, looping on a single address or a halt operation). in an alternate system implementation using discrete eprom, sram and other discrete components, the system will consume operating power during the entire bus cycle. this is because the chip select inputs on the memory devices are usually active throughout the entire cycle. the ac power consumption of the zpsd may be calculated using the ale frequency. integrated power management tm operation ale discrete eprom, sram & logic address eprom access sram access eprom access i cc zpsd zpsd zpsd time figure 1. zpsd power operation vs. discrete implementation zpsd4xx family 5-4 the zpsd4xx series of field programmable microcontroller peripherals represent a major advance in the evolution of programmable peripherals. they combine an innovative architecture with state of the art technology to provide user programmability (logic, functions, memory), flexibility, high integration, optimum performance, and low power . for example, the psd413a2 can implement a full peripheral subsystem and has the following features: o two zplds with a total of 59 inputs, 126 product terms outputs, 24 macrocells and 24 i/o pins. o 40 individually programmable i/o pins that are divided into 5 ports. o 4-bit page register for external memory addressing o 1 mbit eprom consisting of four 256 kbit blocks. o 16 kbit of standby sram that can automatically switch into standby mode. o power management unit with automatic standby and sleep modes. o security mode. figure 2 is a top level block diagram of the zpsd4xx. refer to table 1 and other sections for details on functionality, dc/ac specifications, packages and ordering information. at the core of the zpsd4xx are zplds dedicated to the functions they perform: o decoding zpld (dpld) o general purpose zpld (gpld) both zplds receive the same inputs through the zpld bus and are differentiated by their output destinations. the decoder pld (dpld) has as its main function to perform address space decoding for the internal i/o ports, four blocks of eprom, standby sram and peripheral mode of port a. the address decoding can be based on any address input, control signal (rd, psen, etc.) and page logic. address inputs originate from either the microcontroller interface (adio port) or other i/o ports for additional decoding. the dpld also supports special requirements of 8031 architecture based designs that need to store data in the eprom or execute programs from the sram. the general purpose pld (gpld) is a general purpose zpld that can be used to implement state machines and logic . the gpld has up to 59 inputs, 118 product terms, 24 flexible macrocells and 24 i/o pins that are connected to ports a, b and e. the gpld can also decode the microcontroller address bus and generate chip selects to external peripherals or memories. the zplds are designed to consume minimum power using zero power design techniques. a configuration bit (turbo bit), that can be set by the mcu, will automatically place the zplds into standby if no inputs are changing. any unused product terms will be turned off during programming and will not consume any power in the system. the zpsd4xx has 40 i/o pins that are divided into 5 ports. each i/o pin can be individually configured to provide many functions. ports a, b and e have the capability to be configured as standard mcu i/o ports, gpld i/o, or latched address outputs for multiplexed address/data controllers. ports c and d are standard i/o ports that can also be configured as zpld inputs or as a data bus for microcontrollers with a non-multiplexed bus. the zpsd4xx can easily interface with no ?lue-logic?to a variety of 8 and 16-bit microcontrollers with a multiplexed or non-multiplexed bus. all of the control signals are connected to the two zplds enabling the user to generate timing and decoding signals for external peripherals. for controllers that do not have a reset output, the zpsd4xx can generate a reset output based on its reset input. this input includes hysteresis. general description zpsd4xx family 5-5 prog. bus intrf adio port prog. port prog. port port c prog. port port d control rd, wr ad0 ?ad15 pc0 ?pc7 pd0 ?pd7 clkin clkin page reg. zpld input bus global config. & security port a power manager unit vstdby pa0 ?pa7 prog. port port b pb0 ?pb7 prog. port port e pe0 ?pe7 address/data/control bus port a macrocells port b macrocells port e macrocells (note 2) 27pt (note 1) (note 1) 80pt 11pt clkin 256k 1m bit eprom 16 k bits sram i/o decoder eprom selects sram select peripheral selects macrocell feedback or port input csiop general pld (gpld) 24 macrocells decode pld (dpld) figure 2. zpsd4xx block diagram notes: 1. zpld input bus e a1 = 36 + clock = 37 inputs e a2 + 58 + clock = 59 inputs 2. port e macrocells available on a2 versions only. zpsd4xx family 5-6 general description (cont.) the zpsd4xx contains eprom and scratchpad sram. the eprom densities are 256 kbit, 512 kbit and 1 mbit and are divided into four blocks. each block can be located in a different address location. the access time of the eprom includes the address latching and dpld decoding. the 16 kbit standby sram may be used as an extension of the microcontroller sram and also to store backup information that is necessary after a system power down. backup power to the sram is supplied by the vstdby pin. switching between v cc and vstdby occurs automatically when v cc power is removed. a four bit page register enables easy access to the i/o section, eprom and sram for microcontrollers with limited address space . the page register outputs are connected to all zplds and can be used to page external devices as well as the internal zpsd4xx functional units. a power management unit (pmu) in the zpsd4xx enables the user to control the power consumption on selected functional blocks based on system requirements. for microcontrollers that do not generate a chip select input (csi) to the peripheral device, the pmu includes an automatic power down unit (apd) that will turn off the zpsd4xx (into standby or sleep mode) based on inactivity of the ale. the polarity of ale inactivity can be defined by the user. in addition to standby mode, the zpsd4xx includes a sleep mode that will reduce the power consumption to 1 ?. the zpsd4xx family is supported by the wsi-psd development system (psdsoft, see figure 3) which runs under ms-windows on the pc. design entry is done using psdabel which creates a minimized logic implementation. psdabel also provides logic simulation of the zpld. the zpsd4xx desired configuration is entered using a simple windows based menu. the psdcompiler, which consists of a fitter and address translator, generates an object file from the psdabel and mcu code files. the object file can be down loaded to a programmer (magicpro , data i/o or other third party) or to psdsim (silos iii logic simulator) providing full chip simulation. the zpsd4xx standard versions include up to 1 mb of eprom, 16 kbit sram, decode pld (dpld), general purpose pld (gpld), and five 8-bit i/o ports. they are ideal for general purpose embedded systems applications. the zpsd4xxv low-voltage, low-power versions operate down to 2.7 volts and feature sleep mode current of only 1 microamp (typical). the zpsd4xxm mask-programmable versions deliver the lowest cost zpsd4xx solution. see the masked-psd ordering information chapter in this databook for the mask-programmable zpsd4xxm ordering procedure. references in this document to zpsd4xx versions are generic and also specifically include any ?on-v?products (zpsd4xx, zpsd4xxm, and zpsd4xxrm). references to zpsd4xxv versions include zpsd4xxv and zpsd4xxvm products. references to zpsd4xxm versions include zpsd4xxm and zpsd4xxvm products. zpsd4xx family 5-7 figure 3. psdsoft development tools psdsilos iii silosiii chip simulation psd programmer magicpro chip programming psd compiler (zpld fitting, address translation) ms ?windows editor: .abl file psdabel zpld description (state machine, decoding) psd configuration chip configuration third party programmers code file zpsd4xx family 5-8 zpsd4xx family there are 12 unique devices in the psd4xx family. the part classifications are based on zpld configuration and size, eprom size, and data bus width. the features of each part are listed in table 1. part bus dpld + gpld i/o pmu eprom sram # bit inputs product registered pins k bit k bit terms macrocells 401a1 x8/x16 37 113 8 40 yes 256 16 411a1 x8 37 113 8 40 yes 256 16 402a1 x8/x16 37 113 8 40 yes 512 16 412a1 x8 37 113 8 40 yes 512 16 403a1 x8/x16 37 113 8 40 yes 1024 16 413a1 x8 37 113 8 40 yes 1024 16 401a2 x8/x16 59 126 24 40 yes 256 16 411a2 x8 59 126 24 40 yes 256 16 402a2 x8/x16 59 126 24 40 yes 512 16 412a2 x8 59 126 24 40 yes 512 16 403a2 x8/x16 59 126 24 40 yes 1024 16 413a2 x8 59 126 24 40 yes 1024 16 table 1. zpsd4xx product matrix note: pmu = power management unit. zpsd4xx family 5-9 pin name pin function type function descriptions adio0 ?adio15 address/data bus i/o 1. address/data bus, multiplexed bus mode 2. address bus, non-multiplexed bus mode rd multiple names i multiple functions 1. read 1. read signal 2. e 2. e signal (clock) 3. ds 3. data strobe signal 4. lds 4. low byte data strobe wr multiple names i multiple functions 1. wr 1. write signal 2. r/w 2. read-write signal 3. wrl 3. low byte write signal csi chip select input i active low, select zpsd4xx standby mode if high. reset reset input i reset i/o ports, zpld/macrocells, and configuration registers. active low. clkin input clock i clock input to zpld macrocells, zpld array and apd counter. connect to ground if clock input not used. pa0 ?pa7 i/o port a i/o multiple functions 1. i/o port 2. zpld/macrocell i/o port 3. latched address outputs (pa0 ?pa7) ? (a0 ?a7) 4. high address inputs (a16 ?a23) pb0 ?pb7 i/o port b i/o multiple functions 1. i/o port 2. zpld/macrocell i/o port 3. latched address outputs (pb0?b7) ? (a0 a7) or (a8?15) pc0 ?pc7 i/o port c i/o multiple functions cmos 1. i/o port or 2. zpld input port * od 3. latched address outputs (pc0 ?pc7) ? (a0 a7) 4. data port (d0 ?d7, non-multiplexed bus) pd0 ?pd7 i/o port d i/o multiple functions cmos 1. i/o port or 2. zpld input port * od 3. latched address outputs (pd0?d7) ? (a0 a7) or (a8?15) 4. data port (d8 d15, non-multiplexed bus) * available only in zpsd4xxa2 series. table 2. zpsd4xx pin descriptions the following table describes the pin names and pin functions of the zpsd4xx. pins that have multiple names and/or functions are defined by user configuration. zpsd4xx family 5-10 pin name pin function type function descriptions pe0 port pe, pin 0 i/o multiple functions 1. bhe 1. high byte enable, 16 bit data 2. psen 2. read program memory, 8031 signal 3. wrh 3. write high data byte 4. uds 4. upper data strobe 5. siz0 5. byte enable, 68300 signal 6. pe0 6. i/o pin 7. pe0 7. zpld i/o pin 8. pe0 8. latched address out ?a0 pe1 port pe, pin 1 i/o multiple functions 1. ale 1. address strobe 2. pe1 2. i/o pin 3. pe1 3. zpld i/o pin 4. pe1 4. latched address out ?a1 pe2 port pe, pin 2 multiple functions 1. pe2 i/o 1. i/o pin 2. pe2 2. zpld i/o pin * 3. pe2 3. latched address out ?a2 pe3 port pe, pin 3 multiple functions 1. pe3 i/o 1. i/o pin 2. pe3 2. zpld i/o pin * 3. pe3 3. latched address out ?a3 pe4 port pe, pin 4 multiple functions 1. pe4 i/o 1. i/o pin 2. pe4 2. zpld i/o pin * 3. pe4 3. latched address out ?a4 pe5 port pe, pin 5 multiple functions 1. pe5 i/o 1. i/o pin 2. pe5 2. zpld i/o pin * 3. pe5 3. latched address out ?a5 pe6 port pe, pin 6 multiple functions 1. pe6 i/o 1. i/o pin 2. pe6 2. zpld i/o pin * 3. pe6 3. latched address out ?a6 pe7 port pe, pin 7 multiple functions 1. apd clk 1. automatic power down clock input 2. pe7 i/o 2. i/o pin 3. pe7 3. zpld i/o pin * 4. pe7 4. latched address out ?a7 vstdby vstdby i sram power pin for standby operation (battery backup) v cc v cc iv cc power pin gnd gnd i ground pin * available only in zpsd4xxa2 series. table 2. zpsd4xx pin descriptions (cont.) zpsd4xx family 5-11 general description the zpld block has 2 embedded pld devices: o dpld the address decoding pld, generating select signals to internal i/o or memory blocks. o gpld the general purpose pld provides 8 registered and combinatorial programmable macrocells for general or complex logic implementation; dedicated to user application. figure 4 shows the architecture of the zpld. the pld devices all share the same input bus. the true or complement of the 37 input signals are fed to the programmable and-array. names and sources of the input signals are shown in table 3. the pb signals, depending on user configuration, can either be macrocell feedbacks or inputs from port b. key features o 2 embedded zpld devices o 8 registered and 8 combinatorial macrocells o combinatorial/registered outputs o maximum 113 product terms o programmable output polarity o user configured register clear/preset o user configured register clock input o 37 inputs o accessible via 16 i/o pins o power saving mode o uv-erasable the zpsd4xxa1 zpld block the zpsd4xx architecture zpsd4xx consists of five major functional blocks: o zpld block o bus interface o i/o ports o memory block o power management unit the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. the chip configurations are specified by the user in the psdsoft development software. other configurations are specified by setting up the appropriate bits in the configuration registers during run time. the zpld block the zpsd4xx series devices provide two zpld configurations. the zpld in the zpsd4xxa1 devices has 8 registered macrocells, 8 combinatorial macrocells, and up to 113 product terms. the zpsd4xxa2 has a full function zpld with 24 registered macrocells and up to 126 product terms. zpsd4xx family 5-12 figure 4. zpld block diagram page reg. adio port pmu csi rd/ e/ds pe1 (psen/bhe) pe0 (ale/as) wr / r_w reset clkin pgr0 ?3 a8 ?a15 a0, a1 and array and array dpld es0 ?es3 rs0 csiop psel0 ?psel1 8 i /o macrocells pa 8 i /o macrocells pb (note 1) 80 pt pb0 ?pb7 pa0 ?pa7 prog. port port a prog. port port b dpld gpld zpld input bus (decoding pld) (general purpose pld) note 1: a1 = 25 pt on port a a2 = 27 pt on port a zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-13 signal name from pa0 ?pa7 port a inputs or macrocell pa feedback pb0 ?pb7 port b inputs or macrocell pb feedback pe0 ?pe1 port e inputs (signals ale, psen/bhe) pgr0 ?pgr3 page mode register a8 ?a15, a0, a1 mcu address lines rd/e/ds mcu bus signal wr/r_w mcu bus signal clkin input clock reset reset input csi csi input (ored with power down from pmu) table 3. zpld input signals zpsd4xxa1 zpld block (cont.) the dpld the dpld is used for internal address decoding generating the following eight chip select signals: o es0 e es3 eprom selects, block 0 to block 3 o rs0 sram block select o csiop i/o decoder chip select o psel0 e psel1 peripheral i/o mode select signals the i/o decoder enabled by the csiop generates chip selects for on-chip registers or i/o ports based on address inputs a[7:0]. as shown in figure 5, the dpld consists of a large programmable and array. there are a total of 37 inputs and 8 outputs. each output consists of a single product term. although the user can generate select signals from any of the inputs, the select signals are typically a function of the address and page register inputs. the select signals are defined by the user in the abel file (psdabel). the address line inputs to the dpld include a0, a1 and a8 ?a15. if more address lines are needed, the user can bring in the lines through port a to the dpld. zpsd4xx family 5-14 the gpld the structure of the general purpose pld consists of a programmable and array and 2 sets of i/o macrocells. the array has 37 input signals, same as the dpld. from these inputs, ?nded?functions are generated as product term inputs to the macrocells. the i/o macrocell sets are named after the i/o ports they are linked to, e.g., the macrocells connected to port b are named pb macrocells. the pb macrocells are registered macrocells with d-type flip-flops, where pa consists of combinatorial macrocells. pa macrocell structure figure 6 shows the pa macrocell block, which consists of 8 identical combinatorial macrocells. each macrocell output can be connected to its own i/o pin on port a. there is one user programmable global product term that is output from the gpld s and array which is shared by all the macrocells in port a: o pa.oe enable or tri-state port a output pins the circuit of a pa macrocell is shown in figure 7. there are 4 product terms from the gpld s and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o gpld input use port a pin as dedicated input o gpld output use port a pin as dedicated output zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-15 figure 5. dpld logic array pa0 ?pa7 (8) (8) (2) (10) (3) (1) (1) (inputs) pb0 ?pb7 pe0 ?pe1 (4) pgr0 ?pgr3 a8 ?a15, a0, a1 csi, clkin reset rd/e/ds wr /r_w es0 es1 es2 es3 rs0 csiop psel0 psel1 4 eprom block selects ram select i /o decoder select peripheral i /o selects dpld inputs = 37 dpld outputs = 8 (ale, psen/bhe) zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-16 figure 6. pa macrocell block diagram and array mc0 pa0 mc1 pa1 mc7 pa7 macro. out pa0 input macro. out pa1 input macro. out pa7 input pt [ 2:0 ] pa0 pt [ 2:0 ] pa1 pt [ 2:0 ] pa7 pa.oe port a i/o cells pa macrocell zpld bus zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-17 figure 7. pa macrocell pt pt pt pt and array polarity select pld in select mux pa .oe pt0 pt1 pt2 pai note: i = 7 to 0 macro . out i/o pin pai port a internal address/data bus pai input zpld bus zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-18 port b macrocell structure figure 8 shows the pb macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port b. the two inputs, clkin and macro-rst, are used as clock and clear inputs to all the macrocells. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pb macrocell is shown in figure 9. there are 10 product terms from the gplds and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o registered output select output from d flip flop. o combinatorial output select output from or gate. o gpld input use port b pin as dedicated input. o gpld output use port b pin as dedicated output. o gpld i/o use port b pin as bidirectional pin. o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to a port b pin, port b can be configured to perform other user defined i/o functions. each d flip flop in the macrocells has its own dedicated asynchronous clear, preset and clock input. the signals are defined as follow: o preset active only if defined by a product term (pbi.pr) o clear two selectable inputs: reset input and/or user defined product term (pbi.re) o clk two selectable inputs ? clkin input or user defined product term (pbi.clk). the macrocell is operated in synchronous mode if the clock input is clkin, and is in asynchronous mode if the clock is a product-term clock defined by the user. figure 10 shows the input/output path of a pb macrocell to the port pin with which it is associated. if the port pin is specified as a pb output pin in the psdsoft, the mux in the i/o port cell selects the pb macrocell as an output of the port pin. the output enable signal to the buffer in the i/o cell can be controlled by a product term from the and array. if the port pin is specified as a zpld input pin, the mux in the pb macrocell selects the port input signal to be one of the 61 signals in the zpld input bus. zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-19 the zpld power management the zpld implements a zero power mode, which provides considerable power savings for low to medium frequency operations. to enable this feature, the zpld turbo bit in the power management mode register 0 (pmmr0) has to be turned off. if none of the inputs to the zpld are switching for a time period of 90ns, the zpld puts itself into zero power mode and the current consumption is minimal. the zpld will resume normal operation as soon as one or more of the inputs change state. two other features of the zpld provide additional power savings: 1. clock disable: users can disable the clock input to the zpld and/or macrocells,thereby reducing ac power consumption. 2. product term disable: unused product terms in the zpld are disabled by the psdsoft software automatically for further power savings. the zpld power configuration is described in the power management unit section. zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-20 figure 8. pb macrocell block diagram and array macro .out pb0 .oe pb0 ?input macro .out pb1 .oe pb1 input macro .out pb7 .oe pb7?input ptb0 ? [ 0 . . 5 ] pb0 .pr pb0 .re pb0 .oe pb0 .clk pb0 ptb1 ? [ 0 . . 5 ] pb1 .pr pb1 .re pb1 .oe pb1 .clk pb1 ptb7 ? [ 0 . . 5 ] pb7 .pr pb7 .re pb7 .oe pb7 .clk pb7 clkin macro ?rst port b i/o cells pb macrocell mc0 mc1 mc7 pb0 pb1 pb7 zpld bus zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-21 figure 9. pb macrocell dq pt pt pt pt pt pt pt pt pt pt and array polarity select comb /reg select c pr mux pld in select mux clk select mux pbi pbi .oe pbi .pr pt0 pt1 pt2 pt3 pt4 pt5 pbi .clk pbi .re macro rst clkin macro . out i /o pin pbi port b internal address /data bus pbi ?input zpld bus zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-22 figure 10. pb macrocell input/output port dq psd4xx fig 5 and array pt polarity select cl ck pr control clk select mux pt clock pt output enable (oe) pt reset pts pt clear macro_rst global clock port pin comb./reg. select gpld macrocell output mux mux mux pcr dq wr direction register dq wr d g q ale pdr port input input output address a[0-7] or a[8-15] gpld output gpld macrocell i/o port cell internal address/data/control bus zpld input bus clkin zpsd4xxa1 zpld block (cont.) zpsd4xx family 5-23 the zpsd4xxa2 zpld block key features o 2 embedded zpld devices o 24 macrocells o combinatorial/registered outputs o maximum 126 product terms o programmable output polarity o user configured register clear/preset o user configured register clock input o 59 inputs o accessible via 24 i/o pins o power saving mode o uv-erasable general description the zpld block has 2 embedded pld devices: o dpld the address decoding pld, generating select signals to internal i/o or memory blocks. o gpld the general purpose pld provides 24 programmable macrocells for general or complex logic implementation; dedicated to user application. figure 11 shows the architecture of the zpld. the pld devices all share the same input bus. the true or complement of the 59 input signals are fed to the programmable and-array. names and source of the input signals are shown in table 4. the pa, pb, pe signals, depending on user configuration, can either be macrocell feedbacks or inputs from port a, b or e. zpsd4xx family 5-24 page reg. adio port prog. port port c prog. port port d pmu csi rd/ e/ds wr / r_w reset clkin pgr0 ?3 a8 ?a15 a0, a1 pc0 ?pc7 pd0 ?pd7 and array and array and array dpld es0 ?es3 rs0 csiop psel0 ?psel1 8 i /o macrocells pa 8 i /o macrocells pb 8 i /o macrocells pe 27 pt 80 pt 11 pt pe0 ?pe7 pb0 ?pb7 pa0 ?pa7 prog. port port a prog. port port b prog. port port e dpld gpld zpld input bus (decoding pld) (general purpose pld) zpsd4xxa2 zpld block (cont.) figure 11. zpsd4xxa2 zpld block diagram zpsd4xx family 5-25 signal name from pa0 ?pa7 port a inputs or macrocell pa feedback pb0 ?pb7 port b inputs or macrocell pb feedback pe0 ?pe7 port e inputs or macrocell pe feedback pc0 ?pc7 port c inputs pd0 ?pd7 port d inputs pgr0 ?pgr3 page mode register a8 ?a15, a0, a1 mcu address lines rd/e/ds mcu bus signal wr/r_w mcu bus signal clkin input clock reset reset input csi csi input (ored with power down from pmu) table 4. zpld input signals the dpld the dpld is used for internal address decoding generating the following eight chip select signals: o es0 e es3 eprom selects, block 0 to block 3 o rs0 sram block select o csiop i/o decoder chip select o psel0 e psel1 peripheral i/o mode select signals the i/o decoder enabled by the csiop generates chip selects for on-chip registers or i/o ports based on address inputs a[7:0]. as shown in figure 12, the dpld consists of a large programmable and array. there are a total of 59 inputs and 8 outputs. each output consists of a single product term. although the user can generate select signals from any of the inputs, the select signals are typically a function of the address and page register inputs. the select signals are defined by the user in the abel file (psdabel). the address line inputs to the dpld include a0, a1 and a8 ?a15. if more address lines are needed, the user can bring in the lines through port a to the dpld. zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-26 figure 12. dpld logic array pa0 ?pa7 (8) (8) (8) (8) (8) (4) (10) (3) (1) (1) (inputs) pb0 ?pb7 pe0 ?pe7 pc0 ?pc7 pd0 ?pd7 pgr0 ?pgr3 a8 ?a15, a0, a1 csi, clkin reset rd/e/ds wr /r_w es0 es1 es2 es3 rs0 csiop psel0 psel1 4 eprom block selects ram select i /o decoder select peripheral i /o selects dpld inputs : 59 dpld outputs : 8 zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-27 the gpld the structure of the general purpose pld consists of a programmable and array and 3 sets of i/o macrocells. the array has 59 input signals, same as the dpld. from these inputs, ?nded?functions are generated as product term inputs to the macrocells. the i/o macrocell sets are named after the i/o ports they are linked to, e.g., the macrocells connected to port a are named pa macrocells. the 3 sets of macrocells, pa, pb and pe, are similar in structure and function. figure 13 shows the output/input path of a gpld macrocell to the port pin with which it is associated. if the port pin is specified as a gpld output pin in psdsoft, the mux in the i/o port cell selects the gpld macrocell as an output of the port pin. the output enable signal to the buffer in the i/o cell can be controlled by a product term from the and array. if the port pin is specified as a zpld input pin, the mux in the gpld macrocell selects the port input signal to be one of the 61 signals in the zpld input bus. port a macrocell structure figure 14 shows the pa macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port a. there are 3 user programmable global product terms output from the gpld s and array which are shared by all the macrocells in port a: o pa.oe enable or tri-state port a output pins o pa.pr preset d flip flop in the macrocells o pa.re reset/clear d flip flop in the macrocells two other inputs, clkin and macro-rst, are used as clock and clear inputs to the d flip flop. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pa macrocell is shown in figure 15. there are 6 product terms from the gpld s and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o registered output select output from d flip flop o combinatorial output select output from or gate o gpld input use port a pin as dedicated input o gpld output use port a pin as dedicated output o gpld i/o use port a pin as bidirectional pin o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to a port a pin, port a can be configured to perform other user defined i/o functions. the two global product terms assigned for asynchronous clear (pa.re) and preset (pa.pr) are mainly for proper pa macrocell initialization. the macrocell flip-flop can also be cleared during reset by macro-rst, if such an option is chosen. the clock source is always the input clock clkin. zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-28 dq psd4xx fig. 18 and array pt polarity select cl ck pr control clk select mux pt clock pt output enable (oe) pt reset pts pt clear macro_rst global clock port pin comb./reg. select macrocell output mux mux mux pcr dq wr direction register dq wr d g q ale pdr port input input output address a[0-7] or a[8-15] gpld output latch qd latch only on port a gpld macrocell i/o port cell internal address/data/control bus zpld input bus figure 13. gpld macrocell input/output port zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-29 figure 14. pa macrocell block diagram and array mc0 pa0 mc1 pa1 mc7 pa7 macro. out pa0 input macro. out pa1 input macro. out pa7 input pt [ 2:0 ] pa0 pt [ 2:0 ] pa1 pt [ 2:0 ] pa7 pa.pr pa.re pa.oe clkin macro rst port a i/o cells pa macrocell zpld bus zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-30 figure 15. zpsd4xxa2 pa macrocell dq pt pt pt pt pt pt and array polarity select pld in select c pr mux mux pa .oe pa.pr pt0 pt1 pt2 pa .re pai macro rst note: i = 7 to 0 clkin macro . out i/o pin pai port a comb / reg select internal address/data bus pai input zpld bus zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-31 port b macrocell structure figure 16 shows the pb macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port b. the two inputs, clkin and macro-rst, are used as clock and clear inputs to all the macrocells. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pb macrocell is shown in figure 17. there are 10 product terms from the gpld s and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o registered output select output from d flip flop. o combinatorial output select output from or gate. o gpld input use port b pin as dedicated input. o gpld output use port b pin as dedicated output. o gpld i/o use port b pin as bidirectional pin. o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to a port b pin, port b can be configured to perform other user defined i/o functions. each d flip flop in the macrocells has its own dedicated asynchronous clear, preset and clock input. the signals are defined as follow: o preset active only if defined by a product term (pbx.pr) o clear two selectable inputs: reset input or user defined product term (pbx .re) o clk two selectable inputs ? clkin input or user defined product term (pbx.clk). the macrocell is operated in synchronous mode if the clock input is clkin, and is in asynchronous mode if the clock is a product-term clock defined by the user. zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-32 figure 16. zpsd4xxa2 pb macrocell block diagram and array macro .out pb0 .oe pb0 ?input macro .out pb1 .oe pb1 input macro .out pb7 .oe pb7?input ptb0 ? [ 0 . . 5 ] pb0 .pr pb0 .re pb0 .oe pb0 .clk pb0 ptb1 ? [ 0 . . 5 ] pb1 .pr pb1 .re pb1 .oe pb1 .clk pb1 ptb7 ? [ 0 . . 5 ] pb7 .pr pb7 .re pb7 .oe pb7 .clk pb7 clkin macro ?rst port b i/o cells pb macrocell mc0 mc1 mc7 pb0 pb1 pb7 zpld bus zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-33 dq pt pt pt pt pt pt pt pt pt pt and array polarity select comb /reg select c pr mux pld in select mux clk select mux pbi pbi .oe pbi .pr pt0 pt1 pt2 pt3 pt4 pt5 pbi .clk pbi .re macro rst clkin macro . out i /o pin pbi port b internal address /data bus pbi ?input note: i = 7 to 0 zpld bus figure 17. zpsd4xxa2 pb macrocell zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-34 port e macrocell structure figure 18 shows the pe macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port e. there are 3 user programmable global product terms output from the gpld s and array which are shared by all the macrocells in port e: o pe.oe enable or tri-state port pe output pins o pe.pr preset d flip flop in the macrocells o pe.re reset/clear d flip flop in the macrocells two other inputs, clkin and macro-rst, are used as clock and clear inputs to the d flip flop. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pe macrocell is shown in figure 19. there is only one product term from the gpld s and array as input to the macrocell. users can select the polarity of the output and configure the macrocell to operate as: o registered output select output from d flip flop o combinatorial output select output from or gate o gpld input use port e pin as dedicated input o gpld output use port e pin as dedicated output o gpld i/o use port e pin as bidirectional pin o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to port e pin, port e can be configured to perform other user defined i/o functions. if pins pe0 and pe1 are used as bus control signal inputs (ale, psen/bhe), the corresponding macrocells' feedbacks are disabled. the bus control signals are connected to the zpld input bus. the two global product terms assigned for asynchronous clear (pe.re) and preset (pe.pr) are for proper pe macrocell initialization. the macrocell flip-flop can also be cleared during reset by macro-rst as an option. the clock source is always the input clock clkin. zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-35 the zpld power management the zpld implements a zero power mode, which provides considerable power savings for low to medium frequency operations. to enable this feature, the zpld turbo bit in the power management mode register 0 (pmmr0) has to be turned off. if none of the inputs to the zpld are switching for a time period of 90ns, the zpld puts itself into zero power mode and the current consumption is minimal. the zpld will resume normal operation as soon as one or more of the inputs change state. two other features of the zpld provide additional power savings: 1. clock disable: users can disable the clock input to the zpld and/or macrocells, thereby reducing ac power consumption. 2. product term disable: unused product terms in the zpld are disabled by the psdsoft software automatically for further power savings. the zpld power configuration is described in the power management unit section. zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-36 and array mc0 pe0 mc1 pe1 mc7 pe 7 macro .out pe0 ?input macro .out pe1 ?input macro .out pe7?input pt pe0 pt pe1 pt pe7 pe .pr pe .re pe .oe clkin macro ?rst port e i/o cells pe macrocell zpld bus figure 18. pe macrocell block diagram zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-37 figure 19. pe macrocell dq pt pt pt pt and array polarity select pld in select c pr mux mux pe .oe pe .pr pt pe .re pei macro rst note: i = 7 to 0 clkin macro .out i/o pin pei port e internal address/data bus pei input comb / reg select zpld bus zpsd4xxa2 zpld block (cont.) zpsd4xx family 5-38 zpsd4xx family bus interface the bus interface is very flexible and can be configured to interface to most microcontrollers with no glue logic. table 5 lists some of the bus types to which the bus interface is able to interface. multiplexed data bus bus control microcontroller width signals mux 8 wr, rd, psen, a0 8031 mux/ non-mux 8/16 r/w, e, bhe, a0 6811 mux 8/16 wr, rd, bhe, a0 80196/80186 mux 16 wrl, rd, wrh, a0 80196sp non-mux 16 r/w, lds, uds 68302 non-mux 8/16 r/w, ds, siz0, a0 68340 non-mux 16 r/w, ds, bhe, ble 68330 table 5. typical microcontroller bus types bus interface configuration the bus interface logic is user configurable. the type of bus interface is specified by the user in the psdsoft software (psd configuration). the bus control input pins have multi-function capabilities. by choosing the right configuration, the zpsd4xx is able to interface to most microcontrollers, including the ones listed in table 5. in table 6, the names of the bus control input signal pins and their multiple functions are shown. for example, pin pe0 can be configured by the psd configuration software to perform any one of the five functions. examples on the interface between the zpsd4xx and some typical microcon- trollers are shown in following sections. pin pin pin pin pin pin name function function function function function 123 45 rd rd e ds lds wr wr r/w wrl pe0 bhe psen wrh uds siz0 pe1 ale ad0 a0 ble table 6. alternate pin functions zpsd4xx interface to a multiplexed bus figure 20 shows a typical connection to a microcontroller with a multiplexed bus. the adio port of the zpsd4xx is connected directly to the microcontroller address/data bus (ad0-ad15 for 16 bit bus). the ale input signal latches the address lines internally. in a read bus cycle, data is driven out through the adio port transceivers after the specified access time. the internal adio port connection for a 16 bit multiplexed bus is shown in figure 21. the adio port is in tri-state mode if none of the zpsd4xx internal devices are selected. zpsd4xx family 5-39 zpsd4xx family zpsd4xx interface to non-multiplexed bus figure 22 shows a zpsd4xx interfacing to a microcontroller with a non-multiplexed address/data bus. the address bus is connected to the adio port, and the data bus is connected to port c and/or port d, depending on the bus width. there is no need for the adio port to latch the address internally, but the user is offered the option to do so in the zpsd4xx psdsoft software. the data ports are in tri-state mode when the zpsd4xx is not accessed by the microcontroller. data byte enable microcontrollers have different data byte orientations with regard to the data bus. the following tables show how the zpsd4xx handles the byte enable under different bus configurations. even byte refers to locations with address a0 equal to ?? and odd byte as locations with a0 equal to ?? bhe a0 d7 e d0 x 0 even byte x 1 odd byte table 7. 8-bit data bus table 8. 16-bit data bus with bhe bhe a0 d15 e d8 d7 e d0 0 0 odd byte even byte 0 1 odd byte 1 0 even byte wrh wrl d15 e d8 d7 e d0 0 0 odd byte even byte 0 1 odd byte 1 0 even byte table 9. 16-bit data bus with wrh and wrl siz0 a0 d15 e d8 d7 e d0 0 0 even byte odd byte 1 0 even byte 1 1 odd byte table 10. 16-bit data bus with siz0, a0 lds uds d15 e d8 d7 e d0 0 0 even byte odd byte 1 0 even byte 0 1 odd byte table 11. 16-bit data bus with uds, lds bus interface (cont.) zpsd4xx family 5-40 zpsd4xx family figure 20. multiplexed bus, 8 or 16-bit data bus micro- controller ad ? [ 7:0 ] ad ? [ 15 : 8 ] a ? [ 15 : 8 ] a ? [ 7:0 ] a ? [ 15 : 8 ] (optional) (optional) adio port port e wr rd rst csi bhe ale port c port d port a port b psd4xx bus interface (cont.) zpsd4xx family 5-41 zpsd4xx family figure 21. adio port, 16-bit multiplexed bus interface ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 adio? adio? adio? adio? adio? adio? adio? adio? adio? adio? adio?0 adio?1 adio?2 adio?3 adio?4 adio?5 r_w ale /as psd4xx internal address bus psd4xx internal data bus latch g latch g bus interface (cont.) zpsd4xx family 5-42 zpsd4xx family figure 22. non-multiplexed, 8 or 16-bit data micro- controller d ? [ 15 : 0 ] a ? [ 15 : 0 ] d ? [ 15 : 8 ] d ? [ 7 : 0 ] a [ 23 :16 ] (optional) adio port port e wr rd rst csi bhe ale port c port d port a port b psd4xx 16-bit data only bus interface (cont.) zpsd4xx family 5-43 zpsd4xx family optional features the zpsd4xx provides two optional features to add flexibility to the bus interface: 1. address in port a can be configured as high order address (a16-a23) inputs to the zpld for eprom or other decoding. inputs are latched by ale/as if multiplexed bus is selected. other ports can be configured as address input ports for the zpld. these inputs should not be used for eprom decoding and are not latched internally. 2. address out for multiplexed bus only. latched address lines a0-a15 are available on port a, b, c or d. details on the optional features are described in the i/o port section. bus interface (cont.) bus interface examples the next four figures show the zpsd4xx interfacing with some popular microcontrollers. the examples show only the basic bus connections; some of the pin names on the zpsd4xx parts change to reflect the actual pin functions. figure 23 shows the interface to the 80c31. the 80c31 has a 16 bit address bus and an 8-bit data bus. the lower address byte is multiplexed with the data bus. the rd and wr signals are used for accessing the data memory (sram) and the psen signal is for reading program memory (eprom). the ale signal is active high and is used to latch the address internally. port c provides latched address outputs a[7:0]. ports a, b, d, and e (pe2-pe7) can be configured to perform other functions. the rstout reset to the 80c31 is generated by the zpld from the reset input. this configuration eliminates any reset race condition between the 80c31 and the zpsd4xx. figure 24 shows the 68hc11 interface, which is similar to the 80c31 except the zpsd4xx generates internal rd and wr from the 68hc11 s e and r/w signals. in figure 25, the intel 80c196 microcontroller is interfaced to the zpsd4xx. the 80c196 has a multiplexed 16-bit address and data bus. the bhe signal is used for data byte selection. ports c and d are used as output ports for latched address a[15:0]. pins pe6 and pe7 can be programmed as zpld outputs to provide the ready and buswidth control signals to the 80c196. figure 26 shows motorola s mc68331 interfacing to the zpsd4xx. the mc68331 has a 16-bit data bus and a 24-bit address bus. d15 ?d8 from the mc68331 are connected to port d, and d7 ?d0 are connected to port c. zpsd4xx family 5-44 zpsd4xx family figure 23. interfacing zpsd4xx with 80c31 ea / vp x1 x2 reset int0 int1 t0 t1 p1 . 0 p1 . 1 p1 . 2 p1 . 3 p1 . 4 p1 . 5 p1 . 6 p1 . 7 ad0 /a0 ad1/a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11/a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 rd wr reset csi clkin pe0 / psen pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txd rxd pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 31 19 18 9 12 13 14 15 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 80c31 ad [ 7:0 ] ad [ 7:0 ] reset rstout clock reset clock psd4xx rd wr psen ale 1 2 3 4 5 6 7 8 bus interface (cont.) zpsd4xx family 5-45 zpsd4xx family xt ex reset irq xirq modb pa0 pa1 pa2 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl ad0 /a0 ad1/a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11/a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 e r/w reset csi clkin pe0 pe1 / ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda e as r/w pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 8 7 17 19 18 2 34 33 32 43 44 45 46 47 48 49 50 52 51 31 30 29 28 27 42 41 40 39 38 37 36 35 9 10 11 12 13 14 15 16 20 21 22 23 24 25 3 5 4 6 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 68hc11 psd4xx ad [ 7 : 0 ] ad [ 7 : 0 ] clock reset e ale r/w clock ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 reset figure 24. interfacing zpsd4xx with 68hc11 bus interface (cont.) zpsd4xx family 5-46 zpsd4xx family figure 25. interfacing zpsd4xx with 80c196 x1 nmi ready cde buswidth reset ach0 / p0 . 0 ach1 / p0 . 1 ach2 / p0 . 2 ach3 / p0 . 3 ach4 / p0 . 4 ach5 / p0 . 5 pcs6 / p0 . 6 pcs7/ p0 . 7 p2 . 0 / txd p2 . 1 / rxd p2 . 2 / exint p2 . 3 / t2clk p2 . 4 / t2rst p2 . 5 / pwm p2 . 6 / t2up ?dn p2 . 7/ t2cap hsi .0 hsi .1 hsi .2 / hso .4 hsi .3 / hso .5 vref angnd ea? ad0 /a0 ad1 /a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11 /a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 rd wr reset csi clkin pe0 / bhe pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby x2 p3 . 0 /ad0 p3 . 1 /ad1 p3 . 2 /ad2 p3 . 3 /ad3 p3 . 4 /ad4 p3 . 5 /ad5 p3 . 6 /ad6 p3 . 7/ad7 p4 . 0 /ad8 p4 . 1 /ad9 p4 . 2 /ad10 p4 . 3 /ad11 p4 . 4 /ad12 p4 . 5 /ad13 p4 . 6 /ad14 p4 . 7/ad15 rd wr bhe ale inst clkout p1 .0 p1 .1 p1 .2 p1 .3 p1 .4 p1 .5 p1 .6 p1 .7 hso .0 hso .1 hso .2 hso .3 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 11 3 43 14 64 16 6 5 7 4 11 10 8 9 18 17 15 44 42 39 33 38 24 25 26 27 13 12 2 12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 61 40 41 62 63 65 59 58 57 56 55 48 47 46 50 49 44 43 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 reset d [ 15 : 0 ] d [ 15 : 0 ] reset ready buswidth rd wr bhe ale clkout psd4xx 80c196 bus interface (cont.) zpsd4xx family 5-47 zpsd4xx family figure 26. interfacing zpsd4xx with motorola 68331 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 reset dsack0 dsack1 irq1 irq2 irq3 irq4 irq5 irq6 irq7 ad0 / a0 ad1 / a1 ad2 / a2 ad3 / a3 ad4 / a4 ad5 / a5 ad6 / a6 ad7 / a7 ad8 / a8 ad9 / a9 ad10 / a10 ad11 / a11 ad12 / a12 ad13 / a13 ad14 / a14 ad15 / a15 ds r / w reset csi clkin pe0 / siz0 pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 cs6 a20 cs7 a21 cs8 a22 cs9 a23 cs10 as r w ds siz0 siz1 clkout csboot br cs0 bg cs1 bgack cs2 fc0 cs3 fc1 cs4 fc2 cs5 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 d0 111 d1 110 d2 109 d3 108 d4 105 d5 104 d6 103 d7 102 d8 100 d9 99 d10 98 d11 97 d12 94 d13 93 d14 92 d15 91 68 89 88 77 76 75 74 73 72 71 d0 111 d1 110 d2 109 d3 108 d4 105 d5 104 d6 103 d7 102 d8 100 d9 99 d10 98 d11 97 d12 94 d13 93 d14 92 d15 91 68 89 88 77 76 75 74 73 72 71 90 20 21 22 23 24 25 26 27 30 31 32 33 35 36 37 38 41 42 121 122 123 124 125 82 79 85 81 80 66 112 113 114 115 118 119 120 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 ale rw ds siz0 clkout d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 reset d [ 15 : 0 ] d [ 15 : 0 ] a [ 18 : 0 ] a [ 18 : 0 ] reset psd4xx mc68331 bus interface (cont.) zpsd4xx family 5-48 there are 5 programmable 8-bit i/o ports: port a, port b, port c, port d and port e. these ports all have multiple operating modes, depending on the configuration. some of the basic functions are providing input/output for the zpld, or can be used for standard i/o. each port pin is individually configurable, thus enabling a single 8-bit port to perform multiple func- tions. the i/o ports occupy 256 bytes of memory space as defined by ?siop? refer to the system configuration section for i/o register address offset. to set up the port configuration the user is required to: 1. define i/o port chip select (csiop) in the abel file. 2. initialize certain port configuration registers in the user s program and/or 3. specify the configuration in the zpsd4xx psdsoft software. 4. unused input pins should be tied to v cc or gnd. the following is a description of the operating modes of the i/o ports. the functions of the port registers are described in later sections. standard mcu i/o the standard mcu i/o mode provides additional i/o capability to the microcontroller. in this mode, the ports can perform standard i/o functions such as sensing or controlling various external i/o devices. operation options of this mode are as follows: o configuration 1. declare pins or signals which are used as i/o in the abel file. 2. set the bit or bits in the control register to "1". 3. as output port write output data to data out register set direction register to output mode 4. as input port set direction register to input mode read input from data in register the port remains an output or input port as long as the direction register is not changed. pld i/o the pld i/o mode enables the port to be configured as an input to the zpld, or as an output from the gpld macrocell. the output can be tri-stated with a control signal defined by a product term from the zpld. this mode is configured by the user in the zpsd4xx psdsoft software, and is enabled upon power up. for a detailed description, see the section on the zpld. o configuration 1. declare pins or signals in the abel file (psdsoft). 2. write logic equations in the abel file. 3. psd compiler maps the pld functions to the psd. i/o ports zpsd4xx family 5-49 zpsd4xx family i/o ports (cont.) address out for microcontrollers with a multiplexed address/data bus, the i/o ports in address-out mode are able to provide latched address outputs (a0 ?a15) to external devices. this mode of operation requires the user to: o configuration 1. declare the pins used as address line outputs in the abel file (psdsoft). 2. write ??to the corresponding bit in the control register associated with each i/o port. 3. set the direction register to output mode. address in there are two address in modes: 1. for port a - as other address line (a2-a7 and a16-a23) inputs to the dpld. additional address inputs included in the eprom decoding must come from port a. the address inputs are latched internally by ale/as if multiplexed bus is specified in psdsoft. 2. for ports c and d ? as address inputs to the zpld for general decoding, should not be used in eprom decoding. o configuration 1. declare pins or signals used as address in in the abel file (psdsoft). 2. write latch equations in the .abl file, e.g., a16.le = ale. 3. include latched address in logic equations. data port in this mode, the port is acting as a data bus port for a microcontroller which has a non-multiplexed address/data bus. the data port is connected to the data bus of the microcontroller and the adio port is connected to the address bus. o configuration select the non-multiplexed bus option in psd configuration (psdsoft). alternate function in this mode is per-pin configurable and enables the user to define pin pe7 of port e as automatic power down (apd) clk input. o configuration 1. select input functions in psd configuration. 2. psd compiler assigns pins for the selected options. zpsd4xx family 5-50 zpsd4xx family table 12. operating modes of the i/o ports table 12 summarizes the operating modes of the i/o ports. not all the functions are available to every port. port mode port a port b port c port d port e standard mcu i/o yes yes yes yes yes pld i/o yes yes input only * input only * ye s * address out yes yes yes yes yes address in yes yes ** ye s ** ye s ** data port yes yes alternate function in yes peripheral i/o yes open drain yes yes * zpsd4xxa2 only. ** for external decoding. cannot be latched by ale peripheral i/o this mode enables the microcontroller to read or write to a peripheral though port a. when there is no read/write operation, port a is tri-stated. one of the applications of peripheral i/o is in a dma based design. o configuration 1. declare the pins used as pheripheral i/o in the abel file. 2. write logic equations for psel0 and psel1. 3. write a ??to the pio bit in the vm register to activate the peripheral i/o operation. see the section on peripheral i/o for a detailed description. open drain outputs this mode enables the user to configure ports c and d pins as open drain outputs. cmos output is the default configuration. writing ??to the corresponding bit in the open drain register changes the pin to open drain output. i/o ports (cont.) zpsd4xx family 5-51 zpsd4xx family port registers there are two sets of registers per i/o port: the port configuration registers (pcr) which consist of four 8-bit registers; and the port data registers (pdr) which include three 8-bit registers. the pcr is used for setting up the port configuration, while the pdr enables the microcontroller to write or read port data or status bits. tables 13 and 14 show the names and the registers and the ports to which they belong. all the registers in the pcr and pdr are 8-bits wide and each bit is associated with a pin in the i/o port. in table 15, the lsb of the data in register of port a is connected to pin pa0, and the msb is connected to pa7. this pin configuration also applies to other registers and ports. for example, in the direction register of port a, writing a hex value of 07 to the register configures pins pa0 ?pa2 as output pins, while pa3 ?pa7 remain as input pins. registers can be accessed by the microcontroller during normal read/write bus cycles. the i/o address offset of the registers are listed in the system configuration section. i/o ports (cont.) register name port write/read control register a,b,c,d,e write/read direction register a,b,c,d,e write/read open drain register c,d write/read pld ?i/o register a,b,e read table 13. port configuration registers (pcr) register name port read/write data in register a,b,c,d,e read data out register a,b,c,d,e write/read macrocell out register a,b,e read table 14. port data registers (pdr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pa7 pin pa6 pin pa5 pin pa4 pin pa3 pin pa2 pin pa1 pin pa0 pin table 15. data in register e port a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pa7 pin pa6 pin pa5 pin pa4 pin pa3 pin pa2 pin pa1 pin pa0 pin = 0 = 0 = 0 = 0 = 0 = 1 = 1 = 1 direction register e port a ( example: pins pa0 e pa2 as output, pa3 e pa7 as input) zpsd4xx family 5-52 control register this register is used in both standard mcu i/o mode and address out modes. for setting a standard mcu i/o mode, a ??must be written to the corresponding bit in the register. writing a ??to the register is required for the address out mode. the register has a default value of ??after reset. direction register this register is used to control the direction of data flow in the i/o ports. writing a ??to the corresponding bit in the register configures the port to be an output port, and a ??forces the port to be an input port. the i/o configuration of the port pins can be determined by reading the direction register. after reset, the pins are in input mode. open drain this register determines whether the output pin driver of ports c or d is a cmos driver or an open drain driver. writing a ??to the register selects a cmos driver, while a ??selects an open drain driver. pld e i/o register this is a read only status register. reading a "1" indicates the corresponding pin is configured as a pld pin. a "0" indicates the pin is an i/o pin. data in register this register is used in the standard mcu i/o mode configuration to read the input pins. data out register this register holds the output data in the standard mcu i/o mode. the contents of the register can also be read. macrocell out register this register enables the user to read the outputs of the gpld macrocell (pa, pb, and pe macrocells). i/o register address offset the i/o register can be accessed by the microcontroller during its normal read/write bus cycle. the address of a register is defined as: csiop + register address offset the csiop is the base address that is defined in the abel file and occupies a 256 byte space. the register address offset lies within this 256 byte space. tables 16 and 16a are the address offset of the registers. i/o ports (cont.) table 16a. register address offset (for 16-bit motorola microcontrollers in 16-bit mode. use table 16 if 8-bit mode is selected.) zpsd4xx family 5-53 address offset register name port a port b port c port d port e data in 00 01 10 11 20 control 02 03 12 13 22 data out 04 05 14 15 24 direction 06 07 16 17 26 open drain 18 19 pld ?i/o 0a 0b 2a macrocell out 0c 0d 2c (zpsd4xxa2) table 16. register address offset i/o ports (cont.) address offset register name port a port b port c port d port e data in 01 00 11 10 21 control 03 02 13 12 23 data out 05 04 15 14 25 direction 07 06 17 16 27 open drain 19 18 pld ?i/o 0b 0a 2b macrocell out 0d 0c 2d (zpsd4xxa2) zpsd4xx family 5-54 port a e functionality and structure port a is the most flexible of all the i/o ports. it can be configured to perform one or more of the following functions: o standard mcu i/o mode o pld i/o o address out ? latched address lines a[0-7] are assigned to pins pa[0-7]. o address in ? input port for other address lines, inputs can be latched by ale. o peripheral i/o figure 27 shows the structure of a port a pin. if the pin is configured as an output port, the multiplexer selects one of its three inputs as output. if the pin is configured as an input, the input connects to : 1. data in register as input in standard mcu i/o mode or 2. pa macrocell as pld input or 3. pa macrocell through a latch latched by ale, as address in input. port b e functionality and structure port b is similar to port a in structure. it can be configured to perform one or more of the following functions: o standard mcu i/o mode o pld i/o o address out ? address lines a[0-7] for 8-bit multiplexed bus or address lines a[8-15] for 16-bit multiplexed bus are assigned to pins pb[0-7]. figure 28 shows the structure of a port b pin. if the pin is configured as an output port, the multiplexer selects one of its three inputs as output. if the pin is configured as input, the input connects to : o data in register as input in standard mcu i/o mode or o pb macrocell as pld input i/o ports (cont.) zpsd4xx family 5-55 zpsd4xx family figure 27. port a pin structure mux pdr port a pin dq d g q dq control gpld input pcr ale wr ale pa . oe gpld output ale wr internal address / data bus data out address pcr dir. reg. latch a [ 0 ?7 ] i/o ports (cont.) zpsd4xx family 5-56 zpsd4xx family i/o ports (cont.) figure 28. port b pin structure mux pdr port b pin dq d g q dq control gpld input pcr wr ale pb .oe gpld output ale wr data out address pcr dir. reg. a[0 ?7] or a[8 ?15] internal address / data bus zpsd4xx family 5-57 zpsd4xx family i/o ports (cont.) port c and port d e functionality and structure ports c and d are identical in function and structure and each can be configured to perform one or more of the following operating modes: o standard mcu i/o mode o pld input ? direct input to zpld (zpsd4xxa2 only) o address out ? latched address outputs port c: a[0-7] are assigned to pins pc[0-7] port d: a[0-7] for 8-bit multiplexed bus or a[8-15] for 16-bit multiplexed bus are assigned to pins pd[0-7] o data port port c: d[0-7] for 8-bit non-multiplexed bus port d: d[8-15] for 16-bit non-multiplexed bus o open drain ? select cmos or open drain driver figures 29 and 30 show the structure of a port c or d pin. if the pin is configured as an output port, the multiplexer selects one of the two inputs as output. if the pin is configured as an input, the input connects to : o data in register as input in the standard mcu i/o mode or o zpld input (zpsd4xxa2 only) port e e functionality and structure port e can be configured to perform one or more of the following functions: o standard mcu i/o mode o pld i/o (zpsd4xxa2 only) o address out ? latched address lines a[0-7] are assigned to pins pe[0-7] o alternate function in ? in this mode, the inputs to port e pins are: pe0 bhe or psen or wrh or uds or siz0 pe1 ? ale pe7 apd clk :clock input for automatic power down counter figure 31 shows the structure of a port e pin. the control logic block selects one of four sources through the multiplexer for pin output. if the pin is configured as an input, the input goes to: o data in register as input in standard mcu i/o mode or o pe macrocell as pld input (zpsd4xxa2 only) or o alternate function in zpsd4xx family 5-58 zpsd4xx family figure 29. port c pin structure mux pdr port c pin dq d g q dq control gpld input ** pcr wr ale ale wr data * data out address pcr dir. reg. d [ 0 7 ] a [ 0 7 ] internal address / data bus *data bus d [0 ?] is not connected to gpld?nput. **gpld?nput is available on a2 versions only. i/o ports (cont.) zpsd4xx family 5-59 zpsd4xx family figure 30. port d pin structure mux pdr port d pin dq d g q dq control gpld input ** pcr wr ale ale wr data * data out address pcr dir. reg. d [8 ?5] a [ 0 7 ] or a [8 ?5] internal address / data bus *data bus d [8?5] is not connected to gpld?nput. **gpld?nput is available on a2 versions only. i/o ports (cont.) zpsd4xx family 5-60 zpsd4xx family figure 31. port e pin structure mux pdr port e pin dq d g q dq control gpld input * alt func. in pcr wr ale pe .oe gpld output ale wr data out address pcr dir. reg. internal address / data bus *gpld?nput is available on a2 versions only. i/o ports (cont.) zpsd4xx family 5-61 zpsd4xx family the zpsd4xx provides eprom memory for code storage and sram memory for scratch pad usage. chip selects for the memory blocks come from the dpld decoding logic and are defined by the user in the psdsoft software. figure 32 shows the organization of the memory block. eprom the zpsd4xx provides three zero power eprom densities: 256k bit, 512k bit or 1m bit. the eprom is divided into four 8k, 16k or 32k byte blocks. each block has its own chip select signals (es0 ?es3). the eprom can be configured as 32k x 8, 64k x 8 or 128k x 8 for microcontrollers with an 8-bit data bus. for 16-bit data buses, the eprom is configured as 16k x 16, 32k x 16 or 64k x 16. the eprom powers up only on address changes and consumes power for the necessary time to latch data on its output latches. it then powers down and remains in standby mode. sram the sram has 16k bits of memory, organized as 2k x 8 or 1k x 16. the sram is enabled by chip select signal rs0 from the dpld. the sram has a battery back-up (stby) mode. this back-up mode is invoked when the v cc voltage drops under the vstdby voltage by approximately 0.7 v. the vstdby voltage is connected only to the sram and cannot be lower than 2.7 volts. the sram powers up only on address changes and consumes power for the necessary time to latch data on its output latches. it then powers down and remains in standby mode. memory select map the eprom and sram chip select equations are defined in the abel file in terms of address and other dpld inputs. the memory space for the eprom chip select (es0 es3) should not be larger than the eprom block (8kb, 16kb, or 32kb) it is selecting. the following rules govern how the internal zpsd4xx memory selects/space are defined: o the eprom blocks address space cannot overlap o sram, internal i/o and peripheral i/o space cannot overlap o sram, internal i/o and peripheral i/o space can overlap eprom space, with priority given to sram or i/o. the portion of eprom which is overlapped cannot be accessed. the peripheral i/o space refers to memory space occupied by peripherals when port a is configured in the peripheral i/o mode. memory block zpsd4xx family 5-62 memory select map for 8031 application the 8031 family of microcontrollers has separate code memory space and data memory space. this feature requires a different memory select map. two modes of operation are provided for 8031 applications. the selection of the modes is specified in the zpsd4xx psdsoft software (psdconfiguration): o separate space mode in this mode, the psen signal is used to access code from eprom, and the rd signal is used to access data from sram. the code memory space is separated from the data memory space. o combined space mode in this mode, the eprom can be accessed by psen or rd. the eprom is used for code and data storage. the memory block's address space cannot overlap. if data and code memory blocks must overlap each other, the rd signal can be included as an additional address input in generating the eprom chip select signals (es0 ?es3). in this case the eprom access time is from the rd valid to data valid. figures 33a and 33b show the memory configuration in the two modes. in some applications it is desirable to execute program codes in sram. the zpsd4xx provides this option by enabling psen to access sram. to activate this option, the srcode bit of the vm register must be set to ??(see table 17). sram space can overlap eprom space and has priority when psen is used. memory block (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * *** ** srcode pio 1 = on 1 = on * = reserved for future use, bits set to zero. table 17. vm register zpsd4xx family 5-63 figure 32. memory block diagram (128kb eprom) es0 es1 es2 es3 16k x 8 16k x 8 1k x 8 1k x 8 16k x 8 16k x 8 16k x 8 16k x 8 16k x 8 16k x 8 sram block rs0 odd byte odd byte d [ 8 ?15 ] even byte d [ 0 ?7 ] eprom blocks memory block (cont.) zpsd4xx family 5-64 figure 33a. 8031 memory modes eprom dpld sram es0 es1 es2 es3 rs0 rd oe oe srcode en psen separate space mode memory block (cont.) figure 33b. 8031 memory modes eprom dpld sram es0 es1 es2 es3 rs0 psen rd rd oe oe srcode en psen rd combined space mode zpsd4xx family 5-65 zpsd4xx family the peripheral i/o mode is one of the operating modes of port a. in this mode, port a is connected to the data bus of peripheral devices. port a is enabled only when the microcontroller is accessing the devices, otherwise the port is tri-stated. this feature enables the microcontroller to access external devices without requiring buffers and decoders. figure 34 shows the structure of port a in the peripheral i/o mode. the memory address space occupied by the devices are defined by two signals: psel0 and psel1. the signals are direct outputs from the decoding pld (dpld). whenever any of the signals is active, the port a driver is enabled, and the direction of the data flow is deter- mined by the rd/wr signals. the peripheral i/o mode and the peripheral select signals are configured and defined in the psdsoft software (see the section on i/o port for configuration). the pio bit in the vm register (see table 17) also needs to be set to ??by the user to initialize the peripheral i/o mode. the peripheral i/o mode can be used, for example, in dma applications where the microcontroller does not support dma operations, such as tri-stating the address/data bus. figure 35 shows a block diagram of a microcontroller and zpsd4xx based design that makes use of this mode. in this application, the microcontroller has a multiplexed bus which is connected to the adio port. the c and d ports connect to the peripheral address bus and are both configured in address out mode. port a is configured in the peripheral i/o mode and is connected to the peripheral data bus. ports b and e are used to generate control signals. during normal activity, the microcontroller has access to any peripheral (memory or i/o device) through the zpsd4xx device. when there is a dma request, the microcontroller tri-states the address bus on ports c and d by writing a ??to the port direction registers. the dma controller then takes over the data and address buses after receiving acknowledgement from the microcontroller. peripheral i/o figure 34. port a in peripheral i/o mode rd psel0 psel1 d0 ?d7 wr pa0 ?pa7 zpsd4xx family 5-66 figure 35. zpsd4xx peripheral i/o configuration micro- controller ad [ 0 ?7 ] a [ 8 ?5 ] a [ 0 ?7 ] a [ 8 ?15 ] d [ 0 ?7 ] dma ack adio port port e wr rd rst csi bhe ale port c port d port a port b psd4xx memory i/o device dma controller peripheral # 1 peripheral # 2 dma req rd wr csi peripheral i/o zpsd4xx family 5-67 zpsd4xx family page register the page register is 4 bits wide and consists of four d flip flops.the outputs of the register (pgr0 ?pgr3) are connected to the input bus of the zpld. by including the four outputs as inputs to the dpld, the addressing capability of the microcontroller is increased by a factor of 16. figure 36 shows the page register block diagram. inputs to the four flip flops are connected to data bus d0-d3. the output of the register can be read by the microcontroller. the register can operate as an independent register to the microcontroller if page mode is not implemented. the zpsd4xx has a programmable security bit which offers protection from unauthorized duplication. when the security bit is set, the contents of the eprom, the zpsd4xx non-volatile configuration bits and zpld data cannot be read by eprom programmers. the security bit is set through the psdsoft software and is embedded in the compiled output file. the security bit is uv erasable and a secured part can be erased and then re-programmed. security protection figure 36. page register dpld rs0 gpld zpld es0 ?3 pgr0 pgr1 pgr2 pgr3 r/w d0 d0 ?d3 d1 d2 d3 q0 q1 q2 q3 page reg. reset zpsd4xx family 5-68 the zpsd4xx provides many power saving options. by configuring the pmmrs (power management mode registers), the user can reduce power consumption. table 18 shows the bit configuration of the pmmr0 and pmmr1. the microcontroller is able to control the power consumption by changing the pmmr bits at run time. standby mode there are two standby modes in the zpsd4xx: o power down mode o sleep mode power down mode in this mode, the internal devices are shut down except for the i/o ports and the zpld. there are three ways the zpsd4xx can enter into the power down mode: by controlling the csi input, by activating the automatic power down (apd) logic, the counter/timers, the interrupt controller and the zpld, or when none of the inputs are changing and the turbo bit is off. o the csi the csi input pin is an active low signal. when low, the signal selects and enables the zpsd4xx. the psd5xx enters into power down mode immediately when the signal turns high. this signal can be controlled by the microcontrollers, external logic or it can be grounded. the csi input turns off the internal bus buffers in standby mode. the address and control signals from the microcontroller are blocked from entering the zpld as inputs. o the apd logic the apd unit enables the user to enter a power down mode independent of controlling the csi input. this feature eliminates the need for external logic (decoders and latches) to power down the psd. the apd unit concept is based on tracking the activity on the ale pin. if the apd unit is enabled and ale is not active, the 4-bit apd counter starts counting and will overflow after 15 clocks, generating a pd (power down) signal powering down the psd. if sleep mode is enabled, then pd signal will also activate the sleep mode. immediately after ale starts pulsing the psd will get out of the power down or sleep mode. the operation of apd is controlled by the pmmr (see figure 37a). pmmr1 bit 0 selects the source of the apd counter clock. after reset the apd counter clock is connected to pe7 (apd clk) on the psd. in order to guarantee that the apd will not overflow there should be less than 15 apd clocks between two ale pulses. if clkin frequency is adequate, then it can be connected to the apd and pe7 is used for other functions. the next step is to select the ale power down polarity. usually, mcus entering power down will freeze their ale at logic high or low. by programming bit 1 of pmmr0 the power down polarity can be defined for the apd. if the apd detects that the ale is in the power down polarity for 15 apd counter clocks then the psd will enter a power down mode. to enable the apd operation, bit 2 in the pmmr0 should be set high. sleep mode the sleep mode is activated if the sleep en bit, the apd en bit, and the ale polarity bit in the pmmr are set, and the apd counter has overflowed after 15 clocks ( see figure 37). in sleep mode the zpsd4xx consumes less power than the power down mode, with typical i cc reduced to 1 ?. in this mode, the zpld still monitors the inputs and responds to them. as soon as the ale starts pulsing, the zpsd4xx exits the sleep mode. the psd access time from sleep mode is specified by t lv dv 1 . the zpld response time to an input transition is specified by t lv dv 2 . power management unit zpsd4xx family 5-69 clr clk apd counter apd clk pmmr1 - bit 0 to other circuits mux apd clear logic apd enable pmmr0 - bit 2 ale polarity pmmr0 - bit 1 ale reset apd clk clkin csi sleep enable pmmr1 - bit 1 sleep mode eprom select sram select i/o select power down pd z p l d figure 37. power management unit figure 37a. automatic power down unit (apd) flow chart apd disabled need apd clk yes yes no no reset set apd clk in pmmr1 bit 0 set ale pd polarity in pmmro bit 1 csi = "1" need sleep mode set sleep mode in pmmr1 bit 1 ale idle and 15 apd clock ale idle and 15 apd clock ?set enable apd in pmmr0 bit 2 ?set pmmr0 bit 0 ?set enable apd in pmmr0 bit 2 ?set pmmr0 bit 0 disable clocks zpld aclk, zpld rclk, tmr zpld disable clocks zpld aclk, zpld rclk, tmr zpld psd in power down mode psd in sleep mode power management unit (cont.) zpsd4xx family 5-70 apd en bit ale power ale status apd counter down polarity 0 x x not counting 1 x pulsing not counting 11 1 counting (activates standby mode after 15 clocks) 10 0 counting (activates standby mode after 15 clocks) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr clk zpld zpld zpld apd ale pd * rclk aclk turbo cmiser enable polarity 1 = off 1 = off 1 = off 1 = off 1 = on 1 = on 1 = high pmmr0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * *** ** sleep apd clk mode 1 = on 1 = clkin pmmr1 table 18. power management mode registers (pmmr0, pmmr1) table 19. apd counter operation bit 0 * = should be set to high (1) to operate the apd. bit 1 0 = ale power down (pd) polarity low. 1 = ale power down (pd) polarity high. bit 2 0 = automatic power down (apd) disable. 1 = automatic power down (apd) enable. bit 3 0 = eprom/sram cmiser is off. 1 = eprom/sram cmiser is on. bit 4 0 = zpld turbo is on. zpld is always on. 1 = zpld turbo is off. zpld will power down when inputs are not changing. bit 5 0 = zpld clock input into the array from the clkin pin input is connected. every clock change will power up the zpld when turbo bit is off. 1 = zpld clock input into the array from the clkin pin input is disconnected. bit 6 0 = zpld clock input into the the macrocell registers from the clkin pin input is connected. 1 = zpld clock input into the the macrocell registers from the clkin pin input is disconnected. bit 7 * = in the zpsd4xx should be set to high (1) bit 0 0 = automatic power down unit clock is connected to port e7 (pe7) alternate function input. 1 = automatic power down unit clock is connected to the psd clock input (clkin). bit 1 0 = sleep mode disabled. 1 = sleep mode enabled. bit 2 7 0 = reserved for future use, should be set to zero. power management unit (cont.) zpsd4xx family 5-71 zpsd4xx family power management unit (cont.) other power saving options the zpsd4xx provides additional power saving options. these options, except the sram standby mode, can be enabled/disabled by setting up the corresponding bit in the pmmr. o eprom the eprom power consumption in the psd is controlled by bit 3 in the pmmr0 ?eprom cmiser. upon reset the cmiser bit is off. this will cause the eprom to be on at all times as long as csi is enabled (low). the reason this mode is provided is to reduce the access time of the eprom by 10 ns relative to the low power condition when cmiser is on. if csi is disabled (high) the eprom will be deselected and will enter standby mode (off) overriding the state of the cmiser. if cmiser is set (on) then the eprom will enter the standby mode when not selected. this condition can take place when csi is high or when csi is low and the eprom is not accessed. for example, if the mcu is accessing the sram, the eprom will be deselected and will be in low power mode. an additional advantage of the cmiser is achieved when the psd is configured in the by 8 mode (8 bit data bus). in this case an additional power savings is achieved in the eprom (and also in the sram) by turning off 1/2 of the array even when the eprom is accessed (the array is divided internally into odd and even arrays). the power consumption for the different eprom modes is given in the dc characteristics table under i cc (dc) eprom adder. o sram standby mode the sram has a dedicated supply voltage v stby that can be used to connect a battery. when v cc becomes lower than v stby 0.6 then the zpsd4xx will automatically connect the v stby as a power source to the sram. the sram standby current (i stby ) is typically 0.5 ?. sram data retention voltage v df is 2 v minimum. o zero power zpld zpld power/speed is controlled by the zpld_turbo bit (bit 4) in the pmmr0. after reset the zpld is in turbo mode and runs at full power and speed. by setting the bit to ?? the turbo mode is disabled and the zpld is consuming zero power current if the inputs are not switching for an extended time of 70 ns. the propagation delay time will be increased by 10ns after the turbo bit is set to ??(turned off) if the inputs change at a frequency of less than 15 mhz. see page 5-108 for cmiser errata. zpsd4xx family 5-72 power management unit (cont.) port configuration pin status i/o port unchanged zpld output depend on inputs to the zpld address out undefined data port tri-stated peripheral i/o tri-stated table 20. i/o pin status during power down and sleep mode o input clock the zpsd4xx provides the option to turn off the clock inputs to save ac power consumption. the clock input (clkin) is used as a source for driving the following modules: o zpld array clock input o zpld macrocell clock flip flop o apd counter clock during power down or if any of the modules are not being used the clock to these modules should be disabled. to reduce ac power consumption, it is especially important to disable the clock input to the zpld array if it is not used as part of a logic equation. the zpld array clock can be disabled by setting pmmr0 bit 5 (zpld aclk). the zpld macrocell clock input can be disabled by setting pmmr0 bit 6 (zpld rclk). the timer clock can be disabled by setting pmmr0 bit 7 (tmr clk). the apd counter clock will be disabled automatically if power down or sleep mode is entered through the apd unit. the input buffer of the clkin input will be disabled if bits 5 ?7 pmmr0 are set and the apd has overflowed. pld pld access access typical propagation recovery time recovery standby delay time to time to current normal normal consumed operation access power normal t pd 0 no access t lv dv 40 ? down (note 1) (note 4) sleep t lv dv 2 t lv dv 3 no access t lv dv 1 5 ? (note 2) (note 3) (note 5) summary of zpsd4xx timing and standby current during power down and sleep modes notes: 1. power down does not affect the operation of the zpld. the zpld operation in this mode is based only on the zpld_turbo bit. 2. in sleep mode any input to the zpld will have a propagation delay of t lv dv 2 . 3. pld recovery time to normal operation after exiting sleep mode. an input to the zpld during the transition will have a propagation delay time of t lv dv 3 . 4. typical current consumption assuming all clocks are disabled and zpld is in non-turbo mode. 5. typical current consumption assuming all clocks are disabled. zpsd4xx family 5-73 system configuration the csiop signal, which is generated by the dpld, selects the internal i/o devices or registers. the csiop signal takes up 256 bytes of address space and is defined by the user in the psdsoft software. the following is an address offset map for the various devices relative to the csiop base address. some motorola 16-bit microcontrollers have different data bus/data byte orientation. this requires a different address offset for the internal zpsd4xx i/o devices or registers. tables 21a and 22a in this section are for this group of microcontrollers which include the m68hc16, m68302 and m683xx. register address register address name offset name offset page register e0 vm c0 pmmr1 b1 pmmr0 b0 table 21. register address offset table 21a. register address offset (for 16-bit motorola microcontrollers in 16-bit mode. use table 21 if 8-bit mode is selected.) register address register address name offset name offset page register e1 vm c1 pmmr1 b0 pmmr0 b1 zpsd4xx family 5-74 the following table is the address map offset of the i/o port registers. system configuration (cont.) table 22a. register address offset (for 16-bit motorola microcontrollers in 16-bit mode. use table 22 if 8-bit mode is selected.) address offset register name port a port b port c port d port e data in 00 01 10 11 20 control 02 03 12 13 22 data out 04 05 14 15 24 direction 06 07 16 17 26 open drain 18 19 pld ?i/o 0a 0b 2a macrocell out 0c 0d 2c (zpsd4xxa2) table 22. i/o register address offset address offset register name port a port b port c port d port e data in 01 00 11 10 21 control 03 02 13 12 23 data out 05 04 15 14 25 direction 07 06 17 16 27 open drain 19 18 pld ?i/o 0b 0a 2b macrocell out 0d 0c 2d (zpsd4xxa2) zpsd4xx family 5-75 zpsd4xx family system configuration (cont.) register name register function data in this register is used to read the input on the port pins. control a 0 ? sets the corresponding port pin in address out mode. a 1 ? sets the pin in mcu i/o mode. data out holds the output data in the mcu i/o mode. this register is used to control the data flow in the i/o ports. direction a 0 ? sets the corresponding pin as an input pin. a 1 ? sets the pin as an output pin. open drain a 0 ? sets the corresponding pin driver as a cmos driver. a 1 ? sets the pin driver as an open drain driver. pld ?i/o a read only status register; a 1 ? indicates the corresponding pin is configured as a pld pin. macrocell out this register holds the outputs of the gpld macrocells. page register a 4-bit register that supports paging. 1. configures the zpsd4xx sram to be accessed by psen vm as program space (8031 design). 2. enables the peripheral i/o mode of port a. pmmr0 power management registers; enables the zpsd4xx power down pmmr1 mode and other power saving configurations. table 23. register function zpsd4xx family 5-76 reset input the reset input to the zpsd4xx (reset) is an active low signal which resets some of the internal devices and configuration registers. the timing diagram in the ac/dc characterization section shows the reset signal timing requirement. the active low range has a minimum t1 duration. after the rising edge of reset, the zpsd4xx remains in reset during t2 range. (see figure 48). the zpsd4xx must be reset at power up before it can be used. zpld and memory during reset while the reset input is active, the zpld generates outputs as defined in the psdabel equations. the eprom and sram blocks respond to the microcontroller bus cycle during reset, but the data is not guaranteed. register values during and after reset table 24 summarizes the status of the volatile register values during and after reset. the default values of the volatile registers are ??after reset. zpld macrocell initialization the d flip flops in the macrocells in the gpld can be cleared by: o a product term (.re) defined by the user in psdabel, or o the macro-rst (reset) input, enabled and defined in psdabel. register name device reset state control port a, b, c, d, e set to ? (address out mode) data out (data or address) port a, b, c, d, e set to ?? direction port a, b, c, d, e set to ???input mode open drain port c, d set to ???cmos outputs page register page logic set to ? pmmr0, pmmr1 power management unit set to ? vm volatile memory set to ? system configuration (cont.) table 24. registers reset values port configuration reset stand-by mode port i/o input unchanged zpld output active depend on inputs to the zpld address out tri-stated not defined data port tri-stated tri-stated peripheral i/o tri-stated tri-stated table 25. i/o pin status during reset and standby mode zpsd4xx family 5-77 zpsd4xx family symbol parameter condition min max unit t stg storage temperature cldcc ?65 + 150 ? pldcc ?65 + 125 ? commercial 0 + 70 ? operating temperature industrial ?40 + 85 ? military 55 + 125 ? voltage on any pin with respect to gnd ?0.6 + 7 v v pp programming supply voltage with respect to gnd ?0.6 + 14 v v cc supply voltage with respect to gnd ?0.6 + 7 v esd protection > 2000 v absolute maximum ratings note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. range temperature commercial 0 c to +70? industrial 40 c to +85? symbol parameter condition min typ max unit v cc supply voltage all speeds 4.5 5 5.25 v v cc supply voltage zpsd4xxv versions only, all speeds 2.7 3.0 5.5 v operating range recommended operating conditions zpsd4xx family 5-78 ac/dc parameters the following tables describe the ad/dc parameters of the zpsd4xx family: o dc electrical specification o ac timing specification zpld timing combinatorial delays synchronous clock mode asynchronous clock mode microcontroller timing read timing write timing peripheral mode timing power down and reset timing following are some issues concerning the parameters presented: o in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the zpsd4xx is in each mode. also the supply power is considerably different if the zpld_turbo bit is "off" and eprom_cmiser is "on". o the ac power component gives the zpld, eprom, and sram ma/mhz specification. figure 38 shows the zpld ma/mhz as a function of the number of product terms (pt) used. o in the zpld timing parameters add the required delay when zpld_turbo is "off". o in the mcu timing specification add the required time delay when eprom_cmiser is "on". figure 38a. zpld i cc /frequency consumption (zpsd4xxa1 versions) 0 10 20 60 50 80 70 90 100 40 30 01015 5 20 25 pt100% pt25% bus frequency (mhz) i cc ?(ma) 10 turbo on turbo on turbo off turbo off 5 v 10% zpsd4xx versions see page 5-108 for cmiser errata. zpsd4xx family 5-79 figure 38b. zpld i cc /frequency consumption (zpsd4xxa2 versions) 0 20 60 80 100 120 40 01015 5 20 25 pt100% pt25% bus frequency (mhz) i cc ?(ma) turbo on turbo on turbo off turbo off figure 38c. zpld i cc /frequency consumption (zpsd4xxa1v and zpsd4xxa2v versions) 0 10 20 30 40 50 01015 5 20 25 pt100% pt25% bus frequency (mhz) i cc ?(ma) turbo on turbo on turbo off turbo off 5 v 10% zpsd4xx versions 3 v 10% zpsd4xxv versions zpsd4xx family 5-80 symbol parameter conditions min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v ih high level input voltage 4.5 v < v cc < 5.5 v 2 v cc +.5 v v il low level input voltage 4.5 v < v cc < 5.5 v 0.5 0.8 v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v il1 reset low level input voltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v ol output low voltage i ol = 20 ?, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.15 0.45 v v oh output high voltage i oh = 20 ?, v cc = 4.5 v 4.4 4.49 v i oh = 2 ma, v cc = 4.5 v 2.4 3.9 v v sby sram standby voltage 2.7 v cc v i sby sram standby current v cc = 0 v 0.5 1 a i idle idle current (v stby pin) v cc > v sby 0.1 0.1 ? v df sram data retention voltage only on v stby 2v i sb standby supply power down mode csi >v cc ?3 v (note 2) 25 50 ? current sleep mode csi >v cc ?3 v (note 3) 10 20 ? i li input leakage current v ss < v in < v cc ? ?1 1 ? i lo output leakage current 0.45 < v in < v cc ?0 5 10 ? zpld_turbo = off, i cc (dc) operating f = 0 mhz (note 4) (note 4a) supply current zpld only zpld_turbo = on, f = 0 mhz 400 700 ?/pt zpld ac base (note 4) cmiser = on eprom ac adder (8-bit bus mode) 0.8 2 ma/mhz i cc (ac) all other cases 1.8 4 ma/mhz (note 4a) cmiser = on and 1.4 2.7 ma/mhz 8-bit bus mode sram ac adder cmiser = on and 2 4 ma/mhz 16-bit bus mode cmiser = off 3.8 7.5 ma/mhz dc characteristics (5 v 10% versions) notes: 1. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc . 2. csi deselected or internal pd is active. 3. sleep mode bit is set and internal pd is active. 4. see zpld icc/frequency power consumption graph for details. 4a. i out = 0 ma. zpsd4xx family 5-81 -70 -90 -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off * unit i/o input or feedback to t pd combinatorial output port b, e 25 30 32 34 35 add 10 ns t rpd registered input to (note 5) 27 32 34 36 37 add 10 ns combinatorial output t ea input to output enable any input 25 28 30 32 33 add 10 ns t er input to output disable any input 25 28 30 32 33 add 10 ns t arp register clear or any input 27 30 32 34 35 add 10 ns preset delay t arpw register clear or preset any input 20 25 28 29 30 ns pulse width t ard array delay 16 18 20 22 24 ns combinatorial delays (5 v 10%) note: 5. zpsd4xxa1: port a and latched address from adio (a0, a1, a8 ?a15). zpsd4xxa2: port a and latched address from adio (a0, a1, a8 ?a15). ac/dc parameters e zpld timing parameters (5 v 10% versions) zpsd4xx family 5-82 -70 -90 -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off * unit maximum frequency external feedback 1/(t s + t co ) 30.30 27.03 25.00 23.81 22.22 mhz maximum frequency f max internal feedback 1/(t s +t co ?0) 43.48 37.04 33.33 31.25 28.57 mhz (f cnt ) maximum frequency pipelined data 1/(t ch + t cl ) 50.00 41.67 35.71 33.33 31.25 mhz t s input setup time any input 15 17 19 20 21 add 10 ns t h input hold time any input 00000 0ns t ch clock high time clock input 10 12 14 15 16 0 ns t cl clock low time clock input 10 12 14 15 16 0 ns t co clock to output delay clock input 18 20 21 22 24 0 ns array delay t ard for product term any macrocell 16 18 20 22 24 0 ns expansion t min minimum clock period t ch + t cl 20 24 28 29 29 0 ns synchronous clock mode (5 v 10%) * note: if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 10 ns to the timing parameters. ac/dc parameters e zpld timing parameters (5 v 10% versions) zpsd4xx family 5-83 -70 -90 -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off * unit maximum frequency external feedback 1/(t sa + t coa ) 26.32 25.00 21.74 20.41 19.61 mhz maximum frequency f maxa internal feedback 1/(t sa +t co a ?0) 35.71 33.33 27.78 25.64 24.39 mhz (f cnta ) (note 6) maximum frequency pipelined data 1/(t ch + t cl ) 41.67 41.67 35.71 33.33 31.25 mhz t sa input setup time any input 8 8 10 12 13 add 10 ns t ha input hold time any input 8 8 10 12 13 0 ns t cha clock high time any input 12 12 14 15 16 0 ns t cla clock low time any input 12 12 14 15 16 0 ns t coa clock to output any input to delay port b 30 32 36 37 38 add 10 ns t ard array delay for product term any macrocell 16 18 20 22 24 0 ns expansion t mina minimum clock period 1/f cnt 28 30 36 43 41 0 ns asynchronous clock mode (5 v 10%, note 6) * note: if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 10 ns to the timing parameters. ac/dc parameters e zpld timing parameters (5 v 10% versions) note: 6. only port b has asynchronous outputs. clock into macrocell flip flop is generated by a product term. -70 -90 -12 -15 -20 eprom_cmiser symbol parameter conditions min max min max min max min max min max on unit t lvlx ale or as pulse width 18 20 25 28 30 0 ns t avlx address setup time (note 8) 5 6 9 10 12 0 ns t lxax address hold time (note 8) 7 8 10 11 12 0 ns t avqv address valid to data valid (note 8) 70 90 120 150 200 add 10 ns t slqv cs valid to data valid 80 100 130 150 200 add 10 ns rd to data valid 8/16-bit bus (note 7) 20 32 38 40 45 0 ns t rlqv rd to data valid 8-bit bus, 8031 separate mode (note 7a) 32 38 40 45 50 0 ns t rhqx rd data hold time (note 7) 0 0 0 0 0 0 ns t rlrh rd pulse width (note 7) 30 32 35 38 40 0 ns t rhqz rd to data high-z (note 7) 22 25 30 33 35 0 ns t ehel e pulse width 30 32 35 38 40 0 ns t theh r/w setup time to enable 8 10 15 18 20 0 ns t eltl r/w hold time after enable 00 0 00 0ns in 16-bit data bus 20 30 35 38 40 0 ns address input valid to mode (note 9) t avpv address output delay in 8-bit data bus 22 32 45 48 50 0 ns mode (note 9) zpsd4xx family 5-84 notes: 7. rd timing has the same timing as psen, ds, lds, uds signals. 7a. rd and psen have the same timing for 8031 mode. 8. any input used to select an internal zpsd4xx function. 9. in multiplexed mode latched address generated from adio delay to address output on any port. read timing (5 v 10%) explanation of ac symbols for non zpld timing. example: t avlx time from address valid to ale invalid. a address l logic level low or ale t r/w c power down n reset t time d input data p port signal v valid e ? q output data x no longer a valid logic level h logic level high r wr, uds, lds, ds, iord, psen z float i interrupt s chip select microcontroller interface e ac/dc parameters (5 v 10% versions) zpsd4xx family 5-85 -70 -90 -12 -15 -20 eprom_cmiser symbol parameter conditions min max min max min max min max min max on unit t lvlx ale or as pulse width 18 20 25 28 30 ns t avlx address setup time (note 8) 5 6 9 10 12 ns t lxax address hold time (note 8) 7 8 10 11 12 ns t avwl address valid to leading edge of wr (notes 8 and 10) 18 20 25 30 35 ns t slwl cs valid to leading edge of wr (note 10) 22 25 30 35 40 ns t dvwh wr data setup time (note 10) 12 15 20 22 25 ns t whdx wr data hold time (note 10) 5 5 5 5 5 ns t wlwh wr pulse width (note 10) 18 20 25 28 30 ns t whax trailing edge of wr to address invalid (note 10) 0 0 0 0 0 ns t whpv trailing edge of wr to port output valid (note 10) 25 30 35 38 40 ns in 16-bit data bus 20 30 35 38 40 ns address input valid to mode (note 9) t avpv address output delay in 8-bit data bus 22 32 45 48 50 ns mode (note 9) write timing (5 v 10%) microcontroller interface e ac/dc parameters (5 v 10% versions) note: 10. wr timing has the same timing as e, ds, lds, uds, wrl, wrh signals. zpsd4xx family 5-86 notes: 11. any input used to select port a data peripheral mode. 12. data is already stable on port a. 13. data stable on adio pins to data on port a. -70 -90 -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t avqv (pa) address valid to data valid (note 11) 45 55 60 62 65 add 10 ns t slqv (pa) cs valid to data valid 55 55 60 62 65 add 10 ns rd to data valid (notes 7, 12) 22 26 38 45 50 0 ns t rlqv (pa) rd to data valid 8031 mode 32 38 40 45 50 0 ns t dvqv (pa) data in to data out valid 22 22 25 26 28 0 ns t qxrh (pa) rd data hold time (note 7) 00000 0ns t rlrh (pa) rd pulse width (note 7) 25 30 35 38 40 0 ns t rhqz (pa) rd to data high-z (note 7) 20 25 30 33 35 0 ns port a peripheral data mode read timing (5 v 10%) -70 -90 -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t wlqv (pa) wr to data propagation delay (note 10) 25 27 32 35 38 0 ns t dvqv (pa) data to port a data propagation delay (note 13) 22 22 25 26 28 0 ns t whqz (pa) wr invalid to port a tri-state (note 10) 20 25 30 33 35 0 ns port a peripheral data mode write timing (5 v 10%) microcontroller interface e ac/dc parameters (5 v 10% versions) zpsd4xx family 5-87 -70 -90 -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t lv dv ale access time from power down 100 120 140 150 170 add 10 ns t lv dv 1 ale or csi access time from sleep 120 150 170 200 200 0 ns t lv dv 2 zpld propagation delay in sleep mode 600 600 600 600 600 0 ns t lv dv 3 zpld recovery time after sleep mode 250 250 250 250 250 0 ns t chcl apd clock high time using pe7 10 12 14 15 16 0 ns t clch apd clock low time using pe7 10 12 14 15 16 0 ns f max apd maximum frequency using pe7 35.00 30.00 25.00 22.00 20.00 0 mhz t 1 reset active low time 150 200 250 300 300 0 ns t 2 reset high to operational device 150 200 250 300 300 0 ns power down and reset timing (5 v 10%) microcontroller interface e ac/dc parameters (5 v 10% versions) zpsd4xx family 5-88 symbol parameter conditions min typ max unit v cc supply voltage all speeds 2.7 3 5.5 v v ih high level input voltage 2.7 v < v cc < 5.5 v .7 v cc v cc +.5 v v il low level input voltage 2.7 v < v cc < 5.5 v 0.5 .3 v cc v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v il1 reset low level input voltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v ol output low voltage i ol = 20 ?, v cc = 2.7 v 0.01 0.1 v i ol = 4 ma, v cc = 2.7 v 0.15 0.45 v v oh output high voltage i oh = 20 ?, v cc = 2.7 v 2.9 2.99 v i oh = 1 ma, v cc = 2.7 v 2.4 2.6 v v sby sram standby voltage 2.7 v cc v i sby sram standby current v cc = 0 v 0.5 1 a i idle idle current (v stby pin) v cc > v sby 0.1 0.1 ? v df sram data retention voltage only on v stby 2v i sb standby supply power down mode csi >v cc ?3 v (note 2) 5 15 a current sleep mode csi >v cc ?3 v (note 3) 1 5 ? i li input leakage current v ss < v in < v cc ? ?1 1 ? i lo output leakage current 0.45 < v in < v cc ?0 5 10 ? zpld_turbo = off, i cc (dc) operating f = 0 mhz (note 4) (note 17a) supply current zpld only zpld_turbo = on, f = 0 mhz 200 400 ?/pt zpld ac base (note 4) cmiser = on eprom ac adder (8-bit bus mode) 0.4 1.0 ma/mhz i cc (ac) all other cases 0.9 1.7 ma/mhz (note 17a) cmiser = on and 0.7 1.3 ma/mhz 8-bit bus mode sram ac adder cmiser = on and 1 2 ma/mhz 16-bit bus mode cmiser = off 1.9 3.8 ma/mhz dc characteristics (zpsd4xxv versions, advance information) (3.0 v 10% versions) notes: 14. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc . 15. csi deselected or internal pd is active. 16. sleep mode bit is set and internal pd is active. 17. see zpld icc/frequency power consumption graph for details. 17a. i out = 0 ma. see page 5-108 for cmiser errata. zpsd4xx family 5-89 combinatorial delays (3.0 v 10%) ac/dc parameters e zpld timing parameters (zpsd4xxv versions, advance information) note: 18. port a and latched address from adio (a0, a1, a8 ?a15). * note: -15 available second half 1997. -15* -20 -25 zpld_turbo symbol parameter conditions min max min max min max off unit i/o input or feedback to t pd combinatorial output port b, e 43 55 80 add 20 ns t rpd registered input to (note 18) 42 55 85 add 20 ns combinatorial output t ea input to output enable any input 38 50 80 add 20 ns t er input to output disable any input 38 50 80 add 20 ns t arp register clear or preset delay any input 44 55 80 add 20 ns t arpw register clear or preset any input 29 30 60 ns pulse width t ard array delay 29 33 35 ns zpsd4xx family 5-90 synchronous clock mode (3.0 v 10%) ac/dc parameters e zpld timing parameters (zpsd4xxv versions, advance information) * * note: if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 20 ns to the timing parameters. important: some parameters for the -20 versions are affected by errata notice. refer to page 5-108. ** note: -15 available second half 1997. -15** -20 -25 zpld_turbo symbol parameter conditions min max min max min max off * unit maximum frequency external feedback 1/(t s + t co ) 17.86 28.57 11.11 mhz maximum frequency f max internal feedback (f cnt ) 1/(t s +t co ?0) 21.74 17.24 12.50 mhz maximum frequency pipelined data 1/(t ch + t cl ) 33.33 31.25 18.52 mhz t s input setup time any input 27 35 60 add 20 ns t h input hold time any input 0 0 0 0 ns t ch clock high time clock input 15 16 27 0 ns t cl clock low time clock input 15 16 27 0 ns t co clock to output delay clock input 29 30 33 0 ns t ard array delay for product term expansion any macrocell 22 24 35 0 ns t min minimum clock period t ch + t cl 29 30 30 0 ns -15** -20 -25 zpld_turbo symbol parameter conditions min max min max min max off * unit maximum frequency external feedback 1/(t sa + t coa ) 16.95 14.49 11.11 mhz maximum frequency 1/(t sa +t co a ?0) 20.41 16.95 12.50 mhz f maxa internal feedback (f cnta ) (note 20) maximum frequency pipelined data 1/(t ch + t cl ) 33.33 31.25 18.52 mhz t sa input setup time any input 12 13 30 add 20 ns t ha input hold time any input 12 13 30 0 ns t cha clock high time any input 15 16 27 0 ns t cla clock low time any input 15 16 27 0 ns t coa clock to output delay any input to port b 47 56 60 add 20 ns t ard array delay for product term expansion any macrocell 29 33 35 0 ns t mina minimum clock period 1/f cnt 43 59 80 0 ns zpsd4xx family 5-91 asynchronous clock mode (3.0 v 10%, note 19) ac/dc parameters e zpld timing parameters (zpsd4xxv versions, advance information) note: 19. only port b has asynchronous outputs. clock into macrocell flip flop is generated by a product term. ** note: -15 available second half 1997. important: some parameters for the -20 versions are affected by errata notice. refer to page 5-108. zpsd4xx family 5-92 read timing (3.0 v 10%) explanation of ac symbols for non zpld timing. example: t avlx time from address valid to ale invalid. a address l logic level low or ale t r/w c power down n reset t time d input data p port signal v valid e ? q output data x no longer a valid logic level h logic level high r wr, uds, lds, ds, iord, psen z float i interrupt s chip select microcontroller interface e ac/dc parameters (zpsd4xxv versions, advance information) notes: 20. rd timing has the same timing as psen, ds, lds, uds signals. 20a. rd and psen have the same timing for 8031 mode. 21. any input used to select an internal zpsd4xx function. 22. in multiplexed mode latched address generated from adio delay to address output on any port. * note: -15 available second half 1997. -15* -20 -25 eprom_cmiser symbol parameter conditions min max min max min max on unit t lvlx ale or as pulse width 28 30 30 0 ns t avlx address setup time (note 21) 10 12 15 0 ns t lxax address hold time (note 21) 11 12 17 0 ns t avqv address valid to data valid (note 21) 150 200 250 add 20 ns t slqv cs valid to data valid 150 200 275 add 20 ns rd to data valid 8/16-bit bus (note 20) 36 40 80 0 ns t rlqv rd to data valid 8-bit bus, 8031 separate mode (note 20a) 45 50 90 0 ns t rhqx rd data hold time (note 20) 0 0 0 0 ns t rlrh rd pulse width (note 20) 38 40 70 0 ns t rhqz rd to data high-z (note 20) 45 45 45 0 ns t ehel e pulse width 38 40 70 0 ns t theh r/w setup time to enable 18 20 15 0 ns t eltl r/w hold time after enable 0 0 0 0 ns in 16-bit data bus mode 38 40 60 0 ns address input valid to (note 22) t avpv address output delay in 8-bit data bus mode 48 50 60 0 ns (note 22) important: some parameters for the -20 versions are affected by errata notice. refer to page 5-108. see page 5-108 for cmiser errata. zpsd4xx family 5-93 write timing (3.0 v 10%) microcontroller interface e ac/dc parameters (zpsd4xxv versions, advance information) note: 23. wr timing has the same timing as e, ds, lds, uds, wrl, wrh signals. -15* -20 -25 eprom_cmiser symbol parameter conditions min max min max min max on unit t lvlx ale or as pulse width 28 30 30 ns t avlx address setup time (note 21) 10 12 15 ns t lxax address hold time (note 21) 11 12 17 ns t avwl address valid to leading edge of wr (notes 21 and 23) 30 35 50 ns t slwl cs valid to leading edge of wr (note 23) 35 40 60 ns t dvwh wr data setup time (note 23) 22 25 35 ns t whdx wr data hold time (note 23) 5 5 10 ns t wlwh wr pulse width (note 23) 28 30 30 ns t whax trailing edge of wr to address invalid (note 23) 0 0 0 ns t whpv trailing edge of wr to port output valid (note 23) 38 40 60 ns in 16-bit data bus mode 38 40 60 ns address input valid to (note 22) t avpv address output delay in 8-bit data bus mode 48 50 60 ns (note 22) * note: -15 available second half 1997. important: some parameters for the -20 versions are affected by errata notice. refer to page 5-108. see page 5-108 for cmiser errata. zpsd4xx family 5-94 port a peripheral data mode read timing (3.0 v 10%) port a peripheral data mode write timing (3.0 v 10%) microcontroller interface e ac/dc parameters (zpsd4xxv versions, advance information) notes: 24. any input used to select port a data peripheral mode. 25. data is already stable on port a. 26. data stable on adio pins to data on port a. * note: -15 available second half 1997. -15* -20 -25 zpld_turbo symbol parameter conditions min max min max min max off unit t wlqv (pa) wr to data propagation delay (note 23) 40 50 60 0 ns t dvqv (pa) data to port a data propagation delay (note 26) 30 40 50 0 ns t whqz (pa) wr invalid to port a tri-state (note 23) 33 35 60 0 ns -15* -20 -25 zpld_turbo symbol parameter conditions min max min max min max off unit t avqv (pa) address valid to data valid (note 24) 62 65 120 add 20 ns t slqv (pa) cs valid to data valid 69 80 120 add 20 ns t rlqv (pa) rd to data valid (notes 20 and 25) 45 50 90 0 ns t dvqv (pa) data in to data out valid 26 28 50 0 ns t qxrh (pa) rd data hold time (note 20) 0 0 0 0 ns t rlrh (pa) rd pulse width (note 20) 38 40 70 0 ns t rhqz (pa) rd to data high-z (note 20) 33 35 60 0 ns important: some parameters for the -20 versions are affected by errata notice. refer to page 5-108. zpsd4xx family 5-95 power down and reset timing (3.0 v 10%) microcontroller interface e ac/dc parameters (zpsd4xxv versions, advance information) * note: -15 available second half 1997. -15* -20 -25 zpld_turbo symbol parameter conditions min max min max min max off unit t lv dv ale access time from power down 150 170 250 add 20 ns t lv dv 1 ale or csi access time from sleep 200 200 250 0 ns t lv dv 2 zpld propagation delay in sleep mode 600 600 900 0 ns t lv dv 3 zpld recovery time after sleep mode 250 250 400 0 ns t chcl apd clock high time using pe7 15 16 27 0 ns t clch apd clock low time using pe7 15 16 27 0 ns f max apd maximum frequency using pe7 22.00 20.00 18.52 0 mhz t 1 reset active low time 300 300 400 0 ns t 2 reset high to operational device 300 300 400 0 ns zpsd4xx family 5-96 figure 39. read timing t avlx t lxax t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out read timing ale /as a /d (bhe) multiplexed bus address (bhe/siz0) non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) (lds, uds) e r/w zpsd4xx family 5-97 figure 40. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlwh t dvwh t theh t avpv address valid address valid data valid data valid address out write timing t whpv standard mcu i/o out ale / as a /d (bhe) multiplexed bus address (bhe, siz0) non-multiplexed bus data non-multiplexed bus csi wr (wrh, wrl) (lds, uds) (ds) e r / w zpsd4xx family 5-98 figure 42. peripheral i/o write timing figure 41. peripheral i/o read timing t qxrh ( pa) t rlqv ( pa) t rlrh ( pa) t dvqv ( pa) t rhqz ( pa) t slqv ( pa) t avqv ( pa) address data valid ale /as a /d bus rd data on port a csi tdvqv (pa) twlqv (pa) twhqz (pa) address data out a /d bus wr port a data out ale /as zpsd4xx family 5-99 figure 43. combinatorial timing e zpld tpd trpd input (from port a) any output any output input (from port b, c, d, e) zpsd4xx family 5-100 figure 44. synchronous clock mode timing e zpld figure 45. asynchronous clock mode timing (product-term clock, pb macrocell only) t ch t cl t co t h t s clkin input registered output tcha tcla tcoa tha tsa clock input registered output zpsd4xx family 5-101 figure 46. input to output disable / enable figure 47. asynchronous reset /preset ter tea input input to output enable/disable tarp register output tarpw reset/preset input zpsd4xx family 5-102 figure 48. reset timing figure 49. key to switching waveforms t1 t2 reset timing requirements waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state zpsd4xx family 5-103 symbol parameter 27 conditions typical 28 max unit c in capacitance (for input pins only) v in = 0 v 4 6 pf c out capacitance (for input/output pins) v out = 0 v 8 12 pf c vpp capacitance (for wr/v pp or r/w/v pp )v pp = 0 v 18 25 pf notes: 27. these parameters are only sampled and are not 100% tested. 28. typical values are for t a = 25? and nominal supply voltages. t a = 25 ?, f = 1 mhz pin capacitance figure 50. ac testing input/output waveform figure 51. ac testing load circuit erasure and programming 3.0v 0v test point 1.5v device under test 2.01 v 195 w c l = 30 pf (including scope and jig capacitance) to clear all locations of their programmed contents, expose the window packaged device to an ultra-violet light source. a dosage of 30 w second/cm 2 is required (40 w second/cm 2 for zpsd4xxv versions). this dosage can be obtained with exposure to a wavelength of 2537 ? and intensity of 12000 ?/cm 2 for 40 to 45 minutes (55 to 60 minutes for zpsd4xxv versions). the device should be about 1 inch from the source, and all filters should be removed from the uv light source prior to erasure. the zpsd4xx and similar devices will erase with light sources having wavelengths shorter than 4000 ?. although the erasure times will be much longer than with uv sources at 2537 ?, exposure to fluorescent light and sunlight eventually erases the device. for maximum system reliability, these sources should be avoided. if used in such an environment, the package windows should be covered by an opaque substance. upon delivery from wsi, or after each erasure, the zpsd4xx device has all bits in the pad and eprom in the ??or high state. the configuration bits are in the ??or low state. the code, configuration, and pad map data are loaded through the procedure of programming information for programming the device is available directly from wsi. please contact your local sales representative. zpsd4xx family 5-104 68-pin 68-pin pin no. pldcc/cldcc pin no. pldcc/cldcc package package 1 gnd 35 gnd 2 adio_7 36 pe2 3 adio_6 37 pe1 4 adio_5 38 pe0 5 adio_4 39 csi 6 adio_3 40 reset 7 adio_2 41 rd 8 adio_1 42 clkin 9 adio_0 43 pb7 10 pc7 44 pb6 11 pc6 45 pb5 12 pc5 46 pb4 13 pc4 47 pb3 14 pc3 48 pb2 15 pc2 49 pb1 16 pc1 50 pb0 17 pc0 51 gnd 18 vcc 52 vcc 19 gnd 53 pd7 20 pa7 54 pd6 21 pa6 55 pd5 22 pa5 56 pd4 23 pa4 57 pd3 24 pa3 58 pd2 25 pa2 59 pd1 26 pa1 60 pd0 27 pa0 61 adio_15 28 vstdby 62 adio_14 29 wr 63 adio_13 30 pe7 64 adio_12 31 pe6 65 adio_11 32 pe5 66 adio_10 33 pe4 67 adio_9 34 pe3 68 adio_8 zpsd4xx pin assignments zpsd4xx family 5-105 80-pin 80-pin pin no. tqfp pin no. tqfp package package 1 pc7 41 pb7 2 pc6 42 pb6 3 pc5 43 pb5 4 pc4 44 pb4 5 pc3 45 pb3 6 pc2 46 pb2 7 pc1 47 pb1 8 pc0 48 pb0 9v cc 49 gnd 10 v cc 59 gnd 11 gnd 51 v cc 12 gnd 52 v cc 13 pa7 53 pd7 14 pa6 54 pd6 15 pa5 55 pd5 16 pa4 56 pd4 17 pa3 57 pd3 18 pa2 58 pd2 19 pa1 59 pd1 20 pa0 60 pd0 21 nc 61 nc 22 nc 62 adio_15 23 vstdby 63 adio_14 24 wr 64 adio_13 25 pe7 65 adio_12 26 pe6 66 adio_11 27 pe5 67 adio_10 28 pe4 68 adio_9 29 pe3 69 adio_8 30 gnd 70 gnd 31 gnd 71 gnd 32 pe2 72 adio_7 33 pe1 73 adio_6 34 pe0 74 adio_5 35 csi 75 adio_4 36 reset 76 adio_3 37 rd 77 adio_2 38 clkin 78 adio_1 39 nc 79 adio_0 40 nc 80 nc psd4xx pin assignments zpsd4xx family 5-106 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 v cc gnd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 adio - 0 adio -1 adio - 2 adio - 3 adio - 4 adio - 5 adio - 6 adio - 7 gnd adio - 8 adio - 9 adio -10 adio -11 adio -12 adio -13 adio -14 adio -15 pa0 vstdby wr pe7 pe6 pe5 pe4 pe3 gnd pe2 pe1 pe0 csi reset rd clkin pb7 figure 53. drawing l5 e 68-pin ceramic leaded chip carrier (cldcc) with window (package type l) figure 52. drawing j5 e 68-pin plastic leaded chip carrier (pldcc) (package type j) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 v cc gnd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 adio - 0 adio -1 adio - 2 adio - 3 adio - 4 adio - 5 adio - 6 adio - 7 gnd adio - 8 adio - 9 adio -10 adio -11 adio -12 adio -13 adio -14 adio -15 pa0 vstdby wr pe7 pe6 pe5 pe4 pe3 gnd pe2 pe1 pe0 csi reset rd clkin pb7 zpsd4xx family 5-107 60 pd0 59 pd1 58 pd2 57 pd3 56 pd4 55 pd5 54 pd6 53 pd7 52 v cc 51 v cc 50 gnd 49 gnd 48 pb0 47 pb1 46 pb2 45 pb3 44 pb4 43 pb5 42 pb6 41 pb7 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc v cc gnd gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 54 63 62 61 n/c adio? adio? adio? adio? adio? adio? adio? adio? gnd gnd adio? adio? adio?0 adio?1 adio?2 adio?3 adio?4 adio?5 n/c 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 n/c n/c vstdby wr pe7 pe6 pe5 pe4 pe3 gnd gnd pe2 pe1 pe0 csi reset rd clkin n/c n/c figure 54. drawing u2 e 80-pin plastic thin quad flatpack (tqfp) (package type u) (top view) zpsd4xx product ordering information zpsd4xx family devices are available in a wide range of product selections. options and combinations include: architecture speed (access time) memory size configuration mask programmability operating temperature range supply voltages packages please contact your local wsi sales representative or distributor for the zpsd4xx product selection that best fits your application and objectives. as of the print date of this databook, all zpsd4xxv versions are classified as ?reliminary? zpsd4xx family 5-108 -20 data sheet errata symbol parameter specification specification t rlqv rd to data valid 8/16-bit bus 40 50 t rlqv rd to data valid 8-bit bus, 8031 separate mode 50 57 t whpv trailing edge of wr to port output valid 40 50 t avqv(pa) address valid to data valid 65 95 t slqv(pa) cs valid to data valid 80 100 t dvqv(pa) data in to data out valid 28 35 t wlqv(pa) wr to data propagation delay 50 60 t s input setup time 35 45 t cha clock high time 16 25 zpsd4xxv errata the following errata specifications are in effect for revision c (zpsd4xxv-c) low voltage products. revision d products are scheduled to be released in the second half of 1997 and will meet the data sheet specifications. timing errata: cmiser errata the ?miser?function on the current ?evision c?zpsd4xxv devices does not operate correctly. programming the cmiser bit will cause these devices to fail to meet ac specifications. wsi plans to introduce ?evision d?devices that meet all specifications, including those for which the cmiser is programmed. in the meantime, you may design with the current devices. when the new revision d becomes available, just change your design file by enabling cmiser to achieve the lowest power possible. or, contact your wsi representative for other low voltage, low power solutions. |
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