View PSD412A2_2820845.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4-1 key features programmable peripheral psd4xx family field-programmable microcontroller peripherals o complete family of field programmable microcontroller peripherals enables the user to efficiently implement a highly integrated embedded control system in a short time. the psd4xx family has a variety of functions such as zplds , i/o ports, power management, eprom and sram. o ?o glue-logic?user programmable interface to 8 or 16 bit microcontroller multiplexed and non-multiplexed bus. the bus control logic can directly decode control signals generated by 8031, 80196, 80186, 68hc11, 68hc16, 683xx, 16000, z80, and z8 architecture. extended address capability up to 24 bits of address. o a range of zpld (zero power pld) architectures have up to 24 macrocells, 59 inputs and 126 output product terms. the psd4xx includes 2 functional zplds which enable the user to efficiently implement a variety of state machines, logic functions, address decoding and control of the internal psd4xx functional blocks . o the zplds use a zero power cmos technology that reduces the device standby current to 10 ? typical. unused product terms are disabled to reduce operating power. o 40 i/o ports that can be individually configured by the user as standard mcu i/o ports, pld i/o, latched address outputs and special function i/o. two eight bit i/o ports can be configured as open drain outputs. o the psd4xx family contains eprom densities of 256 kbit, 512 kbit and 1 mbit that can be configured as 8 or 16 bit data width. the eprom is divided into 4 equal blocks that can be mapped to different address spaces. access time is 70 ns which includes address latching and decoding pld. the eprom has a low power mode that is controlled by the cmiser-bit. o the psd4xx family contains a 16 kbit scratch pad sram that can be configured as 8 or 16 bit data width. access time is 70 ns which includes address latching and decoding pld. the sram can be used as standby storage if standby power is supplied to the vstdby pin. switching between v cc and vstdby occurs automatically. o page logic is connected to the zplds and enables address space expansion of microcontrollers with limited address space capability. up to 16 pages are available. o a security bit prevents reading the psd4xx configuration, zpld and eprom contents. this inhibits copying the device on a programmer. o port a can be used as a buffered microcontroller data bus ( peripheral i/o mode) of the microcontroller bus. this provides easy access to sub-systems that require more drive on the data bus or accessing a resource that is shared by another mcu or dma controller. o psd4xx standard versions are ideal for general purpose applications o psd4xxm mask-programmable versions are ideal for code-stable, high-volume low cost applications
psd4xx family 4-2 key featur es (cont.) o lo w po w er oper ation is achie v ed b y using a p o w er management unit (pmu) that enab les automatic stand-b y modes in the epr om, sram, and zplds . it also disab les the cloc k to the zpld . also a v ailab le is an automatic po w er do wn mode using the ale signal. a sleep mode is a v ailab le that consumes only 10 a standb y po w er consumption. o p ac kage choices include 68 pin plastic (j) and cer amic (l) chip carr iers . o the psd4xx f amily is suppor ted with pc based psdsoft ms-windo ws compatib le de v elopment tools . off er ing abel as a design entr y method (psdabel ), an efficient fitter , address t r anslator , magicpro prog r ammer and a full chip sim ulator (silos iii from simucad ) (psdsim ) are included. the psd4xx ser ies of field prog r ammab le microcontroller p er ipher als represent a major adv ance in the e v olution of prog r ammab le p er ipher als . the y combine an inno v ativ e architecture with state of the ar t technology to pro vide user prog r ammability (logic , functions , memor y), fle xibility , high integ r ation, optim um perf or mance , and lo w po w er . f or e xample , the psd413a2 can implement a full per ipher al subsystem and has the f ollo wing f eatures: o t w o zplds with a total of 59 inputs , 126 product ter ms outputs , 24 macrocells and 24 i/o pins . o 40 individually prog r ammab le i/o pins that are divided into 5 p or ts . o 4-bit p age register f or e xter nal memor y addressing o 1 mbit epr om consisting of f our 256 kbit b loc ks . o 16 kbit of standb y sram that can automatically s witch into standb y mode . o p o w er management unit with automatic standb y and sleep modes . o secur ity mode . figure 1 is a top le v el b loc k diag r am of the psd4xx. ref er to t ab le 1 and other sections f or details on functionality , dc/a c specifications , pac kages and order ing inf or mation. at the core of the psd4xx are zplds dedicated to the functions the y perf or m: o decoding zpld (dpld) o gener al pur pose zpld (gpld) both zplds receiv e the same inputs through the zpld b us and are diff erentiated b y their output destinations . the decoder pld (dpld) has as its main function to perf or m address space decoding f or the inter nal i/o p or ts , f our b loc ks of epr om, standb y sram and per ipher al mode of p or t a. the address decoding can be based on an y address input, control signal (rd , pse n , etc.) and page logic. address inputs or iginate from either the microcontroller interf ace (adio p or t) or other i/o p or ts f or additional decoding. the dpld also suppor ts special requirements of 8031 architecture based designs that need to store data in the epr om or e x ecute prog r ams from the sram. general description
psd4xx family 4-3 prog. bus intrf adio port prog. port prog. port port c prog. port port d control rd, wr ad0 ?ad15 pc0 ?pc7 pd0 ?pd7 clkin clkin page reg. zpld input bus global config. & security port a power manager unit vstdby pa0 ?pa7 prog. port port b pb0 ?pb7 prog. port port e pe0 ?pe7 address / data / control bus port a macrocells port b macrocells port e macrocells (note 2) 27pt (note 1) (note 1) 80pt 11pt clkin 256k 1m bit eprom 16 k bits sram i/o decoder eprom selects sram select peripheral selects macrocell feedback or port input csiop general pld (gpld) 24 macrocells decode pld (dpld) figur e 1. psd4xx block diagram no tes: 1. zpld input b us ? a1 = 36 + clock = 37 inputs ? a2 + 58 + clock = 59 inputs 2. por t e ma cr ocells a v ailable on a2 versions onl y .
psd4xx family 4-4 general description (cont.) the gener al pur pose pld (gpld) is a gener al pur pose zpld that can be used to implement state machines and logic . the gpld has up to 59 inputs , 118 product ter ms , 24 fle xib le macrocells and 24 i/o pins that are connected to p or ts a, b and e. the gpld can also decode the microcontroller address b us and gener ate chip selects to e xter nal per ipher als or memor ies . the zplds are designed to consume minim um po w er using zero p o w er design techniques . a configur ation bit (t urbo bit), that can be set b y the mcu , will automatically place the zplds into standb y if no inputs are changing. an y un used product ter ms will be tur ned off dur ing prog r amming and will not consume an y po w er in the system. the psd4xx has 40 i/o pins that are divided into 5 por ts . each i/o pin can be individually configured to pro vide man y functions . p or ts a, b and e ha v e the capability to be configured as standard mcu i/o por ts , gpld i/o , or latched address outputs f or m ultiple x ed address/data controllers . p or ts c and d are standard i/o por ts that can also be configured as zpld inputs or as a data b us f or microcontrollers with a non-m ultiple x ed b us . the psd4xx can easily interf ace with no ?lue-logic?to a v ar iety of 8 and 16-bit microcontrollers with a m ultiple x ed or non-m ultiple x ed b us . all of the control signals are connected to the tw o zplds enab ling the user to gener ate timing and decoding signals f or e xter nal per ipher als . f or controllers that do not ha v e a reset output, the psd4xx can gener ate a reset output based on its reset input. this input includes h ysteresis . the psd4xx contains epr om and scr atchpad sram. the epr om densities are 256 kbit, 512 kbit and 1 mbit and are divided into f our b loc ks . each b loc k can be located in a diff erent address location. the access time of the epr om includes the address latching and dpld decoding. the 16 kbit standb y sram ma y be used as an e xtension of the microcontroller sram and also to store bac kup inf or mation that is necessar y after a system po w er do wn. bac kup po w er to the sram is supplied b y the vs t db y pin. switching betw een v cc and vs t db y occurs automatically when v cc po w er is remo v ed. a f our bit p age register enab les easy access to the i/o section, epr om and sram f or microcontrollers with limited address space . the p age register outputs are connected to all zplds and can be used to page e xter nal de vices as w ell as the inter nal psd4xx functional units . a p o w er management unit (pmu) in the psd4xx enab les the user to control the po w er consumption on selected functional b loc ks based on system requirements . f or microcontrollers that do not gener ate a chip select input (csi) to the per ipher al de vice , the pmu includes an a utomatic p o w er do wn unit (apd) that will tur n off the psd4xx (into standb y or sleep mode) based on inactivity of the ale. the polar ity of ale inactivity can be defined b y the user . in addition to standb y mode , the psd4xx includes a sleep mode that will reduce the po w er consumption to 10 a.
psd4xx family 4-5 figur e 2. psdsoft development t ools psdsilos iii silosiii chip simulation psd programmer magicpro chip programming psd compiler (zpld fitting, address translation) ms ?windows editor: .abl file psdabel zpld description (state machine, decoding) psd configuration chip configuration third party programmers code file the psd4xx f amily is suppor ted b y the wsi-psd de v elopment system (psdsoft, see figure 2) which r uns under ms-windo ws on the pc . design entr y is done using psdabel which creates a minimiz ed logic implementation. psdabel also pro vides logic sim ulation of the zpld . the psd4xx desired configur ation is entered using a simple windo ws based men u. the psdcompiler , which consists of a fitter and address t r anslator , gener ates an object file from the psdabel and mcu code files . the object file can be do wn loaded to a prog r ammer (magicpr o , data i/o or other third par ty) or to psdsim (silos iii logic sim ulator) pro viding full chip sim ulation. the psd4xx standard v ersions include up to 1 mb of epr om, 16 kbit sram, decode pld (dpld), gener al pur pose pld (gpld), and fiv e 8-bit i/o p or ts . the y are ideal f or gener al pur pose embedded systems applications . the psd4xxm mask-prog r ammab le v ersions deliv er the lo w est cost psd4xx solution. see the mask ed-psd order ing inf or mation chapter in this databook f or the mask-prog r ammab le psd4xxm order ing procedure . ref erences in this document to psd4xx v ersions are gener ic and include psd4xxm products . general description (cont.)
psd4xx family 4-6 psd4xx family there are 12 unique de vices in the psd4xx f amily . the par t classifications are based on zpld configur ation and siz e , epr om siz e , and data b us width. the f eatures of each par t are listed in t ab le 1. par t bus dpld + gpld i/o pmu eprom sram # bit inputs pr oduct register ed pins k bit k bit t er ms macr ocells 401a1 x8/x16 37 113 8 40 y es 256 16 411a1 x8 37 113 8 40 y es 256 16 402a1 x8/x16 37 113 8 40 y es 512 16 412a1 x8 37 113 8 40 y es 512 16 403a1 x8/x16 37 113 8 40 y es 1024 16 413a1 x8 37 113 8 40 y es 1024 16 401a2 x8/x16 59 126 24 40 y es 256 16 411a2 x8 59 126 24 40 y es 256 16 402a2 x8/x16 59 126 24 40 y es 512 16 412a2 x8 59 126 24 40 y es 512 16 403a2 x8/x16 59 126 24 40 y es 1024 16 413a2 x8 59 126 24 40 y es 1024 16 t able 1. psd4xx pr oduct matrix no te: pmu = p o w er management unit.
psd4xx family 4-7 pin name pin function t ype function descriptions adio0 ?adio15 address/data b us i/o 1. address/data b us , m ultiple x ed b us mode 2. address b us , non-m ultiple x ed b us mode rd multiple names i multiple functions 1. read 1. read signal 2. e 2. e signal (cloc k) 3. ds 3. data strobe signal 4. lds 4. lo w b yte data strobe wr multiple names i multiple functions 1. wr 1. wr ite signal 2. r / w 2. read-wr ite signal 3. wrl 3. lo w b yte wr ite signal csi chip select input i activ e lo w , select psd4xx standb y mode if high. reset reset input i reset i/o por ts , zpld/macrocells , and configur ation registers . activ e lo w . clkin input cloc k i cloc k input to zpld macrocells , zpld arr a y and apd counter . connect to g round if cloc k input not used. p a0 ?p a7 i/o p or t a i/o multiple functions 1. i/o por t 2. zpld/macrocell i/o por t 3. latched address outputs (p a0 ?p a7) ? (a0 ?a7) 4. high address inputs (a16 ?a23) pb0 ?pb7 i/o p or t b i/o multiple functions 1. i/o por t 2. zpld/macrocell i/o por t 3. latched address outputs (pb 0 ?b7) ? (a 0 a7) or (a8?15) pc0 ?pc7 i/o p or t c i/o multiple functions cmos 1. i/o por t or 2. zpld input por t * od 3. latched address outputs (pc0 ?pc7) ? (a 0 a7) 4. data p or t (d0 ?d7, non-m ultiple x ed b us) pd0 ?pd7 i/o p or t d i/o multiple functions cmos 1. i/o por t or 2. zpld input por t * od 3. latched address outputs (pd 0 ?d7) ? (a 0 a7) or (a 8 ?15) 4. data p or t (d 8 d15, non-m ultiple x ed b us) * a v ailab le only in psd4xxa2 ser ies . t able 2. psd4xx pin descriptions the f ollo wing tab le descr ibes the pin names and pin functions of the psd4xx. pins that ha v e m ultiple names and/or functions are defined b y user configur ation.
psd4xx family 4-8 pin name pin function t ype function descriptions pe0 p or t pe, pin 0 i/o multiple functions 1. bhe 1. high b yte enab le , 16 bit data 2. psen 2. read prog r am memor y , 8031 signal 3. wrh 3. wr ite high data b yte 4. uds 4. upper data strobe 5. siz0 5. byte enab le , 68300 signal 6. pe0 6. i/o pin 7. pe0 7. zpld i/o pin 8. pe0 8. latched address out ?a0 pe1 p or t pe, pin 1 i/o multiple functions 1. ale 1. address strobe 2. pe1 2. i/o pin 3. pe1 3. zpld i/o pin 4. pe1 4. latched address out ?a1 pe2 p or t pe, pin 2 multiple functions 1. pe2 i/o 1. i/o pin 2. pe2 2. zpld i/o pin * 3. pe2 3. latched address out ?a2 pe3 p or t pe, pin 3 multiple functions 1. pe3 i/o 1. i/o pin 2. pe3 2. zpld i/o pin * 3. pe3 3. latched address out ?a3 pe4 p or t pe, pin 4 multiple functions 1. pe4 i/o 1. i/o pin 2. pe4 2. zpld i/o pin * 3. pe4 3. latched address out ?a4 pe5 p or t pe, pin 5 multiple functions 1. pe5 i/o 1. i/o pin 2. pe5 2. zpld i/o pin * 3. pe5 3. latched address out ?a5 pe6 p or t pe, pin 6 multiple functions 1. pe6 i/o 1. i/o pin 2. pe6 2. zpld i/o pin * 3. pe6 3. latched address out ?a6 pe7 p or t pe, pin 7 multiple functions 1. apd clk 1. a utomatic p o w er do wn cloc k input 2. pe7 i/o 2. i/o pin 3. pe7 3. zpld i/o pin * 4. pe7 4. latched address out ?a7 vstdb y vstdb y i sram po w er pin f or standb y oper ation (batter y bac kup) v cc v cc i v cc po w er pin gnd gnd i ground pin * a v ailab le only in psd4xxa2 ser ies . t able 2. psd4xx pin descriptions (cont.)
psd4xx family 4-9 general description the zpld b loc k has 2 embedded pld de vices: o dpld the address decoding pld , gener ating select signals to inter nal i/o or memor y b loc ks . o gpld the gener al pur pose pld pro vides 8 registered and combinator ial prog r ammab le macrocells f or gener al or comple x logic implementation; dedicated to user application. figure 3 sho ws the architecture of the zpld . the pld de vices all share the same input b us . the tr ue or complement of the 37 input signals are f ed to the prog r ammab le and-arra y . names and sources of the input signals are sho wn in t ab le 3. the pb signals , depending on user configur ation, can either be macrocell f eedbac ks or inputs from p or t b . key featur es o 2 embedded zpld de vices o 8 registered and 8 combinator ial macrocells o combinator ial/registered outputs o maxim um 113 product ter ms o prog r ammab le output polar ity o user configured register clear/preset o user configured register cloc k input o 37 inputs o accessib le via 16 i/o pins o p o w er sa ving mode o uv -er asab le the psd4xxa1 zpld block the psd4xx architecture psd4xx consists of fiv e major functional b loc ks: o zpld block o bus inter face o i/o por ts o memor y block o power management unit the functions of each b loc k are descr ibed in the f ollo wing sections . man y of the b loc ks perf or m m ultiple functions , and are user configur ab le . the chip configur ations are specified b y the user in the psdsoft de v elopment softw are . other configur ations are specified b y setting up the appropr iate bits in the configur ation registers dur ing r un time . the zpld block the psd4xx ser ies de vices pro vide tw o zpld configur ations . the zpld in the psd4xxa1 de vices has 8 registered macrocells , 8 combinator ial macrocells , and up to 113 product ter ms . the psd4xxa2 has a full function zpld with 24 registered macrocells and up to 126 product ter ms .
psd4xx family 4-10 figure 3. zpld block diagram page reg. adio port pmu csi rd/ e/ds pe1 (psen/bhe) pe0 (ale/as) wr / r_w reset clkin pgr0 ?3 a8 ?a15 a0, a1 and array and array dpld es0 ?es3 rs0 csiop psel0 ?psel1 8 i /o macrocells pa 8 i /o macrocells pb (note 1) 80 pt pb0 ?pb7 pa0 ?pa7 prog. port port a prog. port port b dpld gpld zpld input bus (decoding pld) (general purpose pld) note 1: a1 = 25 pt on port a a2 = 27 pt on port a psd4xxa1 zpld block (cont.)
psd4xx family 4-11 signal name fr om p a0 ?p a7 p or t a inputs or macrocell p a f eedbac k pb0 ?pb7 p or t b inputs or macrocell pb f eedbac k pe0 ?pe1 p or t e inputs (signals ale, psen/bhe) pgr0 ?pgr3 p age mode register a8 ?a15, a0, a1 mcu address lines rd/e/ds mcu b us signal wr/r_w mcu b us signal clkin input cloc k reset reset input csi csi input (ored with po w er do wn from pmu) t able 3. zpld input signals psd4xxa1 zpld block (cont.) the dpld the dpld is used f or inter nal address decoding gener ating the f ollo wing eight chip select signals: o es0 ?es3 epr om selects , b loc k 0 to b loc k 3 o rs0 sram b loc k select o csiop i/o decoder chip select o psel0 ?psel1 p er ipher al i/o mode select signals the i/o decoder enab led b y the csiop gener ates chip selects f or on-chip registers or i/o por ts based on address inputs a [7:0]. as sho wn in figure 4, the dpld consists of a large prog r ammab le and arra y . there are a total of 37 inputs and 8 outputs . each output consists of a single product ter m. although the user can gener ate select signals from an y of the inputs , the select signals are typically a function of the address and p age register inputs . the select signals are defined b y the user in the abel file (psdabel). the address line inputs to the dpld include a0, a1 and a8 ?a15. if more address lines are needed, the user can br ing in the lines through p or t a to the dpld .
psd4xx family 4-12 the gpld the str ucture of the gener al pur pose pld consists of a prog r ammab le and arra y and 2 sets of i/o macrocells . the arra y has 37 input signals , same as the dpld . f rom these inputs , ?nded?functions are gener ated as product ter m inputs to the macrocells . the i/o macrocell sets are named after the i/o p or ts the y are link ed to , e .g., the macrocells connected to p or t b are named pb macrocells . the pb macrocells are registered macrocells with d-type flip-flops , where p a consists of combinator ial macrocells . pa macrocell structure figure 5 sho ws the p a macrocell b loc k, which consists of 8 identical combinator ial macrocells . each macrocell output can be connected to its o wn i/o pin on p or t a. there is one user prog r ammab le global product ter m that is output from the gpld s and arra y which is shared b y all the macrocells in p or t a: o p a.oe enab le or tr i-state p or t a output pins the circuit of a p a macrocell is sho wn in figure 6. there are 4 product ter ms from the gpld s and arra y as inputs to the macrocell. users can select the polar ity of the output, and configure the macrocell to oper ate as: o gpld input use p or t a pin as dedicated input o gpld output use p or t a pin as dedicated output psd4xxa1 zpld block (cont.)
psd4xx family 4-13 figur e 4. dpld logic ar ray pa0 ?pa7 (8) (8) (2) (10) (3) (1) (1) (inputs) pb0 ?pb7 pe0 ?pe1 (4) pgr0 ?pgr3 a8 ?a15, a0, a1 csi, clkin reset rd/ e / ds wr /r_w es0 es1 es2 es3 rs0 csiop psel0 psel1 4 eprom block selects ram select i /o decoder select peripheral i /o selects dpld inputs = 37 dpld outputs = 8 (ale, psen / bhe) psd4xxa1 zpld block (cont.)
psd4xx family 4-14 figure 5. pa macrocell block diagram and array mc0 pa0 mc1 pa1 mc7 pa7 macro. out pa0 input macro. out pa1 input macro. out pa7 input pt [ 2:0 ] pa0 pt [ 2:0 ] pa1 pt [ 2:0 ] pa7 pa.oe port a i/o cells pa macrocell zpld bus psd4xxa1 zpld block (cont.)
psd4xx family 4-15 figur e 6. p a macr ocell pt pt pt pt and array polarity select pld in select mux pa .oe pt0 pt1 pt2 pai note: i = 7 to 0 macro . out i/o pin pai port a internal address/data bus pai input zpld bus psd4xxa1 zpld block (cont.)
psd4xx family 4-16 por t b macr ocell str uctur e figure 7 sho ws the pb macrocell b loc k, which consists of 8 identical macrocells . each macrocell output can be connected to its o wn i/o pin on p or t b . the tw o inputs , clkin and ma cr o-rst , are used as cloc k and clear inputs to all the macrocells . the clkin comes directly from the clkin input pin. the ma cr o-rst is the same as the reset input pin e xcept it is user configur ab le . the circuit of a pb macrocell is sho wn in figure 8. there are 10 product ter ms from the gplds and arra y as inputs to the macrocell. users can select the polar ity of the output, and configure the macrocell to oper ate as: o registered output select output from d flip flop . o combinatorial output select output from or gate . o gpld input use p or t b pin as dedicated input. o gpld output use p or t b pin as dedicated output. o gpld i/o use p or t b pin as bidirectional pin. o macr ocell feedbac k register f eedbac k f or state machine implementations or e xpander f eedbac k from the combinator ial output, to possib ly e xpand the n umber of product ter ms a v ailab le to another macrocell. in case of "bur ied f eedbac k", where the output of the macrocell is not connected to a p or t b pin, p or t b can be configured to perf or m other user defined i/o functions . each d flip flop in the macrocells has its o wn dedicated asynchronous clear , preset and cloc k input. the signals are defined as f ollo w: o preset activ e only if defined b y a product ter m (pbi.pr) o clear t w o selectab le inputs: reset input and/or user defined product ter m (pbi.re) o clk t w o selectab le inputs ? clkin input or user defined product ter m (pbi.clk). the macrocell is oper ated in synchronous mode if the cloc k input is clkin, and is in asynchronous mode if the cloc k is a product-ter m cloc k defined b y the user . figure 9 sho ws the input/output path of a pb macrocell to the p or t pin with which it is associated. if the p or t pin is specified as a pb output pin in the psdsoft, the mux in the i/o p or t cell selects the pb macrocell as an output of the p or t pin. the output enab le signal to the b uff er in the i/o cell can be controlled b y a product ter m from the and arr a y . if the p or t pin is specified as a zpld input pin, the mux in the pb macrocell selects the p or t input signal to be one of the 61 signals in the zpld input bus . psd4xxa1 zpld block (cont.)
psd4xx family 4-17 the zpld power management the zpld implements a zero p o w er mode , which pro vides consider ab le po w er sa vings f or lo w to medium frequency oper ations . t o enab le this f eature , the zpld t urbo bit in the p o w er management mode register 0 (pmmr0) has to be tur ned off . if none of the inputs to the zpld are s witching f or a time per iod of 90ns , the zpld puts itself into zero p o w er mode and the current consumption is minimal. the zpld will resume nor mal oper ation as soon as one or more of the inputs change state . t w o other f eatures of the zpld pro vide additional po w er sa vings: 1. cloc k disab le: users can disab le the cloc k input to the zpld and/or macrocells ,thereb y reducing a c po w er consumption. 2. pr oduct t erm disab le: un used product ter ms in the zpld are disab led b y the psdsoft softw are automatically f or fur ther po w er sa vings . the zpld po w er configur ation is descr ibed in the p o w er management unit section. psd4xxa1 zpld block (cont.)
psd4xx family 4-18 figure 7. pb macrocell block diagram and array macro .out pb0 .oe pb0 ?input macro .out pb1 .oe pb1 input macro .out pb7 .oe pb7?input ptb0 ? [ 0 . . 5 ] pb0 .pr pb0 .re pb0 .oe pb0 .clk pb0 ptb1 ? [ 0 . . 5 ] pb1 .pr pb1 .re pb1 .oe pb1 .clk pb1 ptb7 ? [ 0 . . 5 ] pb7 .pr pb7 .re pb7 .oe pb7 .clk pb7 clkin macro ?rst port b i/o cells pb macrocell mc0 mc1 mc7 pb0 pb1 pb7 zpld bus psd4xxa1 zpld block (cont.)
psd4xx family 4-19 figure 8. pb macrocell d q pt pt pt pt pt pt pt pt pt pt and array polarity select comb / reg select c pr mux pld in select mux clk select mux pbi pbi .oe pbi .pr pt0 pt1 pt2 pt3 pt4 pt5 pbi .clk pbi .re macro rst clkin macro . out i / o pin pbi port b internal address / data bus pbi ?input zpld bus psd4xxa1 zpld block (cont.)
psd4xx family 4-20 figur e 9. pb macr ocell input/output por t d q psd4xx fig 5 and array pt polarity select cl ck pr control clk select mux pt clock pt output enable (oe) pt reset pts pt clear macro_rst global clock port pin comb./reg. select gpld macrocell output mux mux mux pcr d q wr direction register d q wr d g q ale pdr port input input output address a[0-7] or a[8-15] gpld output gpld macrocell i/o port cell internal address / data/control bus zpld input bus clkin psd4xxa1 zpld block (cont.)
psd4xx family 4-21 the psd4xxa2 zpld block key featur es o 2 embedded zpld de vices o 24 macrocells o combinator ial/registered outputs o maxim um 126 product ter ms o prog r ammab le output polar ity o user configured register clear/preset o user configured register cloc k input o 59 inputs o accessib le via 24 i/o pins o p o w er sa ving mode o uv -er asab le general description the zpld b loc k has 2 embedded pld de vices: o dpld the address decoding pld , gener ating select signals to inter nal i/o or memor y b loc ks . o gpld the gener al pur pose pld pro vides 24 prog r ammab le macrocells f or gener al or comple x logic implementation; dedicated to user application. figure 10 sho ws the architecture of the zpld . the pld de vices all share the same input b us . the tr ue or complement of the 59 input signals are f ed to the prog r ammab le and-arra y . names and source of the input signals are sho wn in t ab le 4. the p a, pb , pe signals , depending on user configur ation, can either be macrocell f eedbac ks or inputs from p or t a, b or e.
psd4xx family 4-22 page reg. adio port prog. port port c prog. port port d pmu csi rd/ e/ds wr / r_w reset clkin pgr0 ?3 a8 ?a15 a0, a1 pc0 ?pc7 pd0 ?pd7 and array and array and array dpld es0 ?es3 rs0 csiop psel0 ?psel1 8 i /o macrocells pa 8 i /o macrocells pb 8 i /o macrocells pe 27 pt 80 pt 11 pt pe0 ?pe7 pb0 ?pb7 pa0 ?pa7 prog. port port a prog. port port b prog. port port e dpld gpld zpld input bus (decoding pld) (general purpose pld) psd4xxa2 zpld block (cont.) figur e 10. psd4xxa2 zpld block diagram
psd4xx family 4-23 signal name fr om p a0 ?p a7 p or t a inputs or macrocell p a f eedbac k pb0 ?pb7 p or t b inputs or macrocell pb f eedbac k pe0 ?pe7 p or t e inputs or macrocell pe f eedbac k pc0 ?pc7 p or t c inputs pd0 ?pd7 p or t d inputs pgr0 ?pgr3 p age mode register a8 ?a15, a0, a1 mcu address lines rd/e/ds mcu b us signal wr/r_w mcu b us signal clkin input cloc k reset reset input csi csi input (ored with po w er do wn from pmu) t able 4. zpld input signals the dpld the dpld is used f or inter nal address decoding gener ating the f ollo wing eight chip select signals: o es0 ?es3 epr om selects , b loc k 0 to b loc k 3 o rs0 sram b loc k select o csiop i/o decoder chip select o psel0 ?psel1 p er ipher al i/o mode select signals the i/o decoder enab led b y the csiop gener ates chip selects f or on-chip registers or i/o por ts based on address inputs a [7:0]. as sho wn in figure 11, the dpld consists of a large prog r ammab le and arra y . there are a total of 59 inputs and 8 outputs . each output consists of a single product ter m. although the user can gener ate select signals from an y of the inputs , the select signals are typically a function of the address and p age register inputs . the select signals are defined b y the user in the abel file (psdabel). the address line inputs to the dpld include a0, a1 and a8 ?a15. if more address lines are needed, the user can br ing in the lines through p or t a to the dpld . psd4xxa2 zpld block (cont.)
psd4xx family 4-24 figur e 11. dpld logic ar ray pa0 ?pa7 (8) (8) (8) (8) (8) (4) (10) (3) (1) (1) (inputs) pb0 ?pb7 pe0 ?pe7 pc0 ?pc7 pd0 ?pd7 pgr0 ?pgr3 a8 ?a15, a0, a1 csi, clkin reset rd/ e / ds wr /r_w es0 es1 es2 es3 rs0 csiop psel0 psel1 4 eprom block selects ram select i /o decoder select peripheral i /o selects dpld inputs : 59 dpld outputs : 8 psd4xxa2 zpld block (cont.)
psd4xx family 4-25 the gpld the str ucture of the gener al pur pose pld consists of a prog r ammab le and arra y and 3 sets of i/o macrocells . the arra y has 59 input signals , same as the dpld . f rom these inputs , ?nded?functions are gener ated as product ter m inputs to the macrocells . the i/o macrocell sets are named after the i/o p or ts the y are link ed to , e .g., the macrocells connected to p or t a are named p a macrocells . the 3 sets of macrocells , p a, pb and pe, are similar in str ucture and function. figure 12 sho ws the output/input path of a gpld macrocell to the p or t pin with which it is associated. if the p or t pin is specified as a gpld output pin in psdsoft, the mux in the i/o p or t cell selects the gpld macrocell as an output of the p or t pin. the output enab le signal to the b uff er in the i/o cell can be controlled b y a product ter m from the and arra y . if the p or t pin is specified as a zpld input pin, the mux in the gpld macrocell selects the p or t input signal to be one of the 61 signals in the zpld input bus . port a macrocell structure figure 13 sho ws the p a macrocell b loc k, which consists of 8 identical macrocells . each macrocell output can be connected to its o wn i/o pin on p or t a. there are 3 user prog r ammab le global product ter ms output from the gpld s and arra y which are shared b y all the macrocells in p or t a: o p a.oe enab le or tr i-state p or t a output pins o p a.pr preset d flip flop in the macrocells o p a.re rese t /clear d flip flop in the macrocells t w o other inputs , clkin and ma cr o-rst , are used as cloc k and clear inputs to the d flip flop . the clkin comes directly from the clkin input pin. the ma cr o-rst is the same as the reset input pin e xcept it is user configur ab le . the circuit of a p a macrocell is sho wn in figure 14. there are 6 product ter ms from the gpld s and arra y as inputs to the macrocell. users can select the polar ity of the output, and configure the macrocell to oper ate as: o registered output select output from d flip flop o combinatorial output select output from or gate o gpld input use p or t a pin as dedicated input o gpld output use p or t a pin as dedicated output o gpld i/o use p or t a pin as bidirectional pin o macr ocell feedbac k register f eedbac k f or state machine implementations or e xpander f eedbac k from the combinator ial output, to e xpand the n umber of product ter ms a v ailab le to another macrocell. in case of "bur ied f eedbac k", where the output of the macrocell is not connected to a p or t a pin, p or t a can be configured to perf or m other user defined i/o functions . the tw o global product ter ms assigned f or asynchronous clear (p a.re) and preset (p a.pr) are mainly f or proper p a macrocell initialization. the macrocell flip-flop can also be cleared dur ing reset b y ma cr o-rst , if such an option is chosen. the cloc k source is alw a ys the input cloc k clkin. psd4xxa2 zpld block (cont.)
psd4xx family 4-26 d q psd4xx fig. 18 and array pt polarity select cl ck pr control clk select mux pt clock pt output enable (oe) pt reset pts pt clear macro_rst global clock port pin comb./reg. select macrocell output mux mux mux pcr d q wr direction register d q wr d g q ale pdr port input input output address a[0-7] or a[8-15] gpld output latch q d latch only on port a gpld macrocell i/o port cell internal address / data/control bus zpld input bus figure 12. gpld macrocell input/output port psd4xxa2 zpld block (cont.)
psd4xx family 4-27 figure 13. pa macrocell block diagram and array mc0 pa0 mc1 pa1 mc7 pa7 macro. out pa0 input macro. out pa1 input macro. out pa7 input pt [ 2:0 ] pa0 pt [ 2:0 ] pa1 pt [ 2:0 ] pa7 pa.pr pa.re pa.oe clkin macro rst port a i/o cells pa macrocell zpld bus psd4xxa2 zpld block (cont.)
psd4xx family 4-28 figur e 14. psd4xxa2 p a macr ocell d q pt pt pt pt pt pt and array polarity select pld in select c pr mux mux pa .oe pa . pr pt0 pt1 pt2 pa .re pai macro rst note: i = 7 to 0 clkin macro . out i/o pin pai port a comb / reg select internal address/data bus pai input zpld bus psd4xxa2 zpld block (cont.)
psd4xx family 4-29 port b macrocell structure figure 15 sho ws the pb macrocell b loc k, which consists of 8 identical macrocells . each macrocell output can be connected to its o wn i/o pin on p or t b . the tw o inputs , clkin and ma cr o-rst , are used as cloc k and clear inputs to all the macrocells . the clkin comes directly from the clkin input pin. the ma cr o-rst is the same as the reset input pin e xcept it is user configur ab le . the circuit of a pb macrocell is sho wn in figure 16. there are 10 product ter ms from the gpld s and arra y as inputs to the macrocell. users can select the polar ity of the output, and configure the macrocell to oper ate as: o registered output select output from d flip flop . o combinatorial output select output from or gate . o gpld input use p or t b pin as dedicated input. o gpld output use p or t b pin as dedicated output. o gpld i/o use p or t b pin as bidirectional pin. o macr ocell feedbac k register f eedbac k f or state machine implementations or e xpander f eedbac k from the combinator ial output, to possib ly e xpand the n umber of product ter ms a v ailab le to another macrocell. in case of "bur ied f eedbac k", where the output of the macrocell is not connected to a p or t b pin, p or t b can be configured to perf or m other user defined i/o functions . each d flip flop in the macrocells has its o wn dedicated asynchronous clear , preset and cloc k input. the signals are defined as f ollo w: o preset activ e only if defined b y a product ter m (pbx.pr) o clear t w o selectab le inputs: reset input or user defined product ter m (pbx .re) o clk t w o selectab le inputs ? clkin input or user defined product ter m (pbx.clk). the macrocell is oper ated in synchronous mode if the cloc k input is clkin, and is in asynchronous mode if the cloc k is a product-ter m cloc k defined b y the user . psd4xxa2 zpld block (cont.)
psd4xx family 4-30 figur e 15. psd4xxa2 pb macr ocell block diagram and array macro .out pb0 .oe pb0 ?input macro .out pb1 .oe pb1 input macro .out pb7 .oe pb7?input ptb0 ? [ 0 . . 5 ] pb0 .pr pb0 .re pb0 .oe pb0 .clk pb0 ptb1 ? [ 0 . . 5 ] pb1 .pr pb1 .re pb1 .oe pb1 .clk pb1 ptb7 ? [ 0 . . 5 ] pb7 .pr pb7 .re pb7 .oe pb7 .clk pb7 clkin macro ?rst port b i/o cells pb macrocell mc0 mc1 mc7 pb0 pb1 pb7 zpld bus psd4xxa2 zpld block (cont.)
psd4xx family 4-31 d q pt pt pt pt pt pt pt pt pt pt and array polarity select comb / reg select c pr mux pld in select mux clk select mux pbi pbi .oe pbi .pr pt0 pt1 pt2 pt3 pt4 pt5 pbi .clk pbi .re macro rst clkin macro . out i / o pin pbi port b internal address / data bus pbi ?input note: i = 7 to 0 zpld bus figur e 16. psd4xxa2 pb macr ocell psd4xxa2 zpld block (cont.)
psd4xx family 4-32 por t e macr ocell str uctur e figure 17 sho ws the pe macrocell b loc k, which consists of 8 identical macrocells . each macrocell output can be connected to its o wn i/o pin on p or t e. there are 3 user prog r ammab le global product ter ms output from the gpld s and arra y which are shared b y all the macrocells in p or t e: o pe.oe enab le or tr i-state p or t pe output pins o pe.pr preset d flip flop in the macrocells o pe.re rese t /clear d flip flop in the macrocells t w o other inputs , clkin and ma cr o-rst , are used as cloc k and clear inputs to the d flip flop . the clkin comes directly from the clkin input pin. the ma cr o-rst is the same as the reset input pin e xcept it is user configur ab le . the circuit of a pe macrocell is sho wn in figure 18. there is only one product ter m from the gpld s and arra y as input to the macrocell. users can select the polar ity of the output and configure the macrocell to oper ate as: o registered output select output from d flip flop o combinatorial output select output from or gate o gpld input use p or t e pin as dedicated input o gpld output use p or t e pin as dedicated output o gpld i/o use p or t e pin as bidirectional pin o macr ocell feedbac k register f eedbac k f or state machine implementations or e xpander f eedbac k from the combinator ial output, to possib ly e xpand the n umber of product ter ms a v ailab le to another macrocell. in case of "bur ied f eedbac k", where the output of the macrocell is not connected to p or t e pin, p or t e can be configured to perf or m other user defined i/o functions . if pins pe0 and pe1 are used as b us control signal inputs (ale, psen/bhe), the corresponding macrocells' f eedbac ks are disab led. the b us control signals are connected to the zpld input bus . the tw o global product ter ms assigned f or asynchronous clear (pe.re) and preset (pe.pr) are f or proper pe macrocell initialization. the macrocell flip-flop can also be cleared dur ing reset b y ma cr o-rst as an option. the cloc k source is alw a ys the input cloc k clkin. psd4xxa2 zpld block (cont.)
psd4xx family 4-33 the zpld power management the zpld implements a zero p o w er mode , which pro vides consider ab le po w er sa vings f or lo w to medium frequency oper ations . t o enab le this f eature , the zpld t urbo bit in the p o w er management mode register 0 (pmmr0) has to be tur ned off . if none of the inputs to the zpld are s witching f or a time per iod of 70ns , the zpld puts itself into zero p o w er mode and the current consumption is minimal. the zpld will resume nor mal oper ation as soon as one or more of the inputs change state . t w o other f eatures of the zpld pro vide additional po w er sa vings: 1. cloc k disab le: users can disab le the cloc k input to the zpld and/or macrocells , thereb y reducing a c po w er consumption. 2. pr oduct t erm disab le: un used product ter ms in the zpld are disab led b y the psdsoft softw are automatically f or fur ther po w er sa vings . the zpld po w er configur ation is descr ibed in the p o w er management unit section. psd4xxa2 zpld block (cont.)
psd4xx family 4-34 and array mc0 pe0 mc1 pe1 mc7 pe 7 macro .out pe0 ?input macro .out pe1 ?input macro .out pe7?input pt pe0 pt pe1 pt pe7 pe .pr pe .re pe .oe clkin macro ?rst port e i/o cells pe macrocell zpld bus figure 17. pe macrocell block diagram psd4xxa2 zpld block (cont.)
psd4xx family 4-35 figur e 18. pe macr ocell d q pt pt pt pt and array polarity select pld in select c pr mux mux pe .oe pe .pr pt pe .re pei macro rst note: i = 7 to 0 clkin macro .out i/o pin pei port e internal address/data bus pei input comb / reg select zpld bus psd4xxa2 zpld block (cont.)
psd4xx family 4-36 psd4xx family bus inter face the bus interf ace is v er y fle xib le and can be configured to interf ace to most microcontrollers with no glue logic. t ab le 5 lists some of the b us types to which the bus interf ace is ab le to interf ace . multiplexed data bus bus contr ol micr ocontr oller w idth signals mux 8 wr, rd , psen, a0 8031 mu x / non-m ux 8/16 r / w , e, bhe, a0 6811 mux 8/16 wr, rd , bhe, a0 80196/80186 mux 16 wrl, rd , wrh, a0 80196sp non-m ux 16 r/w , lds , uds 68302 non-m ux 8/16 r/w , ds , siz0, a0 68340 non-m ux 16 r/w , ds , bhe, ble 68330 t able 5. t ypical micr ocontr oller bus t ypes bus inter face configuration the bus interf ace logic is user configur ab le . the type of b us interf ace is specified b y the user in the psdsoft softw are (psd configur ation). the b us control input pins ha v e m ulti-function capabilities . by choosing the r ight configur ation, the psd4xx is ab le to interf ace to most microcontrollers , including the ones listed in t ab le 5. in t ab le 6, the names of the b us control input signal pins and their m ultiple functions are sho wn. f or e xample , pin pe0 can be configured b y the psd configur ation softw are to perf or m an y one of the fiv e functions . examples on the interf ace betw een the psd4xx and some typical microcon - trollers are sho wn in f ollo wing sections . pin pin pin pin pin pin name function function function function function 1 2 3 4 5 rd rd e ds lds wr wr r/w wrl pe0 bhe psen wrh uds siz0 pe1 ale ad0 a0 ble t able 6. alter nate pin functions psd4xx inter face t o a multiplexed bus figure 19 sho ws a typical connection to a microcontroller with a m ultiple x ed b us . the adio por t of the psd4xx is connected directly to the microcontroller address/data b us (ad0-ad15 f or 16 bit b us). the ale input signal latches the address lines inter nally . in a read b us cycle , data is dr iv en out through the adio p or t tr ansceiv ers after the specified access time . the inter nal adio p or t connection f or a 16 bit m ultiple x ed b us is sho wn in figure 20. the adio p or t is in tr i-state mode if none of the psd4xx inter nal de vices are selected.
psd4xx family 4-37 psd4xx family psd4xx interface to non-multiplexed bus figure 21 sho ws a psd4xx interf acing to a microcontroller with a non-m ultiple x ed address/data b us . the address b us is connected to the adio p or t, and the data b us is connected to p or t c and/or p or t d , depending on the b us width. there is no need f or the adio p or t to latch the address inter nally , b ut the user is off ered the option to do so in the psd4xx psdsoft softw are . the data p or ts are in tr i-state mode when the psd4xx is not accessed b y the microcontroller . data byte enable microcontrollers ha v e diff erent data b yte or ientations with regard to the data b us . the f ollo wing tab les sho w ho w the psd4xx handles the b yte enab le under diff erent b us configur ations . ev en b yte ref ers to locations with address a0 equal to ?? and odd b yte as locations with a0 equal to ?? bhe a0 d7 ?d0 x 0 ev en byte x 1 odd byte t able 7. 8-bit data bus t able 8. 16-bit data bus w ith bhe bhe a0 d15 ?d8 d7 ?d0 0 0 odd b yte ev en b yte 0 1 odd b yte 1 0 ev en b yte wrh wrl d15 ?d8 d7 ?d0 0 0 odd b yte ev en b yte 0 1 odd b yte 1 0 ev en b yte t able 9. 16-bit data bus w ith wrh and wrl si z 0 a0 d15 ?d8 d7 ?d0 0 0 ev en b yte odd b yte 1 0 ev en b yte 1 1 odd b yte t able 10. 16-bit data bus w ith siz0, a0 lds uds d15 ?d8 d7 ?d0 0 0 ev en b yte odd b yte 1 0 ev en b yte 0 1 odd b yte t able 11. 16-bit data bus w ith uds, lds bus interface (cont.)
psd4xx family 4-38 psd4xx family figur e 19. multiplexed bus, 8 or 16-bit data bus micro- controller ad ? [ 7:0 ] ad ? [ 15 : 8 ] a ? [ 15 : 8 ] a ? [ 7:0 ] a ? [ 15 : 8 ] (optional) (optional) adio port port e wr rd rst csi bhe ale port c port d port a port b psd4xx bus inter face (cont.)
psd4xx family 4-39 psd4xx family figur e 20. adio por t, 16-bit multiplexed bus inter face ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 adio? adio? adio? adio? adio? adio? adio? adio? adio? adio? adio?0 adio?1 adio?2 adio?3 adio?4 adio?5 r_w ale / as psd4xx internal address bus psd4xx internal data bus latch g latch g bus inter face (cont.)
psd4xx family 4-40 psd4xx family figur e 21. non-multiplexed, 8 or 16-bit data micro- controller d ? [ 15 : 0 ] a ? [ 15 : 0 ] d ? [ 15 : 8 ] d ? [ 7 : 0 ] a [ 23 :16 ] (optional) adio port port e wr rd rst csi bhe ale port c port d port a port b psd4xx 16-bit data only bus inter face (cont.)
psd4xx family 4-41 psd4xx family optional features the psd4xx pro vides tw o optional f eatures to add fle xibility to the bus interf ace: 1. addr ess in p or t a can be configured as high order address (a16-a23) inputs to the zpld f or epr om or other decoding. inputs are latched b y ale/as if multiple x ed bus is selected. other p or ts can be configured as address input por ts f or the zpld . these inputs should not be used f or epr om decoding and are not latched inter nally . 2. addr ess out f or m ultiple x ed b us only . latched address lines a0-a15 are a v ailab le on p or t a, b , c or d . details on the optional f eatures are descr ibed in the i/o p or t section. bus inter face (cont.) bus interface examples the ne xt f our figures sho w the psd4xx interf acing with some popular microcontrollers . the e xamples sho w only the basic b us connections; some of the pin names on the psd4xx par ts change to reflect the actual pin functions . figure 22 sho ws the interf ace to the 80c31. the 80c31 has a 16 bit address b us and an 8-bit data b us . the lo w er address b yte is m ultiple x ed with the data b us . the rd and wr signals are used f or accessing the data memor y (sram) and the psen signal is f or reading prog r am memor y (epr om). the ale signal is activ e high and is used to latch the address inter nally . p or t c pro vides latched address outputs a [7:0]. p or ts a, b , d , and e (pe2-pe7) can be configured to perf or m other functions . the rst out reset to the 80c31 is gener ated b y the zpld from the reset input. this configur ation eliminates an y reset r ace condition betw een the 80c31 and the psd4xx. figure 23 sho ws the 68hc11 interf ace , which is similar to the 80c31 e xcept the psd4xx gener ates inter nal rd and wr from the 68hc11 s e and r / w signals . in figure 24, the intel 80c196 microcontroller is interf aced to the psd4xx. the 80c196 has a m ultiple x ed 16-bit address and data b us . the bhe signal is used f or data b yte selection. p or ts c and d are used as output por ts f or latched address a [15:0]. pins pe6 and pe7 can be prog r ammed as zpld outputs to pro vide the read y and b uswidth control signals to the 80c196. figure 25 sho ws motorola s mc68331 interf acing to the psd4xx. the mc68331 has a 16-bit data b us and a 24-bit address b us . d15 ?d8 from the mc68331 are connected to p or t d , and d7 ?d0 are connected to p or t c .
psd4xx family 4-42 psd4xx family figur e 22. inter facing psd4xx w ith 80c31 ea / vp x1 x2 reset int0 int1 t0 t1 p1 . 0 p1 . 1 p1 . 2 p1 . 3 p1 . 4 p1 . 5 p1 . 6 p1 . 7 ad0 /a0 ad1/a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11/a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 rd wr reset csi clkin pe0 / psen pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale / p txd rxd pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 31 19 18 9 12 13 14 15 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 80c31 ad [ 7:0 ] ad [ 7:0 ] reset rstout clock reset clock psd4xx rd wr psen ale 1 2 3 4 5 6 7 8 bus inter face (cont.)
psd4xx family 4-43 psd4xx family xt ex reset irq xirq modb pa0 pa1 pa2 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl ad0 /a0 ad1/a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11/a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 e r / w reset csi clkin pe0 pe1 / ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda e as r / w pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 8 7 17 19 18 2 34 33 32 43 44 45 46 47 48 49 50 52 51 31 30 29 28 27 42 41 40 39 38 37 36 35 9 10 11 12 13 14 15 16 20 21 22 23 24 25 3 5 4 6 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 68hc11 psd4xx ad [ 7 : 0 ] ad [ 7 : 0 ] clock reset e ale r / w clock ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 reset figur e 23. inter facing psd4xx w ith 68hc11 bus inter face (cont.)
psd4xx family 4-44 psd4xx family figur e 24. inter facing psd4xx w ith 80c196 x1 nmi ready cde buswidth reset ach0 / p0 . 0 ach1 / p0 . 1 ach2 / p0 . 2 ach3 / p0 . 3 ach4 / p0 . 4 ach5 / p0 . 5 pcs6 / p0 . 6 pcs7/ p0 . 7 p2 . 0 / txd p2 . 1 / rxd p2 . 2 / exint p2 . 3 / t2clk p2 . 4 / t2rst p2 . 5 / pwm p2 . 6 / t2up ?dn p2 . 7/ t2cap hsi .0 hsi .1 hsi .2 / hso .4 hsi .3 / hso .5 vref angnd ea ad0 /a0 ad1 /a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11 /a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 rd wr reset csi clkin pe0 / bhe pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby x2 p3 . 0 /ad0 p3 . 1 /ad1 p3 . 2 /ad2 p3 . 3 /ad3 p3 . 4 /ad4 p3 . 5 /ad5 p3 . 6 /ad6 p3 . 7/ad7 p4 . 0 /ad8 p4 . 1 /ad9 p4 . 2 /ad10 p4 . 3 /ad11 p4 . 4 /ad12 p4 . 5 /ad13 p4 . 6 /ad14 p4 . 7/ad15 rd wr bhe ale inst clkout p1 .0 p1 .1 p1 .2 p1 .3 p1 .4 p1 .5 p1 .6 p1 .7 hso .0 hso .1 hso .2 hso .3 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 11 3 43 14 64 16 6 5 7 4 11 10 8 9 18 17 15 44 42 39 33 38 24 25 26 27 13 12 2 12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 61 40 41 62 63 65 59 58 57 56 55 48 47 46 50 49 44 43 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 reset d [ 15 : 0 ] d [ 15 : 0 ] reset ready buswidth rd wr bhe ale clkout psd4xx 80c196 bus inter face (cont.)
psd4xx family 4-45 psd4xx family figur e 25. inter facing psd4xx w ith motor ola 68331 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 reset dsack0 dsack1 irq1 irq2 irq3 irq4 irq5 irq6 irq7 ad0 / a0 ad1 / a1 ad2 / a2 ad3 / a3 ad4 / a4 ad5 / a5 ad6 / a6 ad7 / a7 ad8 / a8 ad9 / a9 ad10 / a10 ad11 / a11 ad12 / a12 ad13 / a13 ad14 / a14 ad15 / a15 ds r / w reset csi clkin pe0 / siz0 pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 cs6 a20 cs7 a21 cs8 a22 cs9 a23 cs10 as r w ds siz0 siz1 clkout csboot br cs0 bg cs1 bgack cs2 fc0 cs3 fc1 cs4 fc2 cs5 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 d0 111 d1 110 d2 109 d3 108 d4 105 d5 104 d6 103 d7 102 d8 100 d9 99 d10 98 d11 97 d12 94 d13 93 d14 92 d15 91 68 89 88 77 76 75 74 73 72 71 d0 111 d1 110 d2 109 d3 108 d4 105 d5 104 d6 103 d7 102 d8 100 d9 99 d10 98 d11 97 d12 94 d13 93 d14 92 d15 91 68 89 88 77 76 75 74 73 72 71 90 20 21 22 23 24 25 26 27 30 31 32 33 35 36 37 38 41 42 121 122 123 124 125 82 79 85 81 80 66 112 113 114 115 118 119 120 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 ale rw ds siz0 clkout d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 reset d [ 15 : 0 ] d [ 15 : 0 ] a [ 18 : 0 ] a [ 18 : 0 ] reset psd4xx mc68331 bus inter face (cont.)
psd4xx family 4-46 psd4xx family there are 5 prog r ammab le 8-bit i/o por ts: p or t a, p or t b , p or t c , p or t d and p or t e. these por ts all ha v e m ultiple oper ating modes , depending on the configur ation. some of the basic functions are pro viding input/output f or the zpld , or can be used f or standard i/o . each por t pin is individually configur ab le , thus enab ling a single 8-bit por t to perf or m m ultiple func - tions . the i/o por ts occup y 256 b ytes of memor y space as defined b y ?siop? ref er to the system configur ation section f or i/o register address offset. t o set up the por t configur ation the user is required to: 1. define i/o p or t chip select (csiop) in the abel file . 2. initializ e cer tain por t configur ation registers in the user s prog r am and/or 3. specify the configur ation in the psd4xx psdsoft softw are . 4. un used input pins should be tied to v cc or gnd . the f ollo wing is a descr iption of the oper ating modes of the i/o por ts . the functions of the por t registers are descr ibed in later sections . standard mcu i/o the standard mcu i/o mode pro vides additional i/o capability to the microcontroller . in this mode , the por ts can perf or m standard i/o functions such as sensing or controlling v ar ious e xter nal i/o de vices . oper ation options of this mode are as f ollo ws: o configuration 1. declare pins or signals which are used as i/o in the abel file . 2. set the bit or bits in the control register to "1". 3. as output por t wr ite output data to data out register set direction register to output mode 4. as input por t set direction register to input mode read input from data in register the por t remains an output or input por t as long as the direction register is not changed. pld i / o the pld i/o mode enab les the por t to be configured as an input to the zpld , or as an output from the gpld macrocell. the output can be tr i-stated with a control signal defined b y a product ter m from the zpld . this mode is configured b y the user in the psd4xx psdsoft softw are , and is enab led upon po w er up . f or a detailed descr iption, see the section on the zpld . o configuration 1. declare pins or signals in the abel file (psdsoft). 2. wr ite logic equations in the abel file . 3. psd compiler maps the pld functions to the psd . i/o por ts
psd4xx family 4-47 psd4xx family i/o por ts (cont.) address out f or microcontrollers with a m ultiple x ed address/data b us , the i/o por ts in address-out mode are ab le to pro vide latched address outputs (a0 ?a15) to e xter nal de vices . this mode of oper ation requires the user to: o configuration 1. declare the pins used as address line outputs in the abel file (psdsoft). 2. wr ite ??to the corresponding bit in the control register associated with each i/o por t. 3. set the direction register to output mode . address in there are tw o address in modes: 1. f or p or t a - as other address line (a2-a7 and a16-a23) inputs to the dpld . additional address inputs included in the epr om decoding m ust come from p or t a. the address inputs are latched inter nally b y ale/as if multiple x ed bus is specified in psdsoft. 2. f or p or ts c and d ? as address inputs to the zpld f or gener al decoding, should not be used in epr om decoding. o configuration 1. declare pins or signals used as address in in the abel file (psdsoft). 2. wr ite latch equations in the .abl file , e .g., a16.le = ale. 3. include latched address in logic equations . data port in this mode , the por t is acting as a data b us por t f or a microcontroller which has a non-m ultiple x ed address/data b us . the data p or t is connected to the data b us of the microcontroller and the adio por t is connected to the address b us . o configuration select the non-m ultiple x ed b us option in psd configur ation (psdsoft). alternate function in this mode is per-pin configur ab le and enab les the user to define pin pe7 of p or t e as a utomatic p o w er do wn (apd) clk input. o configuration 1. select input functions in psd configur ation. 2. psd compiler assigns pins f or the selected options .
psd4xx family 4-48 psd4xx family table 12. operating modes of the i / o ports t ab le 12 summar iz es the oper ating modes of the i/o por ts . not all the functions are a v ailab le to e v er y por t. por t mode por t a por t b por t c por t d por t e standard mcu i/o y es y es y es y es y es pld i/o y es y es input only * input only * y es * address out y es y es y es y es y es address in y es y es ** y es ** y es ** data p or t y es y es alter nate function in y es p er ipher al i/o y es open dr ain y es y es * psd4xxa2 only . ** f or e xter nal decoding. cannot be latched b y ale peripheral i/o this mode enab les the microcontroller to read or wr ite to a per ipher al though p or t a. when there is no read/wr ite oper ation, p or t a is tr i-stated. one of the applications of p er ipher al i/o is in a dma based design. o configuration 1. declare the pins used as pher ipher al i/o in the abel file . 2. wr ite logic equations f or psel0 and psel1. 3. wr ite a ??to the pio bit in the vm register to activ ate the p er ipher al i/o oper ation. see the section on p er ipher al i/o f or a detailed descr iption. open drain outputs this mode enab les the user to configure p or ts c and d pins as open dr ain outputs . cmos output is the def ault configur ation. wr iting ??to the corresponding bit in the open dr ain register changes the pin to open dr ain output. i/o por ts (cont.)
psd4xx family 4-49 psd4xx family port registers there are tw o sets of registers per i/o por t: the p or t configur ation registers (pcr) which consist of f our 8-bit registers; and the p or t data registers (pdr) which include three 8-bit registers . the pcr is used f or setting up the por t configur ation, while the pdr enab les the microcontroller to wr ite or read por t data or status bits . t ab les 13 and 14 sho w the names and the registers and the por ts to which the y belong. all the registers in the pcr and pdr are 8-bits wide and each bit is associated with a pin in the i/o por t. in t ab le 15, the lsb of the data in register of p or t a is connected to pin p a0, and the msb is connected to p a7. this pin configur ation also applies to other registers and por ts . f or e xample , in the direction register of p or t a, wr iting a he x v alue of 07 to the register configures pins p a0 ?p a2 as output pins , while p a3 ?p a7 remain as input pins . registers can be accessed b y the microcontroller dur ing nor mal read/wr ite b us cycles . the i/o address offset of the registers are listed in the system configur ation section. i/o ports (cont.) register name por t w rit e / read control register a,b ,c ,d ,e wr it e /read direction register a,b ,c ,d ,e wr it e /read open dr ain register c ,d wr it e /read pld ?i/o register a,b ,e read table 13. port configuration registers (pcr) register name por t rea d / w rit e data in register a,b ,c ,d ,e read data out register a,b ,c ,d ,e wr it e /read macrocell out register a,b ,e read t able 14. por t data registers ( pd r ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p a7 pin p a6 pin p a5 pin p a4 pin p a3 pin p a2 pin p a1 pin p a0 pin t able 15. data in register ?por t a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p a7 pin p a6 pin p a5 pin p a4 pin p a3 pin p a2 pin p a1 pin p a0 pin = 0 = 0 = 0 = 0 = 0 = 1 = 1 = 1 dir ection register ?por t a ( example: pins p a0 ?p a2 as outpu t , p a3 ?p a7 as inpu t )
psd4xx family 4-50 contr ol register this register is used in both standard mcu i/o mode and address out modes . f or setting a standard mcu i/o mode , a ??m ust be wr itten to the corresponding bit in the register . wr iting a ??to the register is required f or the address out mode . the register has a def ault v alue of ??after reset. dir ection register this register is used to control the direction of data flo w in the i/o p or ts . wr iting a ??to the corresponding bit in the register configures the por t to be an output por t, and a ??f orces the por t to be an input por t. the i/o configur ation of the por t pins can be deter mined b y reading the direction register . after reset, the pins are in input mode . open drain this register deter mines whether the output pin dr iv er of p or ts c or d is a cmos dr iv er or an open dr ain dr iv er . wr iting a ??to the register selects a cmos dr iv er , while a ??selects an open dr ain dr iv er . pld ?i/o register this is a read only status register . reading a "1" indicates the corresponding pin is configured as a pld pin. a "0" indicates the pin is an i/o pin. data in register this register is used in the standard mcu i/o mode configur ation to read the input pins . data out register this register holds the output data in the standard mcu i/o mode . the contents of the register can also be read. macr ocell out register this register enab les the user to read the outputs of the gpld macrocell (p a, pb , and pe macrocells). i/o register addr ess of fset the i/o register can be accessed b y the microcontroller dur ing nor mal read/wr ite b us cycles . the address of a register is defined as: csiop + register address offset the csiop is the base address that is defined in the abel file and occupies a 256 b yte space . the register address offset lies within this 256 b yte space . t ab les 16 and 16a are the address offset of the registers . i/o por ts (cont.)
t able 16a. register addr ess of fset (f or 16-bit motorola microcontrollers in 16-bit mode . use t ab le 16 if 8-bit mode is selected.) psd4xx family 4-51 addr ess of fset register name por t a por t b por t c por t d por t e data in 00 01 10 11 20 control 02 03 12 13 22 data out 04 05 14 15 24 direction 06 07 16 17 26 open dr ain 18 19 pld ?i/o 0a 0b 2a macrocell out 0c 0d 2c (psd4xxa2) t able 16. register addr ess of fset i/o por ts (cont.) addr ess of fset register name por t a por t b por t c por t d por t e data in 01 00 11 10 21 control 03 02 13 12 23 data out 05 04 15 14 25 direction 07 06 17 16 27 open dr ain 19 18 pld ?i/o 0b 0a 2b macrocell out 0d 0c 2d (psd4xxa2)
psd4xx family 4-52 psd4xx family por t a ? functionality and str uctur e p or t a is the most fle xib le of all the i/o por ts . it can be configured to perf or m one or more of the f ollo wing functions: o standard mcu i/o mode o pld i/o o address out ? latched address lines a [0- 7 ] are assigned to pins p a[0- 7 ]. o address in ? input por t f or other address lines , inputs can be latched b y ale. o p er ipher al i/o figure 26 sho ws the str ucture of a p or t a pin. if the pin is configured as an output por t, the m ultiple x er selects one of its three inputs as output. if the pin is configured as an input, the input connects to : 1. data in register as input in standard mcu i/o mode or 2. p a macrocell as pld input or 3. p a macrocell through a latch latched b y ale, as address in input. por t b ? functionality and str uctur e p or t b is similar to p or t a in str ucture . it can be configured to perf or m one or more of the f ollo wing functions: o standard mcu i/o mode o pld i/o o address out ? address lines a[0-7] f or 8-bit m ultiple x ed b us or address lines a[8-15] f or 16-bit m ultiple x ed b us are assigned to pins pb[0- 7 ]. figure 27 sho ws the str ucture of a p or t b pin. if the pin is configured as an output por t, the m ultiple x er selects one of its three inputs as output. if the pin is configured as input, the input connects to : o data in register as input in standard mcu i/o mode or o pb macrocell as pld input i/o por ts (cont.)
psd4xx family 4-53 psd4xx family figur e 26. por t a pin str uctur e mux pdr port a pin d q d g q d q control gpld input pcr ale wr ale pa . oe gpld output ale wr internal address / data bus data out address pcr dir. reg. latch a [ 0 ?7 ] i/o por ts (cont.)
psd4xx family 4-54 psd4xx family i/o por ts (cont.) figur e 27. por t b pin str uctur e mux pdr port b pin d q d g q d q control gpld input pcr wr ale pb .oe gpld output ale wr data out address pcr dir. reg. a [0 ?7 ] or a [8 ?15 ] internal address / data bus
psd4xx family 4-55 psd4xx family i/o por ts (cont.) port c and port d ? functionality and structure p or ts c and d are identical in function and str ucture and each can be configured to perf or m one or more of the f ollo wing oper ating modes: o standard mcu i/o mode o pld input ? direct input to zpld (psd4xxa2 only) o address out ? latched address outputs p or t c: a[0- 7 ] are assigned to pins pc[0- 7 ] p or t d: a[0-7] f or 8-bit m ultiple x ed b us or a[8-15] f or 16-bit m ultiple x ed b us are assigned to pins pd0- 7 ] o data p or t p or t c: d[0-7] f or 8-bit non-m ultiple x ed b us p or t d: d[8-15] f or 16-bit non-m ultiple x ed b us o open dr ain ? select cmos or open dr ain dr iv er figures 28 and 29 sho w the str ucture of a p or t c or d pin. if the pin is configured as output por t, the m ultiple x er selects one of the tw o inputs as output. if the pin is configured as input, the input connects to : o data in register as input in the standard mcu i/o mode or o zpld input (psd4xxa2 only) port e ? functionality and structure p or t e can be configured to perf or m one or more of the f ollo wing functions: o standard mcu i/o mode o pld i/o (psd4xxa2 only) o address out ? latched address lines a[0- 7 ] are assigned to pins p e [0- 7 ] o alter nate function in ? in this mode , the inputs to p or t e pins are: pe0 bhe or psen or wrh or uds or siz0 pe1 ? ale pe7 apd clk :cloc k input f or a utomatic p o w er do wn counter figure 30 sho ws the str ucture of a p or t e pin. the control logic b loc k selects one of f our sources through the m ultiple x er f or pin output. if the pin is configured as input, the input goes to: o data in register as input in standard mcu i/o mode or o pe macrocell as pld input (psd4xxa2 only) or o alter nate function in
psd4xx family 4-56 psd4xx family figur e 28. por t c pin str uctur e mux pdr port c pin d q d g q d q control gpld input ** pcr wr ale ale wr data * data out address pcr dir. reg. d [ 0 7 ] a [ 0 7 ] internal address / data bus * data bus d [0 ? ] is not connected to gpld?nput. **gpld ?nput is available on a2 versions only. i/o por ts (cont.)
psd4xx family 4-57 psd4xx family figur e 29. por t d pin str uctur e mux pdr port d pin d q d g q d q control gpld input ** pcr wr ale ale wr data * data out address pcr dir. reg. d [8 ?5] a [ 0 7 ] or a [8 ?5] internal address / data bus * data bus d [ 8?5 ] is not connected to gpld?nput. **gpld?nput is available on a2 versions only. i/o por ts (cont.)
psd4xx family 4-58 psd4xx family figur e 30. por t e pin str uctur e mux pdr port e pin d q d g q d q control gpld input * alt func. in pcr wr ale pe .oe gpld output ale wr data out address pcr dir. reg. internal address / data bus *gpld?nput is available on a2 versions only. i/o por ts (cont.)
psd4xx family 4-59 psd4xx family the psd4xx pro vides epr om memor y f or code stor age and sram memor y f or scr atch pad usage . chip selects f or the memor y b loc ks come from the dpld decoding logic and are defined b y the user in the psdsoft softw are . figure 31 sho ws the organization of the memor y bloc k. eprom the psd4xx pro vides three epr om densities: 256k bit, 512k bit or 1m bit. the epr om is divided into f our 8k, 16k or 32k b yte b loc ks . each b loc k has its o wn chip select signals (es0 ?es3). the epr om can be configured as 32k x 8, 64k x 8 or 128k x 8 f or microcontrollers with an 8-bit data b us . f or 16-bit data b uses , the epr om is configured as 16k x 16, 32k x 16 or 64k x 16. sram the sram has 16k bits of memor y , organiz ed as 2k x 8 or 1k x 16. the sram is enab led b y chip select signal rs0 from the dpld . the sram has a batter y bac k-up (stby) mode . this bac k-up mode is in v ok ed when the v cc v oltage drops under the vstdb y v oltage b y appro ximately 0.7 v . the vstdb y v oltage is connected only to the sram and cannot be lo w er than 2.7 v olts . memor y select map the epr om and sram chip select equations are defined in the abel file in ter ms of address and other dpld inputs . the memor y space f or the epr om chip select (es0 es3) should not be larger than the epr om b loc k (8kb , 16kb , or 32kb) it is selecting. the f ollo wing r ules go v er n ho w the inter nal psd4xx memor y selects/space are defined: o the epr om b loc ks address space cannot o v er lap o sram, inter nal i/o and p er ipher al i/o space cannot o v er lap o sram, inter nal i/o and p er ipher al i/o space can o v er lap epr om space , with pr ior ity giv en to sram or i/o . the por tion of epr om which is o v er lapped cannot be accessed. the p er ipher al i/o space ref ers to memor y space occupied b y per ipher als when p or t a is configured in the p er ipher al i/o mode . memor y block
psd4xx family 4-60 memor y select map for 8031 application the 8031 f amily of microcontrollers has separ ate code memor y space and data memor y space . this f eature requires a diff erent memor y select map . t w o modes of oper ation are pro vided f or 8031 applications . the selection of the modes is specified in the psd4xx psdsoft softw are (psdconfigur ation): o separate space mode in this mode , the psen signal is used to access code from epr om, and the rd signal is used to access data from sram. the code memor y space is separ ated from the data memor y space . o combined space mode in this mode , the epr om can be accessed b y psen or rd . the epr om is used f or code and data stor age . the memor y b loc k's address space cannot o v er lap . if data and code memor y b loc ks m ust o v er lap each other , the rd signal can be included as an additional address input in gener ating the epr om chip select signals (es0 ?es3). in this case the epr om access time is from the rd v alid to data v alid. figures 32a and 32b sho w the memor y configur ation in the tw o modes . in some applications it is desir ab le to e x ecute prog r am codes in sram. the psd4xx pro vides this option b y enab ling psen to access sram. t o activ ate this option, the srcode bit of the vm register m ust be set to ??(see t ab le 17). sram space can o v er lap epr om space and has pr ior ity when psen is used. memor y block (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * * * * * * srcode pio 1 = on 1 = on * = reser v ed f or future use , bits set to z ero . t able 17. vm register
psd4xx family 4-61 figur e 31. memor y block diagram ( 128kb eprom ) es0 es1 es2 es3 16k x 8 16k x 8 1k x 8 1k x 8 16k x 8 16k x 8 16k x 8 16k x 8 16k x 8 16k x 8 sram block rs0 odd byte odd byte d [ 8 ?15 ] even byte d [ 0 ?7 ] eprom blocks memor y block (cont.)
psd4xx family 4-62 psd4xx family figur e 32a. 8031 memor y modes eprom dpld sram es0 es1 es2 es3 rs0 rd oe oe srcode en psen separate space mode memor y block (cont.) figure 32b. 8031 memory modes eprom dpld sram es0 es1 es2 es3 rs0 psen rd rd oe oe srcode en psen rd combined space mode
psd4xx family 4-63 psd4xx family the p er ipher al i/o mode is one of the oper ating modes of p or t a. in this mode , p or t a is connected to the data b us of per ipher al de vices . p or t a is enab led only when the microcontroller is accessing the de vices , otherwise the p or t is tr i-stated. this f eature enab les the microcontroller to access e xter nal de vices without requir ing b uff ers and decoders . figure 33 sho ws the str ucture of p or t a in the p er ipher al i/o mode . the memor y address space occupied b y the de vices are defined b y tw o signals: psel0 and psel1. the signals are direct outputs from the decoding pld (dpld). whene v er an y of the signals is activ e , the p or t a dr iv er is enab led, and the direction of the data flo w is deter - mined b y the rd/wr signals . the p er ipher al i/o mode and the per ipher al select signals are configured and defined in the psdsoft softw are (see the section on i/o p or t f or configur ation). the pio bit in the vm register (see t ab le 17) also needs to be set to ??b y the user to initializ e the p er ipher al i/o mode . the p er ipher al i/o mode can be used, f or e xample , in dma applications where the microcontroller does not suppor t dma oper ations , such as tr i-stating the address/data b us . figure 34 sho ws a b loc k diag r am of a microcontroller and psd4xx based design that mak es use of this mode . in this application, the microcontroller has a m ultiple x ed b us which is connected to the adio por t. the c and d por ts connect to the per ipher al address b us and are both configured in address out mode . p or t a is configured in the p er ipher al i/o mode and is connected to the per ipher al data b us . p or ts b and e are used to gener ate control signals . dur ing nor mal activity , the microcontroller has access to an y per ipher al (memor y or i/o de vice) through the psd4xx de vice . when there is a dma request, the microcontroller tr i-states the address b us on p or ts c and d b y wr iting a ??to the por t direction registers . the dma controller then tak es o v er the data and address b uses after receiving ac kno wledgement from the microcontroller . peripheral i / o figure 33. port a in peripheral i / o mode rd psel0 psel1 d0 ?d 7 wr pa0 ?pa7
psd4xx family 4-64 figur e 34. psd4xx peripheral i/o configuration micro- controller ad [ 0 ?7 ] a [ 8 ?5 ] a [ 0 ?7 ] a [ 8 ?15 ] d [ 0 ?7 ] dma ack adio port port e wr rd rst csi bhe ale port c port d port a port b psd4xx memory i / o device dma controller peripheral # 1 peripheral # 2 dma req rd wr csi peripheral i / o
psd4xx family 4-65 psd4xx family page register the p age register is 4 bits wide and consists of f our d flip flops .the outputs of the register (pgr0 ?pgr3) are connected to the input b us of the zpld . by including the f our outputs as inputs to the dpld , the addressing capability of the microcontroller is increased b y a f actor of 16. figure 35 sho ws the p age register b loc k diag r am. inputs to the f our flip flops are connected to data b us d0-d3. the output of the register can be read b y the microcontroller . the register can oper ate as an independent register to the microcontroller if page mode is not implemented. the psd4xx has a prog r ammab le secur ity bit which off ers protection from unauthor iz ed duplication. when the secur ity bit is set, the contents of the epr om, the psd4xx non-v olatile configur ation bits and zpld data cannot be read b y epr om prog r ammers . the secur ity bit is set through the psdsoft softw are and is embedded in the compiled output file . the secur ity bit is uv er asab le and a secured par t can be er ased and then re-prog r ammed. security pr otection figur e 35. page register dpld rs0 gpld zpld es0 ?3 pgr0 pgr1 pgr2 pgr3 r / w d0 d0 ?d3 d1 d2 d3 q0 q1 q2 q3 page reg. reset
psd4xx family 4-66 the psd4xx pro vides man y po w er sa ving options . by configur ing the pmmrs (p o w er management mode registers), the user can reduce po w er consumption. t ab le 18 sho ws the bit configur ation of the pmmr0 and pmmr1. the microcontroller is ab le to control the po w er consumption b y changing the pmmr bits at r un time . standby mode there are tw o standb y modes in the psd4xx: o power down mode o sleep mode power down mode in this mode , the inter nal de vices are shut do wn e xcept f or the i/o por ts and the zpld . there are three w a ys the psd4xx can enter into the p o w er do wn mode: b y controlling the csi input, b y activ ating the a utomatic p o w er do wn (apd) logic , the counter/timers , the interr upt controller and the zpld , or when none of the inputs are changing and the t urbo bit is off . o the csi the csi input pin is an activ e lo w signal. when lo w , the signal selects and enab les the psd4xx. the psd4xx enters into p o w er do wn mode immediately when the signal tur ns high. this signal can be controlled b y the microcontrollers , e xter nal logic or it can be g rounded. the csi input tur ns off the inter nal b us b uff ers in standb y mode . the address and control signals from the microcontroller are b loc k ed from enter ing the zpld as inputs . o the apd logic the apd unit enab les the user to enter a po w er do wn mode independent of controlling the csi input. this f eature eliminates the need f or e xter nal logic (decoders and latches) to po w er do wn the psd . the apd unit concept is based on tr ac king the activity on the ale pin. if the apd unit is enab led and ale is not activ e , the 4-bit apd counter star ts counting and will o v erflo w after 15 cloc ks , gener ating a pd (p o w er do wn) signal po w er ing do wn the psd . if sleep mode is enab led, then pd signal will also activ ate the sleep mode . immediately after ale star ts pulsing the psd will get out of the po w er do wn or sleep mode . the oper ation of apd is controlled b y the pmmr (see figure 36a). pmmr1 bit 0 selects the source of the apd counter cloc k. after reset the apd counter cloc k is connected to pe7 (apd clk) on the psd . in order to guar antee that the apd will not o v erflo w there should be less than 15 apd cloc ks betw een tw o ale pulses . if clkin frequency is adequate , then it can be connected to the apd and pe7 is used f or other functions . the ne xt step is to select the ale po w er do wn polar ity . usually , mcus enter ing po w er do wn will freez e their ale at logic high or lo w . by prog r amming bit 1 of pmmr0 the po w er do wn polar ity can be defined f or the apd . if the apd detects that the ale is in the po w er do wn polar ity f or 15 apd counter cloc ks then the psd will enter a po w er do wn mode . t o enab le the apd oper ation, bit 2 in the pmmr0 should be set high. sleep mode the sleep mode is activ ated if the sleep en bit, the apd en bit, and the ale p olar ity bit in the pmmr are set, and the apd counter has o v erflo w ed after 15 cloc ks (see figure 36). in sleep mode the psd4xx consumes less po w er than the p o w er do wn mode , with typical i cc reduced to 10 a. in this mode , the zpld still monitors the inputs and responds to them. as soon as the ale star ts pulsing, the psd4xx e xits the sleep mode . the psd access time from sleep mode is specified b y t l vd v1 . the zpld response time to an input tr ansition is specified b y t l vd v2 . power management unit
psd4xx family 4-67 clr clk apd counter apd clk pmmr1 - bit 0 to other circuits mux apd clear logic apd enable pmmr0 - bit 2 ale polarity pmmr0 - bit 1 ale reset apd clk clkin csi sleep enable pmmr1 - bit 1 sleep mode eprom select sram select i/o select power down pd z p l d figur e 36. power management unit figur e 36a. automatic power down unit (apd) flow char t apd disabled need apd clk yes yes no no reset set apd clk in pmmr1 bit 0 set ale pd polarity in pmmro bit 1 csi = "1" need sleep mode set sleep mode in pmmr1 bit 1 ale idle and 15 apd clock ale idle and 15 apd clock ?set enable apd in pmmr0 bit 2 ?set pmmr0 bit 0 ?set enable apd in pmmr0 bit 2 ?set pmmr0 bit 0 disable clocks zpld aclk, zpld rclk, tmr zpld disable clocks zpld aclk, zpld rclk, tmr zpld psd in power down mode psd in sleep mode power management unit (cont.)
psd4xx family 4-68 apd en bit ale power ale status apd counter down polarity 0 x x not counting 1 x pulsing not counting 1 1 1 counting (activ ates standb y mode after 15 cloc ks) 1 0 0 counting (activ ates standb y mode after 15 cloc ks) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr clk zpld zpld zpld apd ale pd * rclk a clk turbo cmiser enable p olar ity 1 = off 1 = off 1 = off 1 = off 1 = on 1 = on 1 = high pmmr0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * * * * * * sleep apd clk mode 1 = on 1 = clkin pmmr1 t able 18. power management mode registers (pmmr0, pmmr1) t able 19. apd counter operation bit 0 * = should be set to high (1) to oper ate the apd . bit 1 0 = ale p o w er do wn (pd) p olar ity lo w . 1 = ale p o w er do wn (pd) p olar ity high. bit 2 0 = a utomatic p o w er do wn (apd) disab le . 1 = a utomatic p o w er do wn (apd) enab le . bit 3 0 = epr om/sram cmiser is off . 1 = epr om/sram cmiser is on. bit 4 0 = zpld t urbo is on. zpld is alw a ys on. 1 = zpld t urbo is off . zpld will p o w er do wn when inputs are not changing. bit 5 0 = zpld cloc k input into the arr a y from the clkin pin input is connected. ev er y cloc k change will p o w er up the zpld when t urbo bit is off . 1 = zpld cloc k input into the arr a y from the clkin pin input is disconnected. bit 6 0 = zpld cloc k input into the the macrocell registers from the clkin pin input is connected. 1 = zpld cloc k input into the the macrocell registers from the clkin pin input is disconnected. bit 7 * = in the psd4xx should be set to high (1) bit 0 0 = a utomatic p o w er do wn unit cloc k is connected to p or t e7 (pe7) alter nate function input. 1 = a utomatic p o w er do wn unit cloc k is connected to the psd cloc k input (clkin). bit 1 0 = sleep mode disab led. 1 = sleep mode enab led. bit 2 7 0 = reser v ed f or future use , should be set to z ero . power management unit (cont.)
psd4xx family 4-69 psd4xx family power management unit (cont.) other power saving options the psd4xx pro vides additional po w er sa ving options . these options , e xcept the sram standb y mode , can be enab led/disab led b y setting up the corresponding bit in the pmmr. o eprom the epr om po w er consumption in the psd is controlled b y bit 3 in the pmmr0 ?epr om cmiser . upon reset the cmiser bit is off . this will cause the epr om to be on at all times as long as csi is enab led (lo w). the reason this mode is pro vided is to reduce the access time of the epr om b y 10 ns relativ e to the lo w po w er condition when cmiser is on. if csi is disab led (high) the epr om will be deselected and will enter standb y mode (off) o v err iding the state of the cmiser . if cmiser is set (on) then the epr om will enter the standb y mode when not selected. this condition can tak e place when csi is high or when csi is lo w and the epr om is not accessed. f or e xample , if the mcu is accessing the sram, the epr om will be deselected and will be in lo w po w er mode . an additional adv antage of the cmiser is achie v ed when the psd is configured in the b y 8 mode (8 bit data b us). in this case an additional po w er sa vings is achie v ed in the epr om (and also in the sram) b y tur ning off 1/2 of the arr a y e v en when the epr om is accessed (the arr a y is divided inter nally into odd and e v en arr a ys). the po w er consumption f or the diff erent epr om modes is giv en in the dc char acter istics tab le under i cc (dc) epr om adder . o sram standby mode the sram has a dedicated supply v oltage v stby that can be used to connect a batter y . when v cc becomes lo w er than v stby 0.6 then the psd will automatically connect the v stby as a po w er source to the sram. the sram standb y current (i stby ) is typically 0.5 a. sram data retention v oltage v df is 2 v minim um. o zer o power zpld zpld po w er/speed is controlled b y the zpld_t urbo bit (bit 4) in the pmmr0. after reset the zpld is in t urbo mode and r uns at full po w er and speed. by setting the bit to ?? the t urbo mode is disab led and the zpld is consuming zero p o w er current if the inputs are not s witching f or an e xtended time of 70 ns . the propagation dela y time will be increased b y 10ns after the t urbo bit is set to ??(tur ned off) if the inputs change at a frequency of less than 15 mhz.
psd4xx family 4-70 psd4xx family power management unit (cont.) por t configuration pin status i/o p or t unchanged zpld output depend on inputs to the zpld address out undefined data p or t t r i-stated p er ipher al i/o t r i-stated t able 20. i / o pin status during power down and sleep mode o input clock the psd4xx pro vides the option to tur n off the cloc k inputs to sa v e a c po w er consumption. the cloc k input (clkin) is used as a source f or dr iving the f ollo wing modules: o zpld arr a y cloc k input o zpld macrocell cloc k flip flop o apd counter cloc k dur ing po w er do wn or if an y of the modules are not being used the cloc k to these modules should be disab led. t o reduce a c po w er consumption, it is especially impor tant to disab le the cloc k input to the zpld arr a y if it is not used as par t of a logic equation. the zpld arr a y cloc k can be disab led b y setting pmmr0 bit 5 (zpld a clk). the zpld macrocell cloc k input can be disab led b y setting pmmr0 bit 6 (zpld rclk). the timer cloc k can be disab led b y setting pmmr0 bit 7 (tmr clk). the apd counter cloc k will be disab led automatically if p o w er do wn or sleep mode is entered through the apd unit. the input b uff er of the clkin input will be disab led if bits 5 ?7 pmmr0 are set and the apd has o v erflo w ed. pld pld access access t ypical pr opagation recover y t ime recover y standby delay t ime t o t ime t o cur r ent nor mal nor mal consumed operation access p o w er nor mal t pd 0 no access t l vd v 40 a do wn (note 1) (note 4) sleep t l vd v2 t l vd v3 no access t l vd v1 5 a (note 2) (note 3) (note 5) summar y of psd4xx t iming and standby cur r ent during power down and sleep modes no tes: 1. p o w er do wn does not aff ect the oper ation of the zpld . the zpld oper ation in this mode is based only on the zpld_t urbo bit. 2. in sleep mode an y input to the zpld will ha v e a propagation dela y of t l vd v2 . 3. pld reco v er y time to nor mal oper ation after e xiting sleep mode . an input to the zpld dur ing the tr ansition will ha v e a propagation dela y time of t l vd v3 . 4. t ypical current consumption assuming all cloc ks are disab led and zpld is in non-turbo mode . 5. t ypical current consumption assuming all cloc ks are disab led.
psd4xx family 4-71 system configuration the csiop signal, which is gener ated b y the dpld , selects the inter nal i/o de vices or registers . the csiop signal tak es up 256 b ytes of address space and is defined b y the user in the psdsoft softw are . the f ollo wing is an address offset map f or the v ar ious de vices relativ e to the csiop base address . some motorola 16-bit microcontrollers ha v e a diff erent data b us/data b yte or ientation. this requires a diff erent address offset f or the inter nal psd4xx i/o de vices or registers . t ab les 21a and 22a in this section are f or this g roup of microcontrollers which include the m68hc16, m68302 and m683xx. register addr ess register addr ess name of fset name of fset p a ge register e0 vm c0 pmmr1 b1 pmmr0 b0 t able 21. register addr ess of fset t able 21a. register addr ess of fset (f or 16-bit motorola microcontrollers in 16-bit mode . use t ab le 21 if 8-bit mode is selected.) register addr ess register addr ess name of fset name of fset p a ge register e1 vm c1 pmmr1 b0 pmmr0 b1
psd4xx family 4-72 the f ollo wing tab le is the address map offset of the i/o por t registers . system configuration ( cont.) t able 22a. register addr ess of fset (f or 16-bit motorola microcontrollers in 16-bit mode . use t ab le 22 if 8-bit mode is selected.) addr ess of fset register name por t a por t b por t c por t d por t e data in 00 01 10 11 20 control 02 03 12 13 22 data out 04 05 14 15 24 direction 06 07 16 17 26 open dr ain 18 19 pld ?i/o 0a 0b 2a macrocell out 0c 0d 2c (psd4xxa2) t able 22. i/o register addr ess of fset addr ess of fset register name por t a por t b por t c por t d por t e data in 01 00 11 10 21 control 03 02 13 12 23 data out 05 04 15 14 25 direction 07 06 17 16 27 open dr ain 19 18 pld ?i/o 0b 0a 2b macrocell out 0d 0c 2d (psd4xxa2)
psd4xx family 4-73 psd4xx family system configuration ( cont.) register name register function data in this register is used to read the inputs on the por t pins . control a 0 sets the corresponding por t pin in address out mode . a 1 sets the pin in mcu i/o mode . data out holds the output data in the mcu i/o mode . this register is used to control the data flo w in the i/o por ts . direction a 0 sets the corresponding pin as an input pin. a 1 sets the pin as an output pin. open dr ain a 0 sets the corresponding pin dr iv er as a cmos dr iv er . a 1 sets the pin dr iv er as an open dr ain dr iv er . pld ?i/o a read only status register ; a 1 indicates the corresponding pin is configured as a pld pin. macrocell out this register holds the outputs of the gpld macrocells . p age register a 4-bit register that suppor ts paging. 1. configures the psd4xx sram to be accessed b y psen as vm prog r am space (8031 design). 2. enab les the p er ipher al i/o mode of p or t a. pmmr0 p o w er management registers; enab les the psd4xx p o w er do wn pmmr1 mode and other po w er sa ving configur ations . t able 23. register function
psd4xx family 4-74 psd4xx family reset input the reset input to the psd4xx (reset) is an activ e lo w signal which resets some of the inter nal de vices and configur ation registers . the timing diag r am in the a c/dc char acter ization section sho ws the reset signal timing requirement. the activ e lo w r ange has a minim um t1 dur ation. after the r ising edge of reset , the psd4xx remains in reset dur ing t2 r ange . (see figure 47). the psd4xx m ust be reset at po w er up bef ore it can be used. zpld and memor y during reset while the reset input is activ e , the zpld gener ates outputs as defined in the psdabel equations . the epr om and sram b loc ks respond to the microcontroller b us cycle dur ing reset, b ut the data is not guar anteed. register v alues during and after reset t ab le 24 summar iz es the status of the v olatile register v alues dur ing and after reset. the def ault v alues of the v olatile registers are ??after reset. zpld macr ocell initialization the d flip flops in the macrocells in the gpld can be cleared b y: o a product ter m (.re) defined b y the user in psdabel, or o the ma cr o-rst (reset) input, enab led and defined in psdabel. register name device reset state control p or t a, b , c , d , e set to ? (address out mode) data out (data or address) p or t a, b , c , d , e set to ?? direction p or t a, b , c , d , e set to ???input mode open dr ain p or t c , d set to ???cmos outputs p age register p age logic set to ? pmmr0, pmmr1 p o w er management unit set to ? vm v olatile memor y set to ? system configuration ( cont.) t able 24. registers reset v alues por t configuration reset stand-by mode p or t i/o input unchanged zpld output activ e depend on inputs to the zpld address out t r i-stated not defined data p or t t r i-stated t r i-stated p er ipher al i/o t r i-stated t r i-stated t able 25. i/o pin status during reset and standby mode
psd4xx family 4-75 psd4xx family symbol parameter condition min max unit t stg stor age t emper ature cldcc ?65 + 150 c pldcc ?65 + 125 c commercial 0 + 70 c oper ating t emper ature industr ial ?40 + 85 c militar y ?55 + 125 c v oltage on an y pin with respect to gnd ?0.6 + 7 v v pp prog r amming supply v oltage with respect to gnd ?0.6 + 14 v v cc supply v oltage with respect to gnd ?0.6 + 7 v esd protection > 2000 v absolute maximum rating s no te: stresses abo v e those listed under absolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at these or an y other conditions abo v e those indicated in the oper ational sections of this specification is not implied. exposure to absolute maxim um rating conditions f or e xtended per iods of time ma y aff ect de vice reliability . range t emperatur e v c c v c c t olerance -70 -90 -12 -15 -20 commercial 0 c to +70 c + 5 v 10% 10% 10% 10% 10% industr ial 40 c to +85 c + 5 v 10% 10% 10% militar y 55 c to +125 c + 5 v 10% symbol parameter condition min t yp max unit v cc supply v oltage all speeds 4.5 5 5.5 v operating range recommended operating conditions
psd4xx family 4-76 psd4xx family ac/dc parameters the f ollo wing tab les descr ibe the ad/dc par ameters of the psd4xx f amily: o dc electr ical specification o a c timing specification zpld timing combinator ial dela ys synchronous cloc k mode asynchronous cloc k mode microcontroller timing read timing wr ite timing p er ipher al mode timing p o w er do wn and reset timing f ollo wing are some issues concer ning the par ameters presented: o in the dc specification the supply current is giv en f or diff erent modes of oper ation. bef ore calculating the total po w er consumption, deter mine the percentage of time that the psd4xx is in each mode . also the supply po w er is consider ab ly diff erent if the zpld_turbo bit is "off" and epr om_cmiser is "on". o the a c po w er component giv es the zpld , epr om, and sram ma/mhz specification. figure 37 sho ws the zpld ma/mhz as a function of the n umber of product t er ms (pt) used. o in the zpld timing par ameters add the required dela y when zpld_turbo is "off". o in the mcu timing specification add the required time dela y when epr om_cmiser is "on". figur e 37a. zpld i c c /fr equency consumption (psd4xxa1 v ersions) 0 10 20 60 50 80 70 90 100 40 30 0 10 15 5 20 25 pt100% pt25% bus frequency (mhz) i cc ?(ma) 10 turbo on turbo on turbo off turbo off
psd4xx family 4-77 figur e 37b. zpld i c c /fr equency consumption (psd4xxa2 v ersions) 0 20 60 80 100 120 40 0 10 15 5 20 25 pt100% pt25% bus frequency (mhz) i cc ?(ma) turbo on turbo on turbo off turbo off
psd4xx family 4-78 symbol parameter conditions min t yp max unit v cc supply v oltage all speeds 4.5 5 5.5 v v i h high le v el input v oltage 4.5 v < v cc < 5.5 v 2 v cc +.5 v v i l lo w le v el input v oltage 4.5 v < v cc < 5.5 v 0.5 0.8 v v i h1 reset high le v el input v oltage (note 1) .8 v cc v cc +.5 v v i l1 reset lo w le v el input v oltage (note 1) ?5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v o l output lo w v oltage i ol = 20 a, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.15 0.45 v v o h output high v oltage i oh = 20 a, v cc = 4.5 v 4.4 4.49 v i oh = 2 ma, v cc = 4.5 v 2.4 3.9 v v sby sram standb y v oltage 2.7 v cc v i sby sram standb y current v cc = 0 v 0.5 1 a i idle idle current (v stdby pin) v cc > v sby 0.1 0.1 a v df sram data retention v oltage only on v stby 2 v i sb standb y supply p o w er do wn mode csi >v cc ?3 v (note 2) 40 100 a current sleep mode csi >v cc ?3 v (note 3) 10 20 a i li input leakage current v ss < v in > v cc ? .1 1 a i lo output leakage current .45 < v in > v cc ?0 5 10 a zpld_turbo = off , 0 see f = 0 mhz (note 4) figure 37 zpld adder zpld_turbo = on, f = 0 mhz 400 700 a/pt cmiser = on 0 0 ma and not selected i cc (dc) oper ating cmiser = on and epr om (note 4a) supply current epr om adder selected (x8 data bus) 10 15 ma cmiser = on and epr om 15 20 ma selected (x16 data bus) cmiser = off 15 20 ma sram not selected 0 0 ma cmiser = on, sram sram adder selected (x8 data bus) 25 40 ma cmiser = on, sram selected (x16 data bus) 30 45 ma zpld_turbo = off zpld (note 4) i cc (a c) zpld_turbo = on 2 ma/mhz (note 4a) epr om or sram 2 ma/mhz dc characteristics (5 v 10% v ersions) no tes: 1. reset input has h ysteresis . v il1 is v alid at or belo w .2v cc ?1. v ih1 is v alid at or abo v e .8v cc . 2. csi deselected or inter nal pd is activ e . 3. sleep mode bit is set and inter nal pd is activ e . 4. see zpld icc/f requency p o w er consumption g r aph f or details . 4a. i out = 0 ma.
psd4xx family 4-79 -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off * unit i/o input or f eedbac k to t pd combinator ial output p or t b , c , d , e 25 30 32 34 35 add 10 ns t rpd registered input to (note 5) 27 32 34 36 37 add 10 ns combinator ial output t ea input to output enab le an y input 25 28 30 32 33 add 10 ns t er input to output disab le an y input 25 28 30 32 33 add 10 ns t arp register clear or an y input 27 30 32 34 35 add 10 ns preset dela y t arpw register clear or preset an y input 20 25 28 29 30 ns pulse width t ard arr a y dela y 16 18 20 22 24 ns combinatorial delays (5 v 10% v ersions) no te: 5. p or t a and latched address from adio (a0, a1, a8 ?a15). ac/dc parameters zpld t iming parameters (5 v 10% v ersions) * * no te: if zpld_turbo is off and the zpld is oper ating abo v e 15 mhz, there is no need to add 10 ns to the timing par ameters . ** no te: re vision a and pre vious silicon re visions are 5v 5% f or 90 nsec v ersion only .
psd4xx family 4-80 -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off * unit maxim um f requency exter nal f eedbac k 1/( t s + t co ) 30.30 27.03 25.00 25.00 23.81 mhz maxim um f requency f max inter nal f eedbac k 1/( t s + t c o ?0) 43.48 37.04 33.33 31.25 28.57 mhz ( f cnt ) maxim um f requency pipelined data 1/( t ch + t cl ) 50.00 41.67 35.71 35.71 33.33 mhz t s input setup time an y input 15 17 19 20 21 add 10 ns t h input hold time an y input 0 0 0 0 0 0 ns t ch cloc k high time cloc k input 10 12 14 15 16 0 ns t cl cloc k lo w time cloc k input 10 12 14 15 16 0 ns t co cloc k to output dela y cloc k input 18 20 21 22 24 0 ns t ard arr a y dela y f or product t er m an y macrocell 16 18 20 22 24 0 ns expansion t min minim um cloc k p er iod t ch + t cl 20 24 28 29 28 0 ns synchr onous clock mode (5 v 10%) * * no te: if zpld_turbo is off and the zpld is oper ating abo v e 15 mhz, there is no need to add 10 ns to the timing par ameters . ** no te: re vision a and pre vious silicon re visions are 5v 5% f or 90 nsec v ersion only . ac/dc parameters zpld t iming parameters (5 v 10% v ersions)
psd4xx family 4-81 -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off * unit maxim um f requency exter nal f eedbac k 1/( t sa + t co a ) 26.32 25.00 21.74 21.74 20.41 mhz maxim um f requency f maxa inter nal f eedbac k 1/( t s a + t c o a ?0) 35.71 33.33 27.78 27.78 25.64 mhz ( f cnt a ) (note 6) maxim um f requency pipelined data 1/( t ch + t cl ) 41.67 41.67 35.71 35.71 33.33 mhz t sa input setup time an y input 8 8 10 12 13 add 10 ns t ha input hold time an y input 8 8 10 12 13 0 ns t cha cloc k high time an y input 12 12 14 15 16 0 ns t cla cloc k lo w time an y input 12 12 14 15 16 0 ns t co a cloc k to output an y input to dela y p or t b 30 32 36 37 38 add 10 ns arr a y dela y t ard f or product t er m an y macrocell 16 18 20 22 24 0 ns expansion t mina minim um cloc k p er iod 1/f cnt 28 30 36 43 39 0 ns asynchr onous clock mode (5 v 10% , note 6) * * no te: if zpld_turbo is off and the zpld is oper ating abo v e 15 mhz, there is no need to add 10 ns to the timing par ameters . ** no te: re vision a and pre vious silicon re visions are 5v 5% f or 90 nsec v ersion only . ac/dc parameters zpld t iming parameters (5 v 10% v ersions) no te: 6. only p or t b has asynchronous outputs . cloc k into macrocell flip flop is gener ated b y a product ter m.
-70 -90** -12 -15 -20 eprom_cmiser symbol parameter conditions min max min max min max min max min max on unit t l vlx ale or as pulse width 18 20 25 28 30 0 ns t a vlx address setup time (note 8) 5 6 9 10 12 0 ns t lxax address hold time (note 8) 7 8 10 11 12 0 ns t a vqv address v alid to data v alid (note 8) 70 90 120 150 200 add 10 ns t slqv cs v alid to data v alid 80 100 130 150 200 add 10 ns rd to data v alid 8/16-bit bus (note 7) 20 32 38 40 45 0 ns t rlqv rd to data v alid 8-bit bus , 8031 separ ate mode (note 7a) 32 38 40 45 50 0 ns t rhqx rd data hold time (note 7) 0 0 0 0 0 0 ns t rlrh rd pulse width (note 7) 30 32 35 38 40 0 ns t rhqz rd to data high-z (note 7) 22 25 30 33 35 0 ns t ehel e pulse width 30 32 35 38 40 0 ns t theh r/w setup time to enab le 8 10 15 18 20 0 ns t el tl r/w hold time after enab le 0 0 0 0 0 0 ns in 16-bit data bus 20 30 35 38 40 0 ns t a vpv address input v alid to mode (note 9) address output dela y in 8-bit data bus 22 32 45 48 50 0 ns mode (note 9) no tes: 7. rd timing has the same timing as psen, ds , lds , uds signals (in 8031 combined mode). 7a. rd and psen ha v e the same timing f or 8031 separ ate mode . 8. an y input used to select an inter nal psd4xx function. 9. in m ultiple x ed mode latched address gener ated from adio dela y to address output on an y p or t. ** no te: re vision a and pre vious silicon re visions are 5v 5% f or 90 nsec v ersion only . psd4xx family 4-82 read t iming (5 v 10% v ersions) explanation of a c symbols f or non zpld timing. example: t a v l x time from address v alid to ale in v alid. a address l logic le v el lo w or ale t r/w c p o w er do wn n reset t time d input data p p or t signal v v alid e e q output data x no longer a v alid logic le v el h logic le v el high r wr, uds , lds , ds , iord , psen z float i interr upt s chip select micr ocontr oller inter face ac/dc parameters
psd4xx family 4-83 -70 -90** -12 -15 -20 eprom_cmiser symbol parameter conditions min max min max min max min max min max on unit t l vlx ale or as pulse width 18 20 25 28 30 ns t a vlx address setup time (note 8) 5 6 9 10 12 ns t lxax address hold time (note 8) 7 8 10 11 12 ns t a vwl address v alid to leading edge of wr (notes 8 and 10) 18 20 25 30 35 ns t sl wl cs v alid to leading edge of wr (note 10) 22 25 30 35 40 ns t d vwh wr data setup time (note 10) 12 15 20 22 25 ns t whdx wr data hold time (note 10) 5 5 5 5 5 ns t wl wh wr pulse width (note 10) 18 20 25 28 30 ns t whax t r ailing edge of wr to address in v alid (note 10) 0 0 0 0 0 ns t whpv t r ailing edge of wr to p or t output v alid (note 10) 25 30 35 38 40 ns in 16-bit data bus 20 30 35 38 40 ns address input v alid to mode (note 9) t a vpv address output dela y in 8-bit data bus 22 32 45 48 50 ns mode (note 9) w rite t iming (5 v 10%) micr ocontr oller inter face ac/dc parameters (5 v 10% v ersions) no te: 10. wr timing has the same timing as e, ds , lds , uds , wrl, wrh signals . ** no te: re vision a and pre vious silicon re visions are 5v 5% f or 90 nsec v ersion only .
psd4xx family 4-84 no tes: 11. an y input used to select p or t a data p er ipher al mode . 12. data is already stab le on p or t a. 13. data stab le on adio pins to data on p or t a. ** no te: re vision a and pre vious silicon re visions are 5v 5% f or 90 nsec v ersion only . -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t a vqv (p a) address v alid to data v alid (note 11) 45 55 60 62 65 add 10 ns t slqv (p a) cs v alid to data v alid 55 55 60 62 65 add 10 ns rd to data v alid (notes 7, 12) 22 26 38 45 50 0 ns t rlqv (p a) rd to data v alid 8031 mode 32 38 40 45 50 0 ns t d vqv (p a) data in to data out v alid 22 22 25 26 28 0 ns t qxrh (p a) rd data hold time (note 7) 0 0 0 0 0 0 ns t rlrh (p a) rd pulse width (note 7) 25 30 35 38 40 0 ns t rhqz (p a) rd to data high-z (note 7) 20 25 30 33 35 0 ns por t a peripheral data mode read t iming (5 v 10%) -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t wlqv (p a) wr to data propagation dela y (note 10) 25 27 32 35 38 0 ns t d vqv (p a) data to p or t a data propagation dela y (note 13) 22 22 25 26 28 0 ns t whqz (p a) wr in v alid to p or t a t r i-state (note 10) 20 25 30 33 35 ns por t a peripheral data mode w rite t iming (5 v 10%) micr ocontr oller inter face ac/dc parameters (5 v 10% v ersions)
psd4xx family 4-85 -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t l vd v ale access time from p o w er do wn 100 120 140 150 170 add 10 ns t l vd v1 ale or csi access time from sleep 120 150 170 200 200 0 ns t l vd v2 zpld propagation dela y in sleep mode 600 600 600 600 600 0 ns t l vd v3 zpld reco v er y time after sleep mode 250 250 250 250 250 0 ns t chcl apd cloc k high time using pe7 10 12 14 15 16 0 ns t clch apd cloc k lo w time using pe7 10 12 14 15 16 0 ns f max apd maxim um f requency using pe7 35.00 30.00 25.00 22.00 20.00 0 mhz t 1 reset activ e lo w time 150 200 250 300 300 0 ns t 2 reset high to oper ational de vice 150 200 250 300 300 0 ns power down and reset t iming (5 v 10%) micr ocontr oller inter face ac/dc parameters (5 v 10% v ersions) ** no te: re vision a and pre vious silicon re visions are 5v 5% f or 90 nsec v ersion only .
psd4xx family 4-86 figur e 38. read t iming t avlx t lxax t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out read timing ale /as a / d (bhe) multiplexed bus address (bhe / siz0) non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) (lds, uds) e r / w
psd4xx family 4-87 figur e 39. w rite t iming t avlx t lxax t lvlx t avwl t slwl t whdx t whax t el tl t ehel t wlwh t d vwh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale / as a / d (bhe) multiplexed bus address (bhe, siz0) non-multiplexed bus data non-multiplexed bus csi wr (wrh, wrl) (lds, uds) (ds) e r / w
psd4xx family 4-88 figur e 41. peripheral i/o w rite t iming figur e 40. peripheral i/o read t iming t qxrh ( pa) t rlqv ( pa) t rlrh ( pa) t dvqv ( pa) t rhqz ( pa) t slqv ( pa) t avqv ( pa) address data valid ale /as a / d bus rd data on port a csi tdvqv (pa) twlqv (pa) twhqz (pa) address data out a / d bus wr port a data out ale /as
psd4xx family 4-89 figur e 42. combinatorial t iming ? zpld tpd trpd input (from port a) any output any output input (from port b, c, d, e)
psd4xx family 4-90 figur e 43. synchr onous clock mode t iming ? zpld figur e 44. asynchr onous clock mode t iming (pr oduct-t er m clock, pb macr ocell only) t ch t cl t co t h t s clkin input registered output tcha tcla tcoa tha tsa clock input registered output
psd4xx family 4-91 figur e 45. input to output disabl e / enable figur e 46. asynchr onous rese t / pr eset ter tea input input to output enable / disable tarp register output tarpw reset / preset input
psd4xx family 4-92 figur e 47. reset t iming figur e 48. key to switching w avefor ms t1 t2 waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state
psd4xx family 4-93 symbol paramete r 14 conditions t ypica l 15 max unit c in capacitance (f or input pins only) v in = 0 v 4 6 pf c out capacitance (f or input/output pins) v out = 0 v 8 12 pf c vpp capacitance (f or wr/v pp or r/w/v pp ) v pp = 0 v 18 25 pf no tes: 14. these par ameters are only sampled and are not 100% tested. 15. t ypical v alues are f or t a = 25 c and nominal supply v oltages . t a = 25 c , f = 1 mhz pin capacitanc e figur e 49. ac t esting input/output w avefor m figur e 50. ac t esting load cir cuit erasur e and pr ogramming 3.0v 0v test point 1.5v device under test 2.01 v 195 w c l = 30 pf (including scope and jig capacitance) t o clear all locations of their prog r ammed contents , e xpose the windo w pac kaged de vice to an ultr a-violet light source . a dosage of 30 w second/c m 2 is required. this dosage can be obtained with e xposure to a w a v elength of 2537 ? and intensity of 12000 w/c m 2 f or 40 to 45 min utes . the de vice should be about 1 inch from the source , and all filters should be remo v ed from the uv light source pr ior to er asure . the psd4xx and similar de vices will er ase with light sources ha ving w a v elengths shor ter than 4000 ?. although the er asure times will be m uch longer than with uv sources at 2537 ?, e xposure to fluorescent light and sunlight e v entually er ases the de vice . f or maxim um system reliability , these sources should be a v oided. if used in such an en vironment, the pac kage windo ws should be co v ered b y an opaque substance . upon deliv er y from wsi, or after each er asure , the psd4xx de vice has all bits in the p ad and epr om in the ??or high state . the configur ation bits are in the ??or lo w state . the code , configur ation, and p ad map data are loaded through the procedure of prog r amming inf or mation f or prog r amming the de vice is a v ailab le directly from wsi. please contact y our local sales representativ e .
psd4xx family 4-94 68-pin 68-pin pin no. pldcc/cldcc pin no. pldcc/cldcc package package 1 gnd 35 gnd 2 adio_7 36 pe2 3 adio_6 37 pe1 4 adio_5 38 pe0 5 adio_4 39 csi 6 adio_3 40 reset 7 adio_2 41 rd 8 adio_1 42 clkin 9 adio_0 43 pb7 10 pc7 44 pb6 11 pc6 45 pb5 12 pc5 46 pb4 13 pc4 47 pb3 14 pc3 48 pb2 15 pc2 49 pb1 16 pc1 50 pb0 17 pc0 51 gnd 18 vcc 52 vcc 19 gnd 53 pd7 20 p a7 54 pd6 21 p a6 55 pd5 22 p a5 56 pd4 23 p a4 57 pd3 24 p a3 58 pd2 25 p a2 59 pd1 26 p a1 60 pd0 27 p a0 61 adio_15 28 vstdb y 62 adio_14 29 wr 63 adio_13 30 pe7 64 adio_12 31 pe6 65 adio_11 32 pe5 66 adio_10 33 pe4 67 adio_9 34 pe3 68 adio_8 psd4xx pin assignments
psd4xx family 4-95 80-pin 80-pin pin no. tqfp pin no. tqfp package package 1 pc7 41 pb7 2 pc6 42 pb6 3 pc5 43 pb5 4 pc4 44 pb4 5 pc3 45 pb3 6 pc2 46 pb2 7 pc1 47 pb1 8 pc0 48 pb0 9 v cc 49 gnd 10 v cc 59 gnd 11 gnd 51 v cc 12 gnd 52 v cc 13 p a7 53 pd7 14 p a6 54 pd6 15 p a5 55 pd5 16 p a4 56 pd4 17 p a3 57 pd3 18 p a2 58 pd2 19 p a1 59 pd1 20 p a0 60 pd0 21 nc 61 nc 22 nc 62 adio_15 23 vstdb y 63 adio_14 24 wr 64 adio_13 25 pe7 65 adio_12 26 pe6 66 adio_11 27 pe5 67 adio_10 28 pe4 68 adio_9 29 pe3 69 adio_8 30 gnd 70 gnd 31 gnd 71 gnd 32 pe2 72 adio_7 33 pe1 73 adio_6 34 pe0 74 adio_5 35 csi 75 adio_4 36 reset 76 adio_3 37 rd 77 adio_2 38 clkin 78 adio_1 39 nc 79 adio_0 40 nc 80 nc psd4xx pin assignments
psd4xx family 4-96 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 v cc gnd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 adio - 0 adio -1 adio - 2 adio - 3 adio - 4 adio - 5 adio - 6 adio - 7 gnd adio - 8 adio - 9 adio -10 adio -11 adio -12 adio -13 adio -14 adio -15 pa0 vstdby wr pe7 pe6 pe5 pe4 pe3 gnd pe2 pe1 pe0 csi reset rd clkin pb7 figur e 52. drawing l5 68-pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l) figur e 51. drawing j5 68-pin plastic leaded chip car rier (pldcc) (package t ype j) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 v cc gnd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 adio - 0 adio -1 adio - 2 adio - 3 adio - 4 adio - 5 adio - 6 adio - 7 gnd adio - 8 adio - 9 adio -10 adio -11 adio -12 adio -13 adio -14 adio -15 pa0 vstdby wr pe7 pe6 pe5 pe4 pe3 gnd pe2 pe1 pe0 csi reset rd clkin pb7
psd4xx family 4-97 60 pd0 59 pd1 58 pd2 57 pd3 56 pd4 55 pd5 54 pd6 53 pd7 52 v cc 51 v cc 50 gnd 49 gnd 48 pb0 47 pb1 46 pb2 45 pb3 44 pb4 43 pb5 42 pb6 41 pb7 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc v cc gnd gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 54 63 62 61 n/c adio? adio? adio? adio? adio? adio? adio? adio? gnd gnd adio? adio? adio?0 adio?1 adio?2 adio?3 adio?4 adio?5 n/c 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 n/c n/c vstdby wr pe7 pe6 pe5 pe4 pe3 gnd gnd pe2 pe1 pe0 csi reset rd clkin n/c n/c figur e 53. drawing u2 80-pin plastic thin quad flatpack (tqfp) (package t ype u) (t op view) psd4xx pr oduct or dering infor mation psd4xx f amily de vices are a v ailab le in a wide r ange of product selections . options and combinations include: ar c hitecture speed (access time) memor y siz e configuration mask pr ogrammability operating t emperature rang e p ac ka g es please contact y our local wsi sales representativ e or distr ib utor f or the psd4xx product selection that best fits y our application and objectiv es .

▲Up To Search▲

Price & Availability of PSD412A2

	To Download PSD412A2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .