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ds04-21369-1e fujitsu semiconductor data sheet assp dual s erial input pll frequency synthesizer mb15f78ul n description the fujitsu mb15f78ul is a serial input phase locked loop (pll) frequency synthesizer with a 2600 mhz and a 1200 mhz prescalers. a 32/33 or a 64/65 for the 2600 mhz prescaler, and a 16/17 or a 32/33 for the 1200 mhz prescaler can be selected for the prescaler that enables pulse swallow operation. the bicmos process is used, as a result a supply current is typically 4.5 ma at 2.7 v. the supply voltage range is from 2.4 v to 3.6 v. a refined charge pump supplies well-balanced output current with 1.5 ma and 6 ma selectable by serial date. the data format is the same as the previous one mb15f08sl, mb15f78sp. fast locking is achieved for adopting the new circuit. the new package (bcc20) decreases a mount area of mb15f78ul more than 30 % comparing with the former bcc16 (for dual pll) . mb15f78ul is ideally suited for wireless mobile communications, such as gsm and pcs. n n n n features ? high frequency operation : rx synthesizer : 2600 mhz max. : tx synthesizer : 1200 mhz max. ? low power supply voltage : v cc = 2.4 to 3.6 v ? ultra low power supply current : i cc = 4.5 ma typ. (v cc = vp = 2.7 v, ta = + 25 c, sw tx = sw rx = 0, in tx/rx locking state) (continued) n n n n packages 20-pin plastic tssop 20-pad plastic bcc (fpt-20p-m06) (lcc-20p-m05)
mb15f78ul 2 (continued) ? direct power saving function : power supply current in power saving mode typ. 0.1 m a (v cc = vp = 2.7 v, ta = + 25 c) max. 10 m a (v cc = vp = 2.7 v) ? software selectable charge pump current : 1.5 ma/6.0 ma typ. ? dual modulus prescaler : 2600 mhz prescaler (32/33 or 64/65) /1200 mhz prescaler (16/17 or 32/33) ? 23-bit shift register ? serial input binary 14-bit programmable reference divider : r = 3 to 16,383 ? serial input programmable divider consisting of : - binary 7-bit swallow counter : 0 to 127 - binary 11-bit programmable counter : 3 to 2,047 ? built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit ? on-chip phase control for phase comparator ? on-chip phase comparator for fast lock and low noise ? built-in digital locking detector circuit to detect pll locking and unlocking ? operating temperature : ta = - 40 to + 85 c ? serial data format compatible with mb15f08sl n n n n pin assignments osc in gnd fin tx xfin tx gnd tx v cctx ps tx vp tx do tx ld/fout clock data le fin rx xfin rx gnd rx v ccrx ps rx vp rx do rx 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd do tx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 19 18 17 20 gnd tx v cctx vp tx fin tx ps tx gnd rx le fin rx v ccrx ps rx xfin rx xfin tx osc in ld/fout do rx vp rx data clock (tssop-20) top view (bcc-20) top view (fpt-20p-m06) (lcc-20p-m05)
mb15f78ul 3 n n n n pin description pin no. pin name i/o descriptions tssop bcc 119osc in i the programmable reference divider input pin. tcxo should be connected with an ac coupling capacitor. 220gnd ? ground pin for osc input buffer and the shift register circuit. 31fin tx i prescaler input pin for the tx-pll. connection to an external vco should be via ac coupling. 42xfin tx i prescaler complimentary input pin for the tx-pll section. this pin should be grounded via a capacitor. 53gnd tx ? ground pin for the tx-pll section. 64v cctx ? power supply voltage input pin for the tx-pll section (except for the charge pump circuit) , the oscillator input buffer and the shift register. 75ps tx i power saving mode control pin for the tx-pll section. this pin must be set at l when the power supply is started up. (open is prohibited.) ps tx = h ; normal mode/ps tx = l ; power saving mode 86vp tx ? power supply voltage input pin for the tx-pll charge pump. 97d otx o charge pump output pin for the tx-pll section. 10 8 ld/fout o lock detect signal output (ld) /phase comparator monitoring output (fout) .the output signal is selected by lds bit in the serial data. lds bit = h ; outputs fout signal/lds bit = l ; outputs ld signal 11 9 d orx o charge pump output pin for the rx-pll section. 12 10 vp rx ? power supply voltage input pin for the rx-pll charge pump. 13 11 ps rx i power saving mode control pin for the rx-pll section. this pin must be set at l when the power supply is started up. (open is prohibited.) ps rx = h ; normal mode/ps rx = l ; power saving mode 14 12 v ccrx ? power supply voltage input pin for the rx-pll section (except for the charge pump circuit) 15 13 gnd rx ? ground pin for the rx-pll section 16 14 xfin rx i prescaler complimentary input pin for the rx-pll section. this pin should be grounded via a capacitor. 17 15 fin rx i prescaler input pin for the rx-pll. connection to an external vco should be via ac coupling. 18 16 le i load enable signal input pin (with the schmitt trigger circuit) when le is set h, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 19 17 data i serial data input pin (with the schmitt trigger circuit) data is transferred to the corresponding latch (tx-ref. counter, tx-prog. counter, rx-ref.counter, rx-prog.counter) according to the control bit in a serial data. 20 18 clock i clock input pin for the 23-bit shift register (with a schmitt trigger circuit) one bit of data is shifted into the shift register on a rising edge of the clock.
mb15f78ul 4 n n n n block diagram o : tssop ( ) : bcc (5) 7 (2) (1) 4 3 (19) 1 (14) (15) 16 17 (11) 13 (16) 18 (17) 19 (18) 20 (20) 2 (12) 14 (13) 15 (10) 12 (9) 11 (8) 10 (7) 9 (4) 6 (3) 5 (6) 8 ps tx fin tx xfin tx osc in fin rx xfin rx ps rx le data clock or c n 1 c n 2 gnd v ccrx vp rx gnd rx do rx ld/ fout do tx v cctx gnd tx vp tx lds sw tx fc tx t1 t2 t1 t2 fp tx fp rx ld rx ld tx ld/fout ld fr tx fr rx fp tx fp rx fr tx fr rx lds sw rx fc rx and intermittent mode control (tx-pll) prescaler (tx-pll) (16/17, 32/33) 3 bit latch 7 bit latch binary 7-bit swallow counter tx-pll) 11 bit latch binary 11-bit programmable counter (tx-pll) 2 bit latch 14 bit latch binary 14-bit pro- grammable ref. counter(tx-pll) 1 bit latch c/p setting counter phase comp. (tx-pll) fast lock tuning charge pump (tx-pll) current switch lock det. (tx-pll) lock det. (rx-pll) phase comp. (rx-pll) fast lock tuning charge pump (rx-pll) current switch binary 11-bit programmable counter (rx-pll) 11 bit latch binary 7-bit swallow counter (rx-pll) 7 bit latch 3 bit latch latch selector 23-bit shift register schmitt circuit schmitt circuit schmitt circuit intermittent mode control (rx-pll) prescaler (rx-pll) (32/33, 64/65) 2 bit latch binary 14-bit pro- grammable ref. counter (rf-pll) 14 bit latch c/p setting counter 1 bit latch fast lock tuning
mb15f78ul 5 n nn n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n nn n recommended operating conditions note : v ccr x , v p rx , v cctx and v p t x m ust sup p l y e q ual v o ltag e . even if either rx-pll or tx-pll is not used, power must be supplied to v ccrx , vp rx , v cctx and vp tx to k eep them e q ual. it is recommended that the non-use pll is controlled by power saving function. although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection, observe the following precautions when handling the device. when storing and transporting the device, put it in a conductive case. before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. use a conductive sheet on working bench. before fitting the device into or removing it from the socket, turn the power supply off. when handling (such as transporting) the device mounted board, protect the leads with a conductive sheet. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. power supply voltage v cc - 0.5 4.0 v vp v cc 4.0 v input voltage v i - 0.5 v cc + 0.5 v output voltage ld / fout v o gnd v cc v do tx , do rx v dd gnd vp v storage temperature tstg - 55 + 125 c parameter symbol value unit remarks min. typ. max. power supply voltage v cc 2.4 2.7 3.6 v v ccrx = v cctx vp v cc 2.7 3.6 v input voltage v i gnd ? v cc v operating temperature ta - 40 ?+ 85 c
mb15f78ul 6 n n n n electrical characteristics (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) (continued) parameter symbol condition value unit min. typ. max. power supply current i cctx * 1 fin tx = 910 mhz v cctx = vp tx = 2.7 v 1.1 1.7 2.4 ma i ccrx * 1 fin rx = 2500 mhz v ccrx = vp rx = 2.7 v 1.8 2.8 3.9 ma power saving current i pstx ps tx = ps rx = l ? 0.1 * 2 10 m a i psrx ps tx = ps rx = l ? 0.1 * 2 10 m a operating frequency fin tx * 3 fin tx tx pll 100 ? 1200 mhz fin rx * 3 fin rx rx pll 400 ? 2600 mhz osc in f osc ? 3 ? 40 mhz input sensitivity fin tx pfin tx tx pll, 50 w system - 15 ?+ 2dbm fin rx pfin rx rx pll, 50 w system - 15 ?+ 2dbm osc in v osc ? 0.5 ? v cc v p - p h level input voltage data, le, clock v ih schmitt trigger input 0.7 v cc + 0.4 ?? v l level input voltage v il schmitt trigger input ?? 0.3 v cc - 0.4 v h level input voltage ps tx ps rx v ih ? 0.7 v cc ?? v l level input voltage v il ? ?? 0.3 v cc v h level input current data le clock ps tx ps rx i ih * 4 ? - 1.0 ?+ 1.0 m a l level input current i il * 4 ? - 1.0 ?+ 1.0 m a h level input current osc in i ih ? 0 ?+ 100 m a l level input current i il * 4 ? - 100 ? 0 m a h level output voltage ld/fout v oh v cc = vp = 2.7 v, i oh = - 1 ma v cc - 0.4 ?? v l level output voltage v ol v cc = vp = 2.7 v, i ol = 1 ma ?? 0.4 v h level output voltage do tx do rx v doh v cc = vp = 2.7 v, i doh = - 0.5 ma vp - 0.4 ?? v l level output voltage v dol v cc = vp = 2.7 v, i dol = 0.5 ma ?? 0.4 v high impedance cutoff current do tx do rx i off v cc = vp = 2.7 v v off = 0.5 v to vp - 0.5 v ?? 2.5 na h level output current ld/fout i oh * 4 v cc = vp = 2.7 v ??- 1.0 ma l level output current i ol v cc = vp = 2.7 v 1.0 ?? ma
mb15f78ul 7 (continued) (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) *1 : conditions ; fosc = 12.8 mhz, ta = + 25 c, sw = l in locking state. *2 : v cctx = vp tx = v ccrx = vp rx = 2.7 v, fosc = 12.8 mhz, ta = + 25 c, in power saving mode. ps tx = ps rx = gnd v ih = v cc , v il = gnd (at clk, data, le) *3 : ac coupling. 1000 pf capacitor is connected under the condition of min. operating frequency. *4 : the symbol C (minus) means the direction of current flow. *5 : v cc = vp = 2.7 v, ta = + 25 c (||i 3 | - |i 4 ||) / [ (|i 3 | + |i 4 |) / 2] 100 ( % ) *6 : v cc = vp = 2.7 v, ta = + 25 c [ (||i 2 | - |i 1 ||) / 2] / [ (|i 1 | + |i 2 |) / 2] 100 ( % ) (applied to both l dol and l doh ) *7 : v cc = vp = 2.7 v, [||i do ( + 85 c) | - |i do (C40 c) || / 2] / [|i do ( + 85 c) | + |i do (C40 c) | / 2] 100 ( % ) (applied to both i dol and i doh ) *8 : when charge pump current is measured, set lds = l , t1 = l and t2 = h. parameter symbol condition value unit min. typ. max. h level output current do tx * 8 do rx i doh * 4 v cc = vp = 2.7 v, v doh = vp / 2, ta = + 25 c cs bit = h - 8.2 - 6.0 - 4.1 ma cs bit = l - 2.2 - 1.5 - 0.8 ma l level output current do tx * 8 do rx i dol v cc = vp = 2.7 v, v dol = vp / 2, ta = + 25 c cs bit = h 4.1 6.0 8.2 ma cs bit = l 0.8 1.5 2.2 ma charge pump current rate i dol /i doh i domt * 5 v do = vp / 2 ? 3 ?% vs v do i dovd * 6 0.5 v v do vp - 0.5 v ? 10 ?% vs ta i dota * 7 - 40 c ta + 85 c, v do = vp / 2 ? 5 ?% i 1 i 1 i 3 i 2 i 2 i 4 i dol i doh 0.5 vp / 2 vp vp - 0.5 charge pump output voltage (v)
mb15f78ul 8 n nn n functional description 1. pulse swallow function f vco = [ (p n) + a] f osc ? r f vco : output frequency of external voltage controlled oscillator (vco) p : preset divide ratio of dual modulus prescaler (16 or 32 for tx-pll, 32 or 64 for rx-pll) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127, a < n) f osc : reference oscillation frequency (osc in input frequency) r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) 2. serial data input the serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of tx/rx- pll sections, programmable reference dividers of tx/rx-pll sections are controlled individually. the serial data of binary data is entered through data pin. on rising edge of clock, one bit of the serial data is transferred into the shift register. on a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. (1) shift register configuration the programmable reference counter for the tx-pll the programmable reference counter for the rx-pl the programmable counter and the swallow counter for the tx-pll the programmable counter and the swallow counter for the rx-pll cn1 0 1 0 1 cn2 0 0 1 1 c s : charge pump curr e n t select bit r1 to r14 : divide ratio setting bits for the programmable reference counter (3 to 16,383) t1, 2 : ld/fout output setting bit cn1, 2 : control bit x : dummy bits (set 0 or 1) note : data input with msb first. ? programmable reference counter 1 2 34567891011121314151617181920212223 cn1 cn2 t1 t2 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 cs x x x x (lsb) (msb) data flow
mb15f78ul 9 (2) data setting ? binary 14-bit programmable reference counter data setting note : divide ratio less than 3 is prohibited. ? binary 11-bit programmable counter data setting note : divide ratio less than 3 is prohibited. ? binary 7-bit swallow counter data setting divide ratio r14r13r12 r11 r10 r9 r8 r7 r6r5r4r3r2r1 300000000000011 4 16383 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratio n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 3 00000000011 4 2047 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratio a7 a6 a5 a4 a3 a2 a1 0 0000000 1 127 0 1 0 1 0 1 0 1 0 1 0 1 1 1 ? programmable counter note : data input with msb first. a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) n1 to n11 : divide ratio setting bits for the programmable counter (3 to 2,047) lds : ld/fout signal select bit sw tx/rx : divide ratio setting bit for the prescaler (tx : sw tx , rx : sw rx ) fc tx/rx : phase control bit for the phase detector (tx : fc tx , rx : fc rx ) cn1, 2 : control bit 1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23 cn1 cn2 lds sw tx/rx fc tx/rx a1 a2 a3 a4 a5 a6 a7 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 (lsb) (msb) data flow
mb15f78ul 10 ? prescaler data setting ? charge pump current setting ? ld/fout output selectable bit setting ? phase comparator phase switching data setting z : high - impedance depending upon the vco and lpf polarity, fc bit should be set. divide ratio sw = = = = h sw = = = = l prescaler divide ratio tx-pll 16/17 32/33 prescaler divide ratio rx-pll 32/33 64/65 current value cs 6.0 ma 1 1.5 ma 0 ld/fout pin state lds t1 t2 ld output 000 010 011 fout output fr tx 100 fr rx 110 fp tx 101 fp rx 111 phase comparator input fc = = = = h fc = = = = l do tx /do rx do tx /do rx fr > fp h l fr < fp l h fr = fp z z (1) (2) high max. vco output frequency lpf output voltage (1) vco polarity fc = h (2) vco polarity fc = l note : give attention to the polarity for using active type lpf.
mb15f78ul 11 3. power saving mode (intermittent mode control circut) the intermittent mode control circuit reduces the pll power consumption. by setting the ps pins low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pins high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. notes : when power (v cc ) is first applied, the device must be in standby mode, ps tx = ps rx = low, for at least 1 m s. ps pins must be set at l at power-on status ps tx /ps rx pins normal mode h power saving mode l on off v cc clock data le ps tx ps rx (1) (2) (3) t v 3 1 m s t ps 3 100 ns (1) ps tx = ps rx = l (power saving mode) at power-on (2) set serial data at least 1 m s after the power supply becomes stable (v cc 3 2.2 v) . (3) release power saving mode (ps tx , ps rx : l ? h) at least 100 ns after setting serial data.
mb15f78ul 12 4. serial data input timing divide ratio setting is performed through a serial interface using the data pin, clock pin, and le pin. setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of the le signal. the following diagram shows the data input timing. lsb msb clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 1st data 2nd data control bit invalid data note : le should be l when the data is transferred into the shift register. parameter min. typ. max. unit parameter min. typ. max. unit t 1 20 ?? ns t 5 100 ?? ns t 2 20 ?? ns t 6 20 ?? ns t 3 30 ?? ns t 7 100 ?? ns t 4 30 ?? ns
mb15f78ul 13 n n n n phase comparator output waveform fr tx / fr rx fp tx / fp rx ld do tx / do rx t wu t wl do tx / do rx h l l h z z (fc bit = high) (fc bit = low) ld output logic table note s : phase error detection range = - 2 p to + 2 p pulses on do tx /do rx signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu 3 2/fosc : e.g. t wu 3 156.3 ns when fosc = 12.8 mhz t wu 4/fosc : e.g. t wl 312.5 ns when fosc = 12.8 mhz tx-pll section rx-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l
mb15f78ul 14 n n n n test circuit (for measuring input sensitivity fin/osc in ) 10987654321 11 12 13 14 15 16 17 18 19 20 s.g. s.g. s.g. 50 w 50 w 50 w 1000 pf 1000 pf 1000 pf 1000 pf 1000 pf 0.1 m f 0.1 m f 0.1 m f 0.1 m f v ccrx v cctx vp tx vp rx fout osc in clock data le gnd fin tx fin rx xfin rx xfin tx gnd tx gnd rx v cctx v ccrx ps tx ps rx vp tx vp rx do tx do rx ld/ fout oscilloscope controller (devide ratio setting) note : the terminal number shows that of tssop-20
mb15f78ul 15 n n n n typical characteristics 1. fin input sensitivity v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec spec 10 0 - 10 - 20 - 30 - 40 - 50 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 pfin rx (dbm) fin rx (mhz) rx-pll input sensitivity vs. input frequency 10 0 - 10 - 20 - 30 - 40 - 50 0 200 400 600 800 1000 1200 1400 spec v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec tx-pll input sensitivity vs. input frequency fin tx (mhz) pfin tx (dbm)
mb15f78ul 16 2. osc in input sensitivity spec 10 0 - 10 - 20 - 30 - 40 - 50 - 60 0 50 100 150 200 250 300 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec input sensitivity vs. input frequency input sensitivity v osc (dbm) input frequency f osc (mhz)
mb15f78ul 17 3. do output current ( rx pll ) v cc = vp = 2.7 v 10.0 0 - 10.0 1.0 3.0 0.0 2.0 v cc = vp = 2.7 v 10.0 0 - 10.0 1.0 3.0 0.0 2.0 i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) i do - v do charge pump output voltage v do (v) charge pump output current i do (ma) ? 1.5 ma mode ? 6.0 ma mode
mb15f78ul 18 4. do output current ( tx pll ) 10.0 0 - 10.0 1.0 3.0 v cc = vp = 2.7 v 0.0 2.0 v cc = vp = 2.7 v 10.0 0 - 10.0 1.0 3.0 0.0 2.0 charge pump output voltage v do (v) charge pump output voltage v do (v) charge pump output current i do (ma) charge pump output current i do (ma) i do - v do i do - v do ? 1.5 ma mode ? 6.0 ma mode
mb15f78ul 19 5. fin input impedance 317.09 w - 831.5 w 100 mhz 30.898 w - 233.42 w 400 mhz 13.227 w - 112.79 w 800 mhz 1 : 2 : 3 : start 100.000 000 mhz stop 1 200.000 000 mhz 4 : 9.6016 w- 68.832 w 1.9269 pf 1 200.000 000 mhz 1 3 2 4 43.75 w - 235.95 w 400 mhz 12.82 w - 88.188 w 1 ghz 9.7227 w - 25.9 w 2 ghz 1 : 2 : 3 : start 400.000 000 mhz stop 2 600.000 000 mhz 4 : 12.588 w- 3.4751 w 17.615 pf 2 600.000 000 mhz 1 3 2 4 fin tx input impedance fin rx input impedance
mb15f78ul 20 6. osc in input impedance 1 2 4 3 12.953 k w - 13.003 k w 3 mhz 478.13 w - 3.4268 k w 20 mhz 118.19 w - 1.7321 k w 40 mhz 1 : 2 : 3 : 4 : 28.844 w- 691.13 w 2.3028 pf 100.000 000 mhz start 3.000 000 mhz stop 100.000 000 mhz osc in input impedance
mb15f78ul 21 n n n n reference information (for look-up time, phase noise and reference leakage) (continued) s.g. osc in fin vco d o lpf test circuit spectrum analyzer 15 k w 820 pf 24 k w 82 pf 22 pf atten 10 db rl 0 dbm center 2.490008 ghz rbw 3.0 khz vbw 3.0 khz span 1.000 mhz swp 280 ms d mkr - 67.50 db 200 khz vavg 39 10 db/ d mkr 200 khz - 67.50 db * * d s atten 10 db rl 0 dbm center 2.49000640 ghz rbw 100 hz vbw 100 hz span 10.00 khz swp 802 ms d mkr - 59.33 db 1.00 khz vavg 48 10 db/ d mkr 1.00 khz - 59.33 db * d s f vco = 2490 mhz k v = 52 mhz/v fr = 200 khz f osc = 19.8 mhz lpf v cc = 3.0 v v vco = 2.5 v ta = + 25 c cp : 1.5 ma mode ? pll reference leakage ? pll phase noise
mb15f78ul 22 (continued) 2.550011500 ghz 2.550007500 ghz 2.550003500 ghz - 1.911 ms 3.089 ms 1.000 ms/div t 2 622 m s d 222 m s t 1 400 m s 8.089 ms 2.490011500 ghz 2.490007500 ghz 2.490003500 ghz - 1.911 ms 3.089 ms 1.000 ms/div t 2 689 m s d 267 m s t 1 422 m s 8.089 ms ? pll lock-up time ? pll lock-up time 2.49 ghz ? 2.55 ghz within 1 khz lch ? hch 222 m s 2.55 ghz ? 2.49 ghz within 1 khz hch ? lch 267 m s
mb15f78ul 23 n n n n application example 0.1 m f 18 17 20 19 16 15 14 13 12 11 34 12 5678910 1000 pf 1000 pf output 2.7 v mb15f78ul 1000 pf 1000 pf 1000 pf 2.7 v 0.1 m f 0.1 m f output lock det. vco lpf vco lpf tcxo do rx ps rx vp rx xfin rx gnd rx v ccrx fin rx le data clock do tx ps tx vp tx ld/fout v cctx fin tx xfin tx gnd tx osc in gnd 2.7 v 0.1 m f 2.7 v from controller notes : clock, data, le : the schmitt trigger circuit is provided (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input) . the terminal number shows that of tssop-20.
mb15f78ul 24 n n n n usage precautions (1) v ccrx , vp rx , v cctx and vp tx must be equal voltage. even if either rx-pll or tx-pll is not used, power must be supplied to v ccrx , vp rx , v cctx and vp tx to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions : -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. n n n n ordering information part number package remarks mb15f78ulpft 20-pin, plastic tssop (fpt-20p-m06) MB15F78ULPVA 20-pad, plastic bcc (lcc-20p-m05)
mb15f78ul 25 n n n n package dimensions (continued) 20-pin plastic tssop (fpt-20p-m06) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. dimensions in mm (inches) c 1999 fujitsu limited f20026s-2c-2 6.50?.10(.256?004) * 4.40?.10 6.40?.20 (.252?008) (.173?004) * 0.10(.004) 0.65(.026) 0.24?.08 (.009?003) 1 10 20 11 "a" 0.17?.05 (.007?002) m 0.13(.005) details of "a" part 0~8 (.018/.030) 0.45/0.75 (0.50(.020)) 0.25(.010) (.041?002) 1.05?.05 (mounting height) 0.07 +0.03 ?.07 +.001 ?003 .003 (stand off) lead no. index
mb15f78ul 26 (continued) 20-pad plastic bcc (lcc-20p-m05) dimensions in mm (inches) c 2001 fujitsu limited c20056s-c-2-1 3.60?.10(.142?004) 11 16 16 11 16 1 6 3.40?.10 (.134?004) index area 0.05(.002) 0.55?.05 0.075?.025 (stand off) 0.25?.10 (.010?004) typ 0.50(.020) 3.00(.118)typ 2.80(.110)ref typ 0.50(.020) (.010?004) 0.25?.10 2.70(.106) typ "d" "b" "a" "c" 0.60?.10 (.024?004) 0.50?.10 (.020?004) details of "a" part (.020?004) 0.50?.10 0.30?.10 (.012?004) details of "b" part details of "c" part (.020?004) 0.50?.10 (.024?004) 0.60?.10 c0.20(.008) details of "d" part 0.40?.10 (.016?004) 0.30?.10 (.012?004) (.003?001) (mounting height) (.022?002)
mb15f78ul fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0106 ? fujitsu limited printed in japan

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