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256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram sdram registered module 168pin registered module based on 256mb e-die with 72-bit ecc revision 1.4 may 2004 * samsung electronics reserves the right to ch ange products or specification without notice.
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram revision history revision 0.0 (june, 2003) - first release revision 1.0 (june, 2003) - revision 1.0 release. revision 1.1 (september, 2003) - corrected typo. revision 1.2 (february, 2004) - corrected typo. revision 1.3 (march. 2004) - modified dc characteristics notes. revision 1.4 (may, 2004) - added note 5. sentense of trdl parameter
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram 168pin registered dimm based on 256mb e-die (x4, x8) ordering information operating frequencies part number density organization component composition component package height m390s3253et1-c7a 256mb 32mx72 32mx8(k4s560832e) * 9ea 54-tsop(ii) 1,500mil M390S3253ETU-C7A 256mb 32mx72 32mx8(k4s560832e) * 9ea 1,200mil m390s6450et1-c7a 512mb 64mx72 64mx4(k4s560432e) * 18ea 1,700mil m390s6450etu-c7a 512mb 64mx72 64mx4(k4s560432e) * 18ea 1,200mil m390s6453et1-c7a 512mb 64mx72 32mx8(k4s560832e) * 18ea 1,700mil m390s2858et1-c7a 1gb 128mx72 st.128mx4(k4s510632e) * 18ea 1,700mil m390s2858etu-c7a 1gb 128mx72 st.128mx4(k4s510632e) * 18ea 1,200mil 7a @cl3 @cl2 maximum clock frequency 133mhz(7.5ns) 100mhz(10ns) cl-trcd-trp(clock) 3 - 3 - 3 2 - 2 - 2 feature ? burst mode operation ? auto & self refresh capability (8192 cycles/64ms) ? lvttl compatible inputs and outputs ? single 3.3v 0.3v power supply ? mrs cycle with address key program s latency (access from column address) burst length (1, 2, 4, 8 & full page) data scramble (sequential & interleave) ? all inputs are sampled at the pos itive going edge of the system clock ? serial presence detect with eeprom
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram * samsung electronics co., ltd. re serves the right to change products and specifications without notice. pin configurations (front side/back side) pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 front vss dq0 dq1 dq2 dq3 vdd dq4 dq5 dq6 dq7 dq8 vss dq9 dq10 dq11 dq12 dq13 vdd dq14 dq15 cb0 cb1 vss nc nc vdd we dqm0 pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 front dqm1 **cs0 du vss a0 a2 a4 a6 a8 a10/ap ba1 vdd vdd **clk0 vss du **cs2 dqm2 dqm3 du vdd nc nc cb2 cb3 vss dq16 dq17 pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 front dq18 dq19 vdd dq20 nc *vref **cke1 vss dq21 dq22 dq23 vss dq24 dq25 dq26 dq27 vdd dq28 dq29 dq30 dq31 vss **clk2 nc nc sda scl vdd pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 back vss dq32 dq33 dq34 dq35 vdd dq36 dq37 dq38 dq39 dq40 vss dq41 dq42 dq43 dq44 dq45 vdd dq46 dq47 cb4 cb5 vss nc nc vdd cas dqm4 pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 back dqm5 **cs1 ras vss a1 a3 a5 a7 a9 ba0 a11 vdd **clk1 a12 vss **cke0 **cs3 dqm6 dqm7 *a13 vdd nc nc cb6 cb7 vss dq48 dq49 pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 back dq50 dq51 vdd dq52 nc *vref rege vss dq53 dq54 dq55 vss dq56 dq57 dq58 dq59 vdd dq60 dq61 dq62 dq63 vss **clk3 nc sa0 sa1 sa2 vdd 1. * these pins are not used in this module. 2. p ins 82,83,165,166,167 should be nc in the system which does not support spd. 3. ** about these pins, refer to the block diagram of each. note : pin description pin name function pin name function a0 ~ a12 address input (multiplexed) dqm0 ~ 7 dqm ba0 ~ ba1 select bank v dd power supply (3.3v) dq0 ~ dq63 data input/output v ss ground cb0 ~ cb7 check bit (data-in/data-out) *v ref power supply for reference clk0 ~ 3 clock input rege register enable cke0, cke1 clock enable input sda serial data i/o cs0 ~ cs3 chip select input scl serial clock ras row address strobe sa0 ~ 2 address in eeprom cas colume address strobe du don t use we write enable nc no connection
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram pin configuration description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke clock enable masks system clock to freeze oper ation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. cke should be enabled 1clk+tss prior to valid command. a0 ~ a12 address row/column addresses are multiplexed on the same pins. row address : ra0 ~ ra12 column address : (x4 : ca0 ~ ca9, ca11), (x8 : ca0 ~ ca9) ba0 ~ ba1 bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the posit ive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. dqm0 ~ 7 data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. (byte masking) rege register enable the device operates in the tr ansparent mode when rege is low. when rege is high, the device operates in the registered mode. in registered mode, the address and con- trol inputs are latched if clk is held at a hi gh or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of clk. rege is tied to v dd through 10k ohm resistor on pcb. so if rege of module is floating, this module will be operated as reg- istered mode. dq0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. cb0 ~ 7 check bit check bits for ecc. v dd /v ss power supply/ground power and ground for the input buffers and the core logic.
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram 256mb, 32mx72 ecc module (m390s3253et1) (populated as 1 bank of x8 sdram module) functional block diagram a0~a9 ras ,cas ,we dqm0,1,4,5 cs0 rege pclk2 b 0 a0~b 0 a9 bras ,bcas ,bwe bdqm0,1,4,5 bcs0 74alvcf162835 a10,a11,a12,ba0~1 cs2 cke0 dqm2,3,6,7 b 0 a10,b 0 a11,b 0 a12,bba0~1 bcs2 bcke0 bdqm2,3,6,7 v dd 10k ? oe le 74alvcf162835 oe le clk cs cke add,ctl dqm dq0~7 d0 clk cs cke add,ctl dqm dq0~7 d1 clk cs cke add,ctl dqm dq0~7 d2 clk cs cke add,ctl dqm dq0~7 d3 clk cs cke add,ctl dqm dq0~7 d5 clk cs cke add,ctl dqm dq0~7 d4 clk cs cke add,ctl dqm dq0~7 d6 clk cs cke add,ctl dqm dq0~7 d8 clk cs cke add,ctl dqm dq0~7 d7 10 ? 10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cdcf2509 2g agnd 1g avcl 1y0 1y1 1y2 1y3 1y4 2y0 2y1 2y2 2y3 clk fibin v ss 10 ? v dd clk0 fbout 12pf 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? clk1,2,3 12pf note 1. the actual values of cb will depend upon the pll chosen. cb *1 serial pd sda scl a1 a2 a0 sa1 sa2 sa0 wp 47k ? pclk0 bcs0 bcke0 b 0 a0~b 0 a12,bba0~1,bras ,bcas ,bwe bdqm0 dq0~7 dq8~15 pclk1 bdqm1 cb0~7 bcs2 bdqm2 dq16~23 pclk3 bdqm3 dq24~31 bdqm4 dq32~39 bdqm5 dq40~47 bdqm6 dq48~55 bdqm7 dq56~63 pclk0 pclk1 pclk2 pclk3
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram 256mb, 32mx72 ecc module (m390s3253etu) (populated as 1 bank of x8 sdram module) functional block diagram a0~a6,ba0~1 ras ,cas ,we dqm0,1,4,5 cs0 rege pclk2 b 0 a0~b 0 a6 bras ,bcas ,bwe bdqm0,1,4,5 bcs0 74alvcf162835 v dd 10k ? oe le 74alvcf162835 oe le clk cs cke add,ctl dqm dq0~7 d0 clk cs cke add,ctl dqm dq0~7 d1 clk cs cke add,ctl dqm dq0~7 d2 clk cs cke add,ctl dqm dq0~7 d3 clk cs cke add,ctl dqm dq0~7 d5 clk cs cke add,ctl dqm dq0~7 d4 clk cs cke add,ctl dqm dq0~7 d6 clk cs cke add,ctl dqm dq0~7 d8 clk cs cke add,ctl dqm dq0~7 d7 10 ? 10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cdcf2509 2g agnd 1g avcl 1y0 1y1 1y2 1y3 1y4 2y0 2y1 2y2 2y3 clk fibin v ss 10 ? v dd clk0 fbout 12pf 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? clk1,2,3 12pf note 1. the actual values of cb will depend upon the pll chosen. cb *1 pclk1 ? ? ? serial pd sda scl a1 a2 a0 sa1 sa2 sa0 wp 47k ? pclk0 bcs0 bcke0 b 0 a0~b 0 a12,bba0~1,bras ,bcas ,bwe bdqm0 dq0~7 dq8~15 pclk2 bdqm1 cb0~7 pclk3 bcs2 bdqm2 dq16~23 pclk4 bdqm3 dq24~31 bdqm4 dq32~39 bdqm5 dq40~47 bdqm6 dq48~55 bdqm7 dq56~63 pclk4 pclk5 pclk0 pclk1 pclk2 pclk3 a7~a12,ba0~1 cs2 cke0 dqm2,3,6,7 b 0 a7~b 0 a12,bba0~bba1 bcs2 bcke0 bdqm2,3,6,7
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram functional block diagram 512mb 64mx72 ecc module (m390s6450et1) (populated as 1 bank of x4 sdram module) 10 ? 10 ? clk cs cke add,ctl dqm dq0~3 d0 clk cs cke add,ctl dqm dq0~3 d1 clk cs cke add,ctl dqm dq0~3 d2 clk cs cke add,ctl dqm dq0~3 d3 clk cs cke add,ctl dqm dq0~3 d5 clk cs cke add,ctl dqm dq0~3 d4 clk cs cke add,ctl dqm dq0~3 d6 clk cs cke add,ctl dqm dq0~3 d8 clk cs cke add,ctl dqm dq0~3 d7 clk cs cke add,ctl dqm dq0~3 d9 clk cs cke add,ctl dqm dq0~3 d10 clk cs cke add,ctl dqm dq0~3 d11 clk cs cke add,ctl dqm dq0~3 d12 clk cs cke add,ctl dqm dq0~3 d14 clk cs cke add,ctl dqm dq0~3 d13 clk cs cke add,ctl dqm dq0~3 d15 clk cs cke add,ctl dqm dq0~3 d17 clk cs cke add,ctl dqm dq0~3 d16 cdcf2510 2g agnd 1g avcl iy0 iy1 iy2 iy3 iy4 2y0 2y1 clk fibin v ss 10 ? v dd clk0 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? fbou pclk0 pclk1 pclk2 pclk3 pclk4 pclk5 pclk6 10 ? a 3 ~a 10 ,ba0 74alvcf162835 a 11 ,a 12 ,ba1 cs2 cke0 dqm2,3,6,7 b 0 a 0 ,b 0 a 1 ,b 0 a 2 b 1 a 0 ,b 1 a 1 ,b 1 a 2 b 0 ras , b 0 cas , b 0 we b 1 ras , b 1 cas , b 1 we bcs0 bdqm0,1,4,5 v dd 10k ? oe le 74alvcf162835 oe le pclk6 rege 74alvcf162835 oe le a 0 ,a 1 ,a 2 ras ,cas ,we 12pf 10 ? b 0 a 11 . b 0 a 12. b 0 ba1 b 1 a 11 . b 1 a 12. b 1 ba1 bcs2 b 0 cke0 b 1 cke0 bdqm2,3,6,7 b 0 a 3 ~b 0 a 10 ,b 0 ba0 b 1 a 3 ~b 1 a 10 ,b 1 ba0 cs0 dqm0,1,4,5 10 ? 10 ? clk1,2,3 12pf note 1. the actual values of cb will depend upon the pll chosen. cb *1 serial pd sda scl a1 a2 a0 sa1 sa2 sa0 wp 47k ? pclk0 bcs0 b 0 cke0 b 0 a0~b 0 a12,b 0 ba0,b 0 ba1,b 0 ras ,b 0 cas ,b 0 we bdqm0 dq0~3 dq4~7 pclk1 bdqm1 dq8~11 pclk2 dq12~15 cb0~3 pclk3 bcs2 dq16~19 pclk4 bdqm2 dq20~23 dq24~27 pclk5 b 1 a0~b 1 a12,b 1 ba0,b 1 ba1,b 1 ras ,b 1 cas ,b 1 we bdqm3 dq28~31 b 1 cke0 bdqm4 dq32~35 dq36~39 bdqm5 dq40~43 dq44~47 cb4~7 dq48~51 bdqm6 dq52~55 dq56~59 bdqm7 dq60~63
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram cdcf2510 2g agnd 1g avcl iy0 iy1 iy2 iy3 iy4 iy5 iy6 iy7 iy8 iy9 clk fibin v ss 10 ? v dd clk0 fbout 12pf 10 ? clk1,2,3 12pf note 1. the actual values of cb will depend upon the pll chosen. cb *1 pclk9 pclk5 pclk6 pclk7 pclk8 pclk0 pclk1 pclk2 pclk3 pclk4 serial pd sda scl a1 a2 a0 sa1 sa2 sa0 wp 47k ? a 0 ~a 12 ,ba0~1, ras , cas 74alvcf162835 b 0 we b 1 we v dd 10k ? oe le 74alvcf162835 oe le pclk9 rege 74alvcf162835 oe le cke0 b 0 a 0 ~b 0 a 12 ,b 0 ba0~1, b 0 ras , b 0 cas dqm0~7,cs 0,cs 2 b 1 a 0 ~b 1 a 12 ,b 1 ba0~1, b 1 ras , b 1 cas b 0 cke0 b 1 cke0 we 10 ? 10 ? clk cs cke add,ctl dqm dq0~3 d0 clk cs cke add,ctl dqm dq0~3 d1 clk cs cke add,ctl dqm dq0~3 d2 clk cs cke add,ctl dqm dq0~3 d3 clk cs cke add,ctl dqm dq0~3 d5 clk cs cke add,ctl dqm dq0~3 d4 clk cs cke add,ctl dqm dq0~3 d6 clk cs cke add,ctl dqm dq0~3 d8 clk cs cke add,ctl dqm dq0~3 d7 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? d9 d10 d11 d12 d14 d13 d15 d17 d16 functional block diagram 512mb 64mx72 ecc module (m390s6450etu) (populated as 1 bank of x4 sdram module) bcs0 b 0 cke0 b 0 a 0 ~b 0 a 12 ,b 0 ba0~1, b 0 ras , b 0 cas, b 0 we bdqm0 dq0~3 pclk0 pclk1 dq4~7 pclk2 bdqm1 dq8~11 pclk3 dq12~15 pclk4 cb0~3 pclk5 bcs2 bdqm2 dq16~19 pclk6 dq20~23 pclk7 bdqm3 dq24~27 pclk8 bcs2 b 1 cke0 b 1 a 0 ~b 1 a 12 ,b 1 ba0~1, b 1 ras , b 1 cas, b 1 we dq28~31 bdqm0~7, bcs 0,bcs 2 bdqm4 dq32~35 dq36~39 bdqm5 dq40~43 dq44~47 cb4~7 bdqm6 dq48~51 dq52~55 bdqm7 dq56~59 dq60~63
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram functional block diagram 512mb, 64mx72 ecc module (m390s6453et1) (populated as 2 bank of x8 sdram module) 10 ? 10 ? clk cs cke add,ctl dqm dq0~3 d0 clk cs cke add,ctl dqm dq0~3 d1 clk cs cke add,ctl dqm dq0~3 d2 clk cs cke add,ctl dqm dq0~3 d3 clk cs cke add,ctl dqm dq0~3 d5 clk cs cke add,ctl dqm dq0~3 d4 clk cs cke add,ctl dqm dq0~3 d6 clk cs cke add,ctl dqm dq0~3 d8 clk cs cke add,ctl dqm dq0~3 d7 clk cs cke add,ctl dqm dq0~3 d9 clk cs cke add,ctl dqm dq0~3 d10 clk cs cke add,ctl dqm dq0~3 d11 clk cs cke add,ctl dqm dq0~3 d12 clk cs cke add,ctl dqm dq0~3 d14 clk cs cke add,ctl dqm dq0~3 d13 clk cs cke add,ctl dqm dq0~3 d15 clk cs cke add,ctl dqm dq0~3 d17 clk cs cke add,ctl dqm dq0~3 d16 cdcf2510 2g agnd 1g avcl iy0 iy1 iy2 iy3 iy4 2y0 2y1 clk fibin v ss 10 ? v dd clk0 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? fbout pclk0 pclk1 pclk2 pclk3 pclk4 pclk5 pclk6 10 ? a 3 ~a 10 ,ba0 74alvcf162835 a 11 ,a 12 ,ba1 cs2 cke0 dqm2,3,6,7 b 0 a 0 ,b 0 a 1 ,b 0 a 2 b 1 a 0 ,b 1 a 1 ,b 1 a 2 b 0 ras , b 0 cas , b 0 we b 1 ras , b 1 cas , b 1 we bcs0 bdqm0,1,4,5 v dd 10k ? oe le 74alvcf162835 oe le pclk6 rege 74alvcf162835 oe le a 0 ,a 1 ,a 2 ras ,cas ,we 12pf 10 ? b 0 a 11 . b 0 a 12. b 0 ba1 b 1 a 11 . b 1 a 12. b 1 ba1 bcs2 b 0 cke0 b 1 cke0 bdqm2,3,6,7 b 0 a 3 ~b 0 a 10 ,b 0 ba0 b 1 a 3 ~b 1 a 10 ,b 1 ba0 cs0 dqm0,1,4,5 10 ? 10 ? clk1,2,3 12pf note 1. the actual values of cb will depend upon the pll chosen. cb *1 serial pd sda scl a1 a2 a0 sa1 sa2 sa0 wp 47k ? pclk0 bcs0 b 0 cke0 b 0 a0~b 0 a12,b 0 ba0,b 0 ba1,b 0 ras ,b 0 cas ,b 0 we bdqm0 dq0~3 dq4~7 pclk1 bdqm1 dq8~11 pclk2 dq12~15 cb0~3 pclk3 bcs2 dq16~19 pclk4 bdqm2 dq20~23 dq24~27 pclk5 b 1 a0~b 1 a12,b 1 ba0,b 1 ba1,b 1 ras ,b 1 cas ,b 1 we bdqm3 dq28~31 b 1 cke0 bdqm4 dq32~35 dq36~39 bdqm5 dq40~43 dq44~47 cb4~7 dq48~51 bdqm6 dq52~55 dq56~59 bdqm7 dq60~63
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram 10 ? cb4~7 10 ? cb0~3 10 ? dq12~15 10 ? dq8~11 clk cs1, cke ctl add dqm dq0~3 d0l 10 ? 10 ? 10 ? clk cs0, cke ctl add dqm dq0~3 d0u bcs1 ,b 2 cke0 clk cs1, cke ctl add dqm dq0~3 d1l clk cs0, cke ctl add dqm dq0~3 d1u dq0~3 dq4~7 clk cs0, cke ctl add dqm dq0~3 d9l clk cs1, cke ctl add dqm dq0~3 d9u dq32~35 10 ? clk cs0, cke ctl add dqm dq0~3 d10l clk cs1, cke ctl add dqm dq0~3 d10u dq36~39 clk cs1, cke ctl add dqm dq0~3 d2l clk cs0, cke ctl add dqm dq0~3 d2u clk cs1, cke ctl add dqm dq0~3 d3l clk cs0, cke ctl add dqm dq0~3 d3u pclk2 bdqm1 clk cs1, cke ctl add dqm dq0~3 d4l clk cs0, cke ctl add dqm dq0~3 d4u 10 ? clk cs0, cke ctl add dqm dq0~3 d11l clk cs1, cke ctl add dqm dq0~3 d11u dq40~43 bdqm5 10 ? clk cs0, cke ctl add dqm dq0~3 d12l clk cs1, cke ctl add dqm dq0~3 d12u dq44~47 clk cs0, cke ctl add dqm dq0~3 d13l clk cs1, cke ctl add dqm dq0~3 d13u 10 ? dq28~31 10 ? dq24~27 clk cs1, cke ctl add dqm dq0~3 d5l 10 ? 10 ? 10 ? clk cs0, cke ctl add dqm dq0~3 d5u clk cs1 ctl add dqm dq0~3 d6l clk cs0, cke ctl add dqm dq0~3 d6u dq16~19 dq20~23 clk cs0, cke ctl add dqm dq0~3 d14l clk cs1, cke ctl add dqm dq0~3 d14u dq48~51 bdqm6 10 ? clk cs0, cke ctl add dqm dq0~3 d15l clk cs1, cke ctl add dqm dq0~3 d15u dq52~55 clk cs1, cke ctl add dqm dq0~3 d7l clk cs0, cke ctl add dqm dq0~3 d7u clk cs1, cke ctl add dqm dq0~3 d8l clk cs0, cke ctl add dqm dq0~3 d8u pclk7 bdqm3 10 ? clk cs0, cke ctl add dqm dq0~3 d16l clk cs1, cke ctl add dqm dq0~3 d16u dq56~59 bdqm7 10 ? clk cs0, cke ctl add dqm dq0~3 d17l clk cs1, cke ctl add dqm dq0~3 d17u dq60~63 bdqm4 a 3 ~a 10 ,ba0 b 0 a 3~ b 0 a 10, b 0 ba0 74alvcf162835 cs2 ,cs3 cke0 dqm2,3,6,7 v dd 10k ? oe le 74alvcf162835 oe le pclk9 rege bcs2 ,bcs3 b 0 cke0,b 1 cke0 b 2 cke0,b 3 cke0 bdqm2,3,6,7 74alvcf162835 oe le a 0 ,a 1 ,a 2 ras ,cas ,we cs0 ,cs1 dqm0,1,4,5 cdcf2510 g agnd avdd iy0 iy1 iy2 iy3 iy4 iy5 iy6 iy7 iy8 clk fbin v ss 10 ? v dd clk0 12pf fbou pclk0 pclk1 pclk2 pclk3 pclk4 pclk5 pclk6 pclk7 pclk8 pclk9 pclk8 pclk6 pclk1 pclk3 pclk4 bcs0 ,b 0 cke0 bcs2 ,b 1 cke0 b 1 a0~b 1 a12 b 0 ras ,b 0 cas ,b 0 we, b 0 ba0,b 0 ba1 b 0 a0~b 0 a12 pclk0 bdqm0 bcs3 ,b 3 cke0 b 1 a 3~ b 1 a 10, b 1 ba0 a 11 ,a 12 ,ba1 b 0 a 11, b 0 a 12. b 0 ba1 b 1 a 11 ,b 1 a 12. b 1 ba1 cs2 ,cs3 cke0 dqm2,3,6,7 b 0 a 0 ,b 0 a 1 ,b 0 a 2 b 1 a 0 ,b 1 a 1 ,b 1 a 2 b 0 ras , b 0 cas , b 0 we b 1 ras , b 1 cas , b 1 we bcs0 ,bcs1 bdqm0,1,4,5 b 1 ras ,b 1 cas ,b 1 we, b 1 ba0,b 1 ba1 10 ? clk1,2,3 12pf note 1. the actual values of cb will depend upon the pll chosen. cb *1 serial pd sda scl a1 a2 a0 sa1 sa2 sa0 wp 47k ? functional block diagram 1gb, 128mx72 ecc module (m390s2858et1) (populated as 2 bank of x4 sdram module) pclk5 bdqm2
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram cdcf2510 2g agnd 1g avcl iy0 iy1 iy2 iy3 iy4 iy5 iy6 iy7 iy8 iy9 clk fibin v ss 10 ? v dd clk0 fbout 12pf 10 ? clk1,2,3 12pf note 1. the actual values of cb will depend upon the pll chosen. cb *1 pclk9 pclk5 pclk6 pclk7 pclk8 pclk0 pclk1 pclk2 pclk3 pclk4 serial pd sda scl a1 a2 a0 sa1 sa2 sa0 wp 47k ? a 0 ~a 12 ,ba0~1, ras , cas 74alvcf162835 b 0 we, b 0 cke1 b 1 we, b 1 cke1 v dd 10k ? oe le 74alvcf162835 oe le pclk9 rege 74alvcf162835 oe le cke0 b 0 a 0 ~b 0 a 12 ,b 0 ba0~1, b 0 ras , b 0 cas dqm0~7,cs 0~3 b 1 a 0 ~b 1 a 12 ,b 1 ba0~1, b 1 ras , b 1 cas b 0 cke0 b 1 cke0 we bdqm0~7, bcs 0~3 10 ? 10 ? clk cs cke add,ctl dqm dq0~3 d0l clk cs cke add,ctl dqm dq0~3 d1l clk cs cke add,ctl dqm dq0~3 d2l clk cs cke add,ctl dqm dq0~3 d3l clk cs cke add,ctl dqm dq0~3 d5l clk cs cke add,ctl dqm dq0~3 d4l clk cs cke add,ctl dqm dq0~3 d6l clk cs cke add,ctl dqm dq0~3 d8l clk cs cke add,ctl dqm dq0~3 d7l clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? d9l d10l d11l d12l d14l d13l d15l d17l d16l clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 d9 d10 d11 d12 d14 d13 d15 d17 d16 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 clk cs cke add,ctl dqm dq0~3 d0u d1u d2u d3u d5u d4u d6u d8u d7u 10 ? bcs3 functional block diagram 1gb, 128mx72 ecc module (m390s2858etu) (populated as 2 bank of x4 sdram module) bcs1 pclk0 bcs0 b 0 cke0 b 0 a 0 ~b 0 a 12 ,b 0 ba0~1, b 0 ras , b 0 cas, b 0 we bdqm0 dq0~3 pclk1 dq4~7 pclk2 bdqm1 dq8~11 pclk3 dq12~15 pclk4 cb0~3 pclk5 bcs2 bdqm2 dq16~19 pclk6 dq20~23 pclk7 bdqm3 dq24~27 pclk8 bcs2 b 1 cke0 b 1 a 0 ~b 1 a 12 ,b 1 ba0~1, b 1 ras , b 1 cas, b 1 we bdqm0 dq28~31 bdqm4 dq32~35 dq36~39 bdqm5 dq40~43 dq44~47 cb4~7 bdqm6 dq48~51 dq52~55 bdqm7 dq56~59 bdqm7 dq60~63
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram td, tr = delay of register notes : 1. in case of module timing, command cy cles delayed 1clk with respect to external input timing at the address and input signa l because of the buffering in regi ster. therefore, input/output signal s of read/write function should be issued 1clk earlier as compared to unbuffered dimms. 2. d in is to be issued 1clock after writ e command in external timing because d in is issued directly to module. : don t care standard timing diagram with pll & register (cl=2, bl=4) reg control signal(ras ,cas ,we ) *1 *2 *3 d out *1. register input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk ras cas we ras cas we tsac trdl read row active command row active write command precharge command 1clk td tr td tr *2. register output *3. sdram trac(refer to *1) cas latency(refer to *1) =2clk+1clk dq qa0 qa1 qa2 qa3 db0 db1 db2 db3 precharge command cas latency(refer to *2) =2clk trac(refer to *2)
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 * # of component w short circuit current i os 50 ma permanent device damage may occur if "abso lute maximum ratings" are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended per iods of time could af fect device reliability. note : dc operating conditions and characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note supply voltage v dd 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v ddq +0.3 v 1 input low voltage v il -0.3 0 0.8 v 2 output high voltage v oh 2.4 - - v i oh = -2ma output low voltage v ol --0.4vi ol = 2ma input leakage current i li -10 - 10 ua 3 capacitance(max.) (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref = 1.4v 200 mv) parameter symbol m390s3253et1 m390s3253etu m390s6450et1 m390s6450etu m390s6453et1 m390s2858et1 m390s2858etu unit input capacitance (a0 ~ a11) input capacitance (ras , cas , we ) input capacitance (cke0) input capacitance (clk0) input capacitance (cs0 , cs2 ) input capacitance (dqm0 ~ dqm7) input capacitance (ba0 ~ ba1) data input/output capacitance (dq0~dq63) data input/ouput capacitance (cb0~cb7) c in1 c in2 c in3 c in4 c in5 c in6 c in7 c out1 c out2 15 15 15 23 15 15 15 16 16 15 15 15 20 15 15 15 16 16 19 19 33 12 12 12 12 19 19 15 15 15 20 15 15 15 22 22 pf pf pf pf pf pf pf pf pf 1. v ih (max) = 5.6v ac.the over shoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. notes :
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram dc characteristics (recommended operating conditi on unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note 7a operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i o = 0 ma 1,220 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 370 ma i cc2 ps cke & clk v il (max), t cc = 20 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 530 ma i cc2 ns cke v ih (min), clk v il (max), t cc = input signals are stable 95 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 405 ma i cc3 ps cke & clk v il (max), t cc = 60 active standby current in non power-down mode (one bank active) i cc3 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 575 ma i cc3 ns cke v ih (min), clk v il (max), t cc = input signals are stable 230 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 1,400 ma 1 refresh current i cc5 t rc t rc (min) 2,120 ma 2 self refresh current i cc6 cke 0.2v 380 ma m390s3253etu(1) (32m x 72, 256mb module) (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note 7a operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i o = 0 ma 1,940 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 370 ma i cc2 ps cke & clk v il (max), t cc = 40 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 710 ma i cc2 ns cke v ih (min), clk v il (max), t cc = input signals are stable 185 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 460 ma i cc3 ps cke & clk v il (max), t cc = 110 active standby current in non power-down mode (one bank active) i cc3 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 800 ma i cc3 ns cke v ih (min), clk v il (max), t cc = input signals are stable 455 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 2,300 ma 1 refresh current i cc5 t rc t rc (min) 3,740 ma 2 self refresh current i cc6 cke 0.2v 405 ma m390s6450etu(1) (64m x 72, 512mb module) notes : 1. measured with outputs open. 2. refresh period is 64ms. 3. unless otherwise noted, input swing level is cmos(v ih /v il =v ddq /v ssq )
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note 7a operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i o = 0 ma 1,445 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 390 ma i cc2 ps cke & clk v il (max), t cc = 40 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 710 ma i cc2 ns cke v ih (min), clk v il (max), t cc = input signals are stable 185 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 460 ma i cc3 ps cke & clk v il (max), t cc = 110 active standby current in non power-down mode (one bank active) i cc3 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 800 ma i cc3 ns cke v ih (min), clk v il (max), t cc = input signals are stable 455 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 1,625 ma 1 refresh current i cc5 t rc t rc (min) 2,345 ma 2 self refresh current i cc6 cke 0.2v 405 ma m390s6453et1 (64m x 72, 512mb module) dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note 7a operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i o = 0 ma 2,390 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 425 ma i cc2 ps cke & clk v il (max), t cc = 75 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 1,070 ma i cc2 ns cke v ih (min), clk v il (max), t cc = input signals are stable 365 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 570 ma i cc3 ps cke & clk v il (max), t cc = 220 active standby current in non power-down mode (one bank active) i cc3 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 1,250 ma i cc3 ns cke v ih (min), clk v il (max), t cc = input signals are stable 905 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 2,750 ma 1 refresh current i cc5 t rc t rc (min) 4,190 ma 2 self refresh current i cc6 cke 0.2v 460 ma m390s2858etu(1) (128m x 72, 1gb module) notes : 1. measured with outputs open. 2. refresh period is 64ms. 3. unless otherwise noted, input swing level is cmos(v ih /v il =v ddq /v ssq )
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram 3.3v 1200 ? 870 ? output 50pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50 ? output 50pf z0 = 50 ? (fig. 2) ac output load circuit (fig. 1) dc output load circuit ac operating test conditions (v dd = 3.3v 0.3v, t a = 0 to 70 c) parameter value unit ac input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 operating ac parameter notes : (ac operating conditions unless otherwise noted) parameter symbol version unit note 7a row active to row active delay t rrd (min) 15 ns 1 ras to cas delay t rcd (min) 20 ns 1 row precharge time t rp (min) 20 ns 1 row active time t ras (min) 45 ns 1 t ras (max) 100 us row cycle time t rc (min) 65 ns 1 last data in to row precharge t rdl (min) 2 clk 2,5 last data in to active delay t dal (min) 2 clk + trp - 5 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 1. the minimum number of cloc k cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. 5. in 100mhz and below 100mhz operating conditions, trdl=1clk and tdal=1clk + 20ns is also supported. samsung recommends trdl=2clk and tdal=2clk + trp .
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, trans ient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. notes : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol 7a unit note min max clk cycle time cas latency=3 t cc 7.5 1000 ns 1 cas latency=2 10 clk to valid output delay cas latency=3 t sac 5.4 ns 1,2 cas latency=2 6 output data hold time cas latency=3 t oh 3 ns 2 cas latency=2 3 clk high pulse width t ch 2.5 ns 3 clk low pulse width t cl 2.5 ns 3 input setup time t ss 1.5 ns 3 input hold time t sh 0.8 ns 3 clk to output in low-z t slz 1ns2 clk to output in hi-z cas latency=3 t shz 5.4 ns cas latency=2 6 refer to the individual componenet, not the whole module.
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 0 ~ a 9, a 11, a 12 note register mode register set h x l l l l x op code 1,2 refresh auto refresh h h ll lhx x 3 self refresh entry l 3 exit l h lh hh xx 3 hx x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable hxlhlhxv l column address 4 auto precharge enable h 4,5 write & column address auto precharge disable h x lhllx v l column address 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge bank selection hxllhlx vl x all banks xh clock suspend or active power down entry h l hx x x x x lv vv exit l h x x x x x precharge power down mode entry h l hx x x x x lh hh exit l h hx x x x lv vv dqm h v x 7 no operation command h x hx x x xx lh hh 1. op code : operand code a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be iss ued after 2 clock cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical prec harge without row precharge command is meant by "auto". auto/self refresh can be is sued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row acti ve and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row acti ve and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row ac tive and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row ac tive and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto prec harge, new read/write co mmand can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is va lid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 cl k cycles after. (read dqm latency is 2) notes : x
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram package dimensions : 32mx72 (m390s3253et1) units : inches (millimeters) 0.250 (6.350) detail a 0.123 0.005 (3.125 0.125) 0.250 (6.350) detail b 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.079 0.004 (2.000 0.100) tolerances : 0.005(.13) unless otherwise specified the used device is 32mx8 sdram, tsopii sdram part no. : k4s560832e this module is based on je dec pc133 specification 5.250 5.014 r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.700 (17.780) (8.890) a c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100) 0.054 (1.372) (127.350) (133.350) 1.500 (38.1) 0.118 (3.000) b reg pll reg 0.150 max 0.050 0.0039 (1.270 0.10) 0.157 min (3.99 min) (3.81 max) 0.050 0.008 0.006 (0.200 0.150) (1.270) detail c 0.039 0.002 (1.000 0.050) .118dia + 0.004/-0.000 (3.000dia + 0.100/-0.000) 0.0984 0.008 (2.500 0.2 ) (2.500 0.2 ) 0.0984 0.008
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram package dimensions : 32mx72 (m390s3253etu) units : inches (millimeters) 0.250 (6.350) detail a 0.123 0.005 (3.125 0.125) 0.250 (6.350) detail b 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.079 0.004 (2.000 0.100) tolerances : 0.005(.13) unless otherwise specified the used device is 32mx8 sdram, tsopii sdram part no. : k4s560832e this module is based on je dec pc133 specification 5.250 5.014 r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.0984 0.008 (2.500 0.2 ) 0.700 (17.780) .118dia + 0.004/-0.000 (3.000dia + 0.100/-0.000) (8.890) a c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100) 0.054 (1.372) (127.350) (133.350) 1.200 (38.1) 0.118 (3.000) b reg pll 0.150 max 0.050 0.0039 (1.270 0.10) 0.157 min (3.99 min) (3.81 max) 0.050 0.008 0.006 (0.200 0.150) (1.270) detail c 0.039 0.002 (1.000 0.050) reg (2.500 0.2 ) 0.0984 0.008
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram package dimensions : 64mx72 (m390s6450et1) 0.250 (6.350) detail a 0.123 0.005 (3.125 0.125) 0.250 (6.350) detail b 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.079 0.004 (2.000 0.100) tolerances : 0.005(.13) unless otherwise specified the used device is 64mx4 sdram, tsopii sdram part no. : k4s560432e this module is based on je dec pc133 specification 5.250 5.014 units : inches (millimeters) 0.150 max 0.050 0.0039 (1.270 0.10) r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.700 (17.780) (8.890) a c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100) 0.054 (1.372) (127.350) (133.350) 1.700 (43.18) 0.118 (3.000) 0.165 min (4.19 min) (3.81 max) b reg reg pll reg 0.050 0.008 0.006 (0.200 0.150) (1.270) detail c 0.039 0.002 (1.000 0.050) (2.500 0.2 ) 0.0984 0.008 0.0984 0.008 (2.500 0.2 ) .118dia + 0.004/-0.000 (3.000dia + 0.100/-0.000)
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram package dimensions : 64mx72 (m390s6450etu) 0.250 (6.350) detail a 0.123 0.005 (3.125 0.125) 0.250 (6.350) detail b 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.079 0.004 (2.000 0.100) tolerances : 0.005(.13) unless otherwise specified the used device is 64mx4 sdram, tsopii sdram part no. : k4s560432e this module is based on je dec pc133 specification 5.250 5.014 units : inches (millimeters) r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.700 (17.780) (8.890) a c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100) 0.054 (1.372) (127.350) (133.350) 1.200 (30.48) 0.118 (3.000) b pll 0.050 0.008 0.006 (0.200 0.150) (1.270) detail c 0.039 0.002 (1.000 0.050) 0.150 max 0.050 0.0039 (1.270 0.10) 0.157 min (3.99 min) (3.81 max) reg reg reg .118dia + 0.004/-0.000 (3.000dia + 0.100/-0.000) 0.0984 0.008 (2.500 0.2 ) (2.500 0.2 ) 0.0984 0.008
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram package dimensions : 64mx72 (m390s6453et1) 0.250 (6.350) detail a 0.123 0.005 (3.125 0.125) 0.250 (6.350) detail b 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.079 0.004 (2.000 0.100) tolerances : 0.005(.13) unless otherwise specified the used device is 32mx8 sdram, tsopii sdram part no. : k4s560832e this module is based on je dec pc133 specification 0.050 0.039 0.002 0.008 0.006 (0.200 0.150) (1.000 0.050) (1.270) detail c 5.250 5.014 units : inches (millimeters) 0.150 max 0.050 0.0039 r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.700 (17.780) (8.890) a c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100) 0.054 (1.372) (127.350) (133.350) 1.700 (43.18) 0.118 (3.000) 0.165 min (4.19 min) (3.81 max) reg b pll reg reg (1.270 0.10) .118dia + 0.004/-0.000 (3.000dia + 0.100/-0.000) 0.0984 0.008 (2.500 0.2 ) (2.500 0.2 ) 0.0984 0.008
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram 0.250 (6.350) detail a 0.123 0.005 (3.125 0.125) 0.250 (6.350) detail b 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.079 0.004 (2.000 0.100) tolerances : 0.005(.13) unless otherwise specified sdram part no. : k4s510632e - the used device is stacked 128mx4 sdram, tsopii - staktek?s stacking technology is samsung?s stacking technology of choice this module is based on je dec pc133 specification 5.250 5.014 units : inches (millimeters) 0.254 max 0.050 0.0039 (1.270 0.10) r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.100 min (2.540 min) 0.700 (17.780) .118dia 0.004 (3.000dia 0.100) (8.890) a c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100) 0.054 (1.372) (127.350) (133.350) 1.700 (43.18) 0.118 (3.000) 0.157 min (3.99 min) (6.452 max) b reg reg pll reg 0.050 0.008 0.006 (0.200 0.150) (1.270) 0.100 min (2.540 min) detail c 0.039 0.002 (1.000 0.050) package dimensions : 128mx72 (m390s2858et1)
256mb, 512mb, 1gb registered dimm rev. 1.4 may 2004 sdram tolerances : 0.005(.13) unless otherwise specified sdram part no. : k4s510632e - the used device is stacked 128mx4 sdram, tsopii - staktek?s stacking technology is samsung?s stacking technology of choice this module is based on je dec pc133 specification 0.250 (6.350) detail a 0.123 0.005 (3.125 0.125) 0.250 (6.350) detail b 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.079 0.004 (2.000 0.100) 5.250 5.014 units : inches (millimeters) r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.100 min (2.540 min) 0.700 (17.780) .118dia 0.004 (3.000dia 0.100) (8.890) a c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100) 0.054 (1.372) (127.350) (133.350) 1.200 (30.48) 0.118 (3.000) b pll 0.050 0.008 0.006 (0.200 0.150) (1.270) 0.100 min (2.540 min) detail c 0.039 0.002 (1.000 0.050) reg reg reg 0.254 max 0.050 0.0039 (1.270 0.10) 0.157 min (3.99 min) (6.452 max) package dimensions : 128mx72 (m390s2858etu)

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