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1 white electronic designs corporation ? (602) 437-1520 www.whiteedc.com W72M64V-XBX 2mx64 3.3v simultaneous operation flash multi-chip package features ! access times of 100, 120, 150ns ! packaging 159 pbga, 13x22mm - 1.27mm pitch ! 1,000,000 erase/program cycles ! sector architecture bank 1 (8mb): eight 4k word, fifteen 32k word bank 2 (24mb): forty-eight 32k word ! bottom boot block ! zero power operation ! organized as 2mx64 or 2x2mx32 ! commercial, industrial and military temperature ranges ! 3.3 volt for read and write operations ! simultaneous read/write operation: data can be continuously read from one bank while executing erase/program functions in another bank zero latency between read and write operations ! erase suspend/resume suspends erase operations to allow programming in same bank ! data polling and toggle bits provides a software method of detecting the status of program or erase cycles ! unlock bypass program command reduces overall programming time when issuing multiple program command sequences ! ready/busy output (ry/by) hardware method for detecting program or erase cycle completion ! hardware reset pin (reset) hardware method of resetting the internal state machine to the read mode ! wp/acc input pin write protect (wp) function allows protection of two outermost boot sectors, regardless of sector protect status acceleration (acc) function accelerates program timing ! sector protection hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector temporary sector unprotect allows changing data in protected sectors in-system note: for programming information refer to flash programming W72M64V-XBX application note. november 2003 rev. 1 * preliminary datasheet. this datasheet describes a product that is not characterized or qualified and is subject to change without notice. *preliminary
2 white electronic designs corporation phoenix az (602) 437-1520 W72M64V-XBX 1 2345678910 a b c d e f g h j k l m n p r t gnd a 2 wp/a cc a 11 gnd v cc a 7 a 10 a 15 gnd gnd oe a 0 dnu v cc a 12 a 16 dnu* a 20 gnd gnd cs 3 dq 34 dq 36 dq 38 cs 4 dq 50 dq 52 dq 54 gnd v cc dq 32 dq 42 dq 44 dq 46 dq 48 dq 58 dq 60 dq 62 v cc v cc dq 40 dq 35 dq 37 dq 39 dq 56 dq 51 dq 53 dq 55 v cc v cc dq 33 dq 43 dq 45 dq 47 dq 49 dq 59 dq 61 dq 63 v cc v cc gnd dq 41 we 3 v cc dq 57 dnu we 4 v cc v cc gnd gnd gnd v cc v cc gnd gnd gnd v cc v cc gnd gnd gnd v cc v cc gnd gnd gnd v cc v cc v cc dq 25 dq 27 dq 22 cs 1 dq 2 dq 12 gnd v cc v cc cs 2 dq 18 dq 20 dq 30 dq 0 dq 10 dq 5 dq 14 v cc v cc dq 16 dq 26 dq 28 dq 23 dq 8 dq 3 dq 13 dq 7 v cc v cc dq 24 dq 19 dq 21 dq 31 dq 1 dq 11 dq 6 dq 15 v cc gnd dq 17 we 2 dq 29 dnu dq 9 dq 4 we 1 a 19 gnd gnd a 4 a 17 ry/by gnd a 14 a 5 a 18 a 8 gnd gnd a 3 a 6 a 9 v cc gnd a 1 reset a 13 gnd fig 1: pin configuration for W72M64V-XBX pin description dq 0-63 data inputs/outputs a 0-20 address inputs we 1-4 write enables cs 1-4 chip selects oe output enable reset hardware reset wp/acc hardware write protect/acceleration ry/by ready/busy output v cc power supply gnd ground dnu do not use block diagram top view dq 0-15 dq 16-31 dq 32-47 dq 48-63 cs 1 cs 2 cs 3 cs 4 2m x 16 2m x 16 2m x 16 2m x 16 byte byte byte byte we 4 we 3 we 2 we 1 wp/acc v cc a 0-20 ry/by reset oe * ball g8 is dnu on this device and will become a 21 on the w74m64v-xbx
3 white electronic designs corporation (602) 437-1520 www.whiteedc.com W72M64V-XBX parameter symbol conditions min max unit input leakage current i li v cc = 3.6v, v in = gnd to v cc -10 10 a output leakage current i lo v cc = 3.6v, v out = gnd to v cc -10 10 a v cc active current for read (1) i cc1 cs = v il , oe = v ih , f = 5mhz 65 ma v cc active current for program or erase (2,3) i cc2 cs = v il , oe = v ih, we = v il 120 ma v cc standby current (2) i cc3 cs = reset = v cc 0.3v 20 a v cc reset current (2) i cc4 reset = v ss 0.3v 20 a automatic sleep mode (2,4) i cc5 v ih = v cc 0.3v; v il = v ss 0.3v 20 a v cc active read-while-program current (1,2) i cc6 cs = v il, oe = v ih 180 ma v cc active program-while-erase current (1,2) i cc7 cs = v il, oe = v ih 180 ma v cc active program-while-erase-suspended i cc8 current (2,5) cs = v il, oe = v ih 140 ma a cc accelerated program current i acc a cc pin 40 cs = v il, oe = v ih v cc pin 120 ma input low voltage v il -0.5 0.8 v input high voltage v ih 0.7 x vcc vcc + 0.3 v voltage for wp/acc sector protect/unprotect and program acceleration v hh vcc = 3.0v + 0.3v 8.5 9.5 v voltage for autoselect and temporary sector unprotect v id vcc = 3.0v + 0.3v 8.5 12.5 v output low voltage v o l i ol = 4.0 ma, v cc = 3.0v 0.45 v output high voltage v oh1 i oh = -2.0 ma, v cc = 3.0v 0.85 x v cc v low v cc lock-out voltage (5) v lko 2.3 2.5 v absolute maximum ratings notes: 1. stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. parameter unit operating temperature -55 to +125 c supply voltage range (v cc ) -0.5 to +4.0 v signal voltage range -0.5 to vcc +0.5 v storage temperature range -55 to +150 c endurance (write/erase cycles) 1,000,000 min. cycles recommended operating conditions parameter symbol min max unit supply voltage v cc 3.0 3.6 v operating temp. (mil.) t a -55 +125 c operating temp. (ind.) t a -40 +85 c capacitance (t a = +25c) dc characteristics - cmos compatible (v cc = 3.3v 0.3v, t a = -55c to +125c) notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 5 mhz). the frequency component typically is less than 8 ma/mhz, with oe at v ih . 2. maximum i cc specifications are tested with v cc = v cc max 3. i cc active while embedded algorithm (program or erase) is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30ns. 5. not 100% tested. data retention parameter t est conditions min unit pattern data 150c 10 y ears retention time 125c 20 y ears parameter symbol conditions max unit we 1-4 capacitance c we v in = 0 v, f = 1.0 mhz 25 pf cs 1-4 capacitance c cs v in = 0 v, f = 1.0 mhz 25 pf data i/o capacitance c i/o v i/o = 0 v, f = 1.0 mhz 12 pf address input capacitance c ad v in = 0 v, f = 1.0 mhz 25 pf reset capacitance c rs v in = 0 v, f = 1.0 mhz 20 pf ry/by capacitance c rb v in = 0 v, f = 1.0 mhz 20 pf wp/a cc capacitance c wa v in = 0 v, f = 1.0 mhz 30 pf this parameter is guaranteed by design but not tested.
4 white electronic designs corporation phoenix az (602) 437-1520 W72M64V-XBX parameter symbol -100 -120 -150 unit min max min max min max write cycle time t avav t wc 100 120 150 ns write enable setup time t wlel t ws 000ns chip select pulse width t eleh t cp 45 50 50 ns address setup time t avwl t as 000ns data setup time t dveh t ds 45 50 50 ns data hold time t ehdx t dh 000ns address hold time t elax t ah 45 50 50 ns chip select pulse width high t ehel t cph 30 30 30 ns duration of byte programming operation (1) t whwh1 300 300 300 s sector erase time (2) t whwh2 15 15 15 sec read recovery time before write (3) t ghel 000ns chip programming time (4) 108 108 108 sec 1. typical value for t whwh 1 is 7s. 2. typical value for t whwh 2 is 0.7 sec. 3. guaranteed by design, but not tested. 4. typical value is 36 sec. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. ac characteristics ? write/erase/program operations - cs controlled (v cc = 3.3v 0.3v, t a = -55c to +125c) fig 2: ac test circuit ac test conditions notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z 0 = 75 ? . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. parameter typ unit input pulse levels v il = 0, v ih = 2.5 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v current source current source i ol i oh c eff = 50 pf v z 1.5v (bipolar supply d.u.t.
5 white electronic designs corporation (602) 437-1520 www.whiteedc.com W72M64V-XBX parameter symbol -100 -120 -150 unit min max min max min max write cycle time t avav t wc 100 120 150 ns chip select setup time t elwl t cs 000 ns write enable pulse width t wlwh t wp 50 50 65 ns address setup time t avwl t as 000 ns data setup time t dvwh t ds 50 50 65 ns data hold time t whdx t dh 000 ns address hold time t wlax t ah 50 50 65 ns write enable pulse width high t whwl t wph 30 30 35 ns duration of byte programming operation (1) t whwh 1 300 300 300 s sector erase (2) t whwh 2 15 15 15 sec read recovery time before write (3) t ghwl 000 ns vcc setup time t vcs 50 50 50 s chip programming time (4) 108 108 108 sec address setup time to oe low during toggle bit polling t aso 15 15 15 ns address hold time from cs or oe high during toggle t aht 000 ns output enable high during toggle bit polling t oeph 20 20 20 ns latency between read and write operations t sr / w 000 ns write recovery time from ry/by t rb 000 ns program/erase valid to ry/by t busy 90 90 90 ns ac characteristics ? write/erase/program operations - we controlled (v cc = 3.3v 0.3v, t a = -55c to +125c) 1. typical value for t whwh 1 is 7s. 2. typical value for t whwh 2 is 0.7 sec. 3. guaranteed by design, but not tested. 4. typical value is 36 sec. the typical chip programming time is considerably less than the maximum chip programming time listed , since most bytes program faster than the maximum program times listed. ac characteristics ? read-only operations (v cc = 3.3v 0.3v, t a = -55c to +125c) parameter symbol -100 -120 -150 unit min max min max min max read cycle time t avav t rc 100 120 150 ns address access time t avqv t acc 100 120 150 ns chip select access time t elqv t ce 100 120 150 ns output enable to output valid t glqv t oe 40 50 55 ns chip select high to output high z (1) t ehqz t df 20 20 20 ns output enable high to output high z (1) t ghqz t df 20 20 20 ns output hold from addresses, cs or oe change, t axqx t oh 000ns whichever occurs first read t oeh 000 output enable hold time (1) toggle and data polling 10 10 10 1. guaranteed by design, not tested.
6 white electronic designs corporation phoenix az (602) 437-1520 W72M64V-XBX fig 3: ac waveforms for read operations a ddresses cs oe we outputs high z addresses stable t oe t rc output valid t ce t acc t oh high z t df reset ry/by ov t oeh
7 white electronic designs corporation (602) 437-1520 www.whiteedc.com W72M64V-XBX ry/by cs, oe reset t rp t ready t rh t ready t rb t rp ry/by cs, oe reset ac characteristics ? hardware reset (reset) parameter symbol -100 -120 -150 unit min max min max min max reset pin low (during embedded algorithms) to read mode (see note) t ready 20 20 20 s reset pin low (not during embedded algorithms) to read mode (see note) t ready 500 500 500 ns reset pulse width t rp 500 500 500 ns reset high time before read (see note) t rh 50 50 50 ns reset low to standby mode t rpd 20 20 20 s ry/by recovery time t rb 000ns note: not tested. fig 4: reset timings not during embedded algorithms fig 5: reset timings during embedded algorithms
8 white electronic designs corporation phoenix az (602) 437-1520 W72M64V-XBX notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d out is the output of the data written to the device. 4. figure indicates last two bus cycles of four bus cycle sequence. fig 6: program operation a ddresses cs oe we data ry/by v cc 555h pa pa t wc t as t whwh1 pd status d out a0h t busy pa t as t ch t wp t cs t wph t ds t dh t vcs t rb
9 white electronic designs corporation (602) 437-1520 www.whiteedc.com W72M64V-XBX fig 8: chip/sector erase operation timings notes: 1. sa = sector address (for sector erase), va = valid address for reading status data fig 7: accelerated program timing diagram v hh t vhh t vhh v il or v ih wp/a cc v il or v ih a ddresses cs oe we data ry/by v cc 2aah sa va t wc t ah t whwh2 30h in progress complete 55h t busy va t as t ch t wp t cs t wph t ds t dh t vcs t rb 10 for chip erase 555h for chip erase
10 white electronic designs corporation phoenix az (602) 437-1520 W72M64V-XBX fig 9: back to back read/write cycle timings note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read c ycle. fig. 10: data polling timings (during embedded algorithms) a ddresses cs oe we data t ah valid ra valid pa valid pa valid pa t wc t rc t acc t wp t dh t wc t wc t ce t cph t cp t oe t wph t oeh t ghwl t df valid in valid in t ds t oh t sr/w valid out valid in we controlled write cycle read cycle cs controlled write cycle a ddresses va va va t rc cs complement complement true dq 0 -dq 6 t ce t ch t oe oe we t oeh t df t oh valid data high z ry/by t busy dq 7 t acc status data status data true valid data high z
11 white electronic designs corporation (602) 437-1520 www.whiteedc.com W72M64V-XBX we dq 6 dq 2 enter embedded erasing erase suspend enter erase suspend program erase resume erase erase suspend read erase suspend program erase suspend read erase erase complete fig 11: toggle bit timings (during embedded algorithms) note: va = valid address, not required for dq 6 . illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. fig 12: dq2 vs. dq6 note: dq 2 toggles only when read at an address within an erase-suspended sector. the system may use oe or cs to toggle dq 2 and dq 6 . ry/by dq 6 /dq 2 oe cs a ddresses we t as t aht t aht t aso t ceph t oeh t oeph t dh valid data valid status valid data t oe (first read) (second read) (stops toggling) valid status valid status
12 white electronic designs corporation phoenix az (602) 437-1520 W72M64V-XBX parameter speed options jedec std description 100 120 150 unit t avav t wc write cycle time (1) min 90 120 150 ns t avwl t as address setup time min 0 0 0 ns t elax t ah address hold time min 45 50 50 ns t dveh t ds data setup time min 45 50 50 ns t ehdx t dh data hold time min 0 0 0 ns t ghel t ghel read recovery time before write (oe high to we low) min 0 0 0 ns t wlel t ws we setup time min 0 0 0 ns t ehwh t wh we hold time min 0 0 0 ns t eleh t cp cs pulse width min 45 50 50 ns t ehel t cph cs pulse width high min 30 30 30 ns t whwh 1 t whwh 1 programming operation byte typ 9 9 9 s t whwh 1 t whwh 1 accelerated programming operation, word or byte typ 7 7 7 s t whwh 2 t whwh 2 sector erase operation typ 0.7 0.7 0.7 sec oe cs reset we sa, a 6 , a 1 , a 0 data 1 s v id v ih valid* valid* valid* sector/sector block protect or unprotect 60h 60h 40h status verify sector/sector block protect: 150 s sector/sector block unprotect: 15 ms fig 13: sector/sector block protect and unprotect timing diagram notes: for sector protect, a 6 = 0, a 1 = 1, a 0 = 0. for sector unprotect, a 6 = 1, a 1 = 1, a 0 = 0. ac characteristics ? alternate cs controlled erase and program operations note: 1. not tested.
13 white electronic designs corporation (602) 437-1520 www.whiteedc.com W72M64V-XBX fig 14: alternate cs controlled write (erase/program) operation timings notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq 7 is the complement of the data written to the device. d out is the data written to the device. a ddresses 555 for program 2aa for erase pa t wc we oe cs data t as t ah t cph t ws dq 7 reset t dh t ds pd for program 30 for sector erase 10 for chip erase pa for program sa for sector erase 555 for chip erase data polling t wh t ghel t whwh1 or 2 t busy t hr a0 for program 55 for erase ry/by t cp d out
14 white electronic designs corporation phoenix az (602) 437-1520 W72M64V-XBX w 7 2m64 v xxx b x ordering information package: 159 pbga all linear dimensions are in millimeters and parenthetically in inches. bottom view 13.1 (0.516) max 11.43 (0.450) nom 1.27 (0.050) nom 1.27 (0.050) nom 19.05 (0.750) nom 22.1 (0.870) max a b c d e f g h j k l m n p r t 10 9 8 7 6 5 4 3 2 1 159 y ? 0.762 (0.030) nom 2.03 (0.080) max 0.61 (0.024) nom white electronic designs corp. flash organization, 2m x 64 user configurable as 2 x 2m x 32 3.3v power supply access time (ns) 100 = 100ns 120 = 120ns 150 = 150ns package type: b = 159 plastic bga, 13mm x 22mm device grade: m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c
15 white electronic designs corporation (602) 437-1520 www.whiteedc.com W72M64V-XBX document title 2m x 64 simultaneous operation flash multi-chip package revision history rev # history release date status rev 0 initial release november 2002 advanced rev 1 update (pg 1, 14, 15) november 2003 preliminary 1.1 change status to preliminary 1.2 change mechanical drawing to new style

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