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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a OP186 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 5 m a, rail-to-rail output operational amplifier functional block diagram 5-lead sot-23 (rt suffix) top view (not to scale) 5 4 1 2 3 out v+ +in vC Cin OP186 features low supply current: 5.5 m a max single-supply operation: 2.2 v to 12 v wide bandwidth: 160 khz wide input voltage range rail-to-rail output swing no phase reversal output short circuit current: 6 10 ma applications portable phones comparator battery powered instrumentation safety monitoring remote sensors low voltage strain gauge amplifiers general description the OP186 is a single, low voltage, ultralow power single- supply, amplifier featuring rail-to-rail outputs. specifications are guaranteed at +2.2 v, +2.7 v, and +5.0 v single supply as well as 5 v dual supplies. fabricated on analog devices cbcmos process, the OP186 features a bipolar input and an output that swings to within millivolts of the supplies while continuing to sink or source current all the way to the supplies. applications for these amplifiers include safety monitoring, portable equipment, battery and power supply control, and as signal conditioning and interface for transducers in very low power systems. the outputs ability to swing rail-to-rail and not increase supply current when the output is driven to a supply enables the OP186 to be used as a comparator in very low power systems. the OP186 is specified over the extended industrial (C40 c to +125 c) temperature range. the OP186 is available in the sot-23-5 package.
C2C rev. 0 OP186Cspecifications electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 1 0.8 5 mv 0 c t a +125 c6mv input bias current i b 37 na 0 c t a +125 c10na input offset current i os 0.1 2 na 0 c t a +125 c5na input voltage range v cm 0 1.2 v common-mode rejection ratio cmrr v cm = 0 v to 1.2 v 65 90 db 0 c t a +125 c60 db large signal voltage gain a vo r l = 1 m w , v o = 0.3 v to 1.9 v 5 18 v/mv 0 c t a +125 c 2 v/mv offset voltage drift d v os / d t 3.5 m v/ c bias current drift d i b / d t 30 pa/ c offset current drift d i os / d t 3 pa/ c output characteristics output voltage high v oh r l = 100 k w to gnd 2.125 2.16 v 0 c to +125 c 2.1 v output voltage low v ol r l = 100 k w to v+ 25 60 mv 0 c to +125 c75mv short circuit limit i sc 500 m a power supply power supply rejection ratio psrr v s = 2.2 v to 12 v 78 95 db 0 c t a +125 c76 db supply current/amplifier i sy 45 m a 0 c t a +125 c 5.5 m a dynamic performance slew rate sr r l = 100 k w , c l = 15 pf 60 v/ms turn-on time a v = 1, v o = 1 17 m s a v = 20, v o = 1 35 m s gain bandwidth product gbp 150 khz phase margin f o 60 degrees noise performance voltage noise density e n f = 1 khz 80 nv/ ? hz current noise density i n <1 pa/ ? hz note 1 v os is tested under a no load condition. specifications subject to change without notice. (v s = +2.2 v, v cm = +1.1 v, t a = +25 8 c unless otherwise noted)
C3C rev. 0 OP186 electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 2 0.6 5 mv C40 c t a +125 c6mv input bias current i b 37 na C40 c t a +125 c10na input offset current i os 0.1 2 na C40 c t a +125 c5na input voltage range v cm 0 1.7 v common-mode rejection ratio cmrr v cm = 0 v to 1.7 v 65 90 db C40 c t a +125 c60 db large signal voltage gain a vo r l = 1 m w , v o = 0.3 v to 2.4 v 5 22 v/mv C40 c t a +125 c 2 v/mv offset voltage drift d v os / d t 3.5 m v/ c bias current drift d i b / d t 30 pa/ c offset current drift d i os / d t 3 pa/ c output characteristics output voltage high v oh r l = 100 k w to gnd 2.625 2.665 v C40 c to +125 c 2.6 v output voltage low v ol r l = 100 k w to v+ 22 50 mv C40 c to +125 c75mv short circuit limit i sc 0.8 ma power supply power supply rejection ratio psrr v s = 2.7 v to 12 v 78 95 db C40 c t a +125 c76 db supply current/amplifier i sy 4.2 5.5 m a C40 c t a +125 c7 m a dynamic performance slew rate sr r l =100 k w , c l = 15 pf 61 v/ms turn-on time a v = 1, v o = 1 17 m s a v = 20, v o = 1 25 m s gain bandwidth product gbp 155 khz phase margin f o 59 degrees noise performance voltage noise density e n f = 1 khz 80 nv/ ? hz current noise density i n <1 pa/ ? hz notes 1 +2.7 v specifications are guaranteed by +2.2 v and 5 v testing. 2 v os is tested under a no load condition. specifications subject to change without notice. (v s = +2.7 v, v cm = +1.35 v, t a = +25 8 c unless otherwise noted) 1
C4C rev. 0 OP186Cspecifications electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 2 0.6 5 mv C40 c t a +125 c6mv input bias current i b 37 na C40 c t a +125 c10na input offset current i os 0.1 2 na C40 c t a +125 c5na input voltage range v cm 04v common-mode rejection ratio cmrr v cm = 0 v to 4.0 v 65 90 db C40 c t a +125 c60 db large signal voltage gain a vo r l = 1 m w , v o = 0.5 v to 4.5 v 5 40 v/mv C40 c t a +125 c 2 v/mv offset voltage drift d v os / d t C40 c t a +125 c 3.3 m v/ c bias current drift d i b / d t 25 pa/ c offset current drift d i os / d t 3 pa/ c output characteristics output voltage high v oh r l = 100 k w to gnd 4.925 4.965 v C40 c t a +125 c 4.9 v output voltage low v ol r l = 100 k w to v+ 20 50 mv C40 c t a +125 c75mv short circuit limit i sc 3.5 ma power supply power supply rejection ratio psrr v s = 2.7 v to 12 v 78 95 db C40 c t a +125 c76 db supply current/amplifier i sy 4.7 6 m a C40 c t a +125 c 7.5 m a dynamic performance slew rate sr r l = 100 k w , c l = 15 pf 62 v/ms gain bandwidth product gbp 155 khz phase margin f o 59 degrees saturation recovery time 60 m s noise performance voltage noise e n p-p 0.1 hz to 10 hz 6 m v p-p voltage noise density e n f = 1 khz 80 nv/ ? hz f = 10 khz 70 nv/ ? hz current noise density i n <1 pa/ ? hz notes 1 +5 v specifications are guaranteed by +2.2 v and 5 v testing. 2 v os is tested under a no load condition. specifications subject to change without notice. (v s = +5.0 v, v cm = +2.5 v, t a = +25 8 c unless otherwise noted) 1
C5C rev. 0 OP186 electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 1 0.6 5 mv C40 c t a +125 c6mv input bias current i b 37 na C40 c t a +125 c10na input offset current i os 0.1 2 na C40 c t a +125 c5na input voltage range v cm C5 +4 v common-mode rejection cmrr v cm = C5.0 v to +4.0 v 65 90 db C40 c t a +125 c60 db large signal voltage gain a vo r l = 1 m w , v o = 4.0 v, 50 250 v/mv C40 c t a +125 c 10 v/mv offset voltage drift d v os / d t3 m v/ c bias current drift d i b / d t 25 pa/ c offset current drift d i os / d t 3 pa/ c output characteristics output voltage swing v o r l = 100 k w to gnd 4.95 4.98 v C40 c to +125 c 4.90 v short circuit limit i sc 10 ma power supply power supply rejection ratio psrr v s = 1.35 v to 6 v 78 95 db C40 c t a +125 c76 db supply current/amplifier i sy v o = 0 v 5.2 7 m a C40 c t a +125 c8 m a dynamic performance slew rate sr r l = 100 k w , c l = 15 pf 62 v/ms gain bandwidth product gbp 170 khz phase margin f o 58 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 6 m v p-p voltage noise density e n f = 1 khz 80 nv/ ? hz f = 10 khz 70 nv/ ? hz current noise density i n <1 pa/ ? hz note 1 v os is tested under a no load condition. specifications subject to change without notice. (v s = 6 5.0 v, t a = +25 8 c unless otherwise noted)
OP186 C6C rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the OP186 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 v input voltage . . . . . . . . . . . . . . . . . . . . . . . gnd to v s + 10 v differential input voltage 2 . . . . . . . . . . . . . . . . . . . . . . 3.5 v output short-circuit duration to gnd . . . . . . . . . indefinite storage temperature range rt package . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range OP186g . . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +125 c junction temperature range rt package . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 for supplies less than 5 v the differential input voltage is limited to the supplies. ordering guide temperature package package model range description option OP186grt C40 c to +125 c 5-lead sot-23 rt-5 package type u ja 1 u jc units 5-lead sot-23 (rt) 230 140 c/w note 1 q ja is specified for worst case conditions, i.e., q ja is specified for device in socket for sot packages.
OP186 C7C rev. 0 input offset voltage C mv 2 2 45 0 5 40 35 30 25 20 15 10 v s = +2.2v t a = +25 8 c 2 1.5 2 1 2 0.5 0 0.5 1 1.5 2 quantity C a figure 1. input offset voltage distribution 45 0 5 v s = 6 5v t a = +25 8 c 40 35 30 25 20 15 10 input offset voltage C mv 2 2 2 1.5 2 1 2 0.5 0 0.5 1 1.5 2 quantity C a figure 4. input offset voltage distribution input bias current C na temperature C 8 c 2 40 2 7 2 6 2 5 2 4 2 3 2 2 2 1 0 2 20 0 20 40 60 80 100 120 140 v s = +2.7v v s = 6 5.5v figure 7. input bias current vs. temperature 45 0 5 v s = +2.7v t a = +25 8 c 40 35 30 25 20 15 10 input offset voltage C mv 2 2 2 1.5 2 1 2 0.5 0 0.5 1 1.5 2 quantity C a figure 2. input offset voltage distribution temperature C 8 c 2 40 2 100 2 50 0 50 100 150 200 250 300 350 2 20 0 20 40 60 80 100 120 140 v s = +2.7v input offset voltage C m v v s = 6 5v v s = +2.2v figure 5. input offset voltage vs. temperature common-mode voltage C volts 2 4.0 0 0.5 2 3.5 2 3.0 2 2.5 2 2.0 2 1.5 2 1.0 2 0.5 0 0.5 1.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v s = +5v t a = +25 8 c input bias current C na figure 8. input bias current vs. common-mode voltage 45 0 5 v s = +5v t a = +25 8 c 40 35 30 25 20 15 10 input offset voltage C mv 2 2 2 1.5 2 1 2 0.5 0 0.5 1 1.5 2 quantity C a figure 3. input offset voltage distribution input bias current C na temperature C 8 c 2 40 2 7 2 6 2 5 2 4 2 3 2 2 2 1 0 2 20 0 20 40 60 80 100 120 140 v s = 6 5v v s = +2.2v figure 6. input bias current vs. temperature input offset current C na temperature C 8 c C40 C0.3 C0.2 C0.1 0 0.1 0.2 0.3 0.4 C20 0 20 40 60 80 100 120 140 v s = +2.7v, +5v figure 9. input offset current vs. temperature typical performance characteristicsC
OP186 C8C rev. 0 load current C m a 10 0.1 1 100 1k 1 1000 10 100 v s = +2.7v t a = +25 8 c source sink output voltage C mv figure 10. output voltage to supply rail vs. load current frequency C hz 100 2 10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 270 225 180 135 90 45 0 v s = +2.2v t a = +25 8 c r l = 100k v open-loop gain C db phase shift C degrees phase gain 2 20 2 30 figure 13. open-loop gain and phase vs. frequency 0 10 20 30 40 50 frequency C hz C30 10 C20 C10 100k 10k 1k 100 1m closed-loop gain C db v s = +5v t a = +25 8 c r l = figure 16. closed-loop gain vs. frequency load current C m a 10 0.1 1 100 1k 1 1000 10 100 v s = +5v t a = +25 8 c source sink output voltage C mv figure 11. output voltage to supply rail vs. load current frequency C hz 100 C30 C20 C10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 270 225 180 135 90 45 0 v s = +5v t a = +25 8 c r l = 100k v open-loop gain C db phase shift C de g rees gain phase figure 14. open-loop gain and phase vs. frequency cmrr C db frequency C h z 20 40 60 80 100 120 10k 1m 10m t a = +25 8 c 100k 1k +2.7v # v s # +5v figure 17. cmrr vs. frequency load current C m a 10 0.1 1 100 1k 1 1000 10 100 v s = 6 5v t a = +25 8 c source sink output voltage C mv figure 12. output voltage to supply rail vs. load current frequency C hz 100 C30 C20 C10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 270 225 180 135 90 45 0 v s = 6 5v t a = +25 8 c r l = 100k v open-loop gain C db phase shift C degrees gain phase figure 15. open-loop gain and phase vs. frequency psrr C db frequency C hz 0 10 100 1k 10k 100k 1m 20 40 60 80 100 120 +2.7v # v s # +5v t a = +25 8 c r l = ` figure 18. psrr vs. frequency
OP186 C9C rev. 0 capacitance C pf 0 10 1000 100 5 10 15 20 25 30 35 40 45 50 55 60 65 v s = +5v v in = 100mv p-p a vcl = +1 r l = 100k v t a = +25 8 c 2 os +os small signal overshoot C % figure 19. small signal overshoot vs. load capacitance temperature C 8 c C40 3 3.5 4 4.5 5 5.5 6.5 C20 0 20 40 60 80 100 120 140 6 input bias current C na v s = +2.7v v s = +2.2v v s = 6 5v v s = 6 5v v s = +5v figure 22. bias current vs. temperature 500mv 100 m s v s = +2.7v a v = +1 r l = 100k v c l = 50pf t a = +25 8 c figure 25. large signal transient response frequency C hz 10 2 100 1k 10k 100k 3 0 1 v s = +2.7v v in = 2v p-p a vcl = +1 r l = t a = +25 8 c maximum output swing C v p-p figure 20. maximum output swing vs. frequency supply voltage C 6 v 6 3 0 0 0.5 5 4 2 1 5.5 4.5 3.5 2.5 1.5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 t a = +25 8 c supply current C m a figure 23. supply current vs. supply voltage 1.0v 100 m s v s = +5v a v = +1 r l = 100k v c l = 50pf t a = +25 8 c figure 26. large signal transient response frequency C hz 5 10 2 100 1k 10k 100k 3 0 1 4 v s = +5v v in = 4v p-p a vcl = +1 r l = t a = +25 8 c maximum output swing C v p-p figure 21. maximum output swing vs. frequency common mode voltage C v 2 0 0.5 2.25 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 v s = +5v r l = t a = +25 8 c 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 supply current C m a figure 24. supply current vs. common-mode voltage 50mv 100 m s v s = 6 1.35v a v = +1 r l = 100k v c l = 50pf t a = +25 8 c figure 27. small signal transient response
OP186 C10C rev. 0 applications the OP186 is very similar in design to the op181. please see the op181/op281/op481 data sheet for applications information. design of the OP186 was based on the op181. the major dif- ference is that the trim structures have been removed. this results in the offset of the OP186 being higher than the op181. there are no other major changes to the circuit. other perfor- mance differences, such as the higher bandwidth and slightly higher supply current, also result from the removal of the trim resistors. 50mv 100 m s v s = 6 2.5v a v = +1 r l = 100k v c l = 50pf t a = +25 8 c figure 28. small signal transient response 100 m s v s = C2.5v a vol = circuit v in = C1v p-p r l = t a = +25 8 c 1.0v figure 31. saturation recovery time 1.0v 200 m s v s = +5v t a = +25 8 c figure 29. no phase reversal 500mv 100 m s v s = 6 1.35v a vol = circuit v in = 6 1v p-p r l = t a = +25 8 c figure 30. saturation recovery time
OP186 C11C rev. 0 spice model * OP186 spice macro-model typical values * 2/98, ver. 1 * tam / adsc * * copyright 1998 by analog devices * * refer to readme.doc file for license state- * ment. use of this * model indicates your acceptance of the terms * and provisions in * the license statement. * * node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output *|| | || *|| | || .subckt OP186 1 2 99 50 45 * * input stage * q1 4 1 3 pix q2 6 7 5 pix rc1 4 50 100e3 rc2 6 50 100e3 re1 3 8 6.452e3 re2 5 8 6.452e3 c1 4 6 50e-15 i1 99 8 1e-6 eos 7 2 poly(2) (12,98) (73,98) 800e-6 1 1 ios 1 2 50e-12 v1 99 9 0.9 v2 99 10 0.9 d1 3 9 dx d2 5 10 dx * * cmrr 90db, zero at 1khz * ecm1 11 98 poly(2) (1,98) (2,98) 0 .5 .5 rcm1 11 12 1.59e6 ccm1 11 12 100e-12 rcm2 12 98 50 * * psrr=100db, zero at 200hz * rps1 70 0 1e6 rps2 71 0 1e6 cps1 99 70 1e-5 cps2 50 71 1e-5 epsy 98 72 poly(2) (70,0) (0,71) 0 1 1 rps3 72 73 1.59e6 cps3 72 73 500e-12 rps4 73 98 15.9 * * internal voltage reference * eref 98 0 poly(2) (99,0) (50,0) 0 .5 .5 gsy 99 50 poly(1) (99,50) 2e-6 .1e-6 * * pole at 600khz; zero at 900khz * g1 98 20 (4,6) 11.3e-6 r1 20 98 88.46e3 r2 20 21 176.8e3 c2 21 98 1e-12 * * gain stage * g4 98 30 (20,98) 19.54e-6 r7 30 98 111.6e6 cf 45 30 32e-12 d3 30 31 dx d4 32 30 dx v3 99 31 0.6 v4 32 50 0.6 * * output stage * m1 45 46 99 99 pox l=2u w=100u m2 45 47 50 50 nox l=2u w=98u eg1 99 46 poly(1) (98,30) 0.82 1 eg2 47 50 poly(1) (30,98) 0.79 1 * * models * .model pox pmos (level=2, kp=10e-6, + vto=-0.75, lambda=0.01) .model nox nmos (level=2, kp=17e-6, + vto=0.75, lambda=0.01) .model pix pnp (bf=185,kf=1.6e-12,af=1) .model dx d(is=1e-14) .ends OP186
C12C rev. 0 c3330C8C4/98 printed in u.s.a. OP186 outline dimensions dimensions shown in inches and (mm). 5-lead sot-23 (rt suffix) 0.1181 (3.00) 0.1102 (2.80) pin 1 0.0669 (1.70) 0.0590 (1.50) 0.1181 (3.00) 0.1024 (2.60) 1 3 4 5 0.0748 (1.90) bsc 0.0374 (0.95) bsc 2 0.0079 (0.20) 0.0031 (0.08) 0.0217 (0.55) 0.0138 (0.35) 10 8 0 8 0.0197 (0.50) 0.0138 (0.35) 0.0059 (0.15) 0.0019 (0.05) 0.0512 (1.30) 0.0354 (0.90) seating plane 0.0571 (1.45) 0.0374 (0.95)

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