1 cat24c44 256-bit serial nonvolatile cmos static ram features n single 5v supply n infinite e 2 prom to ram recall n cmos and ttl compatible i/o n low cmos power consumption: Cactive: 3 ma max. Cstandby: 30 m a max. n power up/down protection n 10 year data retention n jedec standard pinouts: C8-pin dip C8-pin soic n 100,000 program/erase cycles (e 2 prom) n auto recall on power-up n commercial, industrial and automotive temperature ranges description the cat24c44 serial nvram is a 256-bit nonvolatile memory organized as 16 words x 16 bits. the high speed static ram array is bit for bit backed up by a nonvolatile e 2 prom array which allows for easy trans- fer of data from ram array to e 2 prom (store) and from e 2 prom to ram (recall). store operations are completed in 10ms max. and recall operations typically within 1.5 m s. the cat24c44 features unlimited ram write operations either through external ram writes or internal recalls from e 2 prom. internal false pin configuration store protection circuitry prohibits store operations when v cc is less than 3.5v (typical) ensuring e 2 prom data integrity. the cat24c44 is manufactured using catalysts ad- vanced cmos floating gate technology. it is designed to endure 100,000 program/erase cycles (e 2 prom) and has a data retention of 10 years. the device is available in jedec approved 8-pin plastic dip and soic pack- ages. pin functions pin name function sk serial clock di serial input do serial data output ce chip enable recall recall store store v cc +5v v ss ground soic package (s) di do 1 2 3 4 ce sk recall v ss v cc store 8 7 6 5 1 2 3 4 8 7 6 5 ce sk di do v cc recall v ss store dip package (p) 5157 fhd f01 ? 1998 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 25019-0a 2/98 n-1
2 cat24c44 doc. no. 25019-0a 2/98 n-1 power-up timing (4) symbol parameter min. max. units vccsr v cc slew rate 0.5 0.005 v/m t pur power-up to read operations 200 m s t puw power-up to write or store operation 5 ms mode selection (1)(2) software write enable previous recall mode store store store store store recall recall recall recall recall instruction latch latch hardware recall (3) 1 0 nop x x software recall 1 1 rcl x x hardware store (3) 0 1 nop set true software store 1 1 sto set true x = dont care block diagram 5157 fhd f09 row decode instruction register column decode e 2 prom array store recall static ram array 256-bit store recall ce di sk instruction decode 4-bit counter control logic v cc v ss do note: (1) the store operation has priority over all the other operations. (2) the store operation is inhibited when v cc is below ? 3.5v. (3) nop designates that the device is not currently executing an instruction. (4) this parameter is tested initially and after a design or process change that affects the parameter.
cat24c44 3 doc. no. 25019-0a 2/98 n-1 absolute maximum ratings* temperature under bias ................. C55 c to +125 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (2) ............. C2.0 to +vcc +2.0v v cc with respect to ground ............... C2.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (3) ........................ 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (3) output shorted for no more than one second. no more than one output shorted at a time. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. reliability characteristics symbol parameter min. max. units reference test method n end (1) endurance 100,000 cycles/byte mil-std-883, test method 1033 t dr (1) data retention 10 years mil-std-883, test method 1008 v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(4) latch-up 100 ma jedec standard 17 capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol parameter max. unit conditions c i/o (1) input/output capacitance 10 pf v i/o = 0v c in (1) input capacitance 6 pf v in = 0v d.c. operating characteristics v cc = 5v 10%, unless otherwise specified. limits symbol parameter min. typ. max. unit conditions i cco current consumption (operating) 3 ma inputs = 5.5v, t a = 0 c all outputs unloaded i sb current consumption (standby) 30 m a ce = v il i li input current 2 m a0 v in 5.5v i lo output leakage current 10 m a0 v out 5.5v v ih high level input voltage 2 v cc v v il low level input voltage 0 0.8 v v oh high level output voltage 2.4 v i oh = C2ma v ol low level output voltage 0.4 v i ol = 4.2ma
4 cat24c44 doc. no. 25019-0a 2/98 n-1 a.c. characteristics v cc = 5v 10%, unless otherwise specified. symbol parameter min. max. units conditions f sk sk frequency dc 1 mhz t skh sk positive pulse width 400 ns t skl sk negative pulse width 400 ns c l = 100pf + 1ttl gate t ds data setup time 400 ns v oh = 2.2v, v ol = 0.65v t dh data hold time 80 ns v ih = 2.2v, v il = 0.65v t pd sk data valid time 375 ns input rise and fall times = 10ns t z ce disable time 1 m s t ces ce enable setup time 800 ns t ceh ce enable hold time 400 ns t cds ce de-select time 800 ns a.c. characteristics, store cycle v cc = 5v 10%, unless otherwise specified. limits symbol parameter min. max. units conditions t st store time 10 ms c l = 100pf + 1ttl gate t stp store pulse width 200 ns v oh = 2.2v, v ol = 0.65v t stz store disable time 100 ns v ih = 2.2v, v il = 0.65v a.c. characteristics, recall cycle v cc = 5v 10%, unless otherwise specified. symbol parameter min. max. units conditions t rcc recall cycle time 2.5 m s t rcp recall pulse width 500 ns c l = 100pf + 1ttl gate t rcz recall disable time 500 ns v oh = 2.2v, v ol = 0.65v t orc recall enable time 10 ns v ih = 2.2v, v il = 0.65v t arc recall data access time 1.5 m s instruction set format instruction start bit address op code operation wrds 1 xxxx 0 0 0 reset write enable latch (disables, writes and stores) sto 1 xxxx 0 0 1 store ram data in e 2 prom write 1 aaaa 0 1 1 write data into ram address aaaa wren 1 xxxx 1 0 0 set write enable latch (enables, writes and stores) rcl 1 xxxx 1 0 1 recall e 2 prom data into ram read 1 aaaa 1 1 x read data from ram address aaaa x = dont care a = address bit
cat24c44 5 doc. no. 25019-0a 2/98 n-1 device operation the cat24c44 is intended for use with standard micro- processors. the cat24c44 is organized as 16 registers by 16 bits. seven 8-bit instructions control the devices operating modes, the ram reading and writing, and the e 2 prom storing and recalling. it is also possible to control the e 2 prom store and recall functions in hard- ware with the store and recall pins. the cat24c44 operates on a single 5v supply and will generate, on chip, the high voltage required during a ram to e 2 prom storing operation. instructions, addresses and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin remains in a high impedance state except when outputting data from the device. the ce (chip enable) pin must remain high during the entire data transfer. the format for all instructions sent to the cat24c44 is a logical 1 start bit, 4 address bits (data read or write operations) or 4 dont care bits (device mode opera- tions), and a 3-bit op code (see instruction set). for data write operations, the 8-bit instruction is followed by 16 bits of data. for data read instructions, do will come out of the high impedance state and enable 16 bits of data to be clocked from the device. the 8th bit of the read instruction is a dont care bit. this is to eliminate any bus contention that would occur in applications where the di and do pins are tied together to form a common di/do line. a word of caution while clocking data to and from the device: if the ce pin is prematurely deselected while shifting in an instruction, that instruction will not be executed, and the shift register internal to the cat24c44 will be cleared. if there are more than or less than 16 clocks during a memory data transfer, an improper data transfer will result. the sk clock is completely static allowing the user to stop the clock and restart it to resume shifting of data. read upon receiving a start bit, 4 address bits, and the 3-bit read command (clocked into the di pin), the do pin of the cat24c44 will come out of the high impedance state and the 16 bits of data, located at the address specified in the instructions, will be clocked out of the device. when clocking data from the device, the first bit clocked out (do) is timed from the falling edge of the 8th clock, all succeeding bits (d1Cd15) are timed from the rising edge of the clock. write after receiving a start bit, 4 address bits, and the 3-bit write command, the 16-bit word is clocked into the device for storage into the ram memory location speci- fied. the ce pin must remain high during the entire write operation. figure 1. ram read cycle timing 5157 fhd f02 note: (1) bit 8 of read instruction is dont care. figure 2. ram write cycle timing 5157 fhd f03 sk ce di d 0 1 23456789101112 222324 1 d 1 d 2 d 3 d 13 d 14 d 15 a1 1 aaa 0 sk ce di do high-z d 0 1 23456789101112 222324 1 d 1 d 2 d 3 d 14 d 15 d 0 ax 11 aaa (8) (1)
6 cat24c44 doc. no. 25019-0a 2/98 n-1 wren/wrds the cat24c44 powers up in the program disable state (the write enable latch is reset). any programming after power-up or after a wrds (ram write/e 2 prom store disable) instruction must first be preceded by the wren (ram write/e 2 prom store enable) instruction. once writing/storing is enabled, it will remain enabled until power to the device is removed, the wrds instruc- tion is sent, or an e 2 prom store has been executed 5157 fhd f05 figure 4. write cycle timing figure 3. read cycle timing 5157 fhd f04 x12n sk ce t skl t skh 1/f sk t ceh t dh t ds t ces t cds di high-z t pd 67891011 t pd t z v ih high-z sk cycle # sk ce di do d0 d1 dn (sto). the wrds (write/store disable) can be used to disable all cat24c44 programming functions, and will prevent any accidental writing to the ram, or storing to the e 2 prom. data can be read normally from the cat24c44 regard- less of the write enable latch status.
cat24c44 7 doc. no. 25019-0a 2/98 n-1 rcl/ recall recall recall recall recall data is transferred from the e 2 prom data memory to ram by either sending the rcl instruction or by pulling the recall input pin low. a recall operation must be performed before the e 2 prom store, or ram write operations can be executed. either a hardware or soft- ware recall operation will set the previous recall latch internal to the cat24c44. power-on recall the cat24c44 has a power-on recall function that transfers the e 2 prom data to the ram. after power-up, all functions are inhibited for at least 200ns (t pur ) from stable v cc . sto/ store store store store store data in the ram memory area is stored in the e 2 prom memory either by sending the sto instruction or by pulling the store input pin low. as security against any inadvertent store operations, the following conditions must each be met before data can be transferred into nonvolatile storage: ? the previous recall latch must be set (either a software or hardware recall operation). ? the write enable latch must be set (wren instruction issued). ? sto instruction issued or store input low. during the store operation, all other cat24c44 func- tions are inhibited. upon completion of the store opera- tion, the write enable latch is reset. the device also provides false store protection whenever v cc falls below a 3.5v level. if v cc falls below this level, the store operation is disabled and the write enable latch is reset. figure 6. hardware store cycle timing 5157 fhd f07 figure 5. recall cycle timing 5157 fhd f06 recall t rcz t orc t rcc t rcp t arc valid data undefined data do high-z store t st t stp do t stz high-z
8 cat24c44 doc. no. 25019-0a 2/98 n-1 figure 7. non-data operations sk ce di 12345678 1 xxxx op-code 5157 fhd f08 24c44 f11 ordering information notes: (1) the device used in the above example is a 24c44si-te13 (soic, industrial temperature, tape & reel) prefix device # suffix 24c44 s i -te13 product number tape & reel te13: 2000/reel package p: pdip s: soic (jedec) cat temperature range blank = commercial (0? - 70?c) i = industrial (-40? - 85?c) a = automotive (-40? - 105?c)* * -40? to +125?c is available upon request optional company id
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