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dm512k64dt6/dm512k72dt6 multibank edo edram 512kb x 64/512kb x 72 enhanced dram dimm product specification ?1996 enhanced memory systems inc. 1850 ramtron drive, colorado springs, co 80921 telephone (800) 545-dram; fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2123-000 the information contained herein is subject to change without notice. enhanced reserves the right to change or discontinue this product without notice. features n 8kbytes sram cache memory for 12ns random reads within four active pages (multibank cache) n fast 4mbyte dram array for 30ns access to any new page n write posting registers for 12ns random writes and burst writes within a page (hit or miss) n 2kbyte wide dram to sram bus for 113.6 gigabytes/second cache fill rate n a hit pin outputs status on on-chip page hit/miss comparators to simplify control n on-chip cache hit/miss comparators automatically maintain cache coherency on writes n hidden precharge & refresh cycles n extended 64ms refresh period for low standby power n cmos/ttl compatible i/o and +5 volt power supply n output latch enable allows extended data output (edo) for faster system operation description the enhanced memory systems 4mb enhanced dram (edram)dimm module provides a single memory module solution for the main memory or local memory of fast 64-bit embedded computers, communications switches, and other high performance systems. due to its fast non-interleave architecture, the edram dimm module supports zero-wait-state burst read or write operation to 83mhz. the edram outperforms conventional sram plus dram or synchronous dram memory systems by minimizing wait states on initial reads (hit or miss) and eliminating writeback delays. each 4mbyte dimm module has 8kbytes of sram cache organized as four 256 x 72 row registers with 12ns initial access time. on a cache miss, the fast dram array reloads an entire 2kbyte row register over a 2kbyte-wide bus in just 18ns for an effective cache fill rate of 113.6 gbytes/second. during write cycles, a write posting register allows the initial write to be posted as early as 5ns after column address is available. edram supports direct non-interleave page writes at up to 83mhz. an on-chip hit/miss comparator automatically maintains cache coherency during writes. architecture the dm512k72dt6 achieves 512kb x 72 density by mounting nine 512kx8 edrams, packaged in low profile 44-pin tsop-ii packages on one side of the multi- layer substrate. three high drive series terminated buffer chips buffer address and control lines. twelve surface mount capacitors are used to decouple the power supply bus. the dm512k64dt contains eight 512kx8 edrams. the parity data component is not populated. the edram memory module architecture is very similar to two standard 2mb dram simm modules configured in a 64-bit wide, non-interleave configuration. the edram module adds an integrated cache and cache control logic which allow the cache to operate much like a page mode or static column dram. the edrams sram cache is integrated into the dram array as tightly coupled row registers. memory reads always occur from the 256 x 72 cache row register associated with a 1mb segment of dram. when the on-chip comparator detects a page hit, only the sram is accessed and data is available in 12ns from column address (the /hit output is low to indicate a page hit). when a page miss is detected, the entire new dram row is loaded into cache and data is available at the output within 30ns from row enable (the /hit output is high to indicate a page miss). subsequent reads within a page (burst reads or random reads) will continue at 12ns cycle time. since reads occur from the sram cache, the dram precharge can occur simultaneously without degrading performance. the on-chip refresh counter with independent cal a 0-10 w/r /f v v sense amps & column write select column decoder row add latch cc ss pd 4- 256 x 72 cache pages (row register) memory array (4 mbyte + parity) /g /s /we dq column add latch 4-bit comp 4- last row read add latches i/o control and data latches refresh counter row decoder row add and refresh control 0-8 /re a 0-7 a 0-9 0-71 c 1-12 /qle functional diagram enhanced memory systems inc.
refresh bus allows the edram to be refreshed during cache reads. memory writes can be posted as early as 6.5ns after row enable and are directed to the dram array . during a write hit, the on-chip address comparator activates a parallel write path to the sram cache to maintain coherency . memory writes do not affect the contents of the cache row register except during write hits. by integrating the sram cache as row registers in the dram array and keeping the on-chip control simple, the edram is able to provide superior system performance at less cost, power , and area than systems implemented with complex synchronous sram cache, cache controllers, and multilevel data busses. functional description the edram is designed to provide optimum memory performance with high speed microprocessors. as a result, it is possible to perform simultaneous operations to the dram and sram cache sections of the edram. this feature allows the edram to hide precharge and refresh operation during reads and maximize hit rate by maintaining page cache contents during write operations even if data is written to another memory page. these capabilities, in conjunction with the faster basic dram and cache speeds of the edram, minimize processor wait states. edram basic operating modes the edram operating modes are specified in the table. hit and miss t er minology in this datasheet, ?it?and ?iss?always refer to a hit or miss to any of the four pages of data contained in the sram cache row registers. there are four cache row registers, one for each of the four banks of dram. these registers are specified by the bank select row address bits a 8 and a 9 . the contents of these cache row registers is always equal to the last row that was read from each of the four internal dram banks (as modified by any write hit data). dram read hit a dram read request is initiated by clocking /re with w/r low and /f high. the edram will compare the new row address to the last row read address latch for the bank specified by row address bits a 8-9 (lrr: a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address matches the lrr, the requested data is already in the sram cache and no dram memory reference is initiated. the data specified by the row and column address is available at the output pins at the greater of times t ac or t gqv . the /hit output is driven low at time t hv after /re to indicate the shorter access time to the 2-138 bank 3 bank 2 bank 1 cal row address latch column address latch last row read address latch + 9-bit compare bank 0 hit0 hit1 hit2 hit3 /hit 1 of 4 selector (0,0) (0,1) (1,0) (1,1) d 0-71 bank 0 bank 1 bank 2 bank 3 ca 0-7 ca 0-7 ra 8 , ra 9 a 0-10 ra 0-10 data-out latch qle g s q 0-71 1m array 1m array 1m array 1m array 256 x 72 cache 256 x 72 cache 256 x 72 cache 256 x 72 cache data-in latch four bank cache ar chitectur e
2-139 external control logic. since no dram activity is initiated, /re can be brought high after time t re1 , and a shorter precharge time, t rp1 , is required. additional locations within the currently active page may be accessed concurrently with precharge by providing new column addresses to the multiplex address inputs. new data is available at the output at time t ac after each column address change in static column mode. during any read cycle, it is possible to operate in either static column mode with /cal=high or page mode with /cal clocked to latch the column address. in page mode, data valid time is determined by either t ac and t cqv . dram read miss a dram read request is initiated by clocking /re with w/r low and /f high. the edram will compare the new row address to the lrr address latch for the bank specified by row address bits a 8-9 (lrr: a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address does not match the lrr, the requested data is not in sram cache and a new row is fetched from the dram. the edram will load the new row data into the sram cache and update the lrr latch. the data at the specified column address is available at the output pins at the greater of times t rac , t ac , and t gqv . the /hit output is driven high at time t hv after /re to indicate the longer access time to the external control logic. /re may be brought high after time t re since the new row data is safely latched into sram cache. this allows the edram to precharge the dram array while data is accessed from sram cache. additional locations within the currently active page may be accessed by providing new column addresses to the multiplex address inputs. new data is available at the output at time t ac after each column address change in static column mode. during any read cycle, it is possible to operate in either static column mode with /cal=high or page mode with /cal clocked to latch the column address. in page mode, data valid time is determined by either t ac and t cqv . dram w rite hit a dram write request is initiated by clocking /re while w/r, /cal, /we, and /f are high. the edram will compare the new row address to the lrr address latch for the bank specified by row address bits a 8-9 (lrr: a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address matches the lrr, the edram will write data to both the dram page in the appropriate bank and its corresponding sram cache simultaneously to maintain coherency . the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low (both /cal and /we must be high when initiating the write cycle with the falling edge of /re). the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . with /g enabled and /we disabled, read operations may be performed while /re is activated in write hit mode. this allows read-modify-write, write-verify , or random read-write sequences within the page with 12ns cycle times. during a write hit sequence, the /hit output is driven low . at the end of any write sequence (after /cal and /we are brought high and t re is satisfied), /re can be brought high to precharge the memory . cache reads can be performed concurrently with precharge (see ?re inactive operation?. when /re is inactive, the cache reads will occur from the page accessed during the last /re active read cycle. dram w rite miss a dram write request is initiated by clocking /re while w/r, /cal, /we, and /f are high. the edram will compare the new row address to the lrr address latch for the bank specified for row address bits a 8-9 (lrr: a 9-bit row address latch for each internal dram bank which is reloaded on each /re active read miss cycle). if the row address does not match any of the lrrs, the edram will write data to the dram page in the appropriate bank and the contents of the current cache is not modified. the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low (both /cal and /we must be high when initiating the write cycle with the falling edge of /re). the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . during a write miss sequence, the /hit output is driven high, cache reads are inhibited, and the output buffers are disabled (independently of /g) until time t wrr after /re goes high. at the end of a write sequence (after /cal and /we are brought high and t re is satisfied), /re can be brought high to precharge the memory . cache reads can be performed concurrently with the precharge (see ?re inactive operation?. when /re is inactive, the cache reads will occur from the page accessed during the last /re active read cycle. /re inactive operation data may be read from the sram cache without clocking /re. this capability allows the edram to perform cache read function /s read hit l /re w/r /f a 0-10 comment l h row = lrr no dram reference, data in cache read miss l l h row 1 lrr dram row to cache write hit l h h row = lrr write to dram and cache, reads enabled write miss l h h row 1 lrr write to dram, cache not updated, reads disabled internal refresh x x l x low power standby h x x x standby current unallowed mode h x l h x h h = high; l = low; x = don? car e; = high-to-low t ransition; lrr = last row read edram basic operating modes
2-140 operations during precharge and refresh cycles to minimize wait states. it is only necessary to select /s and /g and provide the appropriate column address to read data as shown in the table below . in this mode of operation, the cache reads will occur from the page and bank accessed during the last /re active read cycle. t o perform a cache read in static column mode, /cal is held high, and the cache contents at the specified column address will be valid at time t ac after address is stable. t o perform a cache read in page mode, /cal is clocked to latch the column address. when /re is inactive, the hit pin is not driven and is in a high impedance state. this option is desirable when the external control logic is capable of fast hit/miss comparison. in this case, the controller can avoid the time required to perform row/column multiplexing on hit cycles. edo mode and output latch enable operation the qle and /cal inputs can be used to create extended data output (edo) mode timings in either static column or page modes. the dm512k32dt6 has an output latch enable (qle) that can be used to extend the data output valid time. the output latch enable operates as shown in the following table. when qle is low , the latch is transparent and the edram operates identically to the standard edrams. when /cal is high during a static column mode read, the qle input can be used to latch the output to extend the data output valid time. qle can be held high during page mode reads. in this case, the data outputs are latched while /cal is high and open when /cal is not high. w rite-per -bit operation the dm512k72 dimm offers a write-per -bit capability to selectively modify individual parity bits (dq 8, 17, 26, 35, 44, 53, 62, 71 ) for byte write operations. the parity device (dm2213) is selected via /cal 8 . byte write selection to non-parity bits is accomplished via /cal 0-7 . the bits to be written are determined by a bit mask data word which is placed on the parity i/o data pins prior to clocking /re. the logic one bits in the mask data select the bits to be written. as soon as the mask is latched by /re, the mask data is removed and write data can be placed on the data bus. the mask is only specified on the /re transition. during page mode burst write operations, the same mask is used for all write operations. ecc operation the dm512k72dt6-xxn supports error correction coding (ecc) by replacing the parity chip with a normal dm2203 device. this version does not support write-per -bit parity operation. inter nal refr esh if /f is active (low) on the assertion of /re, an internal refresh cycle is executed. this cycle refreshes the row address supplied by an internal refresh counter . this counter is incremented at the end of the cycle in preparation for the next /f refresh cycle. at least 1,024 /f cycles must be executed every 64ms. /f refresh cycles can be hidden because cache memory can be read under column address control throughout the entire /f cycle. /f cycles are the only active cycles where /s can be disabled. /re only refr esh operation although /f refresh using the internal refresh counter is the recommended method of edram refresh, an /re only refresh may be performed using an externally supplied row address. /re refresh is performed by executing a write cycle (w/r, /g, and /f are high) where /cal is not clocked. this is necessary so that the current cache contents and lrr are not modified by the refresh operation. all combinations of addresses a 0-9 must be sequenced every 64ms refresh period. a 10 does not need to be cycled. read refresh cycles are not allowed because a dram refresh cycle does not occur when a read refresh address matches the lrr address latch. low power mode the edram enters its low power mode when /s is high. in this mode, the internal dram circuitry is powered down to reduce standby current. initialization cycles a minimum of eight /re active initialization cycles (read, write, or refresh) are required before normal operation is guaranteed. following these start-up cycles, two read cycles to different row addresses must be performed for each of the four internal banks of dram to initialize the internal cache logic. row address bits a 8 and a 9 define the four internal dram banks. unallowed mode read, write, or /re only refresh operations must not be performed to unselected memory banks by clocking /re when /s is high. reduced pin count operation although it is desirable to use all edram control pins to optimize system performance, the interface to the edram may be simplified to reduce the number of control lines by either tying pins to ground or by tying one or more control inputs together . the /s input can be tied to ground if the low power standby mode is not required. the qle input can be tied low if output latching is not required, or it can be tied high if ?xtended data out?(hyper page mode) is required. the /hit output pin is not necessary for device operation. the w/r and /g inputs can be tied together if reads are not required during a write hit cycle. the simplified control interface still allows the fast page read/write cycle times, fast random read/ write times, and hidden precharge functions available with the edram. pin descriptions /re ?row enable these inputs are used to initiate dram read and write operations and latch a row address. it is not necessary to clock /re to read data from the edram sram row register . on read operations, /re can be brought high as soon as data is loaded into cache to allow early precharge. function /s /cal a 0-7 /g cache read (static column) l l h col adr cache read (page mode) l l col adr qle l /cal comments output transparent x output latched when qle=h (static column edo) h h output latched when /cal=h (page mode edo)
2-141 /cal 0-8 ?column addr ess latch these inputs are used to latch the column address and in combination with /we to trigger write operations. when /cal is high, the column address latch is transparent. when /cal is low , the column address latch contains the address present at the time /cal went low . individual /cal inputs are provided for each byte of edram to allow byte write capability . w/r ?w rite/read this input along with /f input specifies the type of dram operation initiated on the low going edge of /re. when /f is high, w/r specifies either a write (logic high) or read operation (logic low). /f ?refr esh this input will initiate a dram refresh operation using the internal refresh counter as an address source when it is low on the low going edge of /re. /we ?w rite enable this input controls the latching of write data on the input data pins. a write operation is initiated when both the /cal for the specified byte and /we are low . /g ?output enable this input controls the gating of read data to the output data pins during read operations. /s ?chip select this input is used to power up the i/o and clock circuitry . when /s is high, the edram remains in a powered-down condition. read or write cycles must not be executed when /s is high. /s must remain low throughout any read or write operation. only /f refresh operation can be executed when, /s is not enabled. dq 0-71 ?data input/output these cmos/ttl bidirectional data pins are used to read and write data to the edram. on the dm2213 write-per -bit memory , these pins are also used to specify the bit mask used during write operations. a 0-10 ?multiplex addr ess these inputs are used to specify the row and column addresses of the edram data. the 11-bit row address is latched on the falling edge of /re. the 8-bit column address can be specified at any other time to select read data from the sram cache or to specify the write column address during write cycles. qle ?output latch enable this input enables the edram output latches. when qle is low , the output latch is transparent. data is latched when both /cal and qle are high. this allows output data to be extended during either static column or page mode read cycles. /hit ?hit pin this output pin will be driven during /re active read or write cycles to indicate the hit/miss status of the cycle. pd ?pr esence detect this output will indicate if the dimm module is inserted in a socket. when a dimm is inserted, this pin is grounded. when no dimm is present, the pin is open. v cc power supply these inputs are connected to the +5 volt power supply . v ss gr ound these inputs are connected to the power supply ground connection.
2-142 pin no. function 1 vss interconnect (component pin) organization ground 2 3 4 u1-7 byte 0, i/o 2 5 6 +5 volts 7 8 u1-15 byte 0, i/o 5 9 10 dq 11 dq 12 ground 13 14 15 16 17 18 +5 volts 19 20 u3-16 21 u3-18 22 u5-6 23 24 25 +5 volts 26 +5 volts 27 u10a-8 write enable 28 u1-32 u6-32 u10a-14 byte 0 /cal 29 /cal2 byte 2 /cal 30 /s 31 u10b-15 u10b-21 output enable 32 ground 33 a address 0 34 u11a-8 35 36 v ss dd address 2 85 ground 86 u2-4 u2-7 88 dq 89 u2-9 byte 4 i/o 3 90 +5 volts 91 u2-13 byte 4 i/o 4 93 u2-16 byte 4, i/o 6 94 u2-18 u5-13 byte 4, i/o 7 95 dq parity, i/o 4 96 ground 97 98 u4-4 byte 5, i/o 0 99 u4-7 byte 5, i/o 2 100 u4-9 u4-13 byte 5, i/o 3 101 byte 5, i/o 4 102 +5 volts 103 u4-15 byte 5, i/o 5 104 u4-16 byte 5, i/o 6 105 u4-18 106 u5-15 parity, i/o 5 107 ground 108 ground 109 v 110 +5 volts 111 u10d-49 refresh pin 112 u3-32 byte 1 /cal 113 u8-32 byte 3 /cal 114 n.c. 115 u10d-43 write/read mode 116 v 117 u10c-42 u10c-36 118 119 a u11d-49 120 a u11d-43 u11c-42 121 122 a byte 4, i/o 0 dq n.c. a address 1 address 3 address 5 address 7 pin no. function interconnect (component pin) organization byte 1 i/o 6 byte 1 i/o 7 parity, i/o 1 ground ground byte 4, i/o 2 byte 5, i/o 7 address 9 +5 volts u1-4 byte 0, i/o 0 u1-6 byte 0, i/o 1 u1-9 byte 0, i/o 3 u1-13 byte 0, i/o 4 u1-16 u1-18 u5-4 byte 0, i/o 6 byte 0, i/o 7 v u3-4 byte 1, i/o 0 dq 9 dq 10 ss u3-6 byte 1, i/o 1 u3-7 dq 11 dq 12 dq 13 byte 1, i/o 2 u3-9 byte 1, i/o 3 u3-13 byte 1, i/o 4 u3-15 byte 1, i/o 5 chip select address 4 address 6 +5 volts v dd /cal0 /g parity, i/o 0 dq 14 ground dq 0 dq 1 dq 2 dq 3 v dd dq 4 dq 5 dq 6 7 8 dq 15 dq 16 dq 17 v ss v ss v dd v dd /we a 2 0 a 4 u11a-14 u11b-15 u11b-21 a 6 8 w/r n.c. /cal3 /cal1 /f ss 1 3 5 7 dd a 9 v dd v ss dd v ss dq 53 dq 52 dq 51 dq 50 v dd dq 49 dq 48 dq 47 v ss dq 43 44 45 46 dq 42 dq 40 92 u2-15 byte 4 i/o 5 dq 41 v dd dq 39 dq 36 38 u2-6 87 dq byte 4, i/o 1 37 ss u4-6 byte 5, i/o 1 dq 37 a 38 u11c-36 address 10 39 40 v dd v +5 volts 41 42 n.c. +5 volts 123 n.c. 124 125 n.c. n.c. 126 v n.c. n.c. address 8 u12a-8 output latch enable a 10 qle v pinout
2-143 pin no. function 43 interconnect (component pin) organization 45 46 47 u7-32 n.c. byte 6 /cal 48 49 +5 volts 50 51 ground 52 53 dq 54 v 55 byte 2, i/o 2 56 57 58 59 60 61 ground 62 63 64 65 u6-18 u5-7 u8-4 66 67 68 ground 69 byte 3, i/o 1 70 u8-6 71 u8-9 u8-13 byte 3, i/o 3 u8-7 byte 3, i/o 2 72 byte 3, i/o 4 73 74 u8-15 u8-16 u8-18 byte 3, i/o 5 75 byte 3, i/o 6 76 dq byte 3, i/o 7 77 u5-9 78 79 v dd dd parity, i/o 3 127 ground 129 n.c. u9-32 131 /cal7 132 u5-32 parity 133 +5 volts 134 +5 volts 136 u7-4 byte 6, i/o 0 137 u7-6 byte 6, i/o 1 138 v ground 139 byte 6, i/o 2 140 141 u7-9 byte 6, i/o 3 142 u7-15 byte 6, i/o 5 143 u7-16 u12c-36 u12c-42 u12b-15 +5 volts 144 byte 6, i/o 6 145 hit output 146 147 148 149 u7-18 u5-16 u9-4 u9-6 byte 6, i/o 7 150 parity, i/o 6 151 byte 7, i/o 0 152 v 153 byte 7, i/o 1 154 u9-7 byte 7, i/o 2 155 u9-9 byte 7, i/o 3 156 u9-13 byte 7, i/o 4 157 +5 volts 158 u9-15 byte 7, i/o 5 159 160 u9-18 u5-18 u9-16 161 162 163 n.c. n.c. 164 165 dq byte 7, i/o 7 parity, i/o 7 ground pin no. function interconnect (component pin) organization ground byte 2, i/o 7 byte 3, i/o 0 parity, i/o 2 byte 7 ground +5 volts u12a-14 row enable u2-32 byte 4 /cal +5 volts u6-4 u6-6 u6-7 byte 2, i/o 0 byte 2, i/o 1 dq u6-9 byte 2, i/o 3 dq 21 dq 22 u6-13 byte 2, i/o 4 u6-15 dq 23 v dd dq 24 byte 2, i/o 5 +5 volts u6-16 u12b-21 byte 2, i/o 6 n.c. +5 volts ground ground pd dq dq ground n.c. byte 7, i/o 6 /re /cal4 /cal6 n.c. v dd ground v ss v dd v ss dq 18 19 ss 20 n.c. v ss dq 25 26 dq 27 dq v ss dq 28 29 30 dq 31 32 dq 33 34 dq 35 dq v n.c. n.c. ss n.c. n.c. n.c. n.c. v dq dq 65 66 dq 68 dq 69 dq 70 dq 71 v ss n.c. dq 67 ss dd n.c. n.c. n.c. n.c. n.c. 64 63 ss dq 61 dq dq dq 62 v ss n.c. n.c. /hit dq 60 v dd dq 59 56 dq 55 ss 57 58 dq 54 v 135 ground v ss v dd dd /cal8 n.c. u4-32 130 /cal5 byte 5 ss u7-13 byte 6, i/o 4 dq 80 81 n.c. n.c. 82 83 v dd v +5 volts 84 +5 volts 166 167 168 v dd v +5 volts v 44 n.c. 128 ground n.c. ss v dq u7-7 pinout
2-144 dimm edge connector 42 qle 8 u12a qle bank0a qle bank0b qle bank0c qle bank0d 3 2 5 6 45 /re 14 /re bank0a /re bank0b /re bank0c /re bank0d 10 9 12 13 1 58 34 a2 8 u11a a2 bank0a a2 bank0b a2 bank0c a2 bank0d 3 2 5 6 35 a4 14 a4 bank0a a4 bank0b a4 bank0c a4 bankod 10 9 12 13 1 36 a6 15 u11b a6 bank0a a6 bank0b a6 bank0c a6 bank0d 17 16 19 20 37 a8 21 a8 bank0a a8 bank0b a8 bank0c a8 bankod 24 23 26 27 28 43 u12d n.c. n.c. n.c. n.c. 47 48 45 44 49 n.c. n.c. n.c. n.c. 54 55 52 51 147 15 u12b bmo bank0a bmo bank0b bmo bank0c bmo bank0d 17 16 19 20 63 21 vdd be bank0a be bank0b be bank0c be bank0d 24 23 26 27 28 145 36 u12c bm2 bank0a bm2 bank0b bm2 bank0c bm2 bank0d 33 34 31 30 146 42 vdd bm1 bank0a bm1 bank0b bm1 bank0c bm1 bank0d 40 41 38 37 29 buf fer diagrams note: address and control buffers add a minimum of 1.5ns and a maximum of 3.8ns delay to each signal path.
2-145 dimm edge connector 31 38 121 a10 36 u11c a10 bank0a a10 bank0b a10 bank0c a10 bank0d 33 34 31 30 33 118 117 a9 42 a9 bank0a a9 bank0b a9 bank0c a9 bank0d 40 41 38 37 29 28 115 w/r 43 u10d w/r bank0a w/r bank0b w/r bank0c w/r bank0d 47 48 45 44 111 /f 49 /f bank0a /f bank0b /f bank0c /f bankod 54 55 52 51 58 vdd idt74fct162344etpa .22? 7 22 35 50 vcc vcc vcc vcc 4 11 18 25 32 39 46 /g 15 u10b /g bank0a /g bank0b /g bank0c /g bank0d 17 16 19 20 a0 21 a0 bank0a a0 bank0b a0 bank0c a0 bank0d 24 23 26 27 29 a3 36 u10c a3 bank0a a3 bank0b a3 bank0c a3 bank0d 33 34 31 30 a1 42 a1 bank0a a1 bank0b a1 bank0c a1 bank0d 40 41 38 37 120 a7 43 u11d a7 bank0a a7 bank0b a7 bank0c a7 bank0d 47 48 45 44 119 a5 49 a5 bank0a a5 bank0b a5 bank0c a5 bank0d 54 55 52 51 58 27 /we 8 u10a /we bank0a /we bank0b /we bank0c /we bank0d 3 2 5 6 30 /s 14 /s bank0a /s bank0b /s bank0c /s bank0d 10 9 12 13 1 53 buf fer diagrams note: address and control buffers add a minimum of 1.5ns and a maximum of 3.8ns delay to each signal path.
2-146 byte 0 bank 0a a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 w/r /we /f /s /g dq0 dq1 dq2 dq3 /cal 4 6 7 9 dq4 dq5 dq6 dq7 13 15 16 18 dq 0 dq0-71 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dm2203t 32 27 28 29 30 35 36 37 38 39 40 41 43 26 2 42 12 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 /cal8 /cal 7 hit note: for reference to buffer connection, append bank name to address or clock name, i.e., a10 + bank 0a = a10bank0a. refer to buffer interconnect diagram fo r detailed buffer connections. dq0-71 and /cal0-8 are directly connected to pins. * not present on dm512k64 /cal3 w/r /we /f /s /g qle 10 qle /re 33 /re /cal0 /cal4 /cal1 /cal5 /cal2 /cal6 /hit hit 24 u1 byte 4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 4 6 7 9 13 15 16 18 dq 36 dq 37 dq 38 dq 39 dq 40 dq 41 dq 42 dq 43 /cal dm2203t 32 u2 byte 1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 4 6 7 9 13 15 16 18 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 dm2203t /cal 32 u3 byte 5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 4 6 7 9 13 15 16 18 dq 45 dq 46 dq 47 dq 48 dq 49 dq 50 dq 51 dq 52 dm2203t /cal 32 u4 byte 2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 4 6 7 9 13 15 16 18 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dm2203t /cal 32 u6 parity dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 4 6 7 9 13 15 16 18 dq 8 dq 17 dq 26 dq 35 dq 44 dq 53 dq 62 dq 71 dm2213t /cal 32 u5* byte 3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 4 6 7 9 13 15 16 18 dq 27 dq 28 dq 29 dq 30 dq 31 dq 32 dq 33 dq 34 dm2203t /cal 32 u8 byte 7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 4 6 7 9 13 15 16 18 dq 63 dq 64 dq 65 dq 66 dq 67 dq 68 dq 69 dq 70 dm2203t /cal 32 * u9 byte 6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 4 6 7 9 13 15 18 dq 54 dq 55 dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dm2203t /cal 32 u7 16 bank 0a bank 0b bank 0b bank 0c bank 0c bank 0c bank 0d bank 0d inter connect diagram
2-147 ambient operating temperature (t a ) description ratings output voltage (v out ) power supply voltage (v cc ) storage temperature (t s ) static discharge voltage (per mil-std-883 method 3015) short circuit o/p current (i out ) - 1 ~ v cc +1 - 1 ~ 7v input voltage (v in ) - 1 ~ v cc +1 -40 ~ +70? -55 ~ 150? class 1 50ma* absolute maximum ratings (beyond which per manent damage could result) *one output at a time; short duration. description max pins input capacitance input capacitance 10pf 14pf a 0-10 /g, qle input capacitance 14pf /cal 0-8 i/o capacitance 15pf dq 0-71 input capacitance 14pf w/r, /f input capacitance 12pf /hit input capacitance 12pf /re, /s capacitance pin names a 0-10 address inputs row enable data in/data out column address latch write/read control power (+5v) dq 0-71 /cal 0-8 w/r v cc /re /hit qle hit output output latch enable /we /g write enable output enable ground v ss /f /s chip select refresh control pin names function function nc not connected pin names r 1 = 828 w 5ns v il gnd 5.0v output c l = 50pf r 2 = 295 w load circuit input waveforms 5ns v ih v il v ih ac t est load and w avefor ms v in t iming refer ence point at v il and v ih v out t iming refer enced to 1.5 v olts
2-148 symbol parameters min max test conditions v cc supply voltage 4.75v all voltages referenced to v ss v ih 0v v in 6.5v, all other pins not under test = 0v 0v v in , 0v v out 5.5v i out = - 5ma i out = 4.2ma v cc +1 0.8v 90? 0.4v 90? 2.4v -1.0v -90? -90? 2.4v input high voltage input low voltage input leakage current output leakage current output high level output low level 5.25v v il v oh v ol v i(l) v 0(l) electrical characteristics t a = 0 - 70 c (commer cial) symbol operating current -15 max test condition i cc1 random read /re, /cal, /g and addresses cycling: t c = t c minimum all control inputs stable 3 v cc - 0.2v, outputs driven /re, /cal, /we and addresses cycling: t c = t c minimum /cal, /we and addresses cycling: t pc = t pc minimum 1385ma 1160ma 11ma 1295ma fast page mode read static column read standby random write fast page mode write 1970ma 1700ma 33mhz typ (1) 761ma 671ma 11ma 626ma 1166ma 1391ma notes 2, 3 2, 4 2, 4 2, 3 2, 4 /cal, /g and addresses cycling: t pc = t pc minimum /g and addresses cycling: t ac = t ac minimum -12 max 2465ma 1745ma 1430ma 11ma 2150ma 1655ma see "estimating edram operating power" application note average typical operating current 446ma 1 i cc2 i cc3 i cc4 i cc5 i cc6 i cct symbol operating current -15 max test condition i cc1 random read /re, /cal, /g and addresses cycling: t c = t c minimum all control inputs stable 3 v cc - 0.2v, outputs driven /re, /cal, /we and addresses cycling: t c = t c minimum /cal, /we and addresses cycling: t pc = t pc minimum 1270ma 1070ma 10ma 1190ma fast page mode read static column read standby random write fast page mode write 1790ma 1550ma 33mhz typ (1) 696ma 616ma 10ma 576ma 1056ma 1256ma notes 2, 3 2, 4 2, 4 2, 3 2, 4 /cal, /g and addresses cycling: t pc = t pc minimum /g and addresses cycling: t ac = t ac minimum (1) ?3mhz typ?refers to worst case i cc expected in a system operating with a 33mhz memory bus. see power applications note for further details. this parameter is not 100% tested or guaranteed. (2) i cc is dependent on cycle rates and is measured with cmos levels and the outputs op en. (3) i cc is measured with a maximum of one address change while /re = v il (4) i cc is measured with a maximum of one address change while /cal = v ih -12 max 2240ma 1600ma 1320ma 10ma 1960ma 1520ma see "estimating edram operating power" application note average typical operating current 416ma 1 i cc2 i cc3 i cc4 i cc5 i cc6 i cct dm512k72dt6 dm512k64dt6
2-149 symbol description t ac (1) t aqx t asc t asr t c t c1 t cae t ch t cqv t crp t cwl t dh t gqv (1) t gqx (2,3) column address access time column address change to output data invalid column address setup time row enable cycle time row enable cycle time, cache hit (row=lrr), read cycle only row address setup time column address latch active time column address latch high time (latch transparent) column address latch high to data valid column address latch inactive to data invalid column address latch setup time to row enable /we low to /cal inactive data input hold time data input setup time output enable access time output enable to output drive time 5 5 55 20 5 5 5 5 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min max units 12 5 5 15 0 5 t ach column address valid to /cal inactive (write cycle) ns 12 t dmh mask hold time from row enable (write-per-bit) 1 ns t dms mask setup time to row enable (write-per-bit) 5 ns 5 5 5 65 25 5 t chr /cal inactive lead time to /re inactive (write cycles only) -2 ns -2 5 5 5 0 5 min max 15 5 6 15 0 5 15 1.5 5 5 -12 -15 t cqx output turn-off delay from output disabled (/g - ) t nrh /cal, /g, and /we hold time for /re-only refresh t msu /f and w/r mode select setup time t mh /f and w/r mode select hold time ns 0 5 0 5 ns 0 0 ns 5 5 5 12 5 ns ns ns ns ns 0 0 0 t gqz (4,5) t chw column address latch high to write enable low (multiple writes) 0 ns 0 t ds t aci address valid to /cal inactive (qle high) ns 12 15 t ahq column address hold from qle high (/cal=h) ns 0 0 t aqh address valid to qle high ns 12 15 t cah column address hold time ns 0 0 t clv column address latch low to data valid (qle high) 7 ns 7 t cqh column address latch low to data invalid (qle high) 0 ns 0 t hz hit turn-off from row enable going high ns 0 0 t hv hit valid from row enable ns 5 5 t nrs /cal, /g, and /we setup time for /re-only refresh 5 t pc column address latch cycle time 15 t qci qle high to /cal inactive 0 t qh qle high time 5 switching characteristics note: these parameters do not include buf fer delays. see pages 2-144-5 for derating factors. v cc = 5v 5%, t a = 0 to 70 c, c l = 50pf
2-150 symbol description t rgx t rp t rp1 t rrh t rsh output enable don't care from row enable (write, cache miss), dq = hi-z row precharge time row precharge time, cache hit (row=lrr) read cycle write enable don? care from row enable (write only) last write address latch to end of write row enable to column address latch low for second write 9 0 20 8 0 ns ns ns ns ns ns min max units 35 25 10 0 min max 10 t rqx1 (2,5) row enable high to output turn-on after write miss 12 ns 15 40 -12 -15 12 15 t rsw ns t rwl last write enable to end of write ns 12 15 t sc column address cycle time ns 12 15 t shr select hold from row enable ns 0 0 t sqv (1) chip select access time ns 12 15 t sqx (2,3) output turn-on from select low ns 12 15 0 0 output turn-off from chip select ns 8 10 0 0 t ssr select setup time to row enable ns 5 5 t t transition time (rise and fall) ns 10 10 1 1 t wc write enable cycle time ns 12 15 t wch column address latch low to write enable inactive time ns 5 5 t wi write enable inactive time ns 5 5 t wp write enable active time ns t wqx (2,5) data output turn-on from write enable high ns 0 t wqv (1) data valid from write enable high ns 0 12 5 5 5 15 12 15 t re1 t ref row enable active time, cache hit (row=lrr) read cycle refresh period ms 64 64 8 10 ns t whr (6) write enable hold after /re ns 0 0 t sqz (4,5) t rac (1) row enable access time, on a cache miss 30 35 ns t rac1 (1) row enable access time, on a cache hit (limit becomes t ac ) 15 17 ns t rah row address hold time 1 1.5 ns t re row enable active time 30 35 ns 100000 100000 t ql qle low time 5 5 ns t qqh data hold from qle inactive 2 2 ns t qqv data valid from qle low 7.5 7.5 ns data turn-off from write enable low ns 0 0 5 12 15 15 t wqz (3,4) (1) v out timing reference point at 1.5v; (2) parameter defines time when output is enabl ed (sourcing or sinking current) and is not referenced to v oh or v ol ; (3) minimum specification is referenced from v ih and maximum specification is referenced from v il on input control signal; (4) parameter defines time when output achieves open-c ircuit condition and is not referenced to v oh or v ol ; (5) minimum specification is referenced from v il and maximum specification is referenced from v ih on input control signal; (6) on dm2213, t whr minimum is t ds t wrp t wrr write enable setup time to row enable write to read recovery (following write miss) 12 ns ns switching characteristics note: these parameters do not include buf fer delays. see pages 2-144-5 for derating factors. v cc = 5v 5%, t a = 0 to 70 c, c l = 50pf
2-151 /re /f w/r a 0-10 /cal 0-8 /g /s /hit column 1 t sc t sc data 1 open open t gqz t gqx t gqv t sqv t sqx t sqz dq 0-71 don? care or indeterminate /we a 0-7 column 2 column 3 column 4 data 2 data 3 data 4 ac t t aqx t aqx ac t t aqx ac t ac t t sc notes: 1. data accessed during /re inactive read is from the row address specified during the last /re active read cycle. /re inactive cache read hit (static column mode)
2-152 /re /f w/r a 0-10 /cal 0-8 /g /s /hit t cah column 1 column 2 t asc t cah t ch t cae t pc t cqv t ac t cqx data 1 open data 2 t gqz t gqx t gqv t ac t sqz t sqv t sqx row t asc dq 0-71 /we don? care or indeterminate notes: 1. data accessed during /re inactive read is from the row address specified during the last /re active read cycle. a 0-7 /re inactive cache read hit (page mode)
2-153 /re t c1 row /f w/r a 0-10 /cal 0-8 /g /s t re1 t msu t mh t rp1 t asr t rah column 1 t crp t sc t sc t sc t rac1 data 1 open t gqz t gqx t gqv t ssr t sqz t shr t mh t msu dq 0-71 don? care or indeterminate /we a 0-7 column 2 column 3 column 4 data 2 data 3 data 4 ac t t aqx t aqx ac t t aqx ac t ac t /hit t hz open t hv open /re active cache read hit (static column mode)
2-154 /re t c1 row /f w/r a 0-10 /cal 0-8 /g /s t re1 t msu t mh t rp1 t asr t rah t cah column 1 column 2 t crp t asc t cah t ch t cae t pc t cqv t ac t rac1 t cqx data 1 open data 2 t gqz t gqx t gqv t ac t ssr t sqz t shr t mh t msu row t asc dq 0-71 /we don? care or indeterminate /hit t hz open t hv open a 0-7 /re active cache read hit (page mode)
2-155 /re /f w/r a 0-10 /cal 0-8 /g t c column 1 /s t re t rp t msu t msu t asr t mh t mh t rah t sc t crp t aqx t ac t ac t rac t aqx row column 2 row open data 1 data 2 t gqx t gqv t gqz t ssr t sqz t shr dq 0-71 a 0-10 /we a 0-10 don? care or indeterminate /hit t hz open t hv open a 0-7 a 0-7 /re active cache read miss (static column mode)
2-156 /re /f w/r a 0-10 /cal /g /s t msu t c t re t rp t mh t mh t rah t msu t asr t crp t cah t asc t asc t cah t ch t cae t pc t cqv t rac t cqx t ac open t ac t gqz t ssr t gqx t gqv t shr t sqz row column 1 column 2 row data 1 data 2 dq 0-71 a 0-10 a 0-7 a 0-7 /we don? care or indeterminate a 0-10 /hit t hz open t hv open /re active cache read miss (page mode)
2-157 /cal 0-8 t ac a 0-7 t ac t aqx qle t qqv t aqh dq 0-71 t qh t ql t qqh t ahq column 1 column 2 data 1 data 2 output latch enable operation (static column edo mode read) /cal 0-8 t ac a 0-7 t ac qle dq 0-71 t qci t cqh data 2 data 1 column 1 column 2 t cqv t aqx t aci t pc t ch t clv t cae output latch enable operation (page mode edo read) /cal 0-8 a qle dq 0-71 t ch data 1 column 1 t pc 0-7 column 2 column 3 data 2 data 3 t cae t aci t qci t aci t aci t ac t ac t ac t cqv t cqv t qqv t qqh t qqv t qqv t qqh qh t ql t output latch enable operation (asynchr onous access)
2-158 /re /f w/r /cal 0-8 /we /g t re /s column 1 t msu t msu t asr t mh t mh t rah t rsw column 2 row column n cache (column n) open t crp t cah t asc t cwl t cae t cwl t chr t rsh t cae t wrp t wp t rrh t wch t wch t pc t wp t rwl t dh t dh t ds t ds t ac t wrr t gqx t gqv t ssr dq 0-71 a 0-7 a 0-7 a 0-7 data 1 data 2 t ach t ach t ch t whr t wi t wc t chw t rp a 0-10 a 0-10 don? care or indeterminate notes: 1. /g becomes a don? care after t rgx during a write miss. t cah /hit t hz open t hv open burst w rite (hit or miss) followed by /re inactive cache reads
/re /f w/r a 0-10 /cal 0-8 /we /g t re /s column 1 t msu t msu t asr t mh t mh t rah column 2 row column 3 t wrp t gqx t ssr dq 0-71 a 0-7 read data t whr t c t rp don? care or indeterminate notes: 1. if column address one equals column address two, then a read-modify-write cycle is performed. t crp t cae t ach t asc t rsh t wch t rrh t cqv t chr t wp t cwl write data read data t ac t aqx t ds t rwl t wqv t gqv t gqz t dh t gqz t gqv t wqx /hit t hz open t hv open t cah t ac read/w rite during w rite hit cycle (can include read-modify-w rite) 2-159
2-160 /re /cal w/r a 0-10 0-8 /we /f t re /s t rah t msu t a 0-7 asr t mh t ssr dq 0-71 t rp t rsh t cae t chr row column t asc t cah t cwl mask data t t dmh dms t rwl t wch t wrp t ds t dh t wp t rrh t msu t mh t shr t ach t whr don? care or indeterminate notes: 1. 2. data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit wri te. write-per-bit cycle valid only for dm512k72dt6. /hit t hz open t hv open w rite-per -bit cycle (/g=high)
2-161 /re a 0-10 0-8 /s t c w/r, /f /cal , /we, /g t re t rp t asr t rah row t nrs t nrh t msu t mh t ssr t shr don? care or indeterminate notes: 1. 2. all binary combinations of a 0-9 must be refreshed every 64ms interval. a 10 does not have to be cycled, but must remain valid during row address setup and hold times. /re refresh is write cycle with no /cal active cycle. /hit t hz open t hv open /re-only refr esh /re /f t re t msu t mh don? care or indeterminate notes: 1. 2. during /f refresh cycles, the status of w/r, /we, a 0-10 , /cal, /s, and /g is a don? care. /re inactive cache reads may be performed in parallel with /f refresh cycles. t rp /f refr esh cycle
2-162 dm512k72dt 6- 12 n dynamic memory memory depth memory module configuration packaging system access time from cache in nanoseconds 12ns 15ns error check mode (72-bit only) blank - write-per-bit parity n - ecc (no write-per-bit) t = 300 mil, plastic tsop - ii 512k 1m d= dimm i/o width 64 = 64 bits 72 = 72 bits par t numbering system 5.250(133.35) 2.585 (65.66) 0.700 0.040 (1.04) 0.050 (1.27) inches (mm) u8 u9 u7 u6 u5 u4 u3 u2 u1 u1 c10 c10 r3 r1 r2 c11 c12 c1 u2 c2 u3 c3 u4 c4 u5 c5 u6 c6 u77 c7 u8 c8 u9 c9 1.500 .050 (1.27) .104 (2.64) c11 c12 u10 u11 u12 u1-4, u6-9 u5 c1-12 enhanced dm2203t-xx, 512kx8 edram, 300 mil tsop enhanced dm2213t-xx, 512kx8 edram with write-per-bit (not present on dm512k64dt) robinson nugent dims - 168bd5-tr or equivalent 0.22? chip capacitor idt 74fct162344etpa address/clock driver or equivalent socket u10-12 mechancial data 168 pin dimm module configuration the information contained herein is subject to change without notice. enhanced memory systems inc. assumes no responsibility fo r the use of any circuitry other than circuitry embodied in an enhanced product, nor does it convey or imply any license under patent or other rights.

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