february 2001 1 copyright 2000, 2001 by lsi logic corporation. all rights reserved. g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers datasheet lsi logic corporation provides the following driver/receiver input/output (i/o) cells for use as general purpose i/o buffers: the i/o buffers provide off-chip, bidirectional i/o signaling for application- speci? integrated circuit (asic) chips implemented in the lsi logic g12 -p 0.13 m process technology. functionally similar, the i/o buffers ( figure 1 ) provide an asic application with different driver options. figure 1 buffer block diagrams ? BD4F5FSLS33 ? bd4puf5fsls33 ? bd4puodf5fsls33 ? bd4puodf5fscls33 pi tn en a z po io iddtn t d cen pi tn en a z po iddtn cen pi tn en a z po io iddtn t d cen pi tn en a z po io iddtn i/o pad i/o pad i/o pad io i/o pad a) BD4F5FSLS33 b) bd4puf5fsls33 c) bd4puodf5fsls33 d) bd4puodf5fscls33
2 g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers features and bene?s signal descriptions ta b l e 1 describes signal connections for all four buffers. ? up to 20 mhz, 3.3 v i/o operation ? 5-volt tolerant ? fail-safe at high voltages ? feedthrough protection ? 20 a maximum leakage current ? minimum 4 ma current drive into a 40 pf load at 20 mhz ? 1.8 v internal signaling for reduced power consumption ? uses one standard i/o slot table 1 i/o buffer connections signal direction description a in data input to i/o buffer driver from asic circuitry cen 1 1. not available in bd4puodf5fscls33 in enables i/o buffer operation after power-on d 2 2. available only in BD4F5FSLS33 and bd4puf5fsls33. refer to ta bl e 4 for settings. in con?ures driver operating mode en in 0 = normal mode 1 = disable i/o buffer driver iddtn in 0 = power down entire cell 3 1 = normal mode 3. used for production iddq leakage test pi in nand-tree parametric test input t 2 in con?ures driver operating mode tn in 0 = disable i/o buffer driver 1 = normal mode io in/out input/output pad po out nand-tree parametric test output z out i/o buffer receiver output to asic circuitry
g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers 3 general description the buffers include a receiver, driver, and nand-tree circuitry to conform with standard lsi logic test methodology. the buffers translate signals between the 1.8 v operating levels of the asic core circuitry and the 3.3 v operating levels at the i/o pad. they tolerate high dc and transient voltages at the i/o pad, are fail safe, and provide feedthrough protection. voltage tolerance the i/o buffers are 5-volt tolerant. although the off-chip i/o signaling normally operates at 3.3 volts, external circuitry may cause higher voltages, typically upwards of 5 volts, to appear at the chip i/o pad. circuit and process techniques ensure that such dc or transient voltages do not damage the i/o buffer circuitry. failure and feedthrough protection in the absence of a v dd supply, the i/o buffers are fail-safe and protected against voltage feedthrough. with high voltage applied to the chip i/o pad, the i/o buffers can survive without degradation for up to ten years. furthermore, with a low, maximum 20 a leakage current, the high voltage can not power up the asic through voltage feedthrough. functional description of receivers the buffers use the same receiver circuitry. the following truth table ( ta b l e 2 ) describes receiver behavior. table 2 receiver truth table inputs outputs iddtn io pi z po 0 1 1. factory iddq test setting high impedance 1 1 0 10 001 11 011 11 110
4 g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers functional description of drivers the buffers use similar driver circuitry that produces a minimum of 4 ma of output drive. the buffers provide options for selecting the driver output con?uration and power-up mode ( ta b l e 3 ). all the buffers except BD4F5FSLS33 have internal pull-up resistor devices. preset power-up modes avoid unpredictable output behavior. driver output con?uration with the BD4F5FSLS33 ( figure 1 a) or bd4puf5fsls33 ( figure 1 b) buffer, the t and d inputs set a driver output to open-drain, open-source, or totem-pole mode ( ta b l e 4 ). an application can hardwire the t and d inputs, or, to dynamically con?ure a driver output, it can supply the t and d inputs from a register. table 3 i/o buffer driver characteristics i/o buffer cell driver mode pull-up power-up mode application BD4F5FSLS33 dynamically programmable open-drain, open-source, or totem-pole output none 3-state general bd4puf5fsls33 dynamically programmable open-drain, open-source, or totem-pole output ye s , internal 3-state general bd4puodf5fsls33 open-drain output yes, internal current sinking logic level 0 power-on reset bd4puodf5fscls33 open-drain output yes, internal 3-state general table 4 driver output mode selection t d output 0 0 open drain 0 1 totem pole 1 0 totem pole 1 1 open source
g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers 5 the bd4puodf5fsls33 ( figure 1 c) and the bd4puodf5fscls33 ( figure 1 d) buffers ? the output in the open-drain mode. pull-up resistor except for BD4F5FSLS33 , the buffers include a pull-up resistor, which can provide from 100 a to 500 a of current across the speci?d process, voltage, and temperature ranges. note: evaluate the buffer models before simulating a design. models provided for some third-party design environments may not correctly represent or even include the pull-up resistor. power-up modes each buffer has a de?ed power-up mode ( ta b l e 3 ) to avoid unpredictable output behavior. the BD4F5FSLS33 , bd4puf5fsls33 , and bd4puodf5fsls33 buffers preset the driver output to 3-state or current- sinking mode upon power up. the bd4puodf5fscls33 buffer has no preset power-up mode. preset to 3-state (BD4F5FSLS33 and bd4puf5fsls33) at power up, circuitry in the BD4F5FSLS33 and bd4puf5fsls33 buffers forces the io signal at the i/o pad to the high-impedance state. to begin normal operation, the buffers require the asic application to assert cen to high. preset to open-drain (bd4puodf5fsls33) at power up, circuitry in the bd4puodf5fsls33 buffer forces the driver output to open-drain mode. as the driver sinks current, it drives the io signal at the i/o pad to low. designed primarily for power-on-reset applications, the buffer holds circuits connected to the i/o pad in the low reset state until the asic application asserts cen to high, thereby releasing the buffer to operate normally. to drive the cen signal high directly from a source external to the asic, connect cen to a ddrv type i/o pad for esd protection and apply an activation signal. although this activation signal may reach 3.3 v, a signal limited to1.8 v better matches the normal internal signaling level, and is therefore preferable.
6 g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers no preset (bd4puodf5fscls33) the bd4puodf5fscls33 buffer has no cen signal to provide a separate power-up mode. however, power-up characteristics of the buffer circuitry prevent hard driving the io signal at the i/o pad to high, thereby avoiding unpredictable behavior. a relatively high-impedance pull-up device eventually drives io to high unless ? the buffer itself drives it low with a = en = 0 and tn = 1, or ? another device external to the buffer drives it low. truth tables ta b l e 5 describes the driver behavior for the BD4F5FSLS33 and bd4puf5fsls33 buffers. table 5 truth table for BD4F5FSLS33 and bd4puf5fsls33 drivers inputs output without pull-up resistor 1 1. using BD4F5FSLS33 buffer output with pull-up resistor 2 2. using bd4puf5fsls33 buffer. note: spice type simulation may produce different behavior. description iddtn cen a tn en t d x 3 3. don? care state, x = 0 or 1 0 x x x x x high impedance high impedance 3-state power-up mode 0 1 x x x x x high impedance high impedance factory iddq test setting 1 1 x x 1 x x high impedance high impedance 4 4. in silicon, the pull-up resistor actually pulls the output high. however, third-party models do not correctly represent the pull-up resistor. therefore, the truth table shows the output in the high- impedance state. disabled with en 1 1 x 0 x x x high impedance high impedance 4 disabled with tn 1 1 0 1 0 0 0 0 0 open-drain output 1 1 1 1 0 0 0 high impedance high impedance 4 open-drain output 1 1 0 1 0 0 1 0 0 totem-pole output 1 1 1 1 0 0 1 1 1 totem-pole output 1 1 0 1 0 1 0 0 0 totem-pole output 1 1 1 1 0 1 0 1 1 totem-pole output 1 1 0 1 0 1 1 high impedance high impedance 4 open-source output 1 1 1 1 0 1 1 1 1 open-source output
g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers 7 ta b l e 6 describes the bd4puodf5fsls33 driver behavior. ta b l e 7 describes the bd4puodf5fscls33 driver behavior. table 6 truth table for bd4puodf5fsls33 driver inputs output description iddtn cen a tn en io x 1 1. don? care state, x = 0 or 1 0 xxx0 open-drain power-up mode 0 1 x x x high impedance factory iddq test setting 1 1 x x 1 high impedance 2 2. in silicon, the pull-up resistor actually pulls the output high. however, third-party models do not correctly represent the pull-up resistor. therefore, the truth table shows the output in the high-impedance state. disabled with en 1 1 x 0 x high impedance 2 disabled with tn 110100 open-drain output 11110 high impedance 2 open-drain output table 7 truth table for bd4puodf5fscls33 driver inputs output iddtn a tn en io mode 0x 1 1. don? care state, x = 0 or 1 x x high impedance factory iddq test setting 1 x x 1 high impedance 2 2. in silicon, the pull-up resistor actually pulls the output high. however, third- party models do not correctly represent the pull-up resistor. therefore, the truth table shows the output in the high-impedance state. disabled with en 1 x 0 x high impedance 2 disabled with tn 10100 open-drain output 1110 high impedance 2 open-drain output
8 g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers driver slew rate the following slew rate measurement applies to the BD4F5FSLS33 and bd4puf5fsls33 buffers in totem-pole mode. in the rise/fall test, the driver drives a signal across a 40 pf load capacitor ( figure 2 ). ta bl e 8 shows the observed slew rate across the load capacitor measured from 0.6 v to 2.2 v. figure 2 rise/fall test circuit testing the buffers include test circuitry and signals compatible with standard lsi logic test methodology. the pi and po nand-tree signals provide access for parametric testing. the global iddtn signal powers down all circuitry for iddq leakage testing. impor t ant : the iddq leakage test requires the i/o buffers in the high- impedance state. setting iddtn to low usually accom- plishes this condition. however, with the i/o buffers that use cen to preset the power-up mode, iddq may fail due to high leakage current unless cen is also driven high. table 8 driver rise/fall slew rate min. typ. max. unit 600 mv/ns output 40 pf input gnd
g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers 9 speci?ations the buffers adhere to the general speci?ations in ta b l e 9 . ta b l e 1 0 describes the receiver dc characteristics. ta b l e 1 1 describes the driver dc characteristics. table 9 general speci?ations symbol parameter condition min. typ. max. unit v dd supply voltage 2.97 3.30 3.63 v t j junction temperature 0 125 ?c esd electrostatic discharge, human body model (hbm) mil-std-883c, method 3015.7 100 pf @1.5 k ? 2000 v electrostatic discharge, charged device model (cdm) esd ds5.3.1-1996 500 v table 10 receiver dc characteristics 1 1. values apply over all voltage, temperature, and process conditions symbol parameter test condition min. typ. max. units v ih input high voltage 1.5 2.0 v v il input low voltage 1.0 1.5 v v h hysteresis 320 mv i il input leakage current 0 v pa d 3.63 v, v dd = 3.3 v 10% 10 a i lu latchup current ? 2v 10 g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers table 11 driver dc characteristics 1 1. values apply over all voltage, temperature, and process conditions. symbol parameter test condition min. typ. max. units v dd supply voltage v ol and high impedance output only 2.97 3.30 3.63 v v ol output, low i ol = 4 ma 0.4 v v oh output, high i oh = ? 4ma v dd = 3.135 v 2.4 v i ol sink current v ol = 0.4 v maximum, totem-pole and open-drain mode 4 ma i oh source current v oh = 2.4 v minimum, totem-pole and open-source mode ? 4ma i oz 3-stated leakage current 0 v pa d 5.5 v, resistors disabled, v dd = 3.3 v 10% 20 a i lu latchup current ? 2v g12 -p 3.3 v, 4 ma, 5-volt tolerant, fail-safe, general purpose i/o buffers 11 system design guidelines to ensure good system-level operation, lsi logic provides the following guidelines for placing these i/o cells in the asic and for supplying power. placement all these i/o cells have the same dimensions ( ta b l e 1 2 ) and require placement on the i/o ring using one i/o slot. for correct placement of the i/o cells, adhere to the following guidelines: ? these i/o cells may adjoin each other. they may also adjoin a bd4f5fs60ls33 cell. ? separate these i/o cells from any other type of i/o function by at least one i/o slot to avoid n-channel to p-channel design rule violations. if possible, use a vdd or vss pad for the separation. ? because their lengths exceed the length of other standard i/o functions, these i/o cells may not use a corner i/o slot. power for best system-level performance, adhere to the following power guidelines: ? use one power/ground pad pair for every four i/o cells. ? place an i/o cell no more than four slots away from a power pad and no more than four slots away from a ground pad. table 12 cell dimensions on the i/o ring width along the i/o ring length into the chip 45.36 m 397.53 m
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