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adc12130/adc12132/adc12138 self-calibrating 12-bit plus sign serial i/o a/d converters with mux and sample/hold general description the adc12130, adc12132 and adc12138 are 12-bit plus sign successive approximation a/d converters with serial i/o and configurable input multiplexer. the adc12132 and adc12138 hav e a 2 and an 8 channel multiplexer, respec- tively. the differential multiplexer outputs and a/d inputs are available on the muxout1, muxout2, a/din1 and a/din2 pins. the adc12130 has a two channel multiplexer with the multiplexer outputs and a/d inputs internally connected. the adc12130 family is tested with a 5 mhz clock. on request, these a/ds go through a self calibration process that adjusts linearity, zero and full-scale errors to typically less than 1 lsb each. the analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. a fully differential unipolar analog input range (0v to +5v) can be accommodated with a single +5v supply. in the differential modes, valid outputs are ob- tained even when the negative inputs are greater than the positive because of the 12-bit plus sign output data format. the serial i/o is configured to comply with the nsc mi- crowire ? . for voltage references, see the lm4040 or lm4041. features n serial i/o (microwire, spi and qspi compatible) n 2 or 8 channel differential or single-ended multiplexer n analog input sample/hold function n power down mode n programmable acquisition time n variable digital output word length and format n no zero or full scale adjustment required n 0v to 5v analog input range with single 5v power supply key specifications n resolution: 12-bit plus sign n 12-bit plus sign conversion time: 8.8 s (max) n 12-bit plus sign throughput time: 14 s (max) n integral linearity error: 2 lsb (max) n single supply: 3.3v or 5v 10% n power consumption e 3.3v 15 mw (max) e 3.3v power down 40 w (typ) e 5v 33 mw (max) e 5v power down 100 w (typ) applications n pen-based computers n digitizers n global positioning systems adc12138 simplified block diagram tri-state ? is a registered trademark of national semiconductor corporation. cops ? microcontrollers, hpc ? and microwire ? are trademarks of national semiconductor corporation. ds012079-1 march 2000 adc12130/adc12132/adc12138 self-calibrating 12-bit plus sign serial i/o a/d converters with mux and sample/hold ? 2000 national semiconductor corporation ds012079 www.national.com
ordering information industrial temperature range ?40c t a +85c ns package number adc12130cin n16e, dual-in-line adc12130ciwm m16b, wide body so adc12132cimsa msa20, ssop adc12138cin n28b, dual-in-line adc12138ciwm m28b adc12138cimsa msa28, ssop connection diagrams 16-pin dual-in-line and wide body so packages ds012079-2 top view 20-pin ssop package ds012079-47 top view 28-pin dual-in-line, ssop and wide body so packages ds012079-3 top view adc12130/adc12132/adc12138 www.national.com 2
pin descriptions cclk the clock applied to this input controls the su- cessive approximation conversion time interval and the acquisition time. the rise and fall times of the clock edges should not exceed 1 s. sclk this is the serial data clock input. the clock applied to this input controls the rate at which the serial data exchange occurs. the rising edge loads the information on the di pin into the multiplexer address and mode select shift register. this address controls which channel of the analog input multiplexer (mux) is se- lected and the mode of operation for the a/d. with cs low, the falling edge of sclk shifts the data resulting from the previous adc con- version out on do, with the exception of the first bit of data. when cs is low continuously, the first bit of the data is clocked out on the ris- ing edge of eoc (end of conversion). when cs is toggled, the falling edge of cs always clocks out the first bit of data. cs should be brought low when sclk is low. the rise and fall times of the clock edges should not exceed 1 s. di this is the serial data input pin. the data ap- plied to this pin is shifted by the rising edge of sclk into the multiplexer address and mode select register. table 2 through table 4 show the assignment of the multiplexer address and the mode select data. do the data output pin. this pin is an active push/ pull output when cs is low. when cs is high, this output is tri-state. the a/d conversion result (db0db12) and converter status data are clocked out by the falling edge of sclk on this pin. the word length and format of this re- sult can vary (see table 1 ). the word length and format are controlled by the data shifted into the multiplexer address and mode select register (see table 4 ). eoc this pin is an active push/pull output and indi- cates the status of the adc12130/2/8. when low, it signals that the a/d is busy with a con- version, auto-calibration, auto-zero or power down cycle. the rising edge of eoc signals the end of one of these cycles. cs this is the chip select pin. when a logic low is applied to this pin, the rising edge of sclk shifts the data on di into the address register. this low also brings do out of tri-state. with cs low, the falling edge of sclk shifts the data resulting from the previous adc con- version out on do, with the exception of the first bit of data. when cs is low continuously, the first bit of the data is clocked out on the ris- ing edge of eoc (end of conversion). when cs is toggled, the falling edge of cs always clocks out the first bit of data. cs should be brought low when sclk is low. the falling edge of cs resets a conversion in progress and starts the sequence for a new conversion. when cs is brought back low during a conver- sion, that conversion is prematurely termi- nated. the data in the output latches may be corrupted. therefore, when cs is brought back low during a conversion in progress the data output at that time should be ignored. cs may also be left continuously low. in this case it is imperative that the correct number of sclk pulses be applied to the adc in order to re- main synchronous. after the adc supply power is applied it expects to see 13 clock pulses for each i/o sequence. the number of clock pulses the adc expects is the same as the digital output word length. this word length can be modified by the data shifted in on the do pin. table 4 details the data required. dor this is the data output ready pin. this pin is an active push/pull output. it is low when the con- version result is being shifted out and goes high to signal that all the data has been shifted out. conv a logic low is required on this pin to program any mode or change the adc's configuration as listed in the mode programming table ( table 4 ) such as 12-bit conversion, auto cal, auto zero etc. when this pin is high the adc is placed in the read data only mode. while in the read data only mode, bringing cs low and pulsing sclk will only clock out on do any data stored in the adcs output shift register. the data on di will be neglected. a new con- version will not be started and the adc will re- main in the mode and/or configuration previ- ously programmed. read data only cannot be performed while a conversion, auto-cal or auto-zero are in progress. pd this is the power down pin. when pd is high the a/d is powered down; when pd is low the a/d is powered up. the a/d takes a maximum of 700 s to power up after the command is given. ch0ch7 these are the analog inputs of the mux. a channel input is selected by the address infor- mation at the di pin, which is loaded on the ris- ing edge of sclk into the address register (see table 2 and table 3 ). the voltage applied to these inputs should not exceed v a + or go below gnd. exceeding this range on an unselected channel will corrupt the reading of a selected channel. com this pin is another analog input pin. it is used as a pseudo ground when the analog multi- plexer is single-ended. muxout1, muxout2 these are the multiplexer output pins. a/din1, a/din2 these are the converter input pins. muxout1 is usually tied to a/din1. muxout2 is usually tied to a/din2. if external circuitry is placed be- tween muxout1 and a/din1, or muxout2 and a/din2 it may be necessary to protect these pins. the voltage at these pins should not exceed v a + or go below agnd (see figure 5 ). v ref + this is the positive analog voltage reference input. in order to maintain accuracy, the volt- age range of v ref (v ref =v ref +?v ref ?) is adc12130/adc12132/adc12138 www.national.com 3
pin descriptions (continued) 1v dc to 5.0 v dc and the voltage at v ref + cannot exceed v a +. see figure 6 for recom- mended bypassing. v ref ? the negative voltage reference input. in order to maintain accuracy, the voltage at this pin must not go below gnd or exceed v a +. (see figure 6 ). v a +, v d + these are the analog and digital power supply pins. v a + and v d + are not connected together on the chip. these pins should be tied to the same power supply and bypassed separately (see figure 6 ). the operating voltage range of v a + and v d + is 3.0 v dc to 5.5 v dc . dgnd this is the digital ground pin (see figure 6 ). agnd this is the analog ground pin (see figure 6 ). adc12130/adc12132/adc12138 www.national.com 4
absolute maximum ratings (notes 1, 2) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. positive supply voltage (v + =v a +=v d +) 6.5v voltage at inputs and outputs except ch0ch7 and com ?0.3v to v + +0.3v voltage at analog inputs ch0ch7 and com gnd ?5v to v + +5v |v a +?v d +| 300 mv input current at any pin (note 3) 30 ma package input current (note 3) 120 ma package dissipation at t a = 25c (note 4) 500 mw esd susceptability (note 5) human body model 1500v soldering information n packages (10 seconds) 260c so package (note 6): vapor phase (60 seconds) 215c infrared (15 seconds) 220c storage temperature ?65c to +150c operating ratings (notes 1, 2) operating temperature range t min t a t max adc12130cin, adc12130ciwm, adc12132cimsa, adc12138cimsa, adc12138cin, adc12138ciwm ?40c t a +85c supply voltage (v + =v a +=v d +) +3.0v to +5.5v |v a +?v d +| 100 mv v ref + 0vtov a + v ref ? 0vtov ref + v ref (v ref +?v ref ?) 1v to v a + v ref common mode voltage range 0.1 v a + to 0.6 v a + a/din1, a/din2, muxout1 and muxout2 voltage range 0v to v a + a/d in common mode voltage range 0v to v a + converter electrical characteristics the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = 3.3v, v ref + = 2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j =t min to t max ; all other limits t a =t j = 25c. (notes 7, 8, 9) symbol parameter conditions typical (note 10) limits units (limits) (note 11) static converter characteristics resolution 12 + sign bits (min) +ile positive integral linearity error after auto-cal (notes 12, 18) 1/2 2 lsb (max) ?ile negative integral linearity error after auto-cal (notes 12, 18) 1/2 2 lsb (max) dnl differential non-linearity after auto-cal 1.5 lsb (max) positive full-scale error after auto-cal (notes 12, 18) 1/2 3.0 lsb (max) negative full-scale error after auto-cal (notes 12, 18) 1/2 3.0 lsb (max) offset error after auto-cal (notes 5, 18) 1/2 2 lsb (max) v in (+)=v in (?) = 2.048v dc common mode error after auto-cal (note 15) 2 lsb (max) tue total unadjusted error after auto-cal 1 lsb (notes 12, 13, 14) adc12130/adc12132/adc12138 www.national.com 5
converter electrical characteristics the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = 3.3v, v ref + = +2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j = t min to t max ; all other limits t a =t j = 25c. (notes 7, 8, 9) (continued) symbol parameter conditions typical (note 10) limits units (limits) (note 11) static converter characteristics (continued) multiplexer channel to channel 0.05 lsb matching power supply sensitivity v + = +5v 10% v ref = +4.096v offset error 0.5 lsb + full-scale error 0.5 lsb ? full-scale error 0.5 lsb + integral linearity error 0.5 lsb ? integral linearity error 0.5 lsb unipolar dynamic converter characteristics s/(n+d) signal-to-noise plus f in = 1 khz, v in =5v pp ,v ref + = 5.0v 69.4 db distortion ratio f in = 20 khz, v in =5v pp ,v ref + = 5.0v 68.3 db f in = 40 khz, v in =5v pp ,v ref + = 5.0v 65.7 db ?3 db full power bandwidth v in =5v pp , where s/(n+d) drops 3 db 31 khz differential dynamic converter characteristics s/(n+d) signal-to-noise plus f in = 1 khz, v in = 5v, v ref + = 5.0v 77.0 db distortion ratio f in = 20 khz, v in = 5v, v ref + = 5.0v 73.9 db f in = 40 khz, v in = 5v, v ref + = 5.0v 67.0 db ?3 db full power bandwidth v in = 5v, where s/(n+d) drops 3 db 40 khz electrical characteristics the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = +3.3v, v ref + = 2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j = t min to t max ; all other limits t a =t j = 25c. (notes 7, 8, 9) symbol parameter conditions typical limits units (note 10) (note 11) (limits) reference input, analog inputs and multiplexer characteristics c ref reference input capacitance 85 pf c a/d a/din1 and a/din2 analog input 75 pf capacitance a/din1 and a/din2 analog input v in = +5.0v or 0.1 a leakage current v in =0v ch0ch7 and com input voltage gnd ? 0.05 v v a + + 0.05 c ch ch0ch7 and com input capacitance 10 pf c muxout mux output capacitance 20 pf off channel leakage (note 16) on channel = 5v and ?0.01 a ch0ch7 and com pins off channel = 0v on channel = 0v and 0.01 a off channel = 5v adc12130/adc12132/adc12138 www.national.com 6
electrical characteristics (continued) the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = +3.3v, v ref + = 2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j = t min to t max ; all other limits t a =t j = 25c. (notes 7, 8, 9) symbol parameter conditions typical limits units (note 10) (note 11) (limits) reference input, analog inputs and multiplexer characteristics on channel leakage (note 16) on channel = 5v and 0.01 a ch0ch7 and com pins off channel = 0v on channel = 0v and ?0.01 a off channel = 5v muxout1 and muxout2 v muxout = 5.0v or 0.01 a leakage current v muxout =0v r on mux on resistance v in = 2.5v and 850 1900 w (max) v muxout = 2.4v r on matching channel to channel v in = 2.5v and 5 % v muxout = 2.4v channel to channel crosstalk v in =5v pp ,f in = 40 khz ?72 db mux bandwidth 90 khz dc and logic electrical characteristics the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully-differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = +3.3v, v ref + = +2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j = t min to t max ; all other limits t a =t j = 25c. (notes 7, 8, 9) symbol parameter conditions typical (note 10) v + =v a += v + =v a + = units (limits) v d + = 3.3v v d +=5v limits limits (note 11) (note 11) cclk, cs, conv, di, pd and sclk input characteristics v in(1) logical a1o input voltage v a +=v d +=v + +10% 2.0 2.0 v (min) v in(0) logical a0o input voltage v a +=v d +=v + ?10% 0.8 0.8 v (max) i in(1) logical a1o input current v in =v + 0.005 1.0 1.0 a (max) i in(0) logical a0o input current v in = 0v ?0.005 ?1.0 ?1.0 a (min) do, eoc and dor digital output characteristics v out(1) logical a1o v a +=v d +=v + ? 10%, output voltage i out = ?360 a 2.4 2.4 v (min) v a +=v d +=v + ? 10%, 2.9 4.25 v (min) i out = ?10 a v out(0) logical a0o v a +=v d +=v + ? 10% output voltage i out = 1.6 ma 0.4 0.4 v (max) i out tri-state v out = 0v ?0.1 ?3.0 ?3.0 a (max) output current v out =v + ?0.1 3.0 3.0 +i sc output short circuit source current v out = 0v ?14 ma adc12130/adc12132/adc12138 www.national.com 7
dc and logic electrical characteristics (continued) the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully-differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = +3.3v, v ref + = +2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j = t min to t max ; all other limits t a =t j = 25c. (notes 7, 8, 9) symbol parameter conditions typical (note 10) v + =v a += v + =v a + = units (limits) v d + = 3.3v v d +=5v limits limits (note 11) (note 11) do, eoc and dor digital output characteristics ?i sc output short circuit sink current v out =v d +16 ma power supply characteristics i d + digital supply 1.5 2.5 ma (max) current cs = high, powered down, cclk on 600 a cs = high, powered down, cclk off 20 a i a + positive analog 3.0 4.0 ma (max) supply current cs = high, powered down, cclk on 10 a cs = high, powered down, cclk off 0.1 a i ref reference input current cs = high, powered down, cclk on 70 a cs = high, powered down, cclk off 0.1 a ac electrical characteristics the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully-differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = +3.3v, v ref + = +2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j = t min to t max ; all other limits t a =t j = 25c. (note 17) symbol parameter conditions typical limits units (note 10) (note 11) (limits) f ck conversion clock 10 5 mhz (max) (cclk) frequency 1 mhz (min) f sk serial data clock 10 5 mhz (max) sclk frequency 0 hz (min) conversion clock 40 % (min) duty cycle 60 % (max) serial data clock 40 % (min) duty cycle 60 % (max) t c conversion time 12-bit + sign or 12-bit 44(t ck ) 44(t ck ) (max) 8.8 s (max) adc12130/adc12132/adc12138 www.national.com 8
ac electrical characteristics (continued) the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully-differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = +3.3v, v ref + = +2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j = t min to t max ; all other limits t a =t j = 25c. (note 17) symbol parameter conditions typical limits units (note 10) (note 11) (limits) t a acquisition time 6 cycles programmed 6(t ck ) 6(t ck ) (min) (note 19) 7(t ck ) (max) 1.2 s (min) 1.4 s (max) 10 cycles programmed 10(t ck ) 10(t ck ) (min) 11(t ck ) (max) 2.0 s (min) 2.2 s (max) 18 cycles programmed 18(t ck ) 18(t ck ) (min) 19(t ck ) (max) 3.6 s (min) 3.8 s (max) 34 cycles programmed 34(t ck ) 34(t ck ) (min) 35(t ck ) (max) 6.8 s (min) 7.0 s (max) t cal self-calibration time 4944(t ck ) 4944(t ck ) (max) 988.8 s (max) t az auto-zero time 76(t ck ) 76(t ck ) (max) 15.2 s (max) t sync self-calibration or 2(t ck ) 2(t ck ) (min) auto-zero synchronization 3(t ck ) (max) time from dor 0.40 s (min) 0.60 s (max) t dor dor high time when cs is low 9(t sk ) 9(t sk ) (max) continuously for read data and software power up/down 1.8 s (max) t conv conv valid data time 8(t sk ) 8(t sk ) (max) 1.6 s (max) ac electrical characteristics the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully-differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = +3.3v, v ref + = +2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j = t min to t max ; all other limits t a =t j = 25c. (note 17) (continued) symbol parameter conditions typical limits units (note 10) (note 11) (limits) t hpu hardware power-up time, time from 500 700 s (max) pd falling edge to eoc rising edge t spu software power-up time, time from serial data clock falling edge to 500 700 s (max) eoc rising edge t acc access time delay from 25 60 ns (max) cs falling edge to do data valid adc12130/adc12132/adc12138 www.national.com 9
ac electrical characteristics (continued) the following specifications apply for (v + =v a +=v d + = +5v, v ref + = +4.096v, and fully-differential input with fixed 2.048v common-mode voltage) or (v + =v a +=v d + = +3.3v, v ref + = +2.5v and fully-differential input with fixed 1.250v common-mode voltage), v ref ? = 0v, 12-bit + sign conversion mode, source impedance for analog inputs, v ref ? and v ref + 25 w ,f ck =f sk = 5 mhz, and 10 (t ck ) acquisition time unless otherwise specified. boldface limits apply for t a =t j = t min to t max ; all other limits t a =t j = 25c. (note 17) (continued) symbol parameter conditions typical limits units (note 10) (note 11) (limits) t set-up set-up time of cs falling edge to 50 ns (min) serial data clock rising edge t delay delay from sclk falling 0 5 ns (min) edge to cs falling edge t 1h ,t 0h delay from cs rising edge to r l = 3k, c l = 100 pf 70 100 ns (max) do tri-state ? t hdi di hold time from serial data 5 15 ns (min) clock rising edge t sdi di set-up time from serial data 5 10 ns (min) clock rising edge t hdo do hold time from serial data r l = 3k, c l = 100 pf 35 65 ns (max) clock falling edge 5 ns (min) t ddo delay from serial data clock 50 90 ns (max) falling edge to do data valid t rdo do rise time, tri-state to high r l = 3k, c l = 100 pf 10 40 ns (max) do rise time, low to high 10 40 ns (max) t fdo do fall time, tri-state to low r l = 3k, c l = 100 pf 15 40 ns (max) do fall time, high to low 15 40 ns (max) t cd delay from cs falling edge 45 80 ns (max) to dor falling edge t sd delay from serial data clock falling 45 80 ns (max) edge to dor rising edge c in capacitance of logic inputs 10 pf c out capacitance of logic outputs 20 pf note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device is f unc- tional, but do not guarantee specific performance limits. for guaranteed specifications and test conditions, see the electrical characteristics. the guaranteed speci- fications apply only for the test conditions listed. some performance characteristics may degrade when the device is not operated under the listed te st conditions. note 2: all voltages are measured with respect to gnd, unless otherwise specified. note 3: when the input voltage (v in ) at any pin exceeds the power supplies (v in < gnd or v in > v a +orv d +), the current at that pin should be limited to 30 ma. the 120 ma maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 ma to four. note 4: the maximum power dissipation must be derated at elevated temperatures and is dictated by t j max, q ja and the ambient temperature, t a . the maximum allowable power dissipation at any temperature is p d =(t j max ? t a )/ q ja or the number given in the absolute maximum ratings, whichever is lower. for this device, t j max = 150c. the typical thermal resistance ( q ja ) of these parts when board mounted follow: thermal part number resistance q ja adc12130cin 53c/w adc12130ciwm 70c/w adc12132cimsa 134c/w adc12138cin 40c/w adc12138ciwm 50c/w adc12138cimsa 125c/w note 5: the human body model is a 100 pf capacitor discharged through a 1.5 k w resistor into each pin. note 6: see an450 asurface mounting methods and their effect on product reliabilityo or the section titled asurface mounto found in any post 1986 national sem i- conductor linear data book for other methods of soldering surface mount devices. adc12130/adc12132/adc12138 www.national.com 10
ac electrical characteristics (continued) note 7: two on-chip diodes are tied to each analog input through a series resistor as shown below. input voltage magnitude up to 5v above v a + or 5v below gnd will not damage this device. however, errors in the a/d conversion can occur (if these diodes are forward biased by more than 50 mv) if the input voltage m agnitude of selected or unselected analog input go above v a + or below gnd by more than 50 mv. as an example, if v a + is 4.5 v dc , full-scale input voltage must be 4.55 v dc to ensure accurate conversions. note 8: to guarantee accuracy, it is required that the v a + and v d + be connected together to the same power supply with separate bypass capacitors at each v + pin. note 9: with the test condition for v ref (v ref +?v ref ?) given as +4.096v, the 12-bit lsb is 1.0 mv. for v ref = 2.5v, the 12-bit lsb is 610 v. note 10: typicals are at t j =t a = 25c and represent most likely parametric norm. note 11: tested limits are guaranteed to national's aoql (average outgoing quality level). note 12: positive integral linearity error is defined as the deviation of the analog value, expressed in lsbs, from the straight line that passes through posit ive full-scale and zero. for negative integral linearity error, the straight line passes through negative full-scale and zero (see figure 2 and figure 3 ). note 13: zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in lsb. it is the average value of the code transitions be- tween ?1 to 0 and 0 to +1 (see figure 4 ). note 14: total unadjusted error includes offset, full-scale, linearity and multiplexer errors. note 15: the dc common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together. note 16: channel leakage current is measured after the channel selection. note 17: timing specifications are tested at the ttl logic levels, v ol = 0.4v for a falling edge and v ol = 2.4v for a rising edge. tri-state output voltage is forced to 1.4v. note 18: the adc12130 family's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration pro cess will re- sult in a maximum repeatability uncertainty of 0.2 lsb. note 19: if sclk and cclk are driven from the same clock source, then t a is 6, 10, 18 or 34 clock periods minimum and maximum. note 20: the a12-bit conversion of offseto and a12-bit conversion of full-scaleo modes are intended to test the functionality of the device. therefore, the ou tput data from these modes are not an indication of the accuracy of a conversion result. ds012079-4 ds012079-5 figure 1. transfer characteristic adc12130/adc12132/adc12138 www.national.com 11
ac electrical characteristics (continued) ds012079-6 figure 2. simplified error curve vs output code without auto-calibration or auto-zero cycles ds012079-7 figure 3. simplified error curve vs output code after auto-calibration cycle ds012079-8 figure 4. offset or zero error voltage adc12130/adc12132/adc12138 www.national.com 12
typical performance characteristics the following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. linearity error change vs clock frequency ds012079-53 linearity error change vs temperature ds012079-54 linearity error change vs reference voltage ds012079-55 linearity error change vs supply voltage ds012079-56 full-scale error change vs clock frequency ds012079-57 full-scale error change vs temperature ds012079-58 full-scale error change vs reference voltage ds012079-59 full-scale error change vs supply voltage ds012079-60 zero error change vs clock frequency ds012079-61 adc12130/adc12132/adc12138 www.national.com 13
typical performance characteristics the following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. (continued) zero error change vs temperature ds012079-62 zero error change vs reference voltage ds012079-63 zero error change vs supply voltage ds012079-64 analog supply current vs temperature ds012079-65 digital supply current vs clock frequency ds012079-66 digital supply current vs temperature ds012079-67 linearity error change vs temperature ds012079-68 full-scale error change vs temperature ds012079-69 full-scale error change vs supply voltage ds012079-70 zero error change vs temperature ds012079-71 zero error change vs supply voltage ds012079-72 analog supply current vs temperature ds012079-73 adc12130/adc12132/adc12138 www.national.com 14
typical performance characteristics the following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. (continued) typical dynamic performance characteristics the following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. digital supply current vs temperature ds012079-74 bipolar spectral response with 1 khz sine wave input ds012079-75 bipolar spectral response with 10 khz sine wave input ds012079-76 bipolar spectral response with 20 khz sine wave input ds012079-77 bipolar spectral response with 30 khz sine wave input ds012079-78 bipolar spectral response with 40 khz sine wave input ds012079-79 bipolar spectral response with 50 khz sine wave input ds012079-80 adc12130/adc12132/adc12138 www.national.com 15
typical dynamic performance characteristics the following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. (continued) bipolar spurious free dynamic range ds012079-81 unipolar signal-to-noise ratio vs input frequency ds012079-82 unipolar signal-to-noise + distortion ratio vs input frequency ds012079-83 unipolar signal-to-noise + distortion ratio vs input signal level ds012079-84 unipolar spectral response with 1 khz sine wave input ds012079-85 unipolar spectral response with 10 khz sine wave input ds012079-86 unipolar spectral response with 20 khz sine wave input ds012079-87 unipolar spectral response with 30 khz sine wave input ds012079-88 unipolar spectral response with 40 khz sine wave input ds012079-89 adc12130/adc12132/adc12138 www.national.com 16
typical dynamic performance characteristics the following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified. (continued) test circuits timing diagrams unipolar spectral response with 50 khz sine wave input ds012079-90 do atri-stateo (t 1h ,t 0h ) ds012079-13 do except atri-stateo ds012079-14 leakage current ds012079-15 do falling and rising edge ds012079-16 do atri-stateo falling and rising edge ds012079-17 adc12130/adc12132/adc12138 www.national.com 17
timing diagrams (continued) di data input timing ds012079-18 do data output timing using cs ds012079-19 do data output timing with cs continuously low ds012079-20 adc12130/adc12132/adc12138 www.national.com 18
timing diagrams (continued) adc12138 auto cal or auto zero ds012079-21 note: do output data is not valid during this cycle. adc12138 read data without starting a conversion using cs ds012079-22 adc12130/adc12132/adc12138 www.national.com 19
timing diagrams (continued) adc12138 read data without starting a conversion with cs continuously low ds012079-23 adc12138 conversion using cs with 16-bit digital output format ds012079-24 adc12130/adc12132/adc12138 www.national.com 20
timing diagrams (continued) adc12138 conversion with cs continuously low and 16-bit digital output format ds012079-25 adc12138 software power up/down using cs with 16-bit digital output format ds012079-26 adc12130/adc12132/adc12138 www.national.com 21
timing diagrams (continued) adc12138 software power up/down with cs continuously low and 16-bit digital output format ds012079-27 adc12138 hardware power up/down ds012079-28 note: hardware power up/down may occur at any time. if pd is high while a conversion is in progress that conversion will be corrupted and erroneous data will be stored in the output shift register. adc12130/adc12132/adc12138 www.national.com 22
timing diagrams (continued) adc12138 configuration modification e example of a status read ds012079-29 ds012079-30 figure 5. protecting the muxout1, muxout2, a/din1 and a/din2 analog pins adc12130/adc12132/adc12138 www.national.com 23
timing diagrams (continued) ds012079-31 * tantalum * * monolithic ceramic or better figure 6. recommended power supply bypassing and grounding adc12130/adc12132/adc12138 www.national.com 24
tables table 1. data out formats do formats db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 with sign msb first 17xxxx sign msb 10 9 8 7 654321lsb bits 13 sign msb 10 9 8 76543 2 1lsb bits lsb first 17lsb123 4 5678910msb sign xxxx bits 13lsb123 4 5678910msb sign bits without sign msb first 160000msb109876 54321lsb bits 12msb1098 7 65432 1lsb bits lsb first 16lsb123 4 5678910msb 0000 bits 12lsb123 4 5678910msb bits x = high or low state. table 2. adc12138 multiplexer addressing analog channel addressed a/d input multiplexer mode mux and assignment polarity output address with a/din1 tied to muxout1 assignment channel and a/din2 tied to muxout2 assignment di0 di1 di2 di3 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com a/din1 a/din2 muxout1 muxout2 llll+ ? + ? ch0 ch1 l l l h + ? + ? ch2 ch3 l l h l + ? + ? ch4 ch5 l l h h + ? + ? ch6 ch7 differential l h l l ? + ? + ch0 ch1 lhlh ? + ? + ch2 ch3 l h h l ? + ? + ch4 ch5 l h h h ? + ? + ch6 ch7 h l l l + ? + ? ch0 com h l l h + ? + ? ch2 com hlhl + ? + ? ch4 com h l h h + ? + ? ch6 com single-ended h h l l + ? + ? ch1 com h h l h + ? + ? ch3 com h h h l + ? + ? ch5 com hhhh + ? + ? ch7 com adc12130/adc12132/adc12138 www.national.com 25
tables (continued) table 3. adc12130 and adc12132 multiplexer addressing analog channel addressed a/d input multiplexer mode mux and assignment polarity output address with a/din1 tied to muxout1 assignment channel and a/din2 tied to muxout2 assignment di0 di1 ch0 ch1 com a/din1 a/din2 muxout1 muxout2 l l + ? + ? ch0 ch1 differential l h ? + ? + ch0 ch1 h l + ? + ? ch0 com single-ended h h + ? + ? ch1 com note: adc12130 do not have a/din1, a/din2, muxout1 and muxout2 pins. table 4. mode programming adc12138 di0 di1 di2 di3 di4 di5 di6 di7 mode selected (current) do format (next conversion cycle) adc12130 and di0 di1 di2 di3 di4 di5 adc12132 see table 2 or table 3 llll 12bit conversion 12 or 13 bit msb first see table 2 or table 3 l l l h 12 bit conversion 16 or 17 bit msb first see table 2 or table 3 l h l l 12 bit conversion 12 or 13 bit lsb first see table 2 or table 3 lhlh 12bit conversion 16 or 17 bit lsb first l l l l h l l l auto cal no change l l l l h l l h auto zero no change llllhlhl power up no change llllhlhh power down no change llllhhll read status register no change llllhhlh data out without sign no change h l l l h h l h data out with sign no change llllhhhl acquisition time e 6 cclk cycles no change l h l l h h h l acquisition time e 10 cclk cycles no change h l l l h h h l acquisition time e 18 cclk cycles no change h h l l h h h l acquisition time e 34 cclk cycles no change llll hhhh user mode no change hxxxhhhh test mode no change (ch1ch7 become active outputs) note: the a/d powers up with no auto cal, no auto zero, 10 cclk acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit msb first, and user mode. x = don't care table 5. conversion/read data only mode programming cs conv pd mode lll see table 4 for mode l h l read only (previous do format). no conversion. h x l idle x x h power down x = don't care adc12130/adc12132/adc12138 www.national.com 26
tables (continued) table 6. status register status bit db0 db1 db2 db3 db4 db5 db6 db7 db8 location status bit pu pd cal 12 or 13 16 or 17 sign justification test mode device status do output format status function ahigho indicates a power up sequence is in progress ahigho indicates a power down sequence is in progress ahigho indicates an auto-cal sequence is in progress not used ahigho indicates a12or 13 bit format ahigho indicates a16or 17 bit format ahigho indicates that the sign bit is included. when alowo the sign bit is not included. when ahigho the conversion result will be output msb first. when alowo the result will be output lsb first. when ahigho the device is in test mode. when alowo the device is in user mode. application hints 1.0 digital interface 1.1 interface concepts the example in figure 7 shows a typical sequence of events after the power is applied to the adc12130/2/8: the first instruction input to the a/d via di initiates auto cal. the data output on do at that time is meaningless and is completely random. to determine whether the auto cal has been completed, a read status instruction is issued to the a/d. again the data output at that time has no significance since the auto cal procedure modifies the data in the output shift register. to retrieve the status information, an additional read status instruction is issued to the a/d. at this time the status data is available on do. if the cal signal in the status word, is low auto cal has been completed. therefore, the next instruction issued can start a conversion. the data out- put at this time is again status information. to keep noise from corrupting the a/d conversion, status can not be read during a conversion. if cs is strobed and is brought low dur- ing a conversion, that conversion is prematurely ended. eoc can be used to determine the end of a conversion or the a/d controller can keep track in software of when it would be appropriate to comnmunicate to the a/d again. once it has been determined that the a/d has completed a conver- sion, another instruction can be transmitted to the a/d. the data from this conversion can be accessed when the next in- struction is issued to the a/d. note, when cs is low continuously it is important to transmit the exact number of sclk cycles, as shown in the timing diagrams. the data out format sets the number of sclk cycles required in the next i/o cycle. a 12-bit no sign format will require 12 sclks to be transmitted; a 12-bit plus sign format will require 13 sclks to be transmitted, etc. not do- ing so will desynchronize the serial communication to the a/d. (see section 1.3.) 1.2 changing configuration the configuration of the adc12130/2/8 on power up defaults to 12-bit plus sign resolution, 12- or 13-bit msb first, 10 cclk acquisition time, user mode, no auto cal, no auto zero, and power up mode. changing the acquisition time and turning the sign bit on and off requires an 8-bit instruc- tion to be issued to the adc. this instruction will not start a conversion. the instructions that select a multiplexer ad- dress and format the output data do start a conversion. fig- ure 8 describes an example of changing the configuration of the adc12130/2/8. during i/o sequence 1, the instruction on di configures the adc12130/2/8 to do a conversion with 12-bit +sign resolu- tion. notice that when the 6 cclk acquisition and data out without sign instructions are issued to the adc, i/o se- quences 2 and 3, a new conversion is not started. the data output during these instructions is from conversion n which was started during i/o sequence 1. the configuration modi- fication timing diagram describes in detail the sequence of events necessary for a data out without sign, data out with sign, or 6/10/18/34 cclk acquisition time mode selection. table 4 describes the actual data necessary to be input to the adc to accomplish this configuration modification. the next instruction, shown in figure 8 , issued to the a/d starts conversion n+1 with 16-bit format with 12 bits of resolution formatted msb first. again the data output during this i/o cycle is the data from conversion n. the number of sclks applied to the a/d during any conver- sion i/o sequence should vary in accord with the data out word format chosen during the previous conversion i/o se- quence. the various formats and resolutions available are shown in table 1 .in figure 8 , since 16-bit without sign msb first format was chosen during i/o sequence 4, the number of sclks required during i/o sequence 5 is 16. in the follow- ing i/o sequence the format changes to 12-bit without sign msb first; therefore the number of sclks required during i/o sequence 6 changes accordingly to 12. ds012079-32 figure 7. typical power supply power up sequence adc12130/adc12132/adc12138 www.national.com 27
application hints (continued) 1.3 cs low continuously considerations when cs is continuously low, it is important to transmit the exact number of sclk pulses that the adc expects. not do- ing so will desynchronize the serial communications to the adc. when the supply power is first applied to the adc, it will expect to see 13 sclk pulses for each i/o transmission. the number of sclk pulses that the adc expects to see is the same as the digital output word length. the digital output word length is controlled by the data out (do) format. the do format maybe changed any time a conversion is started or when the sign bit is turned on or off. the table below de- tails out the number of clock periods required for different do formats: number of do format sclks expected 12-bit msb or lsb first sign off 12 sign on 13 16-bit msb or lsb first sign off 16 sign on 17 if erroneous sclk pulses desynchronize the communica- tions, the simplest way to recover is by cycling the power supply to the device. not being able to easily resynchronize the device is a shortcoming of leaving cs low continuously. the number of clock pulses required for an i/o exchange may be different for the case when cs is left low continu- ously vs the case when cs is cycled. take the i/o sequence detailed in figure 7 (typical power supply sequence) as an example. the table below lists the number of sclk pulses required for each instruction: instruction cs low cs strobed continuously auto cal 13 sclks 8 sclks read status 13 sclks 8 sclks read status 13 sclks 8 sclks 12-bit + sign conv 1 13 sclks 8 sclks 12-bit + sign conv 2 13 sclks 13 sclks 1.4 analog input channel selection the data input on di also selects the channel configuration for a particular a/d conversion (see table 2 , table 3 and table 4 ). in figure 8 the only times when the channel con- figuration could be modified would be during i/o sequences 1, 4, 5 and 6. input channels are reselected before the start of each new conversion. shown below is the data bit stream required on di, during i/o sequence number 4 in figure 8 ,to set ch1 as the positive input and ch0 as the negative input for the different versions of adcs: part number di data di0 di1 di2 di3 di4 di5 di6 di7 adc12130 lhllhlxx and adc12132 adc12138 lhllllhl where x can be a logic high (h) or low (l). 1.5 power up/down the adc may be powered down at any time by taking the pd pin high or by the instruction input on di (see table 4 and table 5 , and the power up/down timing diagrams). when the adc is powered down in this way, the circuitry necessary for an a/d conversion is deactivated. the circuitry necessary for digital i/o is kept active. hardware power up/ down is controlled by the state of the pd pin. software power-up/down is controlled by the instruction issued to the adc. if a software power up instruction is issued to the adc while a hardware power down is in effect (pd pin high) the device will remain in the power-down state. if a software power down instruction is issued to the adc while a hard- ware power up is in effect (pd pin low), the device will power down. when the device is powered down by software, it may be powered up by either issuing a software power up instruc- tion or by taking pd pin high and then low. if the power down command is issued during an a/d conversion, that conver- sion is disrupted. therefore, the data output after power up cannot be relied upon. 1.6 user mode and test mode an instruction may be issued to the adc to put it into test mode. test mode is used by the manufacturer to verify com- plete functionality of the device. during test mode ch0ch7 become active outputs. if the device is inadvertently put into the test mode with cs continuously low, the serial communi- cations may be desynchronized. synchronization may be re- gained by cycling the power supply voltage to the device. cycling the power supply voltage will also set the device into user mode. if cs is used in the serial interface, the adc may ds012079-33 figure 8. changing the adc's conversion configuration adc12130/adc12132/adc12138 www.national.com 28
application hints (continued) be queried to see what mode it is in. this is done by issuing a aread status registero instruction to the adc. when bit 9 of the status register is high, the adc is in test mode; when bit 9 is low the adc, is in user mode. as an alternative to cy- cling the power supply, an instruction sequence may be used to return the device to user mode. this instruction sequence must be issued to the adc using cs. the following table lists the instructions required to return the device to user mode: instruction di data di0 di1 di2 di3 di4 di5 di6 di7 test mode h x x x hhhh reset test mode instructions llllhhhl llllhlhl llllhlhh user mode llll hhhh power up llllhlhl set do with h or without or l l l h h l h sign l set h h acquisition or or l l h h h l time l l start hhhh hhh a orororor l ororor conversion llll lll x = don't care after returning to user mode with the user mode instruction the power up, data with or without sign, and acquisition time instructions need to be resent to ensure that the adc is in the required state before a conversion is started. 1.7 reading the data without starting a conversion the data from a particular conversion may be accessed without starting a new conversion by ensuring that the conv line is taken high during the i/o sequence. see the read data timing diagrams. table 5 describes the operation of the conv pin. 2.0 description of the analog multiplexer for the adc12138, the analog input multiplexer can be con- figured with 4 differential channels or 8 single ended chan- nels with the com input as the zero reference or any combi- nation thereof (see figure 9 ). the difference between the voltages on the v ref + and v ref ? pins determines the input voltage span (v ref ). the analog input voltage range is 0 to v a + . negative digital output codes result when v in ? > v in + . the actual voltage at v in ? or v in + cannot go below agnd. ch0, ch2, ch4, and ch6 can be assigned to the mux- out1 pin in the differential configuration, while ch1, ch3, ch5, and ch7 can be assigned to the muxout2 pin. in the differential configuration, the analog inputs are paired as fol- lows: ch0 with ch1, ch2 with ch3, ch4 with ch5 and ch6 with ch7. the a/din1 and a/din2 pins can be assigned positive or negative polarity. with the single-ended multiplexer configuration ch0 through ch7 can be assigned to the muxout1 pin. the com pin is always assigned to the muxout2 pin. a/din1 is assigned as the positve input; a/din2 is assigned as the negative in- put. (see figure 10 ). ds012079-34 ds012079-35 figure 9. differential configuration ds012079-36 a/din1 and a/din2 can be assigned as the + or ? input single-ended configuration ds012079-37 a/din1 is + input a/din2 is ? input figure 10. adc12130/adc12132/adc12138 www.national.com 29
application hints (continued) the multiplexer assignment tables for the adc12130/2/8 ( table 2 and table 3 ) summarize the aforementioned func- tions for the different versions of a/ds. 2.1 biasing for various multiplexer configurations figure 11 is an example of biasing the device for single-ended operation. the sign bit is always low. the digi- tal output range is 0 0000 0000 0000 to 0 1111 1111 1111. one lsb is equal to 1 mv (4.1v/4096 lsbs). for pseudo-differential signed operation, the biasing circuit shown in figure 12 shows a signal ac coupled to the adc. this gives a digital output range of ?4096 to +4095. with a 2.5v reference, as shown, 1 lsb is equal to 610 v. al- though, the adc is not production tested with a 2.5v refer- ence, when v a + and v d + are +5.0v linearity error typically will not change more than 0.1 lsb (see the curves in the typical electrical characteristics section). with the adc set to an acquisition time of 10 clock periods, the input biasing resistor needs to be 600 w or less. notice though that the in- put coupling capacitor needs to be made fairly large to bring down the high pass corner. increasing the acquisition time to 34 clock periods (with a 5 mhz cclk frequency) would al- low the 600 w to increase to 6k, which with a 1 f coupling capacitor would set the high pass corner at 26 hz. increas- ing r, to 6k would allow r 2 to be 2k. ds012079-38 figure 11. single-ended biasing adc12130/adc12132/adc12138 www.national.com 30
application hints (continued) an alternative method for biasing pseudo-differential opera- tion is to use the +2.5v from the lm4040 to bias any ampli- fier circuits driving the adc as shown in figure 13 . the value of the resistor pull-up biasing the lm4040-2.5 will depend upon the current required by the op amp biasing circuitry. in the circuit of figure 13 some voltage range is lost since the amplifier will not be able to swing to +5v and gnd with a single +5v supply. using an adjustable version of the lm4041 to set the full scale voltage at exactly 2.048v and a lower grade lm4040d-2.5 to bias up everything to 2.5v as shown in figure 14 will allow the use of all the adc's digital output range of ?4096 to +4095 while leaving plenty of head room for the amplifier. fully differential operation is shown in figure 15 . one lsb for this case is equal to (4.1v/4096) = 1 mv. ds012079-39 figure 12. pseudo-differential biasing with the signal source ac coupled directly into the adc ds012079-40 figure 13. alternative pseudo-differential biasing adc12130/adc12132/adc12138 www.national.com 31
application hints (continued) 3.0 reference voltage the difference in the voltages applied to the v ref + and v ref ? defines the analog input span (the difference between the voltage applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground), over which 4095 positive and 4096 negative codes exist. the voltage sources driving v ref + or v ref ? must have very low output impedance and noise. the circuit in figure 16 is an example of a very stable reference appropriate for use with the device. ds012079-41 figure 14. pseudo-differential biasing without the loss of digital output range ds012079-42 figure 15. fully differential biasing adc12130/adc12132/adc12138 www.national.com 32
application hints (continued) the adc12130/2/8 can be used in either ratiometric or abso- lute reference applications. in ratiometric systems, the ana- log input voltage is proportional to the voltage used for the adc's reference voltage. when this voltage is the system power supply, the v ref + pin is connected to v a + and v ref ? is connected to ground. this technique relaxes the system reference stability requirements because the analog input voltage and the adc reference voltage move together. this maintains the same output code for given input conditions. for absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and temperature stable voltage source can be connected to the reference in- puts. typically, the reference voltage's magnitude will require an initial adjustment to null reference voltage induced full-scale errors. below are recommended references along with some key specifications. output temperature part number voltage coefficient tolerance lm4041ci-adj 0.5% 100ppm/c lm4040ai-4.1 0.1% 100ppm/c circuit of figure 16 adjustable 2ppm/c the reference voltage inputs are not fully differential. the adc12130/2/8 will not generate correct conversions or com- parisons if v ref + is taken below v ref ? . correct conversions result when v ref + and v ref ? differ by 1v and remain, at all times, between ground and v a + . the v ref common mode range, (v ref + +v ref ? )/2 is restricted to (0.1 x v a + ) to (0.6 x v a + ). therefore, with v a + = 5v the center of the reference ladder should not go below 0.5v or above 3.0v. figure 17 is a graphic representation of the voltage restrictions on v ref + and v ref ? . 4.0 analog input voltage range the adc12130/2/8's fully differential adc generate a two's complement output that is found by using the equation shown below: for (12-bit) resolution the output code = round off to the nearest integer value between ?4096 to 4095 if the result of the above equation is not a whole num- ber. examples are shown in the table below: digital v ref + v ref ? v in + v in ? output code +2.5v +1v +1.5v 0v 0,1111,1111,1111 +4.096v 0v +3v 0v 0,1011,1011,1000 +4.096v 0v +2.499v +2.500v 1,1111,1111,1111 +4.096v 0v 0v +4.096v 1,0000,0000,0000 5.0 input current at the start of the acquisition window (t a ) a charging current flows into or out of the analog input pins (a/din1 and a/din2) depending on the input voltage polarity. the analog input pins are ch0ch7 and com when a/din1 is tied to muxout1 and a/din2 is tied to muxout2. the peak value of this input current will depend on the actual input voltage applied, the source impedance and the internal multiplexer switch on resistance. with muxout1 tied to a/din1 and muxout2 tied to a/din2 the internal multiplexer switch on resistance is typically 1.6 k w . the a/din1 and a/din2 mux on resistance is typically 750 w . 6.0 input source resistance for low impedance voltage sources ( < 600 w ), the input charging current will decay, before the end of the s/h's ac- quisition time of 2 s (10 cclk periods with f ck = 5 mhz), to a value that will not introduce any conversion errors. for high source impedances, the s/h's acquisition time can be in- ds012079-43 * tantalum figure 16. low drift extremely stable reference circuit ds012079-44 figure 17. v ref operating range adc12130/adc12132/adc12138 www.national.com 33
application hints (continued) creased to 18 or 34 cclk periods. for less adc accuracy and/or slower cclk frequencies the s/h's acquisition time may be decreased to 6 cclk periods. to determine the number of clock periods (n c ) required for the acquisition time with a specific source impedance for the various resolutions the following equations can be used: 12 bit + sign n c =[ r s + 2.3] x f ck x 0.824 where f ck is the conversion clock (cclk) frequency in mhz and r s is the external source resistance in k w .asanex- ample, operating with a resolution of 12 bits+sign, a 5 mhz clock frequency and maximum acquistion time of 34 conver- sion clock periods the adc's analog inputs can handle a source impedance as high as 6 k w . the acquisition time may also be extended to compensate for the settling or response time of external circuitry connected between the muxout and a/din pins. the acquisition time t a is started by a falling edge of sclk and ended by a rising edge of cclk (see timing diagrams). if sclk and cclk are asynchronous one extra cclk clock period may be inserted into the programmed acquisition time for synchronization. therefore with asnychronous sclk and cclks the acquisition time will change from conversion to conversion. 7.0 input bypass capacitance external capacitors (0.01 f0.1 f) can be connected be- tween the analog input pins, ch0ch7, and analog ground to filter any noise caused by inductive pickup associated with long input leads. these capacitors will not degrade the con- version accuracy. 8.0 noise the leads to each of the analog multiplexer input pins should be kept as short as possible. this will minimize input noise and clock frequency coupling that can cause conversion er- rors. input filtering can be used to reduce the effects of the noise sources. 9.0 power supplies noise spikes on the v a + and v d + supply lines can cause conversion errors; the comparator will respond to the noise. the adc is especially sensitive to any power supply spikes that occur during the auto-zero or linearity correction. the minimum power supply bypassing capacitors recommended are low inductance tantalum capacitors of 10 f or greater paralleled with 0.1 f monolithic ceramic capacitors. more or different bypassing may be necessary depending on the overall system requirements. separate bypass capacitors should be used for the v a + and v d + supplies and placed as close as possible to these pins. 10.0 grounding the adc12130/2/8's performance can be maximized through proper grounding techniques. these include the use of separate analog and digital ground planes. the digital ground plane is placed under all components that handle digital signals, while the analog ground plane is placed under all components that handle analog signals. the digital and analog ground planes are connected together at only one point, either the power supply ground or at the pins of the adc. this greatly reduces the occurence of ground loops and noise. shown in figure 18 is the ideal ground plane layout for the adc12138 along with ideal placement of the bypass capaci- tors. the circuit board layout shown in figure 18 uses three bypass capacitors: 0.01 f (c1) and 0.1 f (c2) surface mount capacitors and 10 f (c3) tantalum capacitor. ds012079-45 figure 18. ideal ground plane adc12130/adc12132/adc12138 www.national.com 34
application hints (continued) 11.0 clock signal line isolation the adc12130/2/8's performance is optimized by routing the analog input/output and reference signal conductors as far as possible from the conductors that carry the clock sig- nals to the cclk and sclk pins. ground traces parallel to the clock signal traces can be used on printed circuit boards to reduce clock signal interference on the analog input/ output pins. 12.0 the calibration cycle a calibration cycle needs to be started after the power sup- plies, reference, and clock have been given enough time to stabilize after initial turn-on. during the calibration cycle, cor- rection values are determined for the offset voltage of the sampled data comparator and any linearity and gain errors. these values are stored in internal ram and used during an analog-to-digital conversion to bring the overall full-scale, offset, and linearity errors down to the specified limits. full-scale error typically changes 0.4 lsb over tempera- ture and linearity error changes even less; therefore it should be necessary to go through the calibration cycle only once after power up if the power supply voltage and the ambient temperature do not change significantly (see the curves in the typical performance characteristics). 13.0 the auto-zero cycle to correct for any change in the zero (offset) error of the a/d, the auto-zero cycle can be used. it may be necessary to do an auto-zero cycle whenever the ambient temperature or the power supply voltage change significantly. (see the curves titled azero error change vs ambient temperatureo and azero error change vs supply voltageo in the typical perfor- mance characteristics.) 14.0 dynamic performance many applications require the a/d converter to digitize ac signals, but the standard dc integral and differential nonlin- earity specifications will not accurately predict the a/d con- verter's performance with ac input signals. the important specifications for ac applications reflect the converter's abil- ity to digitize ac signals without significant spectral errors and without adding noise to the digitized signal. dynamic characteristics such as signal-to-noise (s/n), signal-to-noise + distortion ratio (s/(n + d)), effective bits, full power band- width, aperture time and aperture jitter are quantitative mea- sures of the a/d converter's capability. an a/d converter's ac performance can be measured using fast fourier transform (fft) methods. a sinusoidal wave- form is applied to the a/d converter's input, and the trans- form is then performed on the digitized waveform. s/(n + d) and s/n are calculated from the resulting fft data, and a spectral plot may also be obtained. typical values for s/n are shown in the table of electrical characteristics, and spectral plots of s/(n + d) are included in the typical perfor- mance curves. the a/d converter's noise and distortion levels will change with the frequency of the input signal, with more distortion and noise occurring at higher signal frequencies. this can be seen in the s/(n + d) versus frequency curves. these curves will also give an indication of the full power bandwidth (the frequency at which the s/(n + d) or s/n drops 3 db). effective number of bits can also be useful in describing the a/d's noise performance. an ideal a/d converter will have some amount of quantization noise, determined by its reso- lution, which will yield an optimum s/n ratio given by the fol- lowing equation: s/n = (6.0 2xn+ 1.76) db where n is the a/d's resolution in bits. the effective bits of a real a/d converter, therefore, can be found by: as an example, this device with a differential signed 5v, 10 khz sine wave input signal will typically have a s/n of 78 db, which is equivalent to 12.6 effective bits. 15.0 an rs232 serial interface shown on the following page is a schematic for an rs232 in- terface to any ibm and compatible pcs. the dtr, rts, and cts rs232 signal lines are buffered via level translators and connected to the adc12138's di, sclk, and do pins, respectively. the d flip/flop is used to generate the cs signal. adc12130/adc12132/adc12138 www.national.com 35
application hints (continued) the assignment of the rs232 port is shown below b7 b6 b5 b4 b3 b2 b1 b0 com1 input address 3fe x x x cts x x x x output address 3fc x x x 0 x x rts dtr a sample program, written in microsoft quickbasic, is shown on the next page. the program prompts for data mode select instruction to be sent to the a/d. this can be found from the mode programming table shown earlier. the data should be entered in a1os and a0os as shown in the table with di0 first. next the program prompts for the number of sclks required for the programmed mode select instruction. for instance, to send all a0os to the a/d, selects ch0 as the +input, ch1 as the ?input, 12-bit conversion, and 13-bit msb first data out- put format (if the sign bit was not turned off by a previous in- struction). this would require 13 sclk periods since the out- put data format is 13 bits. the part powers up with no auto cal, no auto zero, 10 cclk acquisition time, 12-bit conver- sion, data out with sign, power up, 12- or 13-bit msb first, and user mode. auto cal, auto zero, power up and power down instructions do not change these default settings. since there is no cs signal to synchronize the serial inter- face the following power up sequence should be followed: 1. run the program 2. prior to responding to the prompt apply the power to the adc12138 3. respond to the program prompts it is recommended that the first instruction issued to the adc12138 be auto cal (see section 1.1). code listing: 'variables dol=data out word length, di=data string for a/d di input, ' do=a/d result string 'set cs# high out <&>h3fc, (<&>h2 or inp (<&>h3fc) 'set rts high out <&>h3fc, (<&>hfe and inp(<&>h3fc) 'set dtr low out <&>h3fc, (<&>hfd and inp (<&>h3fc) 'set rts low out <&>h3fc, (<&>hef and inp(<&>h3fc)) 'set b4 low 10 line input <&ldquo>di data for adc12138 (see mode table on data sheet)<&rdquo>; di$ input <&ldquo>adc12138 output word length (12,13,16 or 17)<&rdquo>; dol 20 'set cs# high out <&>h3fc, (<&>h2 or inp (<&>h3fc) 'set rts high out <&>h3fc, (<&>hfe and inp(<&>h3fc) 'set dtr low out <&>h3fc, (<&>hfd and inp (<&>h3fc) 'set rts low ds012079-46 note: v a + ,v d + , and v ref + on the adc12138 each have 0.01 f and 0.1 f chip caps, and 10 f tantalum caps. all logic devices are bypassed with 0.1 f caps. adc12130/adc12132/adc12138 www.national.com 36
application hints (continued) 'set cs# low out <&>h3fc, (<&>h2 or inp (<&>h3fc) 'set rts high out <&>h3fc, (<&>h1 or inp(<&>h3fc) 'set dtr high out <&>h3fc, (<&>hfd and inp (<&>h3fc) 'set rts low do$=<&ldquo> <&rdquo> 'reset do variable out <&>h3fc, (<&>h1 or inp(<&>h3fc) 'set dtr high out <&>h3fc, (<&>hfd and inp(<&>h3fc)) 'sclk low for n = 1 to 8 temp$ = mid$(di$, n, 1) if temp$=<&ldquo>0<&rdquo> then out <&>h3fc, (<&>h1 or inp(<&>h3fc)) else out <&>h3fc, (<&>hfe and inp(<&>h3fc)) end if 'out di out <&>h3fc, (<&>h2 or inp(<&>h3fc)) 'sclk high if (inp(<&>h3fe) and 16) = 16 then do$ = do$ + <&ldquo>0<&rdquo> else do$ = do$ + <&ldquo>1<&rdquo> end if 'input do out <&>h3fc, (<&>h1 or inp(<&>h3fc) 'set dtr high out <&>h3fc, (<&>hfd and inp(<&>h3fc)) 'sclk low next n if dol > 8 then for n=9 to dol out <&>h3fc, (<&>h1 or inp(<&>h3fc) 'set dtr high out <&>h3fc, (<&>hfd and inp(<&>h3fc)) 'sclk low out <&>h3fc, (<&>h2 or inp(<&>h3fc)) 'sclk high if (inp(<&>h3fe) and <&>h1o) = <&>h1o then do$ = do$ + <&ldquo>0<&rdquo> else do$ = do$ + <&ldquo>1<&rdquo> end if next n end if out <&>h3fc, (<&>hfa and inp(<&>h3fc)) 'sclk low and di high for n = 1 to 500 next n print do$ input <&ldquo>enter <&ldquo>c<&rdquo> to convert else <&ldquo>return<&rdquo> to alter di data<&rdquo>; s$ if s$ = <&ldquo>c<&rdquo> or s$ = <&ldquo>c<&rdquo> then goto 20 else goto 10 end if end adc12130/adc12132/adc12138 www.national.com 37
physical dimensions inches (millimeters) unless otherwise noted order number adc12130ciwm ns package number m16b order number adc12138ciwm ns package number m28b adc12130/adc12132/adc12138 www.national.com 38
physical dimensions inches (millimeters) unless otherwise noted (continued) order number adc12132cimsa ns package number msa20 order number adc12138cimsa ns package number msa28 adc12130/adc12132/adc12138 www.national.com 39
physical dimensions inches (millimeters) unless otherwise noted (continued) order number adc12130cin ns package number n16e order number adc12138cin ns package number n28b adc12130/adc12132/adc12138 www.national.com 40
notes life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. national semiconductor corporation americas tel: 1-800-272-9959 fax: 1-800-737-7018 email: support@nsc.com national semiconductor europe fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer response group tel: 65-2544466 fax: 65-2504466 email: ap.support@nsc.com national semiconductor japan ltd. tel: 81-3-5639-7560 fax: 81-3-5639-7507 www.national.com adc12130/adc12132/adc12138 self-calibrating 12-bit plus sign serial i/o a/d converters with mux and sample/hold national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the righ t at any time without notice to change said circuitry and specifications.

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