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A45L9332A series preliminary 256k x 32 bit x 2 banks synchronous graphic ram preliminary (october, 2001, version 0.1) amic technology, inc. document title 256k x 32bit x 2 banks synchronous graphic ram revision history rev. no. history issue date remark 0.0 initial issue august 21, 2001 preliminary 0.1 update ac and dc data specification october 22, 2001
A45L9332A series preliminary 256k x 32 bit x 2 banks synchronous graphic ram preliminary (october, 2001, version 0.1) 1 amic technology, inc. features n jedec standard 3.3v power supply n lvttl compatible with multiplexed address n dual banks / pulse ras n mrs cycle with address key programs - cas latency (2,3) - burst length (1,2,4,8 & full page) - burst type (sequential & interleave) n all inputs are sampl ed at the positive going edge of the system clock n burst read single - bit write operation n dqm 0 - 3 for byte masking n auto & self refresh n 32ms refresh period (2k cycle) n 100 pin qfp, lqfp (14 x 20 mm) graphics features n smrs cycle - load mask register - loa d color register n write per bit (old mask) n block write (8 columns) general description the A45L9332A is 16,777,216 bits synchronous high data rate dynamic ram organized as 2 x 262,144 words by 32 bits, fabricated with amic?s high performance cmos techn ology. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandw idth, high performance memory system applications. write per bit and 8 columns block write improves performance in graphics system.
A45L9332A series preliminary (october, 2001, version 0.1) 2 amic technology, inc. pin configuration vddq dq 20 dq 21 dq 22 dq 23 dqm 0 ba(a10) a8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 30 27 29 80 79 78 77 76 75 74 72 73 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vddq vssq dq 25 dq 24 vddq dq 15 dq 14 vssq vddq vss vdd dq 11 dq 10 vssq dq 9 dq 8 vddq nc dqm 3 cke dsf nc a9 50 49 48 47 46 45 44 43 42 40 41 39 38 37 36 35 34 33 32 31 a7 a6 a5 a4 vss vdd a3 a1 a0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 vssq dq 2 vssq A45L9332Ae A45L9332Af vddq nc vss vssq vddq vssq vdd vss vssq vddq dqm 2 we cas ras cs dq 1 dq 0 vdd nc nc nc nc nc nc nc nc nc dq 31 dq 30 dq 29 a2 nc nc nc nc nc nc nc nc nc nc dq 13 dq 12 dqm 1 clk dq 27 dq 26 dq 28 dq 3 dq 4 dq 5 dq 6 dq 7 dq 16 dq 17 dq 18 dq 19
A45L9332A series preliminary (october, 2001, version 0.1) 3 amic technology, inc. block diagram (i=0~31) block write control logic mask write control logic mux mask register clock register input buffer timming register column mask dqmi input buffer programing register latency & burst length column decorder sense amplifier 256k x 32 cell array 256k x 32 cell array dqi dqmi row decorder bank selection serial counter column address buffer row address buffer refresh counter address register clock address (a0~a10) clk cke cs ras cas we dsf dqmi
A45L9332A series preliminary (october, 2001, version 0.1) 4 amic technology, inc. pin descriptions symbol name description clk system clock active on the positi ve going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqmi cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one clock + t ss prior to new command. disable input buffers for power down in standby. a0~a9 address row / column addresses are multiplexed on the same pins. row address : ra0~ra9, column address: ca0~ca7 a10(ba) bank select address selects bank to be activated during row address latch time. selects band for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. dqmi data input/output mask makes data output hi - z, t shz after the clock and masks the output. blocks data input when dqm active. (byte masking) dqi data input/output data inputs/outputs are multiplexed on the same pin s. dsf define special function enables write per bit, block write and special mode register set. vdd/vss power supply/ground power supply: +3.3v 0.3v/ground vddq/vs sq data output power/ground provide isolated power/ground to dqs for improved noise immun ity. nc no connection
A45L9332A series preliminary (october, 2001, version 0.1) 5 amic technology, inc. absolute maximum ratings* voltage on any pin relative to vss (vin, vout ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1.0v to +4.6v voltage on vdd supply relative to vss (vdd, vddq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1.0v to +4.6v storage temperature (t stg ) . . . . . . . . . - 55 c to +150 c soldering temperature x time (t sloder ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 c x 10sec power dissipation (p d ) . . . . . . . . . . . . . . . . . . . . . . . . 1w short circuit current (ios) . . . . . . . . . . . . . . . . . . . 50ma *comments permanent device damage may occur if ?absolute maximum ratin gs? are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. capacitance (t a =25 c, f=1mhz) parameter symbol c ondition min typ max unit input capacitance ci1 a0 to a9, ba 2 4 pf ci2 clk, cke, cs , ras , cas , we , dqmi, dsf 2 4 pf data input/output capacitance ci/o dq0 to dq15 2 6 p f dc electrical characteristics recommend operating conditions (voltage referenced to vss = 0v) parameter symbol min typ max unit note supply voltage vdd,vddq 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 vdd+0.3 v input low voltage v il - 0.3 0 0.8 v note 1 output high voltage v oh 2.4 - - v i oh = - 2ma output low voltage v ol - - 0.4 v i ol = 2ma input leakage current i il - 5 - 5 m a note 2 output leakage current i ol - 5 - 5 m a note 3 output loading condition see figure 1 note: 1. v il (min) = - 1.5v ac (pulse width 5ns). 2. any input 0v vin vdd + 0.3v, all other pins are not under test = 0v 3. dout is disabled, 0v vout vdd decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between vdd and vss c dc1 0.1 + 0.01 m f decoupling capacitance between vddq and vssq c dc2 0.1 + 0.01 m f note: 1. vdd and vddq pins are separated each other. all vdd pins are connected in chip. all vddq pins are connected in chip. 2. vss and vssq pins are separated each other all vss pins are connected in chip. all vssq pins are connected in chip.
A45L9332A series preliminary (october, 2001, version 0.1) 6 amic technology, inc. dc electrical characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c) speed symbol parameter test cond itions cas latency - 6 - 7 - 8 unit notes 3 230 210 170 i cc1 operating current (one bank active) burst length = 1 t rc 3 t rc (min), t cc 3 t cc (min ) , i ol = 0ma 2 - 260 160 ma 1 i cc2 p cke v il (max ), t cc = 15ns 4 i cc2 ps precharge standby current in power - down mode cke v il (max), ckl vil(max), t cc = 4 ma i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 35 i cc2 ns precharge standby current in non power - down mode cke 3 v ih (min), clk v il (max), t cc = input signals are stable. 15 ma i cc3 p cke v il (max), t cc = 15ns 6 i cc3 ps active standby current in power - down mode cke v il (max), cke v il (max) t cc = 6 ma i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 60 i cc3 ns active standby current in non power - down mode (one bank active) cke 3 v ih (min), clk v il (max), t cc = input signals are stable. 40 ma 3 310 280 250 i cc4 operating current (burst mod e) i ol = 0ma, page burst all bank activated, t ccd = t ccd (min) 2 - 230 210 ma 1 3 150 120 120 i cc5 refresh current t rc 3 t rc (min) 2 - 180 120 ma 2 i cc6 self refresh current cke 0.2v 4 ma i cc7 operating current (one bank blo ck write) t cc 3 t cc (min), i ol =0ma, t bwc (min) 240 220 190 ma note: 1. measured with outputs open. addresses are changed only one time during t cc (min). 2. refresh period is 32ms. addresses are changed only one time during t cc (min).
A45L9332A series preliminary (october, 2001, version 0.1) 7 amic technology, inc. ac operating test co nditions (vdd = 3.3v 0.3v, t a = 0 c to +70 c) parameter value ac input levels v ih /v il = 2.4v/0.4v input timing measurement reference level 1.4v input rise and all time (see note3) tr/tf = 1ns/1ns output timing measurement reference level 1.4v output load condition see fig.2 output 870 w 1200 w (fig. 1) dc output load circuit z o =50 w output 50 w v tt =1.4v 30pf (fig. 2) ac output load circuit 3.3v 3pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma ac characteristics (ac operating conditions unless otherwise noted) - 6 - 7 - 8 symbol parameter cas latency min max min max min max unit note 3 6 7 8 t cc clk cycle time 2 - 1000 8 1000 10 1000 ns 1 3 - 5.5 - 6 - 6.5 t sac clk to valid output delay 2 - - - 7.5 - 7 ns 1,2 t oh output data hold time 2.5 2.5 2.5 ns 2 3 2.5 2.5 3 t ch clk high pulse width 2 - - 3 - 3 - ns 3
A45L9332A series preliminary (october, 2001, version 0.1) 8 amic technology, inc. ac characteristics (continued) (ac operating condit ions unless otherwise noted) - 6 - 7 - 8 symbol parameter cas latency min max min max min max unit note 3 2.5 2.5 t cl clk low pulse width 2 - - 3 - 3 - ns 3 3 2 2 t ss input setup time 2 - - 2.5 - 2.5 - ns 3 3 t sh input hold time 2 1 - 1 - 1 - ns 3 3 t slz clk to output in low - z 2 1 - 1 - 1 - ns 2 3 - 5.5 - 6 - 6.5 t shz clk to output in hi - z 2 - - - 7.5 - 7 ns *all ac parameters are measured from half to half. note : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2 - 0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [ (tr + tf)/ 2 - 1 ] ns should be added to the parameter.
A45L9332A series preliminary (october, 2001, version 0.1) 9 amic technology, inc. operating ac parameter (ac operating conditions unless otherwise noted) version symbol parameter cas latency - 6 - 7 - 8 unit note 3 t rrd(min) row active to row active delay 2 2 2 2 clk 1 3 3 3 2 t rcd(min) ras to cas delay 2 - 2 2 clk 1 3 3 3 2 t rp(min) row precharge time 2 - 3 2 clk 1 3 8 7 6 t ras(min) 2 - 5 5 clk 1 3 t ras(max) row active time 2 100 m s 3 11 10 9 t rc(min) row cycle time 2 - 7 7 clk 1 3 t cdl(min) last data in new col. address delay 2 1 clk 2 3 2 2 2 t rdl(min) last data in row precharge 2 - 2 2 clk 2 3 t bdl(min) last data in to burst stop 2 1 clk 2 3 t ccd(min) col. address to col. address delay 2 1 clk 3 3 t bpl(min) block write data - in to pre command 2 2 clk 3 t bwc(min) block write cycle time 2 1 clk 1,3 3 2 clk 4 number of valid output data 2 1 clk note: 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. this parameter means minimum cas to cas delay at block write cycle onl y. 4. in case of row precharge interrupt, auto precharge and read burst stop.
A45L9332A series preliminary (october, 2001, version 0.1) 10 amic technology, inc. simplified truth table command cken - 1 cken cs ras cas we dsf dqm a10 a9 a8~a0 notes m ode register set l 1,2 register special mode register set h x l l l l h x op code 1,2,7 auto refresh h 3 entry h l l l l h l x x 3 l h h h 3 refresh self refresh exit l h h x x x x x x 3 write per bite disa ble l 4,5 bank active & row addr. write per bit enable h x l l h h h x v row addr. 4,5,9 auto precharge disable l 4 read & column addr. auto precharge enable h x l h l h l x v h column addr. 4,6 auto precharge disable l 4,5 write & column addr. auto precharge enable h x l h l l l x v h column addr. 4,5,6,9 auto precharge disable l 4,5 block write & column addr. auto precharge enable h x l h l l h x v h column addr. 4,5,6,9 burst stop h x l h h l l x x 7 bank selection v l precharge both banks h x l l h l l x x h x l h h h entry h l h x x x x x clock suspend or active power down exit l h x x x x x x x l h h h entry h l h x x x x x l v v v v precharge power down mode exit l h h x x x x x x dqm h x v x 8 l h h h no operation command h x h x x x x x x (v = valid, x = don?t care, h = logic high, l = logic low) note : 1. op code : operand code a0~a10 : program keys. (@mrs) color register exists only one per dqi which both banks share. so dose mask register. color or mask is loaded into chip through dq pin. 2. mrs can be issued only at both banks precharge state. smrs can be issued only if dq?s are idle. a new command can be issued at the next clock of mrs/smrs. 3. auto refr esh functions as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by ?auto?. auto/self refresh can be issued only at both precharge state.
A45L9332A series preliminary (october, 2001, version 0.1) 11 amic technology, inc. simplified truth table 4. a10 : bank select address. if ?low? at r ead, (block) write, row active and precharge, bank a is selected. if ?high? at read, (block) write, row active and precharge, bank b is selected. if a9 is ?high? at row precharge, a10 is ignored and both banks are selected. 5. it is determined at row activ e cycle. whether normal/block write operates in write per bit mode or not. for a bank write, at a bank row active, for b bank write, at b bank row active. terminology : write per bit = i/o mask (block) write with write per bit mode = masked (block ) write 6. during burst read or write with auto precharge, new read/ (block) write command cannot be issued. another bank read/(block) write command can be issued at t pr after the end of burst. 7. burst stop command is valid only t full page burst length. 8. dqm s ampled at positive going edge of a clk masks the data - in at the very clk (write dqm latency is 0), but makes the data - out hi - z state after 2 clk cycles. (read dqm latency is 2) 9. graphic features added to sdram?s original features. if dsf is tied to low, graphic functions are disabled and chip operates as a 16m sdram with 32 dq?s. sgram vs sdram function mrs bank active write dsf l h l h l h sgram function mrs smrs bank active with write per bit disable bank active with write per bit enable normal w rite block write if dsf is low, sgram functionality is identical to sdram functionality. sgram can be used as an unified memory by the appropriate dsf control ? sdram = graphic memory + main memory
A45L9332A series preliminary (october, 2001, version 0.1) 12 amic technology, inc. mode register filed table to program modes register pro grammed with mrs address a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function rfu w.b.l tm cas latency bt burst length (note 1) (note 2) test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 reserved 0 1 0 0 1 - 1 interleave 0 0 1 2 reserved 1 0 0 1 0 2 0 1 0 4 4 1 1 vendor use only 0 1 1 3 0 1 1 8 8 write burst length 1 0 0 reserved 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 256(full) reserved (note 3) special mode register programmed with smrs address a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function x lc lm x load color load mask a6 function a5 function 0 disable 0 disable 1 enable 1 enable (note 4) power up sequence 1. apply power and start clock, attempt to maintain cke = ?h?, dqm = ?h? and the other pins are nop condition at inputs. 2. maintain stable power, stable clock and no p input condition for a minimum of 200 m s. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto - refresh commands. 5. issue a mode register set command to initialize the mode register. cf.) sequence of 4 & 5 may be changed. the device is now ready for normal operation. note : 1. rfu(reserved for future use) should stay ?0? during mrs cycle. 2. if a9 is high during mrs cycle, ?burst read single bit write? function will be enabled. 3. the full column burst (256bit) is available only at seq uential mode of burst type. 4. if lc and lm both high (1), data of mask and color register will be unknown.
A45L9332A series preliminary (october, 2001, version 0.1) 13 amic technology, inc. burst sequence (burst length = 4) initial address a1 a0 sequential interleave 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 burst sequence (burst length = 8) initial address a2 a1 a0 sequential interleave 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 pixel to dq mapping (at block write) column address 3 byte 2 byte 1 byte 0 byte a2 a1 a0 i/o 3 1 ? i/o 24 i/o 23 ? i/o 16 i/o 15 ? i/o 8 i/o 7 ? i/o 0 0 0 0 dq24 dq16 dq8 dq0 0 0 1 dq25 dq17 dq9 dq1 0 1 0 dq26 dq18 dq10 dq2 0 1 1 dq27 dq19 dq11 dq3 1 0 0 dq28 dq20 dq12 dq4 1 0 1 dq29 dq21 dq13 dq5 1 1 0 dq30 dq22 dq14 dq6 1 1 1 dq31 dq23 dq15 dq7
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 14 amic technology, inc. device operations clock (clk) the clock input is used as the reference for all sgram operations. all operations are synchronized to the positive going edge of the clock. the clock transitions must be monotonic between vil and vih. during operation with c ke high all inputs are assumed to be in valid state (low or high) for the duration of set up and hold time around positive edge of the clock for proper functionality and icc specifications. clock enable (clk) the clock enable (cke) gates the clock onto sgr am. if cke goes low synchronously with clock (set - up and hold time same as other inputs), the internal clock is suspended form the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. all other inputs are ign ored from the next clock cycle after cke goes low. when both banks are in the idle state and cke goes low synchronously with clock, the sgram enters the power down mode form the next clock cycle. the sgram remains in the power down mode ignoring the other inputs as long as cke remains low. the power down exit is synchronous as the internal clock is suspended. when cke goes high at least ?t ss + 1 clock ? before the high going edge of the clock, then the sgram becomes active from the same clock edge accepting all the input commands. bank select (a10) this sgram is organized as two independent banks of 262,144 words x 32 bits memory arrays. the a10 inputs is latched at the time of assertion of ras and cas to select the bank to be used for the operation. when a10 is asserted low, bank a is selected. when a10 is asserted high, bank b is selected. the bank select a10 is latched at bank activate, read, write mode register set and precharge operations. address input (a0 ~ a9) the 18 address bits required to decode the 262,144 word locations are multiplexed into 10 address input pins (a0~a9). the 10 bit row address is latched along with ras and a10 during bank activate command. the 8 bit column address is latched along with cas , we and a10 during read or write command. nop and device deselect when ras , cas and we are high, the sgram performs no operation (nop). no p does not initiate any new operation, but is needed to complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. the device deselect is also a nop and is entered by asserting cs hi gh. cs high disables the command decoder so that ras , cas and we , dsf and all the address inputs are ignored. power - up the following sequence is recommended for power up 1. powe r must be applied to either cke and dqm inputs to pull them high and other pins are nop condition at the inputs before or along with vdd (and vddq) supply. the clock signal must also be asserted at the same time. 2. after vdd reaches the desired voltage, a mi nimum pause of 200 microseconds is required with inputs in nop condition. 3. both banks must be precharged now. 4. perform a minimum of 2 auto refresh cycles to stabilize the internal circuitry. 5. perform a mode register set cycle to program the cas latency, burst length and burst type as the default value of mode register is undefined. at the end of one clock cycle from the mode register set cycle, the device is ready for operation. when the above sequence is used for power - up, all the out - puts will be in high imp edance state. the high impedance of outputs is not guaranteed in any other power - up sequence. cf.) sequence of 4 & 5 may be charged. mode register set (mrs) the mode register stores the data for controlling the various operation modes of sgram. it programs the cas latency, addressing mode, burst length, test mode and various vendor specific options to make sgram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written a fter power up to operate the sgram. the mode register is written by asserting low on cs , ras , cas , we and dsf (the sgram should be in active mode with cke already high prior to writing the mode register). the state of address pins a0~a9 and a10 in the same cycle as cs , ras , cas , we and dsf going low is the data written in the mode register. one clock cycle is required to complete the write in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. the mode register is divided into vari ous fields depending on functionality. the burst length field uses a0~a2, burst type uses a3, addressing mode uses a4~a6, a7~a8 and a10 are used for vendor specific options or test mode. and the write burst length is programmed using a9. a7~a8 and a10 must be set to low for normal sgram operation. refer to table for specific codes for various burst length, addressing modes and cas latencies.
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 15 amic technology, inc. device operations (continued) bank activate the bank activate command is used to select a random row in an idle ba nk. by asserting low on ras and cs with desired row and bank addresses, a row access is initiated. the read or write operation can occur after a time delay of t rcd (min) from the time of bank activation. t rcd (min) is an internal timing parameter of sgram, therefore it is dependent on operating clock frequency. the minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t rcd (min) with cycle time of the clo ck and then rounding off the result to the next higher integer. the sgram has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. also the nois e generated during sensing of each bank of sgram is high requiring some time for power supplies recover before the other bank can be sensed reliably. t rrd (min) specifies the minimum time required between activating different banks. the number of clock cycl es required between different bank activation must be calculated similar to t rcd specification. the minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t ras (min) specification before a precharge command to that active bank can be asserted. the maximum time any bank can be in the active state is determined by t ras (max). the number of cycles for both t ras (min) and t ras (max) can be calculated similar to t rcd specification. burst r ead the burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. the burst read command is issued by asserting low on cs and cas with we being high on the positive edge of the clock. the bank must be active for at least t rcd (min) before the burst read command is issued. the first output appears cas latency number of clock cycles after the issue of burst read command. the burst length, bur st sequence and latency from the burst read command is determined by the mode register which is already programmed. the burst read can be initiated on any column address of the active row. the address wraps around if the initial address does not start from a boundary such that number of outputs from each i/o are equal to the burst length programmed in the mode register. the output goes into high - impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. the bur st read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. the burst stop command is valid only at full page burst length where the output dose not go into high impedance at the end of burst and the burst is wrap around. burst write the burst write command is similar to burst read command, and is used to write data into the sgram consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. by asserting low on cs , cas and we with valid column address, a write burst is initiated. the data inputs are provided for the initial address in the same clock cycle as the burst write command. the input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. the writing can not complete to burst length. the burst write can be terminated by issuing a burst read and dqm for bl ocking data inputs or burst write in the same or the other active bank. the burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrap around. the write burst can also be terminated by u sing dqm for blocking data and precharging the bank ?t rdl ? after the last data input to be written into the active row. see dqm operation also. dqm operation the dqm is used to mask input and output operation. it works similar to oe dur ing read operation and inhibits writing during write operation. the read latency is two cycles from dqm and zero cycle for write, which means dqm masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. dqm operati on is synchronous with the clock, therefore the masking occurs for a complete cycle. the dqm signal is important during burst interrupts of write with read or precharge in the sgram. due to asynchronous nature of the internal write, the dqm operation is cr itical to avoid unwanted or incomplete writes when the complete burst write is not required. dqm is also used for device selection, byte selection and bus control in a memory system. dqm0 controls dq0 to dq7, dqm1 controls dq8 to dq15, dqm2 controls dq16 t o dq23, dqm3 controls dq24 to dq31. dqm masks the dq?s by a byte regardless that the corresponding dq?s are in a state of wpb masking or pixel masking. please refer to dqm timing diagram also. precharge the precharge operation is performed on an active ban k by asserting low on cs , ras , we and a9 with valid a10 of the bank to be precharged. the precharge command can be asserted anytime after t ras (min) is satisfied from the bank activate command in the desired bank. ?t rp ? is defined as the minimum time required to precharge a bank. the minimum number of clock cycles required to complete row precharge is calculated by dividing ?t rp ? with clock cycle time and rounding up to the next higher integer. ca re should be taken to make sure that burst write is completed or dqm is used to inhibit writing before precharge
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 16 amic technology, inc. device operations (continued) command is asserted. the maximum time any bank can be active is specified by t ras (max). therefore, each bank ha s to be precharged within t ras (max) from the bank activate command. at the end of precharge, the bank enters the idle state and is ready to be activated again. entry to power down, auto refresh, self refresh and mode register set etc, is possible only when both banks are in idle state. auto precharge the precharge operation can also be performed by using auto precharge. the sgram internally generates the timing to satisfy t ras (min) and ?t rp ? for the programmed burst length and cas latency. the auto prechar ge command is issued at the same time as burst read or burst write by asserting high on a9. if burst read or burst write command is issued with low on a9, the bank is left active until a new command is asserted. once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. both banks precharge both banks can be precharged at the same time by using precharge all command. asserting low on cs , ras and we with high on a9 after both banks have satisfied t ras (min) requirement, performs precharge on both banks. at the end of trp after performing precharge all, both banks are in idle state. auto refresh the storage cells of sgram need to be re freshed every 32ms to maintain data. an auto refresh cycle accomplishes refresh of a single row of storage cells. the internal counter increments automatically on every auto refresh cycle to refresh all the rows. an auto refresh command is issued by assert ing low on cs , ras and cas with high on cke and we . the auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (c ke is high in the previous cycle). the time required to complete the auto refresh operation is specified by ?t rc (min)?. the minimum number of clock cycles required can be calculated by driving ?t rc ? with clock cycle time and then rounding up to the next hi gher integer. the auto refresh command must be followed by nop?s until the auto refresh operation is completed. both banks will be in the idle state at the end of auto refresh operation. the auto refresh is the preferred refresh mode when the sgram is bein g used for normal data transactions. the auto refresh cycle can be performed once in 15.6us or a burst of 2048 auto refresh cycles once in 32ms. self refresh the self refresh is another refresh mode available in the sgram. the self refresh is the preferre d refresh mode for data retention and low power operation of sgram. in self refresh mode, the sgram disables the internal clock and all the input buffers except cke. the refresh addressing and timing is internally generated to reduce power consumption. t he self refresh mode is entered from all banks idle state by asserting low on cs , ras , cas and cke with high on we . once the self refresh mode is entered, only cke state being l ow matters, all the other inputs including clock are ignored to remain in the self refresh. the self refresh is exited by restarting the external clock and then asserting high on cke. this must be followed by nop?s for a minimum time of ?t rc ? before the s gram reaches idle state to begin normal operation. if the system uses burst auto refresh during normal operation, it is recommended to used burst 2048 auto refresh cycles immediately after exiting self refresh. define special function (dsf) the dsf control s the graphic applications of sgram. if dsf is tied to low, sgram function is 256k x 32 x 2 bank sdram. sdram can be used as an unified memory by the appropriate dsf command. all the graphic function mode can be entered only by setting dsf high when issuin g commands which otherwise would be normal sdram commands. sdram functions such as ras active, write, and wcbr change to sgram functions such as ras active with wpb, block write and swcbr respectively. see the session s below for the graphic functions that dsf controls. special mode register set (smrs) there are two kinds of special mode registers in sgram. one is color register and the other is mask register. those usage will be explained at ?write per bit? and ?block write? session. when a5 and dsf goes high in the same cycle as cs , ras , cas and we going low, load mask register (lmr) process is executed and the mask registers are filled with the masks for associated dq?s through dq pins. and when a6 and dsf goes high in the same cycle as cs , ras , cas and we going low, load color register (lcr) process is executed a nd the color register is filled with color data for associated dq?s through the dq pins. if both a5 and a6 are high at smrs, data of mask and color cycle is required to complete the write in the mask register and the color register at lmr and lcr respectiv ely. the next clock of lmr or lcr, a new commands can be issued. smrs, compared with mrs, can be issued at the active state under the condition that dq?s are idle. as in write operation, smrs accepts the data needed through dq pins. therefore it should be attended not to induce bus contention. the more detailed materials can obtained by referring corresponding timing diagram.
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 17 amic technology, inc. device operations (continued) write per bit write per bit (i.e. i/o mask mode) for sgram is a function that selectively m asks bits of data being written to the devices. the mask is stored in an internal register and applied to each bit of data written when enabled. bank active command with dsf = high enabled write per bit operations is stored in the mask register accessed by swcbr (special mode register set command). when a mask bit = 1, the associated data bit is written when a write command is executed and write per bit has been enabled for the bank being written. when a mask bit = 0, the associated data bit is unaltered wh en a write command is executed and the write per bit has been enabled f or the bank being written. no additional timing conditions are required fo r write per bit operat i ons. write per bit writes can be either single write, burst writes or block writes. dqm masking is the same for write per bit and non - wpb write. block write block write is a feature allowing the simultaneous writing of consecutive 8 columns of data within a ram device during a single access cycle. during block write the data to be written com es from an internal ?color? register and dq i/o pins are used for independent column selection. the block of column to be written is aligned on 8 column boundaries and is defined by the column address with the 3 lsb?s ignored. write command with dsf = 1ena bles block write for the associated bank. a write command with dsf = 0 enables normal write for the associated bank. the block width is 8 column where column = ?n? bits for by ?n? part. the color register is the same width as the data port of the chip. it is written via a swcbr where data present on the dq pin is to be coupled into the internal color register. the color register provides the data masked by the dq column select, wpb mask (if enabled), and dqm byte mask. column data masking (pixel masking) is provided on an individual column basis for each byte of data. the column mask is driven on the dq pins during a block write command. the dq column mask function is segmented on a per bit basis (i.e. dq[0:7] provides the column mask for data bits[0:7], dq[ 8:15] provides the column mask for data bits[8:15], dq0 masks column[0] for data bits[0:7], dq9 masks column [1] for data its [8:15], etc). block writes are always non - burst, independent of the burst length that has been programmed into the mode register. back to back block writes are allowed provided that the specified block write cycle time (t bwc ) is satisfied. if write per bit was enabled by the bank active command with dsf = 1, then write per bit masking of the color register data is enabled. if write per bit was disabled by a bank active command with dsf = 0, the write per bit masking of the color register data is disabled. dqm masking provides independent data byte masking during block write exactly the same as it does during normal write operations, except that the control is extended to the consecutive 8 columns of the block write. timing diagram to illustrate t bwc high 1 clk bw 1 0 2 clock cke cs ras cas we dsf
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 18 amic technology, inc. 1) click suspended during write (bl=4) masked by cke q0 q1 q3 q0 q2 q3 suspended dout 2) clock suspended during read (bl=4) wr masked by cke d0 d1 d2 d3 d0 d1 d2 d3 not written dq(cl3) dq(cl2) internal clk cke cmd clk rd q2 q1 note: clk to clk disable/enable=1 clock summary of 2m byte sgram basic features and benefits features 256k x 32 x 2 sgram benefits interface synchronous better interacti on between memory and system without wait - state of asynchronous dram. high speed vertical and horizontal drawing. high operation frequency allows performance gain for scroll, fill, and bitblt. bank 2 ea pseudo - infinite row length by on - chip interleaving operation. hidden row activation and precharge. page depth / 1 row 256 bit high speed vertical and horizontal drawing. total page depth 2048 bytes high speed vertical and horizontal drawing burst length (read) 1,2,4,8 full page programmable burst of 1 ,2,4,8 and full page transfer per column addresses. 1,2,4,8 full page programmable burst of 1,2,4,8 and full page transfer per column addresses. burst length (write) brsw switch to burst length of 1 at write without mrs burst type sequential & interlea ve compatible with intel and motorola cpu based system. cas latency 2,3 programmable cas latency. block write 8 columns high speed fill, clear, text with color registers. maximum 32 byte data transfers (e.g. for 8bpp : 32 pixels) with plane and byte mask ing functions. color register 1 ea. a and b bank share. mask register 1 ea. write - per - bit capability (bit plane masking). a and b banks share. dqm0 - 3 byte masking (pixel masking for 8bpp system) for data - out/in write per bit each bit of the mask register directly controls a corresponding bit plane. mask function pixel mask at block write byte masking (pixel masking for 8bpp system) for color by dqi basic feature and function descriptions 1. clock suspend
A45L9332A series preliminary (october, 2001, version 0.1) 19 amic technology, inc. 2. dqm operation * note : 1. there are 4 dqmi (i=0~3). each dqmi masks 8 dqi?s. (1 byte, 1 pixel for 8bbp). 2. dqm makes data out hi - z after 2 clocks which should masked by cke ?l?. 1) write mask (bl=4) masked by cke q0 q1 q3 q1 q2 q3 dqm to data-out mask = 2 2) read mask (bl=4) wr masked by cke d0 d1 d3 d0 d1 d3 dqm to data-in mask = 0clk dq(cl3) dq(cl2) dqmi cmd clk rd hi-z hi-z q0 q2 q4 2) read mask (bl=4) rd hi-z hi-z hi-z q6 q7 q8 hi-z q1 q3 hi-z hi-z q5 q6 q7 clk cmd cke dqm dq(cl2) dq(cl3)
A45L9332A series preliminary (october, 2001, version 0.1) 20 amic technology, inc. 3. cas interrupt (i) note : 1. by ?interrupt?, it is possible to stop burst read/write by external command before the end of burst. by ? cas interrupt?, to stop burst read/write by cas access; read, write and block write. 2. t ccd : cas to cas delay. (=1clk) 3. tcdl : last data in to new column address delay. ( = 1clk). 4. pixel : pixel mask. 5. t bwc : block write minimum cycle time. 1) read intreupted by read (bl=4) note 1 rd rd a b qa0 qb0 qb1 qb2 qb3 qa0 qb0 qb1 qb2 qb3 ckl cmd add dq(cl2) dq(cl3) t ccd note2 2) write interrupted by (block) write (bl =2) wr wr a b ckl cmd add wr bw t ccd note2 t ccd note2 c d da0 db0 db1 dc0 pixel note4 t cdl note3 t cdl note3 dq 3) write interrupted by read (bl =2) wr rd a b t ccd note2 da0 qb0 pixel t cdl note3 dq(cl2) qb0 qb1 dq(cl3) da0 2) block write to block write bw bw a b ckl cmd add note4 pixel pixel t bwc note5 dq
A45L9332A series preliminary (october, 2001, version 0.1) 21 amic technology, inc. 4. cas interrupt (ii) : read interrupted write & dqm * note : 1. to prevent bus contention, there shoul d be at least one gap between data in and data out. 2. to prevent bus contention, dqm should be issued which makes a least one gap between data in and data out. rd wr d0 d1 d2 d3 rd wr d0 d1 d2 d3 wr rd hi-z hi-z d0 d1 d2 d3 rd wr d0 d1 d2 d3 q0 hi-z note 1 rd wr d0 d1 d2 d3 rd wr d0 d1 d2 d3 wr rd hi-z d0 d1 d2 d3 rd wr d0 d1 d2 q0 hi-z note 2 d0 d1 d2 d3 rd wr wr (1) cl=2, bl=4 clk i) cmd dqm dq ii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq (2) cl=3, bl=4 clk i) cmd dqm dq ii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq v) cmd dqm dq d3
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 22 amic technology, inc. 5. write interrupted by precharge & dqm note : 1. to inhibit invalid write, dqm should be is sued. 2. this precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation. 6. precharge 7. auto precharge * note : 1. t bpl : block write data - in to pre command delay. 2. number of valid output data after row precharge : 1,2 for cas latency = 2,3 respectively. 3. the row active command of the precharge bank can be issued after trp from this point. the new read/write command of other active bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same/another bank is illegal. wr pre note 2 note 1 d0 d1 d2 d3 masked by dqm clk cmd dqm dq wr pre d0 d1 d2 d3 clk cmd dq 1) normal write (bl=4) bw pixel clk cmd dq 2) block write t bpl note 1 t rdl note 1 rd pre note 2 1 q0 q1 q2 q3 clk cmd dq(cl2) 3) read (bl=4) q0 q1 q2 q3 2 dq(cl3) pre wr d0 d1 d2 d3 clk cmd dq 1) normal write (bl=4) bw pixel clk cmd dq (cl 2,3) 2) block write t bpl note 3 rd q0 q1 q2 q3 clk cmd dq(cl2) 3) read (bl=4) q0 q1 q2 q3 dq(cl3) auto precharge starts note 3 auto precharge starts t rp note 3 auto precharge starts
A45L9332A series preliminary (october, 2001, version 0.1) 23 amic technology, inc. 8. burst stop & precharge interrupt 9. mrs & smrs note : 1.t rdl : 2clk, last data in to row precharge. 2. t bdl : 1cl k, last data in to burst stop delay. 3. number of valid output data after row precharge or burst stop : 1,2 for cas latency=2,3 respectively. 4. pre : both banks precharge if necessary. mrs can be issued only at all bank precharge state. 2) write burst stop (full page only) dq(cl2) dq(cl3) wr pre note 1 d0 d1 d2 d3 clk cmd dqm dq wr stop d1 clk cmd dq t bdl 1) write interrupted by precharge (bl=4) t rdl d0 d2 rd q0 q1 clk cmd dq(cl2) 4) read burst stop (full page only) q0 q1 dq(cl3) stop note 3 1 2 rd q0 q1 clk cmd 3) read interrupted by precharge (bl=4) q0 q1 pre note 3 1 2 2) special mode register set pre mrs note 4 clk cmd smrs bw smrs clk cmd 1clk 2) mode register set 1clk act smrs act t rp 1clk 1clk 1clk
A45L9332A series preliminary (october, 2001, version 0.1) 24 amic technology, inc. 10. clock suspen d exit & power down exit 11. auto refresh & self refresh * note : 1. active power down : one or more bank active state. 2. precharge power down : both bank precharge state. 3. the auto refresh is the same as cbr refresh of conventional dram. no precharge c ommands are required after auto refresh command. during t rc from auto refresh command, any other command can not be accepted. 4. before executing auto/self refresh command, both banks must be idle state. 5. (s)mrs, bank active, auto/self refresh, power dow n mode entry. 6. during self refresh mode, refresh interval and refresh operation are performed internally. after self refresh entry, self refresh mode is kept while cke is low. during self refresh mode, all inputs expect cke will be don?t cared, and outpu ts will be in hi - z state. during t rc from self refresh exit command, any other command can not be accepted. before/after self refresh mode, burst auto refresh cycle (2k cycles ) is recommended. 2) power down (=precharge power down) exit note 1 clk cmd 1) clock suspend (=active power down) exit rd t ss cke internal clk note 2 clk cmd act cke internal clk t ss nop 2) self refresh clk cmd 1) auto refresh cke internal clk clk cmd sr cke pre note 4 pre ar cmd note 5 ~ ~ ~ ~ ~ ~ ~ ~ t rp t rc note 3 note 6 ~ ~ cmd ~ ~ note 4 t rp t rc ~ ~ ~ ~ ~ ~
A45L9332A series preliminary (october, 2001, version 0.1) 25 amic technology, inc. 12. about burst type control sequential counting a t mrs a3=?0?. see the burst sequence tabe.(bl=4,8) bl=1,2,4,8 and full page wrap around. basic mode interleave counting at mrs a3=? 1?. see the burst sequence tabe.(bl=4,8) bl=4,8 at bl=1,2 interleave counting = sequential counting pseud o - decrement sequential counting at mrs a3 = ?1?. (see to interleave counting mode) starting address lsb 3 bits a0 - 2 should be ?000? or ?111?.@bl=8. -- if lsb = ?000? : increment counting. -- if lsb= ?111? : decrement counting. for example, (assume addresses except lsb 3 bits are all 0, bl=8) -- @ write, lsb=?000?, accessed column in order 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 -- @ read, lsb=?111?, accessed column in order 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 at bl=4, same applications are possible. as above example, at interleave counting mode, by conf ining starting address to some values, pseudo - decrement counting mode can be realized. see the burst sequence table carefully. pseudo - mode pseudo - binary counting at mrs a3 = ?0?. (see to sequential counting mode) a0 - 2 = ?111?. (see to full page mode ) using full page mode and burst stop command, binary counting mode can be realized. -- @ sequential counting accessed column in order 3 - 4 - 5 - 6 - 7 - 1 - 2 - 3 (bl=8) -- @ pseudo - binary counting, accessed column in order 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 (burst stop command) note. th e next column address of 256 is 0 random mode random column access t ccd = 1 clk every cycle read/write command with random column address can realize random column access. that is similar to extended data out (edo) operation of convention dram. 13. about burst length control 1 at mrs a2,1,0 = ?000?. at auto precharge, tras should not be violated. 2 at mrs a2,1,0 = ?001?. at auto precharge, tras should not be violated. 4 at mrs a2,1,0 = ?010? 8 at mrs a2,1,0 = ?011?. basic mode full page at mr s a2,1,0 = ?111?. wrap around mode (infinite burst length) should be stopped by burst stop, ras interrupt or cas interrupt. brsw at mrs a9=?1?. read burst = 1,2,4,8, full page/write burst =1 at auto p recharge of write, tras should not be violated. special mode block write 8 column block write. lsb a0 - 2 are ignored. burst length=1. t bwc should not be violated. at auto precharge, tras should not be violated. random mode burst stop t bdl =1, valid dq after burst sto p is 1,2 for cl=2,3 respectively using burst stop command, it is possible only at full page burst length. ras interrupt (interrupted by precharge) before the end of burst, row precharge command of the same bank stops r ead/write burst with row precharge. t rdl =2 with dqm, valid dq after burst stop is 1,2 for cl=2,3 respectively during read/write burst with auto precharge, ras interrupt cannot be issued. interrupt mode cas interrupt before the e nd of burst, new read/write stops read/write burst and starts new read/write burst or block write. during read/write burst with auto precharge, cas interrupt can not be issued.
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 26 amic technology, inc. 14. mask functions 1) normal write i/o masking : by mask at w rite per bit mode, the selected bit planes keep the original data. if bit plane 0,3,7,9,15,22,24, and 31 keep the original value. i) step smrs (lmr) : load mask [31 - 0]=?0111,1110,1011,1111,0111,1101,0111,0110? row active with dsf ?h? : writ per bit mod e enable perform normal write ii) illustration i/o(=dq) 31 24 23 16 15 8 7 0 external data - in 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dqmi dqm3=0 dqm2=0 dqm 1=0 dqm0=1 mask register 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 0 1 1 1 0 1 1 0 before write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 after write 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 1 1 1 1 note 1 2) b lock write pixel masking : by pixel data issued through dq pin, the selected pixels keep the original data. see pixel to dq mapping table. if pixel 0,4,9,13,18, 22, 27 and 31 keep the original white color. assume 8bpp, white = ?0000,0000?, red = ?1010,001 1?, green = ?1110,0001?, yellow = ?0000,1111?, blue = ?1100,0011? i) step smrs(lcr) : load color (for 8bbp, through x32 dq color 0 - 3 are loaded into color registers) load(color3, color2, color1, color0) = (blue, green, yellow, red) = ?1100,0011,1110,0001,0 000,1111,1010,0011? row active with dsf ?l? : i/o mask by write per bit mode disable block write with dq[31 - 0] = ?0111,0111,1011,1011,1101,1101,1110,1110? ii) illustration i/o(=dq) 31 24 23 16 15 8 7 0 dqmi dqm3=0 dqm2=0 dqm1=0 dqm0=1 color register color3=blue color2=green color1=yellow color0=red 000 white dq24=h white dq16=h white dq8=h white dq0=l 001 white dq25=h white dq17=h white dq9=l white dq1=h 010 white dq26=h white dq18=l white dq10=h white dq2=h 011 white dq27=l white dq19=h white dq11=h white dq3=h 100 white dq28=h white dq20=h white dq12=h white dq4=l 101 white dq29=h white dq21=h white dq13=l white dq5=h 110 white dq30=h whi te dq22=l white dq14=h white dq6=h before block write & dq (pixel data) 111 white dq31=l white dq23=h white dq15=h white dq7=h 000 blue green yellow white 001 blue green white white 010 blue white yellow white 011 white green yellow white 100 blue green yellow white 101 blue green white white 110 blue white yellow white after block write 111 white green yellow white note 2 * note : 1. dqm byte masking. 2. at normal write, one column is selected among columns decoded by a2 - 0 (000 - 111) at block write, instead of ignore d address a2 - 0, dq0 - 31 control each pixel.
A45L9332A series preliminary (october, 2001, version 0.1) 27 amic technology, inc. note 1 (continued) pixel and i/o masking : by mask at write per bit mode, the selected bit planes keep the original data. by pixel data issued through dq pin, the selected pixels keep the original data. see pixel to dq mapping tanle. assume 8bpp, white = ?0000,0000?, red = ?1010,0011?, green = ?1110,0001?, yellow = ?0000,1111?, blue = ?1100,0011? i) step smrs (lcr) : load color (for 8bpp, through x 32 dq color0 - 3 are loaded into color registers) load (color3, color2, c olor1, color0) = (blue, green, yellow, red) = ?1100,0011,1110,0001,0000,1111,1010,0011? smrs (lmr) : load mask, mask[31 - 0] = ?1111,1111,1101,1101,0100,0010,0111,0110? ? byte 3:no i/o masking; byte 2:i/o masking; byte 1:i/o and pixel masking; byte 0:dqm b yte masking row active with dsf ?h? : i/o mask by write per bit mode enable block write with dq[31 - 0] = ?0111,0111,1111,1111,0101,0101,1110,1110? (pixel mask) ii) illustratuon i/o(=dq) 31 24 23 16 15 8 7 0 color register blue green yellow red 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 dqmi dqm3=0 dqm2=0 dqm1=0 dqm0=1 mask register 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 1 0 before write yell ow 0 0 0 0 1 1 1 1 yellow 0 0 0 0 1 1 1 1 green 1 1 1 0 0 0 0 1 white 0 0 0 0 0 0 0 0 after write blue 1 1 0 0 0 0 1 1 blue 1 1 0 0 0 0 1 1 red 1 0 1 0 0 0 1 1 white 0 0 0 0 0 0 0 0 i/o(=dq) 31 24 23 16 15 8 7 0 dqmi dqm3=0 dqm2=0 dqm1=0 dqm0=1 color register color3=blue color2=green color1=yellow color0=red 000 yellow dq24=h yellow dq16=h green dq8=h white dq0=l 001 yellow dq25=h yellow dq17=h g reen dq9=l white dq1=h 010 yellow dq26=h yellow dq18=h green dq10=h white dq2=h 011 yellow dq27=l yellow dq19=h green dq11=h white dq3=h 100 yellow dq28=h yellow dq20=h green dq12=h white dq4=l 101 yellow dq29=h yellow dq21=h green dq13=l white dq5 =h 110 yellow dq30=h yellow dq22=h green dq14=h white dq6=h before block write & dq (pixel data) 111 yellow dq31=l yellow dq23=h green dq15=l white dq7=h 000 blue blue red white 001 blue blue green white 010 blue blue red white 011 yellow blue green white 100 blue blue red white 101 blue blue green white 110 blue blue red white after block write 111 yellow blue green white note 2 note 1 pixel mask i/o mask pixel & i/o mask byte mask * note : 1. dqm byte masking. 2. at normal write, one column is s elected among columns decoded by a2 - 0 (000 - 111) at block write, instead of ignored address a2 - 0, dq0 - 31 control each pixel.
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 28 amic technology, inc. power on sequence & auto refresh key key key ra bs ra high level is necessary high level is necessary high-z t rp t rc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a 10 /ba a 9 /ap we dsf dqm dq precharge (all banks) auto refresh auto refresh mode regiser set row active (write per bit enable or disable) : don't care ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
A45L9332A series preliminary (october, 2001, version 0.1) 29 amic technology, inc. single bit read - write - read cycles (same page) @cas latency=3, burst length=1 rb high t rcd t rp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a 10 a 9 we dsf dqm dq row active (write per bit enable or disable) read write or block write row active (write per bit enable or disable : don't care t ch t cl t cc ra ca cb cc bs bs bs bs bs bs ra rb qa db qc t ras t rc t sh t ss *note 1 t sh t ss t ccd t sh t ss t sh t ss t ss t sh *note 2 *note 2,3 *note 2,3 *note 2,3 *note 4 *note 2 *note 3 *note 3 *note 3 *note 4 t sh t ss *note 5 *note 6 *note 3 *note 5 t sh t ss t sh t ss t sh t ss t rac t sac t slz t oh t shz read precharge
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 30 amic technology, inc. * note : 1. all inputs can be don?t care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by a10. a10 active & read/write 0 bank a 1 bank b 3. enable and disable auto precharge function are controlled by a9 in read/write command. a9 a10 operation 0 disable auto precharge, leave bank a active at end of burst. 0 1 disable auto precharge, leave bank b active at end of burst. 0 enable auto precharge, precharge bank a at end of burst. 1 1 enable auto prech arge, precharge bank b at end of burst. 4. a9 and a10 control bank precharge when precharge command is asserted. a9 a10 precharge 0 0 bank a 0 1 bank b 1 x both bank 5. enable and disable write - per bit function are controlled by dsf in row active command. a10 dsf operation l bank a row active, disable write per bit function for bank a 0 h bank a row active, enable write per bit function for bank a l bank b row active, disable write per bit function for bank b 1 h bank b row active, enable w rite per bit function for bank b 6. block write/normal write is controlled by dsf dsf operation minimum cycle time l normal write t ccd h block write t bwc
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 31 amic technology, inc. read & write cycle at same bank @burst length=4 *note : 1. minimum row cycle times is required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [cas latency - 1] valid output data available after row enters precharge. last valid output will be hi - z after t shz from the clock. 3. access time from row address. t cc *( t rcd + cas latency - 1) + t sac 4. output will be hi - z after the end of burst. (1,2,4 & 8) at full page bit burst, burst is wrap - around. high t rc t rcd 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 we dsf dqm dq (cl = 2) row active (a-bank) read (a-bank) precharge (a-bank) row active (a-bank) precharge (a-bank) : don't care *note 1 *note 2 ra ca0 rb cb0 ra rb a9 qa0 t oh qa1 qa2 qa3 db0 db1 db2 db3 t rac t sac *note 3 t shz *note 4 t rdl qa0 t oh qa1 qa2 qa3 db0 db1 db2 db3 t rac t sac *note 3 t shz *note 4 t rdl write (a-bank) dq (cl = 3)
A45L9332A series preliminary (october, 2001, version 0.1) 32 amic technology, inc. page read & write cycle at same bank @burst length=4 *note : 1. to write data before burst read ends, dqm should be asse rted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. high t rcd 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 we dsf dqm dq (cl=2) row active (a-bank) read (a-bank) precharge (a-bank) : don't care *note 2 ra ca0 cb0 cc0 ra a9 qa0 qa1 qb0 qb1 dc0 dc1 dd0 dd1 qa0 qa1 qb0 write (a-bank) cd0 t cdl *note 2 *note1 *note3 dc0 dc1 dd0 dd1 read (a-bank) write (a-bank) dq (cl=3) t rdl
A45L9332A series preliminary (october, 2001, version 0.1) 33 amic technology, inc. block write cycle (with auto precharge) *note : 1. column mask (dqi=l : mask, dqi=h : non mask) 2. at block write, ca0 - 2 are ignored. high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 we dsf dqm row active with write-per-bit enable (a-bank) masked block write (a-bank) block write with auto precharge (b-bank) : don't care raa caa cab rba raa a9 block write (b-bank) cba masked block write with auto precharge (a-bank) row active (b-bank) cbb *note 2 rba pixel mask *note 1 pixel mask pixel mask pixel mask t bwc dq
A45L9332A series preliminary (october, 2001, version 0.1) 34 amic technology, inc. smrs and block/normal write @ burst length=4 * note : 1. at the next clock of special mode set command, new command is possible. high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas a0-2 a3,4,7,8 a6 a9 a10 load color register row active with wpb* enable (a-bank) masked write with auto precharge (b-bank) : don't care raa rba a5 cba row active with wpb* enable (b-bank) color i/o mask pixel mask color raa caa rba cba caa cba raa rba raa caa rba cba raa caa we i/o mask dba0 dba1 dba2 dba3 load color register masked bolck write (a-bank) load mask register load color register wpb* : write-per-bit *note1 dsf dqm dq
A45L9332A series preliminary (october, 2001, version 0.1) 35 amic technology, inc. page read cycle at different bank @burst length = 4 * note : 1. cs can be don?t care when ras , cas and we are high at the clock high going edge. 2. to interrupt a burst read by row precharge, both the read ad the precharge banks must be the same. high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active (a-bank) read (a-bank) : don't care raa caa a9 cbb read (b-bank) row active (b-bank) *note 1 *note 2 rbb cac cbd cae raa rbb we low dsf dqm qbb1 qbb0 qaa0 qaa1 qaa2 qaa3 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 qbb1 qbb0 qaa0 qaa1 qaa2 qaa3 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 read (a-bank) read (b-bank) read (a-bank) precharge (a-bank) dq (cl=2) dq (cl=3)
A45L9332A series preliminary (october, 2001, version 0.1) 36 amic technology, inc. page write cycle at different bank @burst length=4 high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active with write-per-bit enable (a-bank) masked write (a-bank) : don't care raa caa a9 cbb write (b-bank) row active (b-bank) rbb cac cbd raa rbb we dsf dbb1 dbb0 daa0 daa1 daa2 daa3 dbb2 dbb3 dac0 dac1 dbd0 dbd1 masked write with auto precharge (a-bank) write with auto precharge (b-bank) dqm dq key t cdl mask dac2 dac3 dbd2 dbd3 load mask register
A45L9332A series preliminary (october, 2001, version 0.1) 37 amic technology, inc. read & write cyc le at different bank @burst length=4 * note : 1. t cdl should be met to complete write. high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active (a-bank) read (a-bank) : don't care raa caa a9 rbb precharge (a-bank) cbb cac raa we dsf qaa2 qaa1 qaa0 qaa3 dbb0 write (b-bank) read (a-bank) dqm qac0 qac1 rac rac rbb t cdl *note 1 qaa3 qaa2 qaa0 qaa1 dbb0 dbb1 qac0 dbb2 dbb3 qac1 qac2 dq (cl=2) dbb1 dbb2 dbb3 dq (cl=3) row active (a-bank) row active (b-bank)
A45L9332A series preliminary (october, 2001, version 0.1) 38 amic technology, inc. read & write cycle with auto precharge i @burst length=4 *note : 1. trcd should be controlled to meet minimum tras before internal precharge start. (in the case of burst length=1 & 2, brsw mode and block write) high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active (a-bank) row active (b-bank) : don't care raa rbb a9 caa auto precharge start point (a-bank) raa we dsf qaa2 qaa1 qaa0 qaa3 dbb0 auto precharge start point (b-bank) dqmi cbb qaa3 qaa2 qaa0 qaa1 dbb0 dbb1 dbb2 dbb3 dq (cl=2) dbb1 dbb2 dbb3 dq (cl=3) write with auto precharge (b-bank) rbb read with auto precharge (a-bank)
A45L9332A series preliminary (october, 2001, version 0.1) 39 amic technology, inc. read & write cycle with auto precharge ii @burst length=4 * note : 1. when read(write) command with auto precharge is issued at a - bank after a and b bank activation. - if read(write) command w ithout auto precharge is issued at b - bank before a bank auto precharge starts, a bank auto precharge will start at b bank read command input point. - any command can not be issued at a bank during t rp after a bank auto precharge starts. high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active (a-bank) row active (b-bank) : don't care ra rb a9 ca read without auto precharge (b-bank) auto precharge strart point (a-bank) *note 1 ra we dsf qb0 qa1 qa0 qb1 qb2 write with auto precharge (a-bank) dqm cb qb1 qb0 qa0 qa1 qb2 qb3 da0 da1 dq (cl=2) qb3 da0 da1 dq (cl=3) row active (a-bank) rb read with auto pre charge (a-bank) ra ca ra precharge (b-bank)
A45L9332A series preliminary (october, 2001, version 0.1) 40 amic technology, inc. read & write cycle with auto precharge iii @burst length=4 * note : 1. any command to a - bank is not allowed in this period. trp is determined from at auto precharge start point high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active (a-bank) : don't care ra a9 ca ra we dsf qa2 qa1 qa0 qa3 qb0 dqm qa3 qa2 qa0 qa1 qb0 qb1 qb2 qb3 dq (cl=2) qb1 db2 db3 dq (cl=3) auto precharge start point (b-bank) read with auto preharge (a-bank) rb cb rb read with auto precharge (b-bank) auto precharge start point (a-bank) row active (b-bank) * note 1
A45L9332A series preliminary (october, 2001, version 0.1) 41 amic technology, inc. read interrupted by precharge command & read burst stop cycle (@full page only) * note : 1. at full page mode, burst is wrap - around at the end of burst. so auto precharge is impossible. 2. about the valid dq?s after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing d iagram. see the label 1,2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of ?full page write burst stop cycle?. high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active (a-bank) : don't care raa a9 caa raa we dsf qaa3 qaa2 qaa1 qaa4 qab0 dqm qaa4 qaa3 qaa1 qaa2 qab0 qab1 qab2 qab3 dq (cl=2) qab1 qab2 qab3 dq (cl=3) precharge (a-bank) read (a-bank) cab read (a-bank) burst stop * note 1 * note 1 1 * note 2 qaa0 qab4 qab5 1 qaa0 2 qab4 qab5 2
A45L9332A series preliminary (october, 2001, version 0.1) 42 amic technology, inc. write interrupted by precharge command & write burs t stop cycle (@ full page only) * note : 1. at full page mode, burst is wrap - around at the end of burst. so auto precharge is impossible. 2. data - in at the cycle of burst stop command cannot be written into corresponding memory cell. it is defined by ac parameter of tbdl(=1clk). 3. data - in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. it is defined by ac parameter of trdl(2=clk). dqm at write interrupted by precharge command is needed to ens ure trdl of 2clk. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 4. burst stop is valid only at full page burst length. high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active (a-bank) : don't care raa a9 caa raa we dsf dqm daa4 daa3 daa1 daa2 dab0 dab1 dab2 dab3 dq precharge (a-bank) write (a-bank) cab write (a-bank) burst stop * note 1 * note 1 * note 2 daa0 dab4 dab5 t rdl t bdl * note 3
A45L9332A series preliminary (october, 2001, version 0.1) 43 amic technology, inc. high 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active (a-bank) : don't care raa a9 caa raa we dsf qab1 qab0 dbc0 dqm qab1 qab0 dbc0 qad0 dq (cl=2) qad0 dq (cl=3) write with auto precharge (b-bank) write (a-bank) rac row active (a-bank) daa0 qad1 daa0 qad1 * note 2 rbb cab cbc cad rac rbb row active (b-bank) read with auto precharge (a-bank) read (a-bank) precharge (a-bank) bu rst read single bit write cycle @burst length=2, brsw * note : 1. brsw mode is enabled by setting a9 ?high? at mrs (mode register set). at the brsw mode, the burst length at write is fixed to ?1? regardless of programed burst length. 2. wh en brsw write command with auto precharge is executed, keep it in mind that tras should not be violated. auto precharge is executed at the burst - end cycle, so in the case of brsw write command, the next cycle starts the precharge. 3. wpb function is also possible at brsw mode.
A45L9332A series preliminary (october, 2001, version 0.1) 44 amic technology, inc. clock suspension & dqm operation cycle @cas latency = 2, burst length=4 * note : 1. dqm needed to prevent bus contention. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 row active : don't care ra a9 ca ra we dsf dqm qa1 qb0 qb1 dc0 dq clock suspension read cb read qa0 dc2 * note 1 qa2 cc clock suspension t shz qa3 t shz write dqm write read dqm
A45L9332A series preliminary (october, 2001, version 0.1) 45 amic technology, inc. active/precharge power down mode @cas lantency=2, burst length=4 * note : 1. all banks should b e in idle state prior to entering precharge power down mode. 2. cke should be set high at least ?1clk + t ss ? prior to row active command. 3. cannot violate minimum refresh specification. (32ms) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 precharge power-down exit : don't care a9 active power-down entry row active we dsf qa2 read precharge dqm dq qa0 qa1 precharge power-down entry t ss t ss * note 2 * note 1 *note 3 t ss t ss ra ca ra active power-down exit ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
A45L9332A series preliminary (october, 2001, version 0.1) 46 amic technology, inc. self refresh entry & exit cycle * note : to ent er self refresh mode 1. cs , ras & cas with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don?t care except for cke. 3. the device remains in self refresh mode as long as cke stays ?low?. (cf.) once the device enters self refresh mode, minimum tras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum trc is required after cke going high to complete self refresh exit. 7. 2k cycle of burst auto refresh is required before self refresh entry and after self refresh exit. if the system uses burst refresh. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr a10 : don't care a9 we dsf self refresh exit auto refresh dqm dq self refresh entry t ss * note 4 * note 1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ * note 3 * note 2 ~ ~ t ss * note 6 t rc min. ~ ~ ~ ~ * note 5 ~ ~ ~ ~ * note 7 * note 7 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ hi-z hi-z
A45L9332A series preliminary (october, 2001, version 0.1) 47 amic technology, inc. mode register set cycle auto refresh cycle * both banks precharge should be completed before mode register set cycle and auto refresh cycle. mode register set cycle * note : 1. cs , ras , cas & we activation and dsf of low at the same clock cycle with address key will set internal mode register. 2. minimum 1 clock cycles should be met before new ras activation. 3. please refer to mode register set table. 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 clock cke cs ras cas addr : don't care we dsf auto refresh new command dqm dq mrs ~ ~ ~ ~ * note 1 ~ ~ ~ ~ hi-z hi-z high high ~ ~ ~ ~ t rc *note 2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ key ra * note 3 ~ ~ ~ ~ ~ ~ ~ ~ new command ~ ~ ~ ~
A45L9332A series preliminary (october, 2001, version 0.1) 48 amic technology, inc. function truth table (table 1) current state cs ras cas we dsf ba (a10) address action note h x x x x x x nop l h h h x x x nop l h h l x x x illegal 2 l h l x x ba ca illegal 2 l l h h l ba ra row active; latch row address; non - io mask l l h h h ba ra row active; latch row address; io mask l l h l l ba pa nop 4 l l h l h x x illegal l l l h l x x auto ref resh or self refresh 5 l l l h h x x illegal l l l l l op code mode register access 5 idle l l l l h op code special mode register access 6 h x x x x x x nop l h h h x x x nop l h h l x x x illegal 2 l h l h l ba ca,ap begin read; lat ch ca; determine ap l h l h h x x illegal l h l l l ba ca,ap begin write; latch ca; determine ap l h l l h ba ca,ap block write; latch ca; determine ap l l h h x ba ra illegal 2 l l h l l ba pa precharge l l h l h x x illegal l l l h x x x illegal l l l l l x x illegal row active l l l l h op code special mode register access 6 h x x x x x x nop(continue burst to end ? row active) l h h h x x x nop(continue burst to end ? row active) l h h l l x x term burst ? row active l h h l h x x illegal l h l h l ba ca,ap term burst; begin read; latch ca; determine ap 3 l h l h h x x illegal l h l l l ba ca,ap term burst; begin write; latch ca; determine ap 3 l h l l h ba ca,ap term burst; block write; latch ca; determine ap 3 l l h h x ba ra illegal 2 l l h l l ba pa term burst; precharge timing for reads 3 l l h l h x x illegal read l l l x x x x illegal
A45L9332A series preliminary (october, 2001, version 0.1) 49 amic technology, inc. function truth table (table 1, continued) current state cs ras cas we dsf ba (a10) address action note h x x x x x x nop(continue burst to end ? row active) l h h h x x x nop(continue burst to end ? row active) l h h l l x x term burst ? row active) l h h l h x x illegal l h l h l ba ca,ap term burst; begin read; latch ca; determine ap 3 l h l h h x x illegal l h l l l ba ca,ap term burst; begin write; latch ca; determine ap 3 l h l l h ba ca,ap term burst; block write; latch ca; determine ap 3 l l h h x ba ra illegal 2 l l h l l ba pa term burst; precharge timing for writes 3 l l h l h x x illegal write l l l x x x x illegal h x x x x x x nop(continue burst to end ? precharge) l h h h x x x nop(continue burst to end ? precharge) l h h l x x x illegal l h l h x ba ca,ap illegal 2 l h l l x ba ca,ap illegal 2 l l h x x ba ra,pa illegal read with auto precharge l l l x x x x illegal 2 h x x x x x x nop(continue burst to end ? precharge) l h h h x x x nop(continue burst to end ? precha rge) l h h l x x x illegal l h l h x ba ca,ap illegal 2 l h l l x ba ca,ap illegal 2 l l h x x ba ra,pa illegal write with auto precharge l l l x x x x illegal 2 h x x x x x x nop ? idle after t rp l h h h x x x nop ? idle after t rp l h h l x x x illegal l h l x x ba ca,ap illegal 2 l l h h x ba ra illegal 2 l l h l x ba pa nop ? idle after t rp 2 precharge l l l x x x x illegal 4
A45L9332A series preliminary (october, 2001, version 0.1) 50 amic technology, inc. function truth table (table 1, continued) current state cs ras cas we dsf ba (a10) address action note h x x x x x x nop ? row active after t bwc l h h h x x x nop ? row active after t bwc l h h l x x x illegal l h l x x ba ca,ap illegal 2 l l h h x ba ra illegal 2 l l h l x ba pa term block write: precharge timing for block write 2 block write recovering l l l x x x x illegal 2 h x x x x x x nop ? row active after t rcd l h h h x x x nop ? row active after t rcd l h h l x x x illegal l h l x x ba ca,ap illegal 2 l l h h x ba ra illegal 2 l l h l x ba pa illegal 2 row activating l l l x x x x illegal 2 h x x x x x x nop ? idle after t rc l h h x x x x nop ? idle after t rc l h l x x x x illegal l l h x x x x illegal refreshing l l l x x x x illegal abbreviations ra = row a ddress (a0~a9) ba = bank address (a10) pa = precharge all (a9) nop = no operation command ca = column address (a0~a7) ap = auto precharge (a9) note: 1. all entries assume that cke was active (high) during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state : function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idl e state. may precharge bank indicated by ba (and pa). 5. illegal if any banks is not idle. 6. legal only if all banks are in idle or row active state.
A45L9332A series preliminary (october, 2001, version 0.1) 51 amic technology, inc. function truth table for cke (table 2) current state cke n - 1 cke n cs ras cas we dsf address action note h x x x x x x x invalid l h h x x x x x exit self refresh ? abi after t rc 7 l h l h h h x x exit self refresh ? abi after t rc 7 l h l h h l x x illegal l h l h l x x x illegal l h l l x x x x illegal self refresh l l x x x x x x nop(maintain self refresh) h x x x x x x x invalid l h h x x x x x exit power down ? abi 8 l h l h h h x x exit power down ? abi 8 l h l h h l x x ill egal l h l h l x x x illegal l h l l x x x x illegal both bank precharge power down l l x x x x x x nop(maintain power down mode) h h x x x x x x refer to table 1 h l h x x x x x enter power down 9 h l l h h h x x enter power down 9 h l l h h l x x illeg al h l l h l x x x illegal h l l l h x x x illegal h l l l l h l x enter self refresh 9 h l l l l l x x illegal all banks idle l l x x x x x x nop h h x x x x x x refer to operations in table 1 h l x x x x x x begin cl ock suspend next cycle 10 l h x x x x x x exit clock suspend next cycle 10 any state other than listed above l l x x x x x x maintain clock suspend abbreviations : abi = all banks idle note: 7. after cke?s low to high transition to exit self refresh mode. and a time of t rc (min) has to be elapse after cke?s low to high transition to issue a new command. 8. cke low to high transition is asynchronous as if restarts internal clock. a minimum setup time ?tss + one clock? must be satisfied before any command other than exit. 9. power - down and self refresh can be entered only from the all banks idle state. 10. must be a legal command.
A45L9332A series preliminary (october, 2001, version 0.1) 52 amic technology, inc. ordering information part no. cycle time (ns) clock frequency (mhz) access time package A45L9332Af - 6 6 166 5.5 ns @ cl = 3 100 qfp A45L9332Ae - 6 6 166 5.5 n s @ cl = 3 100 lqfp A45L9332Af - 7 7 143 6.0 ns @ cl = 3 100 qfp A45L9332Ae - 7 7 143 6.0 ns @ cl = 3 100 lqfp A45L9332Af - 8 8 125 6.5 ns @ cl = 3 100 qfp A45L9332Ae - 8 8 125 6.5 ns @ cl = 3 100 lqfp * qfp (height = 3.0mm max) lqfp (height = 1.4mm max)
A45L9332A series preliminary (october, 2001, version 0.1) 53 amic technology, inc. package information qfp 100l outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min. nom. max. min. nom. max. a 1 0.004 - - 0.100 - - a 2 0.107 0.112 0.117 2.723 2.85 2.977 b 0.010 - 0.014 0.26 - 0.36 c 0.0057 0.006 0. 0063 0.142 0.150 0.158 h e 0.905 0.913 0.921 22.950 23.200 23.450 e 0.783 0.787 0.791 19.900 20.000 20.100 h d 0.669 0.677 0.685 16.950 17.200 17.450 d 0.547 0.551 0.555 13.900 14.000 14.100 e 0.020 0.026 0.032 0.500 0.650 0.800 l 0.025 0.031 0.037 0. 650 0.800 0.950 l 1 0.057 0.063 0.069 1.450 1.600 1.750 y - - 0.004 - - 0.100 q 0 - 8 0 - 8 notes: 1. dimensions d and e do not include mold protrusion. 2. dimensions b does not include dambar protrusion. total in excess of the b dimension at maxim um material condition. dambar cannot be located on the lower radius of the foot. 31 50 51 80 81 100 h d d e h e 1 30 b d y a 1 a 2 l 1 c e q l
A45L9332A series preliminary (october, 2001, ve rsion 0.1) 54 amic technology, inc. package information lqfp 100l outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min. nom. max. min. nom. max. a 1 0.002 - - 0.05 - - a 2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.011 0.013 0.015 0.27 0.32 0.37 c 0.005 - 0.008 0.12 - 0.20 h e 0.860 0.866 0.872 21.85 22.00 22.15 e 0.783 0.787 0.791 19.90 20.00 20.10 h d 0.624 0.630 0.636 15.85 16.00 16.15 d 0.547 0.551 0.555 13.90 14.00 14.10 e 0.026 bsc 0.65 bsc l 0.018 0.024 0.030 0.45 0.60 0.75 l 1 0.039 ref 1.00 ref y - - 0.004 - - 0.1 q 0 3.5 7 0 3.5 7 notes: 1. dimensions d and e do not include mold protrusion. 2. dimensions b does not include dambar protrusion. total in exce ss of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. 31 50 51 80 81 100 h d d e h e 1 30 b d y a 1 a 2 l 1 c e q l

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