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| ps000902-0501 z02201 1 p roduct s pecification z02201 1 v.22 bis d ata p ump with i ntegrated afe features ? combined data pump and analog front-end (afe) ? full duplex data modem throughput to 2400 bps C itu v.22bis, v.23, v.22, v.21 C bell 212a and bell 103 ? fsk (v.23 1200/75 bps, v.21/bell 103 300 bps), dpsk (v.22/bell 212a 1200 bps), or qam encoding (v.22bis 2400 bps) ? automatic handshake plus full manual control over handshake timings ? scrambler/descrambler functions plus selectable control over internal data pump functions ? programmable bi-quad tone detectors for call-progress tone detection ? adaptive equalization to compensate for a wide variety of line conditions ? programmable transmit attenuation and selectable receive threshold ? fully programmable call-progress detectors, signal quality detectors, tone detectors, tone generators, and transmit signal levels which aid in rapid country qualifi- cations ? simultaneous tone generation and detection ? host port allows direct parallel interface to standard 8-bit microprocessors ? hdlc framing at all speeds ? on-chip peripherals C full-duplex voice band afe with 12-bit resolution C synchronous serial interface port C eye pattern interface ? low power consumption: 50 ma typical ? 44-pin plcc package ? single +5 vdc power supply ?0 c to +70 c commercial temperature range note: international telecommunications union (itu), former- ly ccitt. general description the z02201 is a synchronous single-chip modem solution that provides a means to construct a v.22bis modem capable of 2400 bps full duplex over dial-up lines. the z02201 is specifically designed for use in embedded modem applications where space, performance, and low power consumption are key requirements. operating over the public switched telephone network (pstn), the z02201 meets the modem standards for v.22bis, v.22, v.23, v.21, bell 212a, and bell 103. a typical modem application can be made by simply adding a control microprocessor (host), phone-line interface, and dte interface. the z02201 performs hdlc framing at all speeds. this capability eliminates the requirement for an external serial input/output (sio) device for data terminal equipment (dte) in products incorporating error control. device data pumpafe speed (mhz) z02201 16-bit integrated 12.288
z02201 v.22bis data pump with integrated afe zilog 2 z02201 ps000902-0501 all modulation, demodulation, filtering, a/d and d/a conversion functions for transmit and receive are provided on- chip. automatic and selectable compromise equalizers are included to optimize performance over a wide range of line types. the z02201 device compensates for a wide variety of adverse line conditions by using a combination of fixed link, fixed cable, and adaptive equalizers. the z02201 provides comprehensive selectable and programmable tone generation and detection. all digital i/o signals are ttl compatible. the parallel interface is compatible with standard 8-bit microprocessors, allowing direct access to eight i/o registers and indirect access to the modem ram. the ram access capability allows the host to retrieve diagnostic data, modem/line status and control data, and set programmable coefficients. the serial interface is used for data transfers. all control and status information is transferred by means of the parallel interface. the z02201 transmit drivers and receive amplifiers can be connected directly to a data access arrangement (daa) by means of a transformer. completing this connection reduces the external circuits to a minimum. in addition, the z02201 offers further system level savings by providing built-in filters for both the transmitter analog output and the receiver analog input, thus eliminating the need for external filtering components. the z02201 device operates on a single +5 vdc power supply. during periods of no traffic, the host can place the modem into sleep mode, reducing power consumption to less than 1 percent of full load power. note: all signals with an overline , are active low. for exam- ple, b/w , in which word is active low; or b /w, in which byte is active low. power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 3 figure 1. z02201 block diagram a/d converter d/a converter eye pattern interface digital processor hd7?d0 ha2?a0 hcs hwr hrd hirq parallel interface txd rxd rts rlsd oscillator serial signal rxi+ rxi txo txo+ extal xtal eyeout eyeclk eyestb reset tclk rclk interface 8k rom oh z02201 v.22bis data pump with integrated afe zilog 4 z02201 ps000902-0501 user information the zilog z02201 data pump can be selected for either parallel or serial synchronous data transfer under software control. figure 2 indicates a block diagram of the general modem chip interface. the hardware and software configurations can be customized for a particular modem application. the parallel interface allows direct access to 7 i/o registers, indirect access to the modem ram, and is compatible with the z8, z80, z18x family, and other 8-bit microprocessors. the serial interface is used for data transfer. controls and status information are transferred via the parallel interface. the ram access capability allows indirect access to diagnostic data, additional status control, and programmable coefficients. the hardware and software interfaces are presented in the subsequent sections. figure 2. z02201 system block diagram host processor parallel z02201 eye pattern interface line interface oscilloscope telephone line data access arrangement serial dte speaker (optional) (optional) (optional) z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 5 figure 3. z02201 44-lead plcc pin identi?ation pin description z02201 plcc 7 av dd tx0+ tx0 a gnd vref a gnd cf1 cf2 rxi rxi+ avdd oh txd tclk rxd rlsd hd7 hd6 hd5 hd4 hd3 hd2 hcs ha0 ha1 ha2 hirq hwr v dd hrd gnd hd0 hd1 eyestb eyeout eyeclk test1 gnd reset v dd extal xtal test2/rclk r ts 1 28 18 40 39 6 table 1. z02201 modem pin assignments pin no. symbol direction 1 reset input 2 gnd 3 test1 input 4 eyeclk output 5 eyeout output 6 eyestb output 7av dd 8 tx0+ analog output 9 tx0 analog output 10 a gnd 11 vref analog output 12 a gnd 13 cf1 analog input 14 cf2 analog input 15 rxi analog input 16 rxi+ analog input 17 av dd 18 hcs input 19 ha0 input 20 ha1 input 21 ha2 input 22 hirq output 23 hwr input 24 v dd 25 hrd input 26 gnd 27 hd0 input/output 28 hd1 input/output 29 hd2 input/output 30 hd3 input/output 31 hd4 input/output 32 hd5 input/output 33 hd6 input/output 34 hd7 input/output 35 rlsd output 36 rxd output 37 tclk output 38 txd input 39 oh output 40 r ts input 41 test2/rclk input/output 42 xtal output 43 extal input 44 v dd table 1. z02201 modem pin assignments pin no. symbol direction z02201 v.22bis data pump with integrated afe zilog 6 z02201 ps000902-0501 pin functions hd7 hd0 host data bus (bidirectional, active high). hd0 hd7 constitutes an 8-bit bidirectional data bus used for the transfer of control and status information. hcs host chip select (input, active low). when cs is low, data transfer between the data pump and the host is enabled. data transfers to the data pump registers are 8 bits wide. hwr host write enable strobe (input, active low). the write enable strobe is an active low signal that is used to initiate a write operation to the data pump. during a write operation, data is sent to the data pump by the host via the host data bus. hrd host read enable strobe (input, active low). the read enable strobe is an active low signal that is used to initiate a read operation from the data pump. during a read operation, data is transferred out of the data pump by the host via the host data bus. hirq host interrupt request (output, active low). the hirq is an open-drain output that can be tied through an external pull-up resistor to the digital power supply v dd . the hirq active low data pump output can be activated when the host selects this option or requests by setting the rxie or txie bits in the data pump host register. this pin can be connected to the host interrupt request pin to initiate host service. reset reset (input, active low). the reset signal places the device into its reset state. ha2 ha0 host address (input, active high). these three register select lines (pins) are used for addressing the controller-accessible internal registers of the data pump. when hcs is active, the state of the ha2 ha0 is used as the internal data pump interface register address. ha2 is the most significant bit; ha0 is the least significant bit. rlsd receive line signal detect (output, active low). this pin indicates when an input signal has been detected. rxd receive data (output). the data pump serial receive data is presented by the data pump to the local dte on the rxd output. tclk transmit serial data clock (output). the serial data output clock is a synchronous data clock used to transfer serial data via synchronous serial interface between the data pump and the host. the clock frequencies are 2400, 1200, and 300 hz, corresponding to the supported data bit rates. txd transmit data (input). the data pump accepts the serial transmit data from the local dte on the txd input when the data pump is configured to the serial transmit data mode. the serial transmit data mode is selected when the tdpm bit (bit 4) of the ram control/data pump status register (register 6) is reset to 0. oh off hook relay control (output, active low). this pin is activated to drive a relay which engages the modem with the phone line (the modem equivalent of picking up the receiver). rts request to send (input, active low). the logical or of this pin and the rtsp bit (bit 3 of register 4), determines the data pump mode of operation. when the result of the logical or of these two bits is logic 1 , then the data pump is in transmit mode at the selected speed, thereby placing the data pump in receive mode. in standby mode, the state of this pin is insignificant. eyeclk eye pattern clock (output, active high). data is valid at the rising edge of the clock. the eyeclk can be used to clock an external digital-to-analog (d/a) converter shift register for eye pattern display. eyeout eye pattern data (output, active high). this pin controls the serial 16-bit eye pattern output data. the first 8 bits is the eyex data, and the next 8-bits are the eyey data. this data can be used for display on an oscilloscope x and y-axis following d/a conversion. eyestb serial eye pattern strobe (output, active high). this signal is used for loading an external d/a converter. txo+ transmit differential analog output positive (analog output). the txo+, txoC is capable of driving a 600-ohm resistive load over a leased line or public switched telephone network via a data access arrangement (daa). the txoC and txo+ can be configured either as a differential or single-ended output driver. txo transmit differential analog output negative (analog output). the txoC, txo+ is capable of driving a 600-ohm resistive load over a leased line or public switched telephone network via a data access arrangement (daa). z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 7 rxi receive differential analog input negative (analog input). rxi+ receive differential analog input positive (analog input). test1 test pin 1 (input, active high). this pin is a test pin and must be tied to digital ground. test2/rclk test pin 2, receive data clock (output, active high). this pin is a test pin and must be tied to digital ground through a pull-down resistor. the resistor should be low enough to ensure this pin floats below 0.8v when the part is in the reset state. after reset , this pin becomes the receive data clock output. the resistor should be high enough such that the output can be driven to logic 1 . this pin is a synchronous data clock used to transfer serial data between the data pump and the host. the clock frequencies are 2400, 1200, and 300 hz corresponding to the supported data bit rates. vref reference voltage (output, active high. an internally generated reference voltage. xtal crystal (output, active high). crystal oscillator connection. this pin must be left open if an external clock is used instead of a crystal. the data pump chip can be connected to an external crystal circuit consisting of 24.576-mhz (parallel resonant) crystal, a resistor, and two capacitors. extal external clock/ crystal (input, active high). crystal oscillator connection. an external clock can be input to the z02280 on this pin when a crystal is not used. the oscillator input is not a ttl level (see dc characteristics in table 4). cf1 and cf2 integration capacitor pins 1 and 2 (analog input). connect an 82pf capacitor between cf2 and cf1 to complete the internal feedback integration filter for improved analog-to-digital (a/d) conversion performance. gnd digital ground 0 volts . v dd digital power 5 volts . av dd analog power 5 volts . agnd analog ground 0 volts . z02201 v.22bis data pump with integrated afe zilog 8 z02201 ps000902-0501 absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this rating is a stress rating only. operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. standard test conditions the dc parameters were tested as per table 4. the z02201 tester has active loads which are used to test the loading for i oh and i or. available operating temperature range is: where: s = standard temperature range s = 0 c to +70 c environmental and power requirements the modem power and environmental requirements are indicated in tables 2 and 3. symbol description min max units v cc supply voltage 0.3 +7.0 v t opr (com) operating temperature 0 +70 c t stg storage temperature 65 +150 c voltage current typical @ 25 c current maximum @ 0 c +5 v dc , operating 50 ma <=100 ma +5 v dc , sleep 25 a <=125 a note: all voltages are 5% dc and must have ripple less than 0.1v peak to peak. if switching supply is used, the fre- quency may be between 20 khz and 150 khz. no component of the switching frequency should be present outside of the supply greater than 500 v peak. table 2. environmental requirements parameter value ambient temperature under bias (commercial temp range) 0 c to +70 c storage temperature 65 c to +150 c voltage on any pin to v ss 0.3v to +7v power dissipation 250 mw soldering temperature 0.5 sec +230 c table 3. crystal speci cation (required) for crystal used with z02201) parameter value temperature range (commercial) 0 c to +70 c nominal frequency @ 25 c 24.576 mhz frequency tolerance @ 25 c 20 ppm temperature stability @ 0 c to 70 c 25 ppm calibration mode parallel resonant shunt capacitance 7 pf max. load capacitance 32 0.3 pf drive level 1.0 mw max. aging, per year max. 5 ppm oscillation mode fundamental series resistance 60 ohms max. max. frequency variation with 28.8 or 35.2 pf load 30 ppm z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 9 dc characteristics table 4. tdc pin characteristics parameter description min typ max units test conditions pin types i and i/o: input and input-output v ih input high voltage 2 v cc +0.3 v v il input low voltage 0 0.8 v i l input leakage current 10 10 a gnd z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 11 figure 5. serial port timing diagram table 6. serial interface timing description parameter min typ max units rxd data valid delay time 1 12 ns txd data setup time 2 100 ns txd data hold time 3 100 ns 1 3 2 dclk txd rxd z02201 v.22bis data pump with integrated afe zilog 12 z02201 ps000902-0501 timing diagrams figure 6. eye pattern port timing diagram table 7. analog characteristics table description parameter min typ max units input impedance of transformer interface 1 400 1200 ohm 3 db point of interface 2 21 26.5 32.5 khz external integration capacitance type npo (cog) 3 738290pf eyeclk d15 (msb eyex) d0 (lsb eyey) eyestb eyeout z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 13 analog inputs: type ai these characteristics below are provided for information only. they are not tested except in the functional test vectors. analog outputs: type a0 ac characteristics sym min typ max units input impedance (dc to v ref )z in 15k 25k ? power supply rejection p srr i 40 db input current l i 80 80 a idle channel noise (3950 hz bandwidth) i cni 72 dbm signal to distortion s tdi 30 db characteristics sym min typ max units input capacitance c in 10 pf input bias v dcoff +2.5 v analog input voltage (peak differential), (23) v pki 2.362 +2.362 v analog input voltage (per rxi+. rxi- pin) v pkip 1.181 +1.181 v ac characteristics sym min typ max units power supply rejection p srro 40 db signal to distortion s td0 35 db idle channel noise (3950 hz bandwidth) i cno 72 dbm out of band noise n qo dbm 4 8 khz 20 dbm 8 12 khz 40 dbm 12 khz and above in 4 khz bandwidths 55 dbm characteristics sym min typ max units output impedance zout 0.80 ? output capacitance cout 10 pf analog output voltage (peak differential), (24) vpko 2.375 +2.375 v load impedance (25) zi 400 600 z02201 v.22bis data pump with integrated afe zilog 14 z02201 ps000902-0501 hardware interface signals the z02201 interface consists of the synchronous serial interface port, 8-bit host microprocessor interface, eye pattern interface, voice band afe, system signals, and overhead signals. the z02201 functional interconnect diagram is indicated in figure 7. any signal that is active low is represented by a line over the signal name. synchronous serial interface port the synchronous serial interface port provides no parallel- to-serial/serial-to-parallel conversion hardware. the synchronous serial interface port consists of six signal pins: host port interface the host parallel port interface consists of 15 signal pins: 8-bit bidirectional data bus pins ( hd7 C hd0 ), 3-bit address bus ( ha2 C ha0 ), four control lines, which include the ho st read ( hrd ), host write ( hwr ), host chip selec t ( hcs ), and host interrupt request ( hirq ). multiple interrupt sources are provided in the z02201, each of which can be masked under host control. the host parallel interface allows the host to access the data pump ram address and data bits, transmit and receive data, control the ram and status bits, and read data pump status bits. the host can access eye pattern functions, transmit and receive tones, and access adaptive equalizer coefficients in modem-type applications. the host parallel interface is compatible with standard 8- bit microprocessors, which include the z8 and z80 bus. eye pattern interface the eye pattern interface consists of three pins: eye pattern data ( eyeout ), eye pattern clock ( eyeclk ), and eye pattern strobe ( eyestb ). sixteen bits of data are serially transmitted via eyeout , under control of eyestb and eyeclk . the first byte is the x-coordinate and the second byte is y-coordinate of the sample. the least significant bit is presented first for both figure 7. modem functional interconnect diagram rxi+,rxi txo+,txo oscilloscope data access arrangement eye pattern interface dgnd (2) agnd (2) +5avdd (2) +5vdd (2) optional optional eye pins (3) d(0:7) crystal oscillator rs(0:2) control z02201 2 synchronous serial interface 8 3 4 6 reset xtal1 xtal2 crystal oscillator pstn host processor dte (host) oh pin signal name txd transmit data rxd receive data rts request to send rlsd receive line signal detect tclk transmit data clock rclk receive data clock z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 15 the x and y coordinates. a schematic of an eye pattern circuit is found in figure 14 at the end of this specification. the eye pattern data , eyeout , outputs a serial bit stream containing data for display of the eye pattern on an oscilloscope after d/a conversion. 8 bits of the x-axis data and 8 bits of the y-axis are output as a single 16-bit data stream with the x-axis data first. eyeout is synchronous with the rising edge of eyeclk . eyeout is valid only while the eyestb is low. data is shifted out msb first. data on eyeout is shifted out on each rising edge of the 1.536mhz eyeclk . eyeout data is valid on the following edge of the eye pattern clock , eyeclk . the eyeout data is valid when the eye pattern strobe , eyestb , is low. eyestb changes state on the rising edge of eyeclk . technical specifications configurations and data rates table 8 provides the selectable options, supported data rate, baud rate, and the modulation method. tone generation and tone detection the z02201 provides comprehensive and flexible tone generation and detection, including all tones required to establish a circuit connection and to setup and control a communication session. the tone generation furnishes the dtmf tones for pstn auto dialing, and the supervisory tones for call establishment. the tone detection provides support for call-progress monitoring. the detector can also be user-programmed to recognize up to 16 tones. data encoding the data encoding for the z02201 meets both ituCt recommendations and bell standards. transmitted data spectrum the transmitted data spectrum, with compromise equalization disabled, is shaped in the baseband by the finite impulse response (fir) filter. table 9 reflects the spectrum characteristics. table 8. selectable con gurations con guration 1 modulation 2 carrier freq. data rate (bps) symbol rate (baud) bits per symbol constellation points v.22 bis 2400 qam 1200/2400 2400 600 4 16 v.22 bis 1200 dpsk 1200/2400 1200 600 2 4 v.22 1200 dpsk 1200/2400 1200 600 2 4 v.23 1200/75 fsk 1700/420 1200/75 1200/75 1 v.21 fsk 1080/1750 300 300 1 bell 212a dpsk 1200/2400 1200 600 2 4 bell 103 fsk 1170/2125 300 300 1 notes: 1. configuration is selected through the ram location config. 2. qam=quadrature amplitude modulation fsk=frequency shift keying, dpsk=dual phase shift keying table 9. spectral shaping mode carrier freq spectral power shaping function v.22 1200 sqrt 75% raised cosine at 600 baud v.22bis 2400 sqrt 75% raised cosine at 600 baud note: the carrier and the spectral shaping are selected automatically according to the configuration. z02201 v.22bis data pump with integrated afe zilog 16 z02201 ps000902-0501 transmit levels the transmit output level of the z02201 is programmable in 1 dbm decrements from C6 dbm to C43 dbm. with a default value of C10 dbm, the z02201 is measured differentially across pins tx0+ and tx0C with a sinusoidal waveform. note: to avoid saturation, the tx level should be set to C6 dbm or lower by the host. if a higher transmit level is required, additional op amps may be added during operation. receiver levels the timing recovery circuit can track a 0.01% (100 ppm) frequency error in the associated transmit timing source with less than 1.0 db degradation in performance. clamping received data ( rxd ) is clamped to a constant mark whenever rlsd is off . software interface note: this section refers to the version 0x48 of the datapump firmware. for various versions of the datapump and the differences in firmware refer to the addendum of the product specification. the host microprocessor communicates with the z02201 via the parallel microprocessor bus interface. access is provided to a set of seven 8-bit interface registers, and through these registers, to z02201 ram memory locations. this interface allows the host to request modem status information and receive data, control the configuration, and load data for transmit. table 10 is the parallel interface register map. microprocessor interface register and bit definitions: reg0, reg1 ramdl, ramdh data pump ram data registers. in this case, ramdl is the least significant byte, and ramdh is the most significant byte. after a data pump ram read operation has completed, these registers contain the requested data. when a data pump ram write operation is started, these registers contain the data written to data pump ram. reg2 ramal data pump ram data address. when a data pump ram read or write operation is started, this byte contains the lower 8 bits of the ram address. register 4 (ramah) is the high bit of the ram address. reg3 datap data pump parallel data. this register contains data transferred to or from the remote modem during the parallel modem (see register register 4, bit 4). at any reset, when config register bits 0C6 ( mode ) is 0 ( standby ), the data pump places its firmware version number in register datap . table 10. parallel interface register map function register number rs2 0 b2b1b0 msb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb bit 0 access method ram access low 0 000 ramdl r/w ram access high 1 001 ramdh r/w ram access address 2 010 ramal w parallel data 3 011 datap r/w ram control & status 4 100 txle rxle ramle tpdm rtsp ramrw ramrq ramah r/w modem status 5 101 txi rxi raml dpbusy reserved rtrnd cdet res r hdlc 7 111 0 0 0 0 0 tend rxerr eof r/w z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 17 table 11. reg4: ram control register symbol position name and description ramah reg 4, bit 0 ram address high bit. the most signi cant bit of the data pump ram address. this bit is set to 1 when accessing a data pump ram address that is greater than 255, or set to 0 for any value below 255. ramrq reg 4, bit 1 data pump ram access request bit. set this bit to 1 to request a read or write of the data pump ram. the data pump sets this bit to 0 when the request has been ful lled. ramrw reg 4, bit 2 data pump ram read/write bit. set this bit to 0 to request a read of the data pump ram or a 1 to request a write of data pump ram. rtsp reg 4, bit 3 register request to send bit. a logical or operation is executed using the value of the hardware rts signal received by the data pump on the rts pin. the host sets rts or rtsp to 1 to inform the data pump the host is transmitting data. to control the data pump using the rts signal, set rtsp to 0. to control the data pump using rtsp, hold rts high. tpdm reg 4, bit 4 select parallel data mode. setting this bit selects the parallel data mode. resetting it selects the serial data mode. ramle reg 4, bit 5 ram interrupt enable bit. setting this bit allows the data pump to interrupt the host when a ram read/write request has been completed. rxle reg 4, bit 6 receive data interrupt enable bit, parallel data mode only. this bit, when set, causes the data pump to generate an interrupt whenever the rxi bit is set. txle reg 4, bit 7 transmit data interrupt enable bit, parallel data mode only. this bit, when set, causes the data pump to generate an interrupt whenever the txi bit is set. note: all the bits in this register (reg 4) default to logic 0 at power-up or after reset sequences are completed. bit txie rxie ramie 76 5 4 3 21 0 tpdm ramrw ramrq ramah rtsp z02201 v.22bis data pump with integrated afe zilog 18 z02201 ps000902-0501 table 12. reg5: data pump status register symbol position name and description res reg 5, bit 0 data pump in reset mode. this bit is set whenever the data pump is in reset mode because of a hardware reset or power-on. the data pump sets res to 0 when it completes the reset cycle. cdet reg 5, bit 1 carrier detect. the data pump sets cdet to 1 when it enters any data mode and is ready to transmit data. the data pump sets cdet to 0 during retrains (see reg5, bit 2, rtrnd), and when no signal is detected from the remote modem. see locations rlsdonthresh and rlsdoffthresh for more information. cdet is inverted and re ected on the data pump s rlsd pin. if cdet is 1, rlsd is low (asserted). at any reset, or when the host sets config register, bits 0C6 ( mode ) to 0 (standby), the data pump sets cdet to 0. rtrnd reg 5, bit 2 retrain detect, 2400 bps (v.22bis data mode only). the retrain sequence is detected when this bit is set. the data pump has detected a retrain request sequence from the remote modem. reserved reg 5, bit 3 reserved bit location. dpbusy reg 5, bit 4 data pump busy. this bit is set whenever the data pump starts transmitting data and rtsp is 1. when the link is to be terminated, setting rtsp to 0 causes this bit to be reset after the data pump has nished transmitting the most recent data in its internal buffers. when this bit has been reset, it is safe to set con g. register, bits 0 6 (mode) to standby mode (0) and hang up the telephone, terminating the connection. this bit also indicates when digits are being dialed during timed dialing operation. at any reset, or when the host sets con g register, bits 0 6 ( mode ) to 0 (standby) the data pump sets dpbusy to 0. this bit is not valid during hdlc operation. raml reg 5, bit 5 data pump ram interrupt status. this bit is set when the data pump has processed a ram read/write request. rxl reg 5, bit 6 receive interrupt status. this bit is set when the data pump is in parallel data transfer mode (tpdm is 1) and the data pump has written a new octet to the datap register. a read from the datap register clears this bit. txl reg 5, bit 7 transmit interrupt status. this bit is set when the data pump is in parallel data transfer mode (tpdm is 1) and the data pump has read the datap register. a write to the datap register clears this bit. note: the rxi bit is set to 1 after the reset sequences. all other bits in this register (reg. 5) default to 0 at power up or after reset sequences are completed. bit 76 5 4 3 21 0 txi rxi rami dpbusy rtrnd cdet res reserved z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 19 reg7 data pump register 7. these bits represent the state of hdlc frames when the data pump is in the hdlc framing mode. these bits are valid only if bufctrl. bit 7 (hdlc) is 1 . the host should refrain from writing reg7 to avoid changing the values of bit fields set by the data pump. bits not defined above are reserved or not available for use. the host reads register reg7 immediately before datap . the two crc checksum bytes in received hdlc frames are provided to the host. at any reset, or when the host sets config register, bits 0C6 ( mode ) to 0 ( standby ) the data pump sets tend to 0 , rxerror to 0 , and eof to 0 . table 13. reg7: hdlc register symbol position name and description eof reg 7, bit 0 receive end of frame . the data pump sets eof to 1 when an hdlc frame has been completely received (that is, when frame data has been received and a closing hdlc ag or hdlc abort condition is received). if the frame was correctly received, the data pump also sets reg5, bit 1 (rxerror) to 0, reg5, bit bit 6 (rxi) to 1, and datap to 7eh. see reg7, bit 1 (rxerror) for a description of crc errors and hdlc aborts. eof re ects whether the current register datap value indicates the end of receipt of an hdlc frame. when the rst data byte of the next hdlc frame is received, or if an hdlc abort condition is received when no hdlc frame data was received, the data pump sets eof to 0. this condition may occur only 8 bit times after the data pump sets eof to 1. rxerr reg 7, bit 1 receive error. if an hdlc frame contains a crc error, or an hdlc abort condition is received, the data pump sets rxerror to 1, reg5, bit 6 (rxi) to 1, and datap to the value of 7eh or ffh. if the frame had a crc error, datap has the value of 7eh. if an hdlc abort condition was received, datap is ffh. rxerror re ects whether the current register datap contains an error. when the rst data byte of the next hdlc frame is received, the data pump sets rxerror to 0. this condition may occur only 8 bit times after the data pump set rxerror to 1. tend reg 7, bit 2 transmit end of frame . the data pump sets tend to 1 when it closes an hdlc frame that is transmitted. the data pump sets tend to 0 after transmitting the crc bytes, when it starts transmitting the closing ag of the hdlc frame. the data pump closes an hdlc frame when the host does not provide data to transmit (see datap) in time to be included in the hdlc frame. 0 reg 7, bits 3 7 unused. set these bits to 0. note: 1. all the bits in this register (reg 7) default to 0 at power up or after reset. 2. all undefined bits of this register are reserved. the host writes a 0 to all reserved bit positions when writing this registe r. the host ignores the reserved bits when reading this register. bit 0 0 0 76 5 4 3 21 0 0 tend rxerr eof 0 z02201 v.22bis data pump with integrated afe zilog 20 z02201 ps000902-0501 rami, rxi, and txi interrupts the three most significant bits in the ram control and data pump status registers define the interrupt masks for rami , rxi , and txi . a logical and operation is performed with the ramie , rxie , and txie enable bits of the ram control register and the corresponding interrupt bits in the data pump status register. then, a logical or operation is performed on the outputs driving the hirq pin, providing an interrupt to the host interrupt (see figure 8). interface ram the interface ram is used by the data pump for normal operations. all writes to the interface ram should be read- modify-write, where only the bits that must be changed are affected. all undocumented bits are reserved and must be left intact. notes: 1. data pump ram reads or writes requires ap- proximately 0.1 msec to complete. 2. data pump ram writes take effect at different times, depending upon the location being written to. during data modes, writes typically take ef- fect at the end of the next baud period. during other modes of operation, writes take effect in 0.1 msec. 3. writing reg4, for example, to set reg4, bit 7 (txie) to 0 in an interrupt handler while waiting for the data pump to set reg4, bit 1 (ramrq) to 0 in the background, may cause unwanted side ef- fects. setting reg4, bit 1 (ramrq) to 1 may cause the data pump to repeat the read/write re- quest if the data pump had just set reg4, bit 1 (ramrq) to 0; however, setting reg4, bit 1 (ramrq) to 0 may abort the ram read/write re- quest. data pump interface ram access method to write to the data pump ram: 1. write data to ramdl & ramdh . 2. write the lower 8 bits of the address of the data pump ram location to register ramal . 3. with one write operation to register r4, set the high bit of the data pump ram address in r4, ramah , set r4, bit 2 ( ramrw ) to 1 , and set r4, bit 1 ( ramrq ) to 1 . 4. wait until the data pump sets r4, bit 1 ( ramrq ) to 0 . to read from data pump ram: 1. write the lower 8 bits of the address of the data pump ram location to register ramal . 2. with one write operation to register r4, set the high bit of the data pump ram address in r4, ramah , set r4, bit 2 ( ramrw ) to 0 , and set r4, bit 1 ( ramrq ) to 1 . 3. wait until ramrq is reset to 0 by the data pump or until ramie is set to 1 . 4. read data from ramdl and ramdh . reads and writes to the data pump ram may require 105 s to complete. figure 8. host interrupt circuit diagram ramie rami rxie rxi txie txi hirq z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 21 modem data pump ram map table 14. modem data pump ram map mnemonic address (hex) access mode description con g 01ff r/w data pump con guration trnctrl 01fe r/w training control bufctrl 01fd r/w buffer control tonestatus 01fc r/w dtmf and tone control status dpctrl 01fa r/w data pump miscellaneous controls mstatus 01f7 r/w modem control and status eqmmaxthresh 01f6 r/w mse maximum threshold rlsdoffthresh 01f5 r/w rlsd off threshold rlsdonthresh 01f4 r/w rlsd on threshold conn_mode 01f0 r/w connection speed after handshake is complete notch 01a2 01a6 r/w notch filter coef cients dtmfh_lev 01a1 r/w dtmf high band transmit level dtmfl_lev 01a0 r/w dtmf low band transmit level tonegena 0191 r/w tone generator a tonegenb 0196 r/w tone generator b txlevel 0185 r/w modem transmit level seq3count 18e r/w dial timer inter-pulse count seq2count 18d r/w dial timer off count seq1count 18c r/w dial timer on count biquada 0155 015e r/w biquad a coef cient biquadb 015f 0168 r/w biquad b coef cient dtd0 dtd15 0145 0154 r/w tone detector coef cients eqmlev 092 r/w eye quality monitor level biquadoffthresh 052 r/w biquad detectors off point biquadonthresh 051 r/w biquad detectors on point dtd0lev dtd15lev 026 035 r/w tone detector levels dtdthresh 03 r/w tone detector threshold dtdstatus 00 r/w discrete tone detector status z02201 v.22bis data pump with integrated afe zilog 22 z02201 ps000902-0501 interface ram definitions table 15. modem data pump word de nitions register & address (hex) default value function and explanation con g 01ff 0h data pump config register b15 unused. set this bit to 0. b14 org (set originate mode: all modes) if org is 1, then the modem is in originate mode. otherwise, it is in answer mode. be sure to set org before or at the same time as con g register, bits 0 6 (mode ) , not afterwards. b13 error (data pump error: all modes) this bit is set to 1 when the data pump detects an internal error condition such as an invalid con g code. the host should reset the data pump. b12 reserved b11 reserved b10 mcuctrl (manual handshake: v.22/v.22bis/b212a) this bit allows the host to control the handshake process in v.22bis. (see manual handshake procedures on page 1-38 for more information). b9 reserved b8 sreset (soft reset: all modes) set this bit to soft reset the data pump. the data pump sets sreset to 0 when the software reset completes. b7 unused. set this bit to 0. b0 6 mode (data mode con guration: selects a mode) selects the data pump operation mode. all modes unlisted below should be considered reserved. the host should read mode, one time after writing it, to allow the data pump enough time to begin operation in the new mode. setting mode to 0 (standby) starts the idle mode of operation, not the power-saving sleep mode. data mode speci ed 0 standby 1 transmit tones using both generators simultaneously 2 detect tones/biquads using all discrete tone detectors and biquad tone detectors simultaneously 3dial 4 simultaneous transmission of tones (mode 0x01) and detection of tones (mode 0x02) 8 v.22bis 2400 bps/1200 bps mode 9 v.22 1200 bps mode b bell 212a 1200 bps mode 10 v.21 300 bps mode 11 bell 103 300 bps mode 13 v.23 1200 bps tx/75 bps rx mode 14 v.23 75 bps tx/1200 bps rx mode z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 23 trnctrl 01fe 0h training control register the data pump sets this location to its default value at any reset and when the host sets con g register, bits 0 6 (mode) to 0 or to any data mode. this ram location controls the handshake process during a manual training process (see manual handshake procedures on page 1-38 for an example on the use of this interface). this ram location has no effect when data mode is entered (trnctrl is set to 5 or 6). b7 sb1det scrambled binary 1 detected (1200 bps or 2400 bps). debounced through 30 ms. b6 s1det s1 detected. debounced through 27 ms b5 usb1det unscrambled marks detected (1200 bps) b4 sb0det scrambled binary 0 detected (1200 bps or 2400 bps) b3 v22bis force 16 way decisions. b0 2 txctrl transmitter control. set txctrl to control the output of the data pump, using the table below as a guide. the default frequency for the transmitted tone (txctrl is 7) is 2225 hz, and may be changed after setting txctrl by changing tonegena appropriately. the tone level is controlled by txlevel. value v.22/bell 212a/v.22bis sequence transmitted 0 silence: squelch transmitter 1 transmit unscrambled binary 1 at 1200 bps 2 transmit s1 signal 3 transmit scrambled binary 1 at 1200 bps 4 transmit scrambled binary 1 at 2400 bps 5 begin v.22, or bell212a, 1200 bps data mode 6 begin v.22bis 2400 bps data mode 7 transmit tone. the default frequency for the transmitted tone is 2225 hz, and may be changed after setting txctrl to 7 by changing tonegena approximately. the tone level is controlled by txlevel. value fsk (v.21/ bell 103/ v.23) sequence transmitted 0 silence: squelch transmitter 1 transmit marks (binary 1) 2 transmit spaces (binary 0) 5 begin fsk data mode 7 transmit tone. set the frequency to be transmitted by changing tonegena after setting txctrl is 7. the tone level is controlled by txlevel. table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation z02201 v.22bis data pump with integrated afe zilog 24 z02201 ps000902-0501 bufctrl 01fd 0h buffer control register b15..b8 set these bits to 0 when setting bufctrl.hdlc to 1. b7 hdlc (set hdlc mode: all data modes) set hdlc mode. when parallel data transfer mode is selected (tpdm is 1) and hdlc is set, the data pump transfers data using the synchronous hdlc mode. in serial mode (tpdm is 0), this bit has no effect. the host should set bits 8 15 to 0 when it sets this bit to 1. b3 scrdis (scrambler disable: v.22, v.22bis, bell 212a) set this bit to disable the transmitter scrambler. this action takes precedence over trnctrl/txctrl. b2 txmhld (hold tx output to marks: all modes) set this bit to force the data pump to transmit only marks to the remote modem, disregarding data received from the host. b1 dscrdis (descrambler disable: v.22, v.22bis, bell 212a). set this bit to disable the receiver descrambler. b0 rxmhld (hold rx output to marks: all modes) set rxmhld to 1 to cause the data pump to transmit only marks to the host, disregarding data received from the remote modem. table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 25 tonestatus 01fc 080h biquad tone detector control and status, dial control the data pump sets this location to its default value at any reset . b15 tonea (tone a detected) the tone frequency programmed in biquad detector a is detected if this bit is set. b14 toneb (tone b detected) the tone frequency programmed in biquad detector b is detected if this bit is set. b13 cascade biquad tone detectors a & b the two 4th-order biquad tone detectors can be cascaded to form a single 8th-order biquad tone detector if this bit is set by the host. the result of the cascaded biquad tone detector is available in tonestatus, bit 15. b7 tonedial (use dtmf to dial) this bit causes the data pump to use dtmf tone dialing when in dialing mode ( con g register, bits 0 6 (mode) is 3). b5 sqrdis (squarer disable) set sqrdis to 1 to cause the data pump to provide the output of biquad detector a directly to the input of biquad detector b, without rst squaring it. sqrdis is valid only when the biquad tone detectors are cascaded (see tonestatus, bit 13). b4 timedial (timed dialing) set timedial to 1 to cause the data pump to generate timed dtmf tones or pulse dialing. if timedial to 0, continuous dialing is used. b0 b3 dial digit the dtmf digit to be dialed is set here before con g is set for dtmf transmit. see the table below to determine how to set this parameter. for pulse dialing, only digits 0 through 9 are valid: digit value 00 11 22 33 44 55 66 77 88 99 *10 #11 a12 b13 c14 d15 table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation z02201 v.22bis data pump with integrated afe zilog 26 z02201 ps000902-0501 dpctrl 01fa 0h data pump miscellaneous controls do not modify this location during automatic handshake or retrain. the data pump sets this location to its default value at any reset . b15 txsqlch (squelch transmitter: all modes) b14 agcfrz (freeze autogain control: v.22/v.22bis/bell 212a) set to 1 to freeze agc adaptation. b13 reserved for internal use set to 0 when dpctrl is written by the host. b12 reserved for internal use set to 0 when dpctrl is written by the host. b10 11 leqtype (link equalizer type) set leqtype to 0 for a at line equalizer, or leqtype to 1 for a 3002 line equalizer. b9 gten (guard tone enable: v.22/v.22bis/bell 212a) this bit controls if a v.22/v.22bis/bell 212a link has a guard tone or not. if ia guard tone is set, the tone is transmitted along with the carrier. this bit must not be enabled in modes other than v.22, v.22bis, and bell 212a. this bit must be set prior to selecting the mode in the con g. register. b8 gtsel (guard tone select: v.22/v.22bis/bell212a) this bit selects the guard tone frequency: 0 is 550 hz, and 1 is 1800 hz. this bit must be set prior to selecting the mode in the con g. register. b4 eqe (eqmlev > eqmmaxthresh: v.22, v.22bis, bell 212a) the data pump sets eqe to 1 when eqmlev exceeds the threshold set in eqmmaxthresh. b3 eqfrz (freeze equalizer: all modes) set to 1 to freeze adaptive equalizer (aeq) adaptation. aeq coef cients are lost when a mode change (in the con g. register) occurs. b2 tspace (select t-spaced vs. t/2-spaced equalizer) this bit, when set, selects a t-spaced aeq. when reset, it selects a t/2 spaced aeq. v.22/v.22bis/bell 212a modes always use a t/2-spaced equalizer. table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 27 mstatus 0h modem control and status b11 retrain (force a retrain: v.22bis) when set, this bit forces a retrain if the data pump has a v.22bis connection. the cdet (register 5 bit 1) bit is set to 0 when the retrain begins. the cdet bit is set to 1 when the retrain is complete. the data pump sets retrain to 0 when the retrain procedure begins and when the host sets config register, bits 0 6 ( mode ) to any data mode. b2 offhook (enable off-hook relay) the data pump sets the oh signal to the inverted value of this bit. for example, when offhook is 1, the data pump sets oh low. when oh is low, the off-hook relay closes for the signal from the telephone line to be presented to the data pump. the data pump sets offhook to 1 when the host sets config register, bits 0 6 (mode) to 3 (dial), or to any data mode. the data pump sets offhook to 0 at any reset. modify offhook only when config register, bits 0 6 (mode) is set to 0 (standby) to avoid interference with the data pump s use of this bit. eqm maxthresh 01f6 400h eqm maximum threshold the upper acceptable limit for the eye quality monitor (eqm). during v.22, v.22bis or bell 212a data mode, the eqmlev exceeds eqmmaxthresh, and the data pump sets dpctrl, bit 4 (eqe) to 1. the data pump sets this location to its default value at any reset. changes in value take effect at the end of the next baud period. rlsdoffthresh 01f5 48 dbm received line signal detect off threshold rlsdonthresh 01f4 43 dbm received line signal detect on threshold this register represents the upper and lower thresholds of the received telephone line energy. if reg5, bit 1 (cdet) to 1, and the telephone line energy falls below rlsdoffthresh, then the data pump sets reg5, bit 1 (cdet) to 0. if reg5, bit 1 (cdet) is 1 and the telephone line energy rises above rlsdonthresh then the data pump sets reg5, bit 1 (cdet) to 1. these thresholds stabilize reg5, bit 1 (cdet) by hysteresis when rlsdoffthresh is set to a lower value than rlsdonthresh. use the following formula when thresh is specified in dbm and is less or equal to 0: the data pump sets this location to its default value at any reset. changes in value take effect after the next baud period. table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation 01f7 rlsdval 10 power () 20 ? 30 32767 () = z02201 v.22bis data pump with integrated afe zilog 28 z02201 ps000902-0501 conn_mode 01f0 connection mode register this ram location reports the connection type and speed established after handshake is completed. the values for this location are the same as those for con g register, bits 0 6 (mode): value data mode speci ed 8 v.22bis 2400 bps mode 9 v.22 1200 bps mode b bell 212a 1200 bps mode 10 v.21 300 bps mode 11 bell 103 300 bps mode 13 v.23 1200 bps tx/75 bps rx mode 14 v.23 75 bps tx/1200 bps rx mode notch 01a2-1a6 below notch filter coefficients these ram locations contain the notch filter coefficients. the notch filter is a biquad section (2nd-order iir) used during simultaneous transmission and detection of tones ( config register, bits 0 6 (mode) is 4) to remove a single transmitted tone from the received signal used by the tone detectors. see the section simultaneous transmission and detection of tones on page 1-35 for more information. the default values for these locations are 0, 0, 0, 0, and 0x4000 respectively. the default values cause the notch filter to not modify the received signal used by the tone detectors. the data pump sets these locations to their default values when the host sets config register, bits 0 6 (mode) to 4 to begin simultaneous transmission and detection of tones. the host must not modify these locations unless config register, bits 0 6 (mode) is 4. to calculate the coefficients to remove a frequency f from the received signal, use these following formulae where , r = pole radius (0 r<1), 0.9 is recommended = 2 f /9600, f is the frequency (hz) to be removed, (0 f <4800) = (1-2rcos( )+r 2 )/(2-2cos( ) ) location 0x1a2 0x1a3 0x1a4 0x1a5 0x1a6 name b2 b1 a3 a2 a1 formula -r 2 2rcos( ) -2 cos( ) the cosine function is calculated in radians, not degrees. before writing the coefficients to data pump ram, convert them to the format used by the data pump by multiplying each coefficient by 16,383, then round to the nearest 16-bit signed integer. for example, 2.0 becomes 32,766 (0x7ffe), -1.0 becomes -16,383 (0xc001), -2.0 becomes -32,766 (0x8002). these formulae determine the coefficients of a biquad section with symmetric zeroes, a zero radius of 1.0, a pole radius of r, and pole and zero frequencies of f hz. see simultaneous transmission and detection of tones for more detail and notch filter coefficients for the default frequencies detected by the discrete tone detectors. table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 29 dtmfh_lev 01a1 6 dbm dtmf transmit level high band dtmfl_lev 01a0 9 dbm dtmf transmit level low band these are the transmit levels for the dtmf low band (dtmfl_lev) and dtmf high band (dtmfh_lev) frequencies. the levels are set by the following formula where lev is specified in dbm and less or equal to 0: change in value takes effect in 0.1 msec. the data pump sets these locations to their default values at any reset. tonegena 0191 tone generator a tonegenb 0196 tone generator b the data pump has two independent tone generators, each simultaneously generating a pure tone with its own transmit level when config register, bits 0 6 (mode) is 1 (transmit tones). the outputs of the tone generators are mixed together. the generated frequencies are set by writing a coefficient to location tonegena or tonegenb. the coefficient is defined as the following :where f is the frequency of the tone to be generated: the transmit levels for tone generators a and b are set in locations dtmfl_lev and dtmfh_lev, respectively. see transmitting tones for more information including a description of setting the tone transmission levels. txlevel 0185 10 dbm transmit power level to sets the transmit power level, use the following formula where power is speci ed in dbm and less than or equal to 6: change in value takes effect at the end of the baud period. seq3count 18e none dial timer inter-pulse count see seq1count seq2count 18d 95 msec dial timer off count see seq1count seq1count 18c 95 msec dial timer on count seq1count, seq2count, and seq3count are timer counts in units of 1/9600 of a second, for dtmf and pulse dialing. for dtmf dialing, seq1count is the length of the digit on-time, and seq2count is the length of the digit off-time. for pulse dialing, seq1count is the length of the break period, seq2count is the length of the make period, and seq3count is the length of the pause after dialing a digit. the data pump sets these locations to their default values when the host sets con g register, bits 0 6 (mode) to 3 (dial). table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation dtmflev 10 lev () 20 ? 32767 ? = coeff x 2 f ? 9600 ------------- 4096 ? = txlevel 10 power () 20 ? 2048 ? = z02201 v.22bis data pump with integrated afe zilog 30 z02201 ps000902-0501 biquad a coefficients 0155 015e biquad a and b coefficients biquad b coefficients 015f 0168 these locations program the frequency range for the biquad tone detectors. the coef cients are in the following order: b2, b1, a3, a2, a1, b2, b1, a3, a2, a1. see the section on call-progress monitoring using biquad tone detectors for more information. dtd0 dtd15 0145 0154 tone detector coefficients these locations set the tone detector coef cients for the 16 detectors in the system. the coef cients are set by using the following formula where (2 pi x ftone/9600) is measured in radians: see tone detectors for more information. eqmlev 092 eye quality monitor (eqm) this register provides a measure of line quality during v.22, v.22bis, or bell 212a, while computing a running average of the mean square error (mse) of the received point and decision point. when eqmlev exceeds eqmmaxthresh, dpctrl.eqe is set to 1; otherwise, it is set to 0. table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation coeff tone 2 f tone ? 9600 ------------------------ - ?? ?? cos 32767 ? = z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 31 biquadoffthresh 052 42 dbm biquad tone detectors off point the data pump sets this location to its default value when con g register, bits 0 6 (mode) is set to 2 by the host. this location can be used to set the off point for the biquad tone detectors. if the power level is below this value, the detector will turn off the detection status bit. use the following formula to set the threshold where the level is in dbm: the data pump sets this location to its default value when the host sets config register, bits 0 6 (mode)=2 (detect tones). biquadonthresh 051 35 dbm biquad tone detectors on point the data pump sets this location to its default value when con g register, bits 0 6 (mode) is set to 2 by the host. this location can be used to set the on point for the biquad tone detectors. if the power level is above this value, the detector turns the detection status bit on. use the following formula to set the threshold where level is in dbm: the data pump sets this location to its default value when the host sets config register, bits 0 6 (mode) is 2 (detect tones). dtd0lev 26 35 dtd15lev discrete tone detector levels these locations represent the tone detector levels when in the tone detect mode ( con g register, bits 0 6 (mode) has the value of 02h). these areas may be used by the host to determine which tone is dominant if multiple tones are detected. these particular locations have no default. dtdthresh 03 24 dbm discrete tone detector threshold this location programs the threshold for all discrete tone detectors. any signal whose signal strength is above this threshold turns on the detection bit for that tone. any signal below this threshold turns off the detection bit for that tone. this location can be programmed using the following formula: this location must be programmed after con g register, bits 0 6 (mode) is set to detect tone (02h), because the data pump resets this location to its default when con g register, bits 0 6 (mode) is set to tone detect mode. see tone detectors for more information. table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation threshold 10 level () 20 ? 32767 ? = threshold 10 level () 20 ? 32767 ? = threshold 10 level () 20 ? 32767 ? = z02201 v.22bis data pump with integrated afe zilog 32 z02201 ps000902-0501 transmitting tones the data pump has two tone generators, each with their own transmit level. the outputs are mixed together. the frequency of the tones are programmed by writing coefficients to locations tonegena and tonegenb . the transmit levels are programmed by writing values to locations dtmf_lev and dtmfh_lev . if only one tone is to be transmitted, the other tone generators transmit level is set to 0 to disable it. figure 9. transmitting tones for example, to generate a 2100 hz answer tone for 3.3 seconds at C10dbm: 1. set location tonegena to 015feh . 2. set location dtmfl_lev to 0287h . 3. set location dtmfh_lev to 0 , disabling tonegenb . 4. set config register, bits 0C6 ( mode ) to 1 (transmit tone). 5. wait 3.3 seconds, then set config register, bits 0C6 ( mode ) to 0 ( standby ). dtdstatus 00 discrete tone detector status this location contains the status of the tone detectors when in tone detect mode ( con g register, bits 0 6 (mode) is 02h). bit 0 contains the status of detector 0, bit 1 (the status of detector 1), and so on. this location is only valid when in tone detection mode. the response time of the tone detectors is dependent upon the frequency of the tone being detected and sampling rate of the data pump. when the host sets con g register, bits 0 6 (mode) to 0 (standby), or resets the data pump, the data pump writes its part number into this location. table 15. modem data pump word de nitions (continued) register & address (hex) default value function and explanation + * * high band tone (0x196) low band tone (0x196) dtmfh_lev (0x1a1) dtmfl_lev (0x1a0) transmitted tones z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 33 tone detectors there are 16 tone detectors in the data pump. they are programmed by setting up one word for each tone detector. there is one global threshold setting for all 16 tone detectors. the address for the tone detectors are as follows: ? tone detector coefficients 0145 C 0154h (tone0Ctone15) ? tone detector receive levels 026h C 035h (dtd0levCdtd15lev) ? tone detector thresholdC 03h ? tone detector statusC 00h ? the tone coefficients are calculated as follows: ? the default values on reset are represented in table 16: ? the threshold is calculated as follows: where level is in dbm. the default value for the threshold is C24 dbm. this value is set every time config register, bits 0C6 ( mode ) is set up to detect tones. if the user wishes a different value, it should be reloaded after config register, bits 0C6 ( mode ) is set to detect tones. to use the tone detectors, perform the following steps: 1. set up the tone detector coefficients ( 0145 C 0154h ). 2. set config register, bits 0C6 ( mode ) to tone detect mode ( 02h ). note: tone detect mode is the same mode used for biquad tone detectors, because both biquad tone detectors and tone detectors run concurrently. as a result, the host is al- lowed to look for individual answer tones as well as call- progress tones. 3. set up the tone detector threshold dtdthresh . 4. inspect the tone detector status. 5. when the detection phase is complete, set config register, bits 0C6 ( mode ) to standby ( 00h ). table 16. tone detector default values tone detector frequency detected (hz) 0 697 1 770 2 852 3 941 4 1209 5 1336 6 1477 7 1633 8 1750 9 1800 10 1650 11 2225 12 2250 13 1300 14 2100 15 600 coeff tone 2 f tone ? 9600 ----------------------- - ?? ?? cos 32767 ? = threshold 10 level () 20 ? 32767 ? = z02201 v.22bis data pump with integrated afe zilog 34 z02201 ps000902-0501 figure 10. tone detectors call-progress monitoring using biquad tone detectors the data pump contains two biquad tone detectors that are capable of detecting energy in a frequency band. these detectors are useful for call-progress monitoring, where the exact frequency of the incoming signal is not known. each biquad tone detector is composed of two cascaded, independently programmable, biquad sections. the order of biquad coefficients in ram is: b2, b1, a3, a2, a1, b2, b1, a3, a2, a1 the addresses for the coefficients for the two sections start at 0155h ( tonea ) and 015fh ( toneb ). the sample rate is 9600 hz. the transfer equation for each section of the biquad tone detector is of the form: there are two threshold settings affecting both biquad tone detectors. the locations biquadoffthresh and biquadonthresh define the on and off hysteresis points where level is in dbm: 1. biquadoffthresh C 052h Coff point. 2. biquadonthresh C 051h Con point. use the following formula to set the thresholds: the default values are C35 dbm (biquadonthresh) and C42dbm (biquadoffthresh). the biquad tone detector status is contained in tonestatus , bit 15 ( tonea ) and tonestatus , bit 14 ( toneb ). the response time of the biquad tone detectors depends on the coefficients and the input signal frequency. the biquad tone detectors can be cascaded to form one tone detector with 4 biquad sections (an 8th order iir filter) by setting tonestatus.cascade. in this case, level 0 tone 0 tone 15 level 15 tone detector levels (026h 035h) threshold (03h) comparator tone detector status (00h) tone detector coefficients (0145h 0154h) h n 2a 1 a 2 z 1 a 3 z 2 ++ () 12b 1 z 1 2b 2 z 2 () ---------------------------------------------------------- - = threshold 10 level () 20 ? 32767 ? = z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 35 tonestatus , bit 15 ( tonea ) contains the status of the cascaded tone detector, and tonestatus , bit 5 ( sqrdis ) controls whether the output of biquad tone detector b is squared before being input to biquad tone detector a. the default settings for the biquad tone detector coefficients are indicated in table 17 and table 18, where the first row is tonea and the second row is toneb . the data pump sets the biquad tone detector coefficients to their default settings at any reset. to use the biquad tone detectors to perform call-progress monitoring, execute the following: 1. set the coefficients. coefficients which are changed remain valid until the next reset. 2. set config register, bits 0C6 ( mode ) to 2 (detect tones). the biquad tone detectors and the discrete tone detectors operate simultaneously to allow the host to look for call-progress tones and individual answer tones at the same time. 3. set the biquadonthresh and biquadoffthresh values. 4. if the two biquad tone detectors are to be cascaded, set tonestatus , bit 13 ( cascade ) to 1 . if required, set tonestatus , bit 5 ( sqrdis ) to 1 to disable the squarer when the tone detectors are cascaded. 5. inspect tonestatus , bit 15 ( tonea ) and tonestatus , bit 14 ( toneb ) for the detection status. if tonestatus , bit 13 ( cascade ) is set, only inspect tonestatus , bit 15 ( tonea ). 6. time the on time and the off time of the tone(s) to provide the cadence, which is used to identify the type of call-progress tone detected.after call-progress monitoring is complete, set config register, bits 0C6 ( mode ) to 0 ( standby ). simultaneous transmission and detection of tones setting config register, bits 0C6 ( mode ) to 4 enables the simultaneous operation of all discrete tone detectors, biquad tone detectors, and tone generators. please refer to the sections transmitting tones, tone detectors and for descriptions of how to use each of these features by itself. the host uses simultaneous transmission and detection of tones when it needs to detect tones while generating a single tone. an example during the call establishment phase of a special purpose modem. to prevent a single generated tone from interfering with the tone detectors the host programs data pump ram locations 0x1a2 through 0x1a6 with coefficients for a notch filter to remove a single tone from the received signal used by the tone detectors. the notch filter coefficients are set to their default values when the host sets config register, bits 0C6 ( mode ) to 4 , so the host writes new values to these locations after setting config register, bits 0C6 ( mode ) to begin simultaneous transmission and detection of tones. the default notch filter coefficient values cause the notch filter to not change the received signal used by the tone detectors. the notch filter is a biquad section (2nd-order iir filter). the values of the coefficients determine the frequency to be removed. refer to the description of ram location notch for the formulae used to compute these commonly used coefficient values: table 17. biquad section 1 coef cients (hex) band (hz) b2 b1 a3 a2 a1 245?50 c774 7601 0716 f5fb 0716 360 440 c148 7a66 ff5c 0000 00a4 table 18. biquad section 2 coef cients (hex) band (hz) b2 b1 a3 a2 a1 245 650 c63e 6fe1 f8ea 0000 0716 360 440 c7cd 7438 01aa febc 01aa z02201 v.22bis data pump with integrated afe zilog 36 z02201 ps000902-0501 notes: 1. failing to program the notch filter to the same frequency as the transmitted tone when config register, bits 0C6 ( mode ) is 4 seriously reduces the accuracy and sensitivity of the data pump's tone detectors. 2. it is not possible to generate two tones simultaneously when config register, bits 0C6 ( mode ) is 4 without seriously reducing the accuracy and sensitivity of the data pump's tone detectors, even if the notch filter is programmed to remove one of the generated tones. 3. the notch filter attenuates received signals at frequencies close to the notched frequency. for the commonly used coefficient values shown, signals within 100 hz of the notch frequency are attenuated by 6 db or more, signals 320 hz or more from the notch frequency are attenuated by less than 1 db. table 19. notch filer coef cients f (hz) 0x1a2 0x1a3 0x1a4 0x1a5 0x1a6 default 0x0 0x0 0x0 0x0 0x4000 600 0xcc2a 0x6a6d 0x3dcd 0x8dcf 0x3dcd 1300 0xcc2a 0x4bf4 0x3a89 0xb2cf 0x3a89 1650 0xcc2a 0x364d 0x3a34 0xc921 0x3a34 1750 0xcc2a 0x2f8a 0x3a24 0xd002 0x3a24 1800 0xcc2a 0x2c15 0x3a1d 0xd385 0x3a1d 2100 0xcc2a 0x1679 0x39fe 0xe95f 0x39fe 2225 0xcc2a 0x0d2a 0x39f5 0xf2c1 0x39f5 2250 0xcc2a 0x0b4a 0x39f4 0xf4a4 0x39f4 z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 37 dialing the data pump may be programmed to dial using either dtmf tones, or make/break pulses. by default, the data pump is configured for tone (dtmf) dialing. tone dialing tone dialing may be either continuous or timed. continuous dialing generates the required tone until the host specifically shuts it off. timed dialing allows the host to specify the on/off timing of the digit dialed. the following example assumes the host controls the data pumps rts through reg4, bit 3 ( rtsp ). to perform tone dialing: 1. set reg4, bit 3 ( rtsp ) to 0 , tonestatus , bit 4 ( timedial ) to 1 for timed dialing, or to 0 for continuous dialing. then, set config register, bits 0C6 ( mode ) to 3 ( dial ). if timed dialing is required, set the timer locations seq1count and seq2count to 1 . 2. control the twist by setting locations dtmfh_lev and dtmfl_lev to specify the transmit levels of the high tone and the low tone, respectively. 3. set up the digit to be dialed in tonestatus bits 0 C 3 ( digit ) according to the following table: 4. for continuous operation, set reg4, bit 3 ( rtsp ) to 1 to start transmitting the dtmf tone, and to 0 to stop. 5. for timed operation, set reg4, bit 3 ( rtsp ) to 1 to dial the digit. the data pump sets reg5, bit 4 ( dpbusy ) to 1 while it dials the digit. set reg4, bit 3 ( rtsp ) to 0 after the digit has been dialed. the data pump sets reg5, bit 4 ( dpbusy ) to 0 when the dial sequence is completed. 6. to dial additional digits, repeat the procedure starting at step 3. 7. when dialing is complete, set config register, bits 0C6 ( mode ) to 0 ( standby ). the z02922 data pump exhibits limited maximum output power. this feature applies not only to data mode, but also to dtmf and other tone generation. during dtmf or tone generation, if the sum of the transmit levels programmed into dtmfh_lev and dtmfl_lev exceeds 30720 (0x7800) the data pump may not properly transmit the tones. when transmitting dtmf with a required twist (power difference between high and low bands), use this formula to determine the maximum dtmf transmit levels where x is the dtmf low band ( dtmfl_lev ) transmit level in dbm, and x+b is the dtmf high band ( dtmfh_lev ) transmit level in dbm ( b is the twist in dbm): 10^(x/20) + 10^((x+b)/20) <= 30720/32768 the values for maximum transmit levels ( dtmfl_lev + dtmfh_lev = 30720 ) at common twist values are described in the following table: pulse dialing pulse dialing is very similar to timed dialing, with the exception that the tone generated is a cadence of pulses output on the oh pin and mirrored in ram location mstatus , bit 2 ( offhook ). to implement pulse dialing, follow the instructions for timed tone dialing, except: 1. select pulse instead of tone dial mode by setting location tonestatus , bit 7 ( tonedial ) to 0 tonestatus , bit 4 ( timedial ) has no effect. pulse dialing is always timed. table 20. tone dialing digit value 00 11 22 33 44 55 66 77 88 99 *10 #11 a12 b13 c14 d15 dtmfl_lev dtmfh_lev x x+b b 14,477 16,243 -7.10 -6.10 1 13,599 17,121 -7.64 -5.64 2 12,733 17,987 -8.21 -5.21 3 z02201 v.22bis data pump with integrated afe zilog 38 z02201 ps000902-0501 2. after setting config register, bits 0C6 ( mode ) to 3 ( dial ), set seq1count , seq2count , and seq3count to the required make and break times, pausing after each digit is dialed. for north american applications requiring a 100 msec cadence, a 39%/61% make/break ratio, and a 0.75 second pause, set locations seq1count to 024ah , seq2count to 0176h , and seq3count to 01c20h . manual handshake procedures the v.22bis data pump software allows the host to control every aspect of the handshake procedure. the host instructs the data pump which signal to send at which time. the data pump sets status bits when it receives signals from the remote modem. the host begins a manual handshake by setting config register, bit 10 ( mcuctrl ) to 1 to prevent the data pump from transmitting its own handshake signals. the host monitors the receive signal status bits in location trnctrl and transmits its own responding signals by setting trnctrl , bits 0 C 2 (txctrl) transmits the following values: in the following section, certain acronyms shall be used to denote the various v.22bis handshake signals. these are: originating modem 1. take the telephone line off-hook and dial. 2. program the discrete tone detectors and the biquad tone detectors for answer tones (2100 hz) and call- progress tones (200C600 hz). look for both the answer tone and call-progress tones (such as busy tones, ring back and so on). 3. upon receiving the 2100 hz answer tone, set config to 4409h (v.22, v.22bis originate, manual handshake). 4. wait for trnctrl , bit 5 ( usb1det ) to be set to 1 ( usb1 detected) continuously for 155 msec. 5. wait for 456 msec. 6. set trnctrl , bits 0 C 2 ( txctrl ) to 2 ( transmit s1 signal ) for 100 msec. 7. set trnctrl , bits 0 C 2 ( txctrl ) to 3 ( transmit sb1 ), and inspect trnctrl , bit 6 ( s1det ) and trnctrl , bit 7 ( sb1det ) repeatedly for either a received s1 signal or sb1. if sb1 is received for 270 msec, proceed to step 11. if s1 is received, wait for the s1 to end. wait for an additional 450 msec. 8. set trnctrl , bit 3 ( v22bis ) to 1 (force a 16-way receive decision). wait for 150 msec. 9. set trnctrl , bits 0 C 2 ( txctrl ) to 4 (transmit sb1 at 2400 bps). wait for 200 msec. 10. set trnctrl , bits 0 C 2 ( txctrl ) to 6 (2400 bps data mode). data is now being transmitted and received at 2400 bps. 11. in step 7, if sb1 is detected instead of the s1 signal, wait for 765 msec. proceed to set trnctrl , bits 0 C 2 ( txctrl ) to 5 (1200 bps data mode ) . data is now being transmitted and received at 1200 bps. answering modem 1. at a ring signal or a command from the host, take the phone off-hook and transmit silence for 1.8 to 2.5 seconds. 2. if required, use the tone generators to transmit a 2100 hz tone for 2.6 to 4 seconds. this tone is the v.25 answer tone. 3. set config register, bits 0C6 ( mode ) to 0 ( standby ) and transmit silence for 75 msec. 4. set config to 8 ( answer mode, manual handshake ). after setting config, the host is ready to receive data from the remote modem. the data pump holds the received data to marks (that is, receives nothing) until the modem is able to receive data from the remote modem. table 21. signal transmit values trnctrl value signal transmitted 0 silence 1 1200 bps unscrambled binary 1 2s1 3 1200 bps scrambled binary 1 4 2400 bps scrambled binary 1 5 1200 bps data mode or fsk 6 2400 bps data mode 7 2225 hz tone table 22. handshake acronyms name meaning usb1 unscrambled binary 1 sb1 scrambled binary 1 s1 s1 signal z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 39 5. set trnctrl , bits 0 C 2 ( txctrl ) to 1 (transmit usb1). 6. inspect trnctrl , bit 6 ( s1det ) and trnctrl , bit 7 ( sb1det ) repeatedly for either a received s1 signal or sb1 . if sb1 is received continuously for 270 msec, proceed to step 12. if an s1 signal is received ( trnctrl , bit 6 ( s1det ) is 1 ) wait for the s1 to end. 7. set trnctrl , bits 0 C 2 ( txctrl ) to 2 (transmit s1 signal) for 100 msec. 8. set trnctrl , bits 0 C 2 ( txctrl ) to 3 ( transmit sb1 ) for 350 msec. 9. set trnctrl , bit 3 ( v22bis ) to 1 (force 16-way receive decisions). wait for 150 msec. 10. set trnctrl , bits 0 C 2 ( txctrl ) to 4 ( transmit sb1 at 2400 bps). wait for 200 msec. 11. set trnctrl , bits 0 C 2 ( txctrl ) to 6 (2400 bps data mode). data is now being transmitted and received at 2400 bps. 12. if in step 6., sb1 is received instead of an s1 signal, set trnctrl , bits 0 C 2 ( txctrl ) to 3 ( t ransmit sb1) for 765 msec. from that point, set trnctrl , bits 0 C 2 ( txctrl ) to 5 (1200 bps data mode). data is now transmitted and received at 1200 bps. making a v.22bis connection in the following example, all timing is performed by the host. originating modem 1. take the telephone line off-hook and dial. 2. program the discrete tone detectors and the biquad tone detectors for answer tones (2100 hz) and call- progress tones (200C600 hz). look for the answer tone and call-progress tones (busy tones, ring back, etc.) 3. upon receiving the 2100 hz answer tone, set config to 4008h (v.22bis originate). after setting config, the host should be prepared to receive data from the remote modem. the data pump holds the received data to marks (that is, receives nothing) until the modem is able to receive data from the remote modem. 4. when the data pump establishes a v.22bis connection, and is ready to transmit data to the remote modem, it sets reg5, bit 1 ( cdet ) to 1. data may now be transmitted or received between the modems. answering modem 1. upon a ring signal or command from the terminal, take the phone off-hook and transmit silence for 1.8C2.5 seconds. 2. if required, use the tone generators to transmit a 2100 hz tone for 2.6C4 seconds. this tone is the v.25 answer tone. 3. set config register, bits 0C6 ( mode ) to 0 ( standby ) and transmit silence for 75 msec. 4. set config to 8 ( v.22bis answer ). after setting config, the host should be prepared to receive data from the remote modem. the data pump holds the received data to marks (that is, receives nothing) until the modem is able to receive data from the remote modem. 5. when the data pump establishes a v.22bis connection, and is ready to transmit data to the remote modem, it sets reg5, bit 1 ( cdet ) to 1 . data may now be transmitted or received between the modems. notes: 1. the data pump sets reg5, bit 1 (cdet) to 0 dur- ing carrier dropouts, retrains, and when the re- mote modem hangs up the telephone line. depending on the data mode, the host may use reg5, bit 1 (cdet), reg5, bit 2 (rtrnd), dpc- trl.eqe, eqmlev and eqmmaxthresh to determine when the remote modem has initiated a retrain, or has hung up the telephone line. 2. during 2400 bps v.22bis data mode, the host may use dpctrl.eqe and eqmmaxthresh or eqmlev, to determine when to initiate a retrain (see table 15, mstatus.retrain) to improve the quality of the connection. z02201 v.22bis data pump with integrated afe zilog 40 z02201 ps000902-0501 using hdlc the data pump includes hdlc firmware operating in all data modes. the hdlc firmware performs all the necessary operations to frame host-supplied data into hdlc format, including automatic opening and closing flag generation, zero insertion and deletion, flag and abort detection, and crc checksum computation and checking. hdlc operation during hdlc operation, the data pump frames host- supplied asynchronous data into a synchronous data stream in the transmitter, and extracts the same asynchronous data from the received synchronous data stream in the receiver. the inclusion of 16-bit cyclic redundancy check (crc) information in the frames allows the receiving host to check whether the data has been correctly received. hdlc data is sent in frames. a frame consists of a number of bytes, each composed of 8 data bits. a frame contains an opening flag, frame data bytes, two crc checksum bytes, and a closing flag, respectively. opening flags and closing flags indicate the start and the end of a frame, respectively. a flag, byte value 07eh , is one of two hdlc control symbols. the other is an abort, which is any sequence of consecutive binary 1s more than six bits long. if the frames do not use the bandwidth of the data mode (for example, when there is no host data to transmit), the modem fills the remaining bandwidth by sending flags between frames. frame data bytes for transmission are supplied by the host to the data pumps datap register. these bytes are modified by the data pump to ensure that no more than five consecutive binary 1 bits are sent. to accomplish this modification, the transmitting modem inserts a single 0 bit after every five consecutive binary 1 bits in the host supplied data. this zero insertion process allows the receiving modems data pump to distinguish between frame data, flags, and aborts. the receiving modems data pump uses a zero deletion process to remove each inserted 0 bit before returning the data to the receiving modem's host. when a frame is to be closed, the frame's two crc checksum bytes are sent immediately following the frame data. the crc checksum is computed without the inserted zeroes. the frames closing flag is transmitted following the crc. this flag may also serve as the opening flag of the next frame, saving bandwidth. enabling hdlc operation the data pumps hdlc firmware is disabled at power-up and any reset, and can be enabled only in parallel mode (reg4., bit 4 ( tpdm ) is 1). to enable hdlc, set bufctrl , bit 7 ( hdlc ) to 1 , and bits 8C15 of bufctrl to 0 prior to beginning data mode operation. the host also reads register datap just before starting data mode to clear datap . these examples demonstrate the use of the data pump in parallel mode to transmit and receive hdlc data frames. the examples assume that the data pump has just been put in data mode, and hdlc operation is enabled. the data to be sent or received is the sequence of n bytes (byte1Cbyten), where byte1 is sent (or received) first. transmitting 1. when reg5, bit 7 ( txi ) is 1 , write byte1 to datap . repeat this step for each byte to be transmitted. if reg4, bit 7 ( txie ) is 1 , the data pump generates an interrupt when it is ready to transmit the next byte, for example, when the byte sets reg5, bit 7 ( txi ) to 1 . 2. when the last byte, byten, has been sent, wait for the data pump to set reg7, bit 2 ( tend ) to 1 . this function indicates the data pump has closed the current frame. the data pump now computes and transmits the crc checksum and closing flag for the frame. the data pump does not set reg7, bit 7 ( tend ) to 1 until at least 8 bit times after it has set reg4, bit 7 ( txi ) to 1 , indicating the data pump is ready to transmit another data byte. to transmit another frame, repeat steps 1C2. 3. when the data pump begins sending the frame's closing flag, it sets reg7, bit 2 ( tend ) to 0 . transmission of the frame is complete 8 bit times after the data pump sets reg7, bit 7 ( tend ) to 0 . receiving 1. prepare to receive a new frame. 2. when reg5, bit 6 ( rxi ) is 1 , the data pump has received a byte. first read register reg7, followed by datap . register 7 (reg7) is read first, because the data pump may change it any time after datap is read. if reg4, 6 ( rxie ) is 1 , the data pump generates an interrupt when it sets reg5, bit 6 ( rxi ) 1 . act on the value of reg7 read in step 2 as follows: 3. if rxerror is 0 and eof is 0 , then the datap value read in step 2 is an hdlc frame byte. repeat step 2 to receive all remaining frame bytes. z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 41 4. if rxerror is 0 and eof is 1 , then an hdlc frame with a correct checksum has been received. 5. if byte1Cbyten+3 have been read, with byten+3 being the datap value just read, then the two previous bytes (byten+1 and byten+2), are the frame checksum bytes; the remaining bytes (byte1Cbyten) are the frame data bytes. 6. continue from step 1 to receive the next frame. if rxerror is 1, discard any received frame bytes and continue from step 1 to receive the next frame. 7. if datap was 0ff , an hdlc abort sequence was received. if datap was 07eh , an hdlc frame with an incorrect checksum was received. getting the data pump firmware version number and part number the data pump code version can be obtained any time the ram location config register, bits 0C6 ( mode ) is set to 0 . the data pump writes the part number to data pump ram location 0 and the code version number to the datap register. to obtain the version and part number from the data pump, the following steps must be performed: 1. set config register, bits 0C6 ( mode ) to 0 ( standby ), then read location config to provide the data pump enough time to begin standby operation. 2. read the datap register. this register returns the code release version number (an 8 bit value, for example, 030h indicates version 30). 3. read ram location 0. this location returns the part number (for example, 02201h for a z02201 part). sleep mode the data pump incorporates a low-power sleep mode. in this mode, the data pump clock is shut down, effectively stopping the part. to enter sleep mode, the controller can set config to mode 7. to exit sleep mode, the controller can either reset the data pump (asserting the reset signal) or write any value to the datap register. the host must then wait at least 2 msec before accessing the data pump registers. typical performance data the bit error rate ( ber ) and block error rate ( bler ) curves in figure 11 and figure 12 represent typical performance over a variety of signal to noise conditions (snr). note: modems usually exhibit lower bit error rates receiving in the low band as opposed to the high band. when an analog link is completed, the adaptive equalizer ( aeq ) is frozen. the noise level is then increased without making new links. these tests were conducted using a consultronics tcs500 telephone line simulator, and a hewlett packard 4951b protocol analyzer/bert tester under the following conditions: table 23. performance testing conditions line simulation flat transmit level 10 dbm receive level 16.0 dbm data transmitted 511 pseudo-random pattern number of bits sent 1,000,000 number of blocks sent 1,000 bits per block 1,000 aeq frozen after link establishment noise calibration c-message z02201 v.22bis data pump with integrated afe zilog 42 z02201 ps000902-0501 figure 11. typical performance data z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 43 figure 12. typical modem using z02201 and a z02205 controller v c c a v c c v c c v c c v c c v c c v c c a v c c v c c v c c v c c v c c d e c o u p l i n g c a p a c i t o r s e y e p a t t e r n g e n e r a t o r i s o p t i o n a l . d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 0 a 1 a 2 / d p r e s / d p r e s / d p w r / d p w r / d p r d / d p r d / d p c s / d p c s / d p i r q / d p i r q s o u t s i n / u p o h / u p o h / s h u n t / s h u n t / r i n g / r i n g d c d d t r r x d s i n s i n t x c r x c / t s t 2 r x c / t s t 2 e y e o u t e y e o u t e y e c l k e y e c l k e y e s t b e y e s t b / m u t e / m u t e / d o h / d o h / d o h y 2 0 1 1 4 . 7 4 5 6 m h z y 2 0 2 2 4 . 5 7 6 m h z c 2 0 1 4 7 p f c 2 0 6 1 0 u f + + + + u 2 0 4 7 4 h c 5 9 5 s e r 1 4 s r c l k 1 1 s r c l r 1 0 r c l k 1 2 g 1 3 q a 1 5 q b 1 q c 2 q d 3 q e 4 q f 5 q g 6 q h 7 q h ' 9 u 2 0 5 a 7 4 h c t 0 4 1 2 r 2 0 3 1 0 0 k z 2 0 2 b 1 u f + + + + j 2 0 1 r 2 0 2 1 0 k u 2 0 2 z 0 2 2 0 1 t x d / d a c k 3 8 r x d / d r e q 3 6 d c l k 3 7 r t s 4 0 o h 3 9 r l s d 3 5 d 0 2 7 d 1 2 8 d 2 2 9 d 3 3 0 d 4 3 1 d 5 3 2 d 6 3 3 d 7 3 4 r s 0 1 9 r s 1 2 0 r s 2 2 1 c s 1 8 r d 2 5 w r 2 3 i r q 2 2 e y e o u t 5 e y e c l k 4 e y e s t b 6 t x o + 8 t x o - 9 r x i + 1 6 r x i - 1 5 c f 1 1 3 c f 2 1 4 x t a l 1 4 3 x t a l 2 4 2 t s t 1 3 t s t 2 4 1 v d d 2 4 v d d 4 4 v s s 2 v s s 2 6 a v d d 7 a v d d 1 7 a v s s 1 0 a v s s 1 2 r e s e t 1 z 2 0 1 b 1 u f + + + + l 2 0 1 1 0 u h z 2 0 2 e 1 u f + + + + u 2 0 3 a d 5 5 7 d 7 1 d 6 2 d 5 3 d 4 4 d 3 5 d 2 6 d 1 7 d 0 8 c s 1 0 c e 9 v o u t 1 6 v a 1 5 v b 1 4 v c c 1 1 g n d 1 2 g n d 1 3 c n 3 0 2 s o c k e t p l c c s m t 4 4 x 2 0 1 s h u n t c n 3 0 1 s o c k e t d i p 2 8 j 2 0 2 j 2 0 3 c 2 0 3 4 7 p f r 2 0 1 1 0 k r 2 0 6 1 0 k c 2 0 2 8 2 p f c 2 0 4 6 8 p f c 2 0 5 6 8 p f r 2 0 5 1 0 k c 2 0 7 0 . 1 u f z 2 0 2 a 0 . 1 u f u 2 0 6 a d 5 5 7 d 7 1 d 6 2 d 5 3 d 4 4 d 3 5 d 2 6 d 1 7 d 0 8 c s 1 0 c e 9 v o u t 1 6 v a 1 5 v b 1 4 v c c 1 1 g n d 1 2 g n d 1 3 u 2 0 7 7 4 h c 5 9 5 s e r 1 4 s r c l k 1 1 s r c l r 1 0 r c l k 1 2 g 1 3 q a 1 5 q b 1 q c 2 q d 3 q e 4 q f 5 q g 6 q h 7 q h ' 9 u 2 0 5 b 7 4 h c t 0 4 3 4 u 2 0 5 c 7 4 h c t 0 4 5 6 u 2 0 5 d 7 4 h c t 0 4 9 8 z 2 0 2 c 0 . 1 u f z 2 0 2 d 0 . 1 u f z 2 0 2 f 0 . 1 u f z 2 0 1 a 0 . 1 u f z 2 0 3 0 . 1 u f z 2 0 4 0 . 1 u f z 2 0 5 0 . 1 u f z 2 0 6 0 . 1 u f z 2 0 7 0 . 1 u f u 2 0 1 z 0 2 2 0 5 vcc 8 gnd 22 x t a l 1 1 0 x t a l 2 9 t x d 1 6 o h 1 7 s h u n t 1 5 d c d 1 4 d t r / l c s 1 3 r i n g d e t / l c s 1 2 d p i r q 1 1 r x d 1 8 d 7 3 d 6 2 d 5 1 d 4 2 8 d 3 2 7 d 2 2 6 d 1 2 5 d 0 2 4 m u t e / r i 7 d p r e s e t 6 d p w r 5 d p r d 4 d p c s 2 3 a 2 2 1 a 1 2 0 a 0 1 9 s o u t d c d d t r s i n / s h u n t / o h / r i n g r x d t x c r x c / m u t e t x a + t x a - r x a + r x a - z02201 v.22bis data pump with integrated afe zilog 44 z02201 ps000902-0501 example daa figure 13 indicates an example daa configuration for north america. isolation transformer, t1, couples the primary (line) and secondary (modem) sides, while providing high voltage isolation. this wet transformer (allowing dc current) simplifies the circuit, while reducing the cost of the daa. on the secondary side, the transmit (txa+ and txaC) and receive (rxa+ and rxaC) are combined in the 4-wire to 2- wire hybrid circuit. this hybrid can be either passive or active. the more complex active hybrid allows operation to lower signal levels. it cancels out most of the transmit signal from the receive signal. on the primary side, the off-hook relay switches the phone line between a local handset (phone) or the modem. the ring detect circuit consists of dc blocking capacitor c4, current limiting resistor r2, zener diodes cr3 and cr4, optocoupler u3, and its reverse protection diode d3. protection elements rv1, f1, c1, and c2 (and transformer t1s isolation) will provide higher voltage capability for approval in some foreign markets. c1 and c2, for example, may must be replaced by metal oxide varistors (movs) or gas discharge tubes (gdts). the shunt relay reduces the daa impedance during pulse dialing. this operation is required for some country regulations. z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 45 figure 13. example daa v c c v c c v c c v c c v c c - 1 0 v v c c - 1 0 v v c c - 1 0 v d e c o u p l i n g c a p a c i t o r s a c t i v e d a a p a s s i v e d a a r i n g d e t e c t h o o k / s h u n t / t r a n s f o r m e r n o t e s 1 / j 3 0 1 s e l e c t s a c t i v e o r p a s s i v e d a a . 2 / j 3 0 2 t h r o u g h j 3 0 6 s e l e c t c y g 2 1 x x o r s o f t a r t d a a ( r i n g d e t e c t a n d h o o k / s h u n t / t r a n s f o r m e r ) . 3 / f o r c y g 2 1 x x r 3 0 6 , r 3 0 7 a n d r 3 1 2 m u s t b e c h a n g e d . 4 / c 3 0 6 , c 3 0 7 a n d c 3 1 2 a r e t o o p t i m i z e r e t u r n l o s s ( w h e r e n e c e s s a r y ) . 5 / f o r g e r m a n y a n d s w i t z e r l a n d u s e t h e c y g 2 3 x x s e r i e s . t r x a 2 t r x a 1 t r x a 2 t r x a 1 c 3 0 3 0 . 0 3 3 u f t 3 0 1 6 7 1 - 8 0 0 1 1 4 2 3 f 3 0 1 f u s e r v 3 0 1 2 2 0 l a 3 0 c 3 0 4 0 . 4 7 u f c r 3 0 3 1 n 4 7 4 2 a c r 3 0 1 1 n 5 2 2 8 b k 3 0 1 t q 2 e h - 5 v + + + + 3 2 4 8 9 7 1 0 1 c r 3 0 2 1 n 5 2 2 8 b d 3 0 3 m m b d 9 1 4 c r 3 0 4 1 n 4 7 4 2 a c n 3 0 1 r j 1 1 1 2 3 4 5 6 7 8 u 3 0 3 4 n 3 5 2 1 5 4 6 q 3 0 1 m m b t 3 9 0 6 r 3 0 2 7 k 5 r 3 0 3 4 7 k q 3 0 2 m m b t 3 9 0 6 d 3 0 2 m m b d 9 1 4 r 3 0 1 1 0 0 k 3 0 2 t q 2 e h - 5 v + + + + 3 2 4 8 9 7 1 0 1 z 3 0 1 a 0 . 1 u f r 3 0 4 1 0 k r 3 0 5 1 0 k d 3 0 1 m m b d 9 1 4 r 3 0 6 2 3 7 r 3 0 9 4 0 k 2 c 3 0 8 . 1 u f j 3 0 4 j 3 0 3 x 3 0 1 s h u n t x 1 3 c n 3 0 4 b h e a d e r r e c e p t i c a l - 2 c n 3 0 4 a h e a d e r r e c e p t i c a l - 7 c 3 1 4 1 n f j 3 0 5 c 3 1 2 x x x c 3 0 6 x x x c 3 0 7 x x x u 3 0 2 a l f 3 5 3 3 2 1 8 4 u 3 0 1 a l f 3 5 3 3 2 1 8 4 l 3 0 1 e m i b e a d j 3 0 6 c 3 1 3 1 . 5 n f l 3 0 2 e m i b e a d r 3 0 7 2 3 7 r 3 1 2 4 7 5 r 3 0 8 4 0 k 2 r 3 1 1 4 0 k 2 r 3 1 0 4 0 k 2 r 3 1 3 4 0 k 2 r 3 1 5 1 0 0 k r 3 1 6 2 0 k 5 r 3 1 4 2 0 k 5 r 3 1 9 6 0 k 4 r 3 2 0 4 0 k 2 r 3 1 7 8 0 k 6 r 3 1 8 2 0 k 5 c 3 1 0 . 1 u f u 3 0 2 b l f 3 5 3 5 6 7 z 3 0 2 a 0 . 1 u f z 3 0 4 0 . 1 u f c 3 0 9 . 1 u f c 3 1 1 . 1 u f c 3 0 2 1 n f 1 k v c 3 0 1 1 n f 1 k v j 3 0 1 a j 3 0 2 a z 3 0 1 b 0 . 1 u f z 3 0 2 b 0 . 1 u f u 3 0 4 c y g 2 1 x x l i n e 1 1 l i n e 2 2 r i n g d e t 3 gnd 4 o h 5 m u t e 6 vcc 7 t i p 1 1 r i n g 1 0 / r i n g t x a + t x a - r x a - r x a + s p e a k e r / s h u n t / o h o p t i o n a l z02201 v.22bis data pump with integrated afe zilog 46 z02201 ps000902-0501 eye pattern circuit figure 14 is the eye pattern circuitry used in the z0220100zco modem evaluation board, and can be used with modem components such as the zilog z02201 and z02201 that have an eye pattern interface. the z02201 eye pattern port consists of 3 signals: data (eyeout). the most significant and least significant bytes of this 16 bit word are the x and y coordinates respectively for the eye pattern display. each byte is most significant bit first. clock (eyeclk) . data is set on the rising edge of the eyeclk , and should be read on the falling edge. strobe (eyestb). this signal is active low when the data is valid. data is shifted through a pair of 8 bit serial-in parallel-out shift registers (74hc594) in response to the falling edge of eyeclk , then latched into a pair of 8 bit dacs on the rising edge of eyestb . the output of these dacs can be viewed on an oscilloscope in x y mode to see the received signal quality. figure 14. eye pattern circuit z02202 zilog v.22bis data pump with integrated afe ps000902-0501 z02201 47 package information figure 15. 44-lead plcc package diagram z02201 v.22bis data pump with integrated afe zilog 48 z02201 ps000902-0501 ordering information z02201 12.288 mhz 44-pin plcc refer to the z02201 product update for the software differences between the two rom codes versions. the product update also lists the work-arounds for ver. 0x31 of the rom code. for fast results, contact your local zilog sales office for assistance in ordering the part required. codes disclaimer ?2001 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devices sold by zilog, inc. are covered by warranty and limitation of liability provisions appearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantability or fitness for any purpose. except with the express written approval of zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. rom code version 0x48 Z0220112VSCR4078 rom code version 0x31 z0220112vscr3470 speed 12=12.288 mhz package v=plastic leaded chip carrier temperature s=0 c to +70 c environmental c = plastic standard rom code r4078 = rom code number 4078 (rom code version 0x48) r3470 = rom code number 3470 (rom code version 0x31) package environmental flow temperature zilog prefix speed product number example z02201 12 v s c r 4078 is a z02201 with rom code r4078, 12.288 mhz, plcc, 0 c to +70 c, plastic standard flow rom code number rom code |
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