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sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 1 of 15 product features supports pentium processors. 3 hi drive cpu clocks. up to 8 sdram clocks for 2 dimms. supports power management. 7 pci synchronous clocks. optional common or mixed supply mode: (vdd = vddq3 = vddq2 = 3.3v) or (vdd = vddq3 = 3.3v, vddq2 = 2.5v) < 250ps skew cpu and sdram clocks. < 250ps skew among pci clocks. i 2 c 2-wire serial interface programmable registers featuring: - enable/disable each output pin - mode as tri-state, test, or normal - 24/48 mhz selections 1 ioapic clock for multiprocessor support. 48-pin ssop and tssop package spread spectrum technology for up to 13db of emi reduction block diagram ref osc xin xout 3 buffers ref0,1,2 ioapic0 vddq2 pll1 sel 3 cpuclk vddq2 buffer buffers buffers 8 sdram0~7 vddq3 dly buffers 6 pciclk0~5 pll2 buffer buffer 48/24mhz 48/24mhz buffer pciclk_f sdata sdclk pci_stop# cpu_stop# pwr_dwn# mode cpumclk (0:1) frequency table sel cpu pci 0 60.0 30.0 1 66.6* 33.3* *spread spectrum mode capable connection diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ref1 ref0 vss xin xout mode vddq3 pciclk_f pciclk0 pciclk1 pciclk2 pciclk3 pciclk4 pciclk5 vss vss vddq3 sel sdata vddq3 48/24mhz 48/24mhz vss vdd sdram7/pci_stop# sdram6/cpu_stop# vddq3 sdram5 vss sdram4 sdram2 sdram1 sdram0 n/c cpumclk1 cpuclk cpumclk0 sdram3 vddq3 vss vddq2 vss pwr_dwn# ioapic0 vddq2 ref2 vdd sdclk imisg571d purchase of i 2 c components of international microcircuits, inc. or one of its sublicensed associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 2 of 15 pin description xin, xout - these pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal (nominally 14.318 mhz). xin may also serve as input for an externally generated reference signal. sel - standard frequency select input. it has internal pull-up. cpuclk - hose clock output primarily use to drive the sdram. cpumclk(0:1) - high drive host clock output primarily used to drive mobil pentium processor modules. sdram(0:5) - synchronous dram dims clocks. they are powered by vddq3. sdram6/cpu_stop# - if mode=1, this pin is a synchronous dram dims clock output. if mode=0, this pin is a cpu_stop# input signal, where a low level stops the cpu however, the sdram clocks will stay active. it has an internal pull-up. sdram7/pci_stop# - if mode=1, this pin is a synchronous dram dims clock output. if mode=0, this pin is a pci_stop# input signal, where a low level stops the pci clocks. it has an internal pull-up. mode - a low level on this pin causes pins 26, and 27 to be power management inputs pci_stop#, and cpu_stop# respectly. a high level on this pin causes pins 26, and 27 to be clock output signals sdram7, and sdram6 respectively. it has an internal pull-up resistor. pciclk(0:5) - low skew (<250ps) clock outputs for pci frequencies. these buffers voltage level is controlled by vddq3 pciclk_f - a pci clock output that does not stop until in power down mode. it is synchronous with other pci clocks. ref(0:2) - buffered outputs of on-chip reference. ioapic0 - buffered output of 14.3mhz for multiprocessor support. it is powered by vddq2. pwr_dwn# - power down pin. when this pin is asserted low, the ic is in shutdown mode where all circuitry is turned off including vco, crystal buffer and pciclk_f. it has an internal pull-up. the i 2 c interface is disabled with the pwr_dwn# pin is low. 48/24mhz(0:1) - programmable 48 mhz or 24 mhz clock outputs. sdata - serial data of i 2 c 2-wire control interface. has internal pull-up resistor. sdclk - serial clock of i 2 c 2-wire control interface. has internal pull-up resistor. vss - ground pins for the chip. vdd - 3.3 volt power supply pins for analog circuit and core logic. vddq3 - power supply pins for 3.3v io pins. vddq2 - power supply pins for 2.5v/3.3v io pins.
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 3 of 15 power management functions all clocks can be individually enabled or stopped via the 2-wire control interface. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. on power up, the vcos will stabilize to the correct pulse widths within about 0.2 ms. the cpu, sdram, and pci clocks transition between running and stopped by waiting for one positive edge on pciclk_f followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. when mode=0, pins 26 and 27 are inputs pci_stop# and cpu_stop# respectively (when mode=1, these functions are not available). a particular output is enabled only when both the serial interface and these pins indicate that it should be enabled. the imisg571d clocks may be disabled according to the following table in order to reduce power consumption. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stopped. on low to high transitions of pwr_dwn#, external circuitry should allow 0.2 ms for the vcos to stabilize prior to assuming the clock periods are correct. the cpu and pci clocks transition between running and stopped by waiting for one positive edge on pciclk_f followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. cpu_stop# pci_stop# pwr_dwn# cpuclk pciclk other clks xtal & vcos x x 0 low low low off 0 0 1 low low running running 0 1 1 low 33/30 mhz running running 1 0 1 66/60 mhz low running running 1 1 1 66/60 mhz 33/30 mhz running running power management timing pciclk_f pci_stop# pciclk(0:5) cpu_stop# cpuclk(0:2)
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 4 of 15 2-wire i 2 c control interface the 2-wire control interface implements a write only slave interface. the imisg571d cannot be read back. sub- addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. the 2- wire control interface allows each clock output to be individually enabled or disabled. it also allows 24/48 mhz frequency selection and test mode enable. during normal data transfer, the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high. there are two exceptions to this. a high to low transition on sdata while sdclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sdclk is high indicates the end of a data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is a 7-bit address with a read/write bit as the lsb. data is transferred msb first. the device will respond to writes to 10 bytes (max) of data to address d2 by generating the acknowledge (low) signal on the sdata wire following reception of each byte. the device will not respond to any other control interface conditions. the i 2 c interface is disabled when the pwr_dwn# pin is low. previously set control registers are retained. serial control registers note: the pin# column lists the affected pin number where applicable. the @pup column gives the state at true power up. bytes are set to the values shown only on true power up, and not when the pwr_dwn# pin is activated. following the acknowledge of the address byte (d2), two additional bytes must be sent: 1) command code byte, and 2) byte count byte. although the data (bits) in these two bytes are considered dont care, they must be sent and will be acknowledged. byte 0: function select register bit @pup pin# description 70 * reserved 60 * reserved 50 * reserved 40 * reserved 3 1 23 48/24 mhz (a1 sets the output to 48mhz, a 0 sets the output to 24mhz) 2 1 22 48/24 mhz (a1 sets the output to 48mhz, a 0 sets the output to 24mhz) 1 0 0 0 bit1 bit0 1 1 tri-state 1 0 spread spectrum operatin g mode 0 1 test mode 0 0 normal operating mode
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 5 of 15 serial control registers (cont.) function table function outputs description cpu pci sdram ref ioapic 24mhz 48mhz tri-state hi-z hi-z hi-z hi-z hi-z hi-z hi-z test mode tclk/2 tclk/4 tclk/2 tclk tclk tclk/4 tclk/2 normal sel=1 66 cpu/2 cpu 14.318 14.318 24 48 normal sel=0 60 cpu/2 cpu 14.318 14.318 24 48 notes: 1. tclk is a test clock over driven on the xin input during test mode. 2. the frequency ratio fout/fin for the usb output is 3.35294. byte 1: cpu, 48/24 mhz clock register ( 1 = enable, 0 = stopped) bit @pup pin# description 7 1 23 48/24 mhz enable/stopped 6 1 22 48/24 mhz enable/stopped 5 x - reserved 4 x - reserved 3,2 1 39 power control for cpumclk1 bit 2 bit 3 0 0 = disabled 1 0 = not allowed 0 1 = not allowed 1 1 = high drive 1 1 41 cpuclk enable/stopped 0 1 42 cpumclk0 enable/stopped byte 2: pci clock register (1 = enable, 0 = stopped) bit @pup pin# description 7x - reserved 6 1 8 pciclk_f enable/stopped 5 1 16 pciclk5 enable/stopped 4 1 14 pciclk4 enable/stopped 3 1 13 pciclk3 enable/stopped 2 1 12 pciclk2 enable/stopped 1 1 11 pciclk1 enable/stopped 0 1 9 pciclk0 enable/stopped
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 6 of 15 serial control registers(continued) byte 3: sdram clock register ( 1 = enable, 0 = stopped ) bit @pup pin# description 7 1 26 sdram7 enable/stopped 6 1 27 sdram6 enable/stopped 5 1 29 sdram5 enable/stopped 4 1 30 sdram4 enable/stopped 3 1 32 sdram3 enable/stopped 2 1 33 sdram2 enable/stopped 1 1 35 sdram1 enable/stopped 0 1 36 sdram0 enable/stopped byte 4: additional sdram clock register (1 = enable, 0 = stopped) bit @pup pin# description 7x - reserved 6x - reserved 5x - reserved 4x - reserved 3x - reserved 2x - reserved 1x - reserved 0x - reserved byte 5: peripheral control (1 = enable, 0 = stopped) bit @pup pin# description 7x - reserved 6x - reserved 5 1 - reserved 4 1 45 ioapic0 enable/stopped 3x - reserved 2 1 47 ref2 enable/stopped 1 1 1 ref1 enable/stopped 0 1 2 ref0 enable/stopped
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 7 of 15 spread spectrum clock generation (sscg) spread spectrum is a modulation technique applied here for maximum efficiency in minimizing electro-magnetic interference radiation generated from repetitive digital signals mainly clocks. a clock accumulates em energy at the center frequency it is generating. spread spectrum distributes this energy over a small frequency bandwidth therefore spreading the same amount of energy over a spectrum. this technique is achieved by modulating the clock down from its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). in this product, the modulation is 1.0% down from the resting frequency. amplitude (db ) frequency(mhz ) modulated center frequency without spectrum spread with spectrum spread spectrum analysis rested center frequency
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 8 of 15 maximum ratings voltage relative to vss: -0.3v voltage relative to vdd: 0.3v storage temperature: -65oc to + 150oc operating temperature: 0oc to +70oc maximum power supply: 7v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 9 of 15 switching characteristics characteristic symbol min typ max units conditions output duty cycle - 45 50 55 % measured at 1.5v cpu to pci offset toff 1 - 4 ns 15 pf load measured at 1.5v buffer out skew all cpu and pci buffer outputs tskew - - 250 ps 15 pf load measured at 1.5v d period adjacent cycles d p - - +250 ps - jitter spectrum 20 db bandwidth from center bw j 500 khz overshoot/undershoot beyond power rails v over - - 1.5 v 22 ohms @ source of 8 inch pcb run to 15 pf load ring back exclusion v rbe 0.7 2.1 v note1 vdd = vddq3 =3.3v 5 %, vddq2 = 2.5v 5 % , ta = 0oc to +70oc note 1: ring back must not enter this range. tb40_v type buffer characteristics for ioapic and cpuclks characteristic symbol min typ max units conditions pull-up current ioh 22 - 31 ma vout = vdd - .5v pull-up current ioh 37 - 56 ma vout = 1.25v pull-down current iol 30 - 41 ma vout = 0.4v pull-down current iol 75 - 102 ma vout = 1.2v rise/fall time min between 0.4 v and 2.0 v trf min 0.4 - - ns 10 pf load rise/fall time max between 0.4 v and 2.0 v trf max - - 1.9 ns 20 pf load vdd = vddq3 =3.3v 5 %, vddq2 = 2.5v 5 % , ta = 0oc to +70oc tb5l type buffer characteristics for ref(1:2) and 48/24 mhz characteristic symbol min typ max units conditions pull-up current ioh 13 - 17 ma vout = vdd - .5v pull-up current ioh 30 - 44 ma vout = 1.5v pull-down current iol 13 - 19 ma vout = 0.4v pull-down current iol 32 44 19 ma vout = 1.5v rise/fall time min between 0.4 v and 2.4 v trf min 1.0 - - ns 10 pf load rise/fall time max between 0.4 v and 2.4 v trf max - - 2.0 ns 20 pf load vdd = vddq3 =3.3v 5 %, vddq2 = 2.5v 5 % , ta = 0oc to +70oc
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 10 of 15 tb40ax type buffer characteristics for ref0 and sdram(0:7) characteristic symbol min typ max units conditions pull-up current ioh 30 - 39 ma vout = vdd - .5v pull-up current ioh 75 - 109 ma vout = 1.5v pull-down current iol 30 - 40 ma vout = 0.4v pull-down current iol 75 - 103 ma vout = 1.2v rise/fall time min between 0.4 v and 2.4 v trf min 0.5 - - ns 20 pf load rise/fall time max between 0.4 v and 2.4 v trf max - - 2.0 ns 30 pf load vdd = vddq3 = 3.3v 5 % , vddq2 = 2.5v 5 % , ta = 0oc to +70oc tb4l type buffer characteristics for pciclk(0:5,f) characteristic symbol min typ max units conditions pull-up current ioh 18 - 23 ma vout = vdd -.5v pull-up current ioh 44 - 64 ma vout = 1.5v pull-down current iol 18 - 25 ma vout = 0.4v pull-down current iol 50 - 70 ma vout = 1.5v rise/fall time min between 0.4 v and 2.4 v trf min 0.5 - - ns 15 pf load rise/fall time max between 0.4 v and 2.4 v trf max - - 2.0 ns 30 pf load vdd = vddq3 =3.3v 5 %, vddq2 = 2.5v 5 % , ta = 0oc to +70oc
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 11 of 15 type 6 buffer characteristics for cpumclk in high drive mode characteristic symbol min typ max units conditions pull-up current ioh 130 180 250 ma vout = 1.0 v pull-up current ioh 65 90 120 ma vout = 2.0 v pull-down current iol 125 170 220 ma vout = 1.2 v pull-down current iol 40 60 80 ma vout = 0.3 v rise/fall time min between 0.4 v and 2.0 v trf min 0.4 - - ns 10 pf load rise/fall time max between 0.4 v and 2.0 v trf max - - 1.6 ns 20 pf load vdd = vddq3 =3.3v 5 %, vddq2 = 2.5v 5 % , ta = 0oc to +70oc crystal and reference oscillator parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerence tc - - +/-100 ppm calibration note 1 ts - - +/- 100 ppm stability (ta -10 to +60c) note 1 ta - - 5 ppm aging (first year @ 25c) note 1 mode om - - - parallell resonant pin capacitance cp 6 pf capacitance of xin and xout pins to ground (each) dc bias voltage v bias 0.3vdd vdd/2 0.7vdd v startup time ts - - 30 m s load capacitance cl - 20 - pf the crystals rated load. note 1 effective series resonant resistance r1 - - 40 ohms power dissipation dl - - 0.10 mw note 1 shunt capacitance co - -- 8 pf crystals internal package capacitance (total) for maximum accuracy,the total circuit loading capacitance should be equal to cl. this loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (cp) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. budgeting calculations typical trace capacitance, (< half inch) is 4 pf, load to the crystal is therefore 2.0 pf clock generator internal pin capacitance of 36 pf, load to the crystal is therefore 3.0 pf external crystal loading capacitors (connect to ground) 15.0 pf the total parasitic capacitance would therefore be = 20.0.0 pf. note 1: it is recommended but not mandatory that a crystal meets these specifications.
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 12 of 15 pcb layout suggestion this is only a layout recommendation for best performance and lower emi. the designer may choose a different approach but c4, c5, c6, c7, c8, c9, c10, c11and c12 (all are 0.1 m f) should always be used and placed close to their vdd pins. imisg571d via to vdd island via to gnd plane vcc 3 . 3v 1 2 3 4 5 6 c4 7 8 10 9 11 12 13 14 c5 15 17 16 18 19 20 c6 21 23 22 24 47 39 38 37 36 35 c9 34 32 33 31 30 29 c8 28 26 27 c12 48 c11 46 45 44 43 42 41 c7 25 c10 40 c3 22 m f fb1 vcc 2 . 5v c14 22 m f fb2
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 13 of 15 package drawing and dimensions 48 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.20 0.31 0.41 a2 0.085 0.090 0.095 2.16 2.29 2.41 b 0.008 0.010 0.0135 0.203 0.254 0.343 c 0.005 .008 0.010 0.127 0.20 0.254 d 0.620 0.625 0.637 15.75 15.88 16.18 e 0.291 0.295 0.299 7.39 7.49 7.59 e 0.0256 bsc 0.640 bsc h 0.395 0.408 0.420 10.03 10.36 10.67 l 0.024 0.030 0.040 0.61 0.76 1.02 a0o 4o8o 0o4o8o b e a a 1 a 2 e a l c d h
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 14 of 15 package drawing and dimensions (cont.) bo surfaces roughness: 6+ 27n(rz) d -b- 385 e1 l20 r0.1 b e -c- c 0.07 rd 4 [10 typ r1.30 1.0 0.10~0.15 0.00 ~ 0.05 section v-v e 0.05 max. 0.05 max. 1.0 1.0 e 4 [2? r0.15 a a1 0.25 a2 r l1 l a (8?) b c c1 b1 det .08 cb a det 48 pin tssop dimensions inches millimeters symbol min nom max min nom max a - - 0.0433 - - 1.10 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.033 0.035 0.037 0.85 0.90 0.95 l 0.019 0.023 0.029 0.50 0.60 0.75 r 0.043 - - 0.10 - - b 0.006 - 0.010 0.170 - 0.27 b1 0.006 0.008 0.009 0.170 0.20 0.225 c 0.004 - 0.007 0.105 - 0.175 c1 0.004 0.005 0.006 0.105 0.125 0.145 q 0 - 8 0 - 8 e 0.020 bsc 0.50 bsc d 0.488 0.492 0.496 12.40 12.50 12.60 e 0.313 0.319 0.325 7.95 8.1 8.25 e1 0.236 0.240 0.244 6.00 6.1 6.20
sg571d i 2 c frequency clock generator w/ emi reduction spread spectrum technology for pentium processor based designs. approved product international microcircuits, inc. 525 los coches st. rev.1.4 8/10/98 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 15 of 15 ordering information part number package type production flow IMISG571DYB 48 pin ssop commercial, 0oc to +70oc imisg571dtb 48 pin tssop commercial, 0oc to +70oc note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: imi sg571dyb date code, lot # IMISG571DYB flow b = commercial, 0oc to + 70oc package y = ssop t = tssop revision imi device number

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