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april 2005 document control #ml0028 rev 0.8 1 STK18TA8 nvtime tm event data recorder serial peripheral interface nvsram quantumtrap tm cmos nonvolatile static ram preliminary features ? data integrity of simt ek nvsram combined with full-featured real-time clock ? 40 mhz spi interface with compatible commands to industry standards 1 mbit spi eeproms ? store to quantumtrap? nonvolatile elements is initiated by software , device pin or autostore ? on power down ? recall to sram initiated by software or power restore ? unlimited read and write and recall cycles ? watchdog timer ? clock alarm with programmable interrupts ? capacitor or battery backup for rtc ? single 3v +20%, -10% operation ? commercial and industrial temperatures ? high-reliability o endurance to 1 million cycles o retention to 100 years at 85 oc ? package: 48-pin ssop description the simtek STK18TA8 combines a 1 mbit nonvolatile static ram and a full-featured real-time clock, in a reliable, monolithic integrated circuit. a serial peripheral interface (spi) makes system integration simple. the embedded nonvolatile elements incorporate simtek?s quantumtrap tm technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap tm cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. the real-time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. the alarm function is programmable for one-time alarms or periodic seconds, minutes, hours, or days. there is also a programmable watchdog timer for process control. block diagram column dec column i/o power control store/ recall control quantum trap 1024 x 1024 static ram array 1024 x 1024 store recall v cc v cap rtc x 1 x 2 int v rtcbat v rtccap row decoder address data spi controller sck si so cs hsb hold figure 1. block diagram
STK18TA8 april 2005 document control #ml0028 rev 0.8 2 packages pin descriptions pin name i/o description si - serial input input the si pin is used to transfer data into the device. data is latched from this pin on the rising edge of the sck clock pin. instructions, addresses and data are all transmitted over this pin. so - serial output 3-state output the so pin is used to transfer data out of the STK18TA8. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. cs - chip select input a low level on this pin selects the device. a falling edge is required on cs before each command code. nonvolatile operations which are already in progress will be completed regardless of the cs input signal. when the device is deselected, so goes to the high impedance state allowing other devices to share the spi bus. when cs is held high and all internal commands have completed the device enters the standby mode (low-power). sck - serial clock input the sck is used to synchronize the communication between a master and the STK18TA8. instructions, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data placed on the so pin changes on the falling edge of the clock input. hold input the hold pin is used to pause the serial interface. if hold is driven low, the chip ignores all serial input as long as cs is held low. when hold is again driven high, normal operation resumes on the next clock edge. if cs is driven high at any time, the hold operation is aborted. this pin has an internal pullup. v cc - chip power power the v cc pin supplies the power for the chip during normal operation. v ss - chip ground power ground. v cap - power for non- volatile autostore tm power a capacitor should be connected with a minimum of 17uf, 5v minimum. upon power down, v cap supplies the power for the autostore tm operation whereby sram data elements are transferred in parallel to the nonvolatile quantumtrap tm elements. v rtccap power capacitor supplied backup rtc supply voltage. (left unconnected if v rtcbat is used.) v rtcbat power battery supplied backup rtc supply voltage. (left unconnected if v rtccap is used. ) x 1 - crystal out output crystal connection, drives crystal on startup. x 2 - crystal in input crystal connection, 32.768khz crystal. hsb - store request and status in/output when low this output indicates a hardware store is in progress. when pulled low externally to the chip it will initiate a nonvolatile store operation. left undriven the pin is weakly pulled up internal to the chip. store operation will not be started when v cc is below v switch . int - interrupt out output pin which can be programmed to respond to the clock alarm, the watchdog timer, or the power monitor. programmable to either active high (push/pull) or active low (open-drain). (blank) no connect unlabeled pins should be left with no connections on the printed circuit board. 48 pin ssop v cap v ss v rtcbat int v cc v ss v rtccap 1 2 3 4 5 6 7 8 9 1 0 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 si x 1 sck x 2 so v cc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 hsb cs v ss v ss hold pcb area usage. see website for detailed package size specifications. ssop
STK18TA8 april 2005 document control #ml0028 rev 0.8 3 package thermal characteristics see website: http://www.simtek.com/ dc characteristics commercial industrial symbol parameter min max min max units notes i cc1 average v cc current 10 10 ma based on 40mhz cycle rate. values obtained without output loads. i cc2 average v cc current during store 3 3 ma all inputs don?t care, v cc = max average current for duration of store cycle (t store ). i cc4 average v cap current during autostore ? cycle 3 3 ma all inputs don?t care average current for duration of store cycle (t store ). i sb v cc standby current (standby, stable cmos input levels) 2 2 ma all others v in 0.2v or (v cc ? 0.2v) standby current level after nonvolatile cycle is complete. v cc = max i ilk input leakage current 1 1 a v in = v ss to v cc v cc = max i olk off-state output leakage current 1 1 a v in = v ss to v cc v ih input logic ?1? voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v all inputs v il input logic ?0? voltage v ss ? 0.5 0.8 v ss ? 0.5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ?2ma v ol output logic ?0? voltage 0.4 0.4 v i out = 4ma t a operating temperature 0 70 ?40 85 o c v cc operating voltage 2.7 3.6 2.7 3.6 v nominal 3.0v +20%, -10% used for tested specifications. v cap storage capacitor 17 57 17 57 f between vcap pin and vss, 5v rated. absolute maximum ratings a power supply voltage voltage on input relative to v ss voltage on outputs temperature under bias junction temperature storage temperature power dissipation dc output current (1 output at a time, 1s duration) notes a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at con- ditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability. -0.5v to +4.1v -0.5v to (v cc + 0.5v) -0.5v to (v cc + 0.5v) ?55 c to 125 c ?55 c to 140 c ?65 c to 150 c 1w 15ma
STK18TA8 april 2005 document control #ml0028 rev 0.8 4 ac test conditions capacitance b (t a = 25 c, f = 1.0mhz) symbol parameter max units conditions c in input capacitance 7 pf ? v = 0 to 3v c out output capacitance 7 pf ? v = 0 to 3v notes b: these parameters are guaranteed but not tested 3.0v 30 pf including scope and fixture 577 ohms 789 ohms output 3.0v 5 pf including scope and fixture 577 ohms 789 ohms output figure 3. ac output loading, for tri- state specs ( t dis ) figure 2. ac output loading input pulse levels input rise and fall times input and output timing reference levels output load 0v to 3v 5ns 1.5v see figure 2 and figure 3
STK18TA8 april 2005 document control #ml0028 rev 0.8 5 rtc dc characteristics commercial industrial symbol parameter min max min max units notes i bak rtc backup current - 300 - 350 na from either v rtccap or v rtcbat v rtcbat rtc battery pin voltage 1.8 3.3 1.8 3.3 v typical = 3.0 volts during normal operation v rtccap rtc capacitor pin voltage 1.2 2.7 1.2 2.7 v typical = 2.4 volts during normal operation - 1 - 1 min @ min temperature from power up or enable t oscs rtc oscillator time to start - 10 - 10 sec @25oc from power up or enable rtc recommended component configuration c 1 x 1 x 2 c 2 rf y 1 recommended values y 1 = 32.768 khz rf = 10m ohm c 1 = 2.2 pf c 2 = 47 pf figure 4. rtc component configuration
STK18TA8 april 2005 document control #ml0028 rev 0.8 6 ac parameters STK18TA8 no. symbols parameter min max units 1 f clk clock frequency 40 mhz 2 t css cs setup time 5 ns 3 t csh cs hold time 25 ns 4 t wh sck high time 10 ns 5 t wl sck low time 10 ns 6 t su si, setup time 3 ns 7 t h si, hold time 5 ns 8 t cs cs high time 5 ns 9 t v falling sck to output valid 7 ns 10 t ho output hold time 3 ns 11 t dis output disable time 10 ns spi tm input timing cs sck 2 t css 1 1/f clk 6 t su 7 t h 4 t wh 5 t wl si 8 t cs 3 t csh spi tm output timing cs sck so 7 11 t dis hi-z 6 5 9 t v delay byte
STK18TA8 april 2005 document control #ml0028 rev 0.8 7 autostore ? /power-up recall STK18TA8 no. symbols parameter min max units notes 12 t hrecall power-up recall duration 20 ms c 13 t store store cycle duration 12.5 ms d 14 v switch low voltage trigger level 2.55 2.65 v 15 t vccrise v cc rise time 150 s notes c: t hrecall starts from the time v cc rises above v switch d: if an sram write has not taken place since the last nonvolatile cycle, no store will take place note: read and write cycles will be ignored during store, recall and while v cc is below v switch. power-up recall v cc 13 t store 12 t hrecall 14 v switch autostore tm power down autostore tm brown-out autostore tm power-up recall read & write inhibited 15 t vccrise 13 t store 12 t hrecall power-up recall store occurs only if a sram write has happened. no store occurs without at least one sram write.
STK18TA8 april 2005 document control #ml0028 rev 0.8 8 hardware store cycle symbols STK18TA8 no. standard alternate parameter min max units notes 16 t hlhx hardware store pulse width 15 ns 17 t hlbl hardware store low to store busy 300 ns hsb (in) (out) hsb 16 t hlhx 13 t store 17 t hlbl hi-z software store cycle (ctlseq command) symbols STK18TA8 no. standard alternate parameter min max units notes 18 t recall recall duration 40 s note: the parameter t store or t recall are substituted for store or recall command respectively. endurance parameters symbols STK18TA8 no. standard alternate parameter min max units notes 19 sram write cycles infinite cycles 20 number of store cycles 1 x 10 6 cycles
STK18TA8 april 2005 document control #ml0028 rev 0.8 9 hold signal timing symbols STK18TA8 no. standard alternate parameter min max units notes 21 t ch sck to hold change 5 ns e 22 t hqz hold active to output inactive 10 ns 23 t hqx hold inactive to output active 0 ns notes e: it is recommended that hold change on negative transitions of the sck or while sck is low. cs sck 21 t ch so hold 21 t ch 22 t hqz 23 t hqx 22 t hqz 23 t hqx normal operation hold delayed to falling edge of sck normal operation hold changes while sck low (recommended) normal operation
STK18TA8 april 2005 document control #ml0028 rev 0.8 10 serial interface description the STK18TA8 is a 1 mbit serial nvsram (sram + nonvolatile element in a combined cell) with 128k x 8 organization designed to interface directly with the serial peripheral interface (spi) port of many popular microcontrollers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/o lines programmed properly with the software. the STK18TA8 spi interface contains an 8-bit instruction register. data is clocked into the device through the si pin on the rising edge of sck. the cs pin must be low for the entire data transfer. table 1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses, and data are transferred msb first, lsb last. data is sampled on the first rising edge of sck after cs goes low. refer to figure 5 which shows the connection of multiple spi devices. the so output is shared since only the slave selected by cs and a valid opcode is returns data to the master. if no slave is selected the so pin is tri-stated. if the master device has a bi-directional pin capability, the so and si pins may be shared by having the master switch the pin to input when data is expected from one of the slave spi devices. data out (mosi) data in (miso) clock (spick) ss0 ss1 ss2 ss3 si so sck cs# si so sck cs# si so sck cs# si so sck cs# master: mpu slave: devices figure 5. multiple device system serial peripheral interface
STK18TA8 april 2005 document control #ml0028 rev 0.8 11 table 1. spi tm instruction set instruction name code description read 0x03 read sram data from selected address. write 0x02 write sram data from selected address. fread 0x0b fast read of sram data from selected address. (first byte is the delay byte). ctlseq 0x0f device control command sequence. table 2. control command sequences command name cmd bytes description store 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 commands device to transfer the sram data to the nonvolatile memory elements. recall 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 commands device to transfer the nonvolatile memory contents to the sram memory. autoena 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 turns on the autostore tm feature of the device, enabling automatic stores to nonvolatile memory when v cc drops below v switch . autodis 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 turns off the autostore tm feature of the device, disabling the automatic stores to nonvolatile memory. stores invoked by the control command store sequence and stores invoked by driving the hsb pin remain enabled.
STK18TA8 april 2005 document control #ml0028 rev 0.8 12 spi modes explained spi mode 0 and 3 are supported for the STK18TA8 device. in both modes, data is received from the spi master by presenting data t su ns before the rising edge of the clock. data is driven out the so pin on the falling edge of sck and received by the spi master on the rising edge. mode 0 and mode 3 differ in the state of the sck signal when cs falls or rises. mode 0 has sck=0 during sck falls or rises. mode 3 has sck high when cs falls or rises. the mode is important for hardware spi controllers and less so for firmware based control. refer to figure 6 for a diagram of signal waveforms. cs sck 0 si so 7 6 1 0 mode 3 mode 0 23 22 21 2 1 0 7 6 1 0 1 6 7 8 9 30 31 29 10 32 33 38 39 7 6 1 0 40 41 46 47 mode 0 mode 3 figure 6. spi mode waveforms
STK18TA8 april 2005 document control #ml0028 rev 0.8 13 nvsram the STK18TA8 nvsram is made up of two functional components paired in the same physical cell. these are a sram memory cell and a nonvolatile quantumtrap ? cell . the sram memory cell operates as a standard fast static ram. data in the sram can be transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique architecture allows all cells to be stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the STK18TA8 supports unlimited reads and writes just like a typical sram. in addition, it provides unlimited recall operations from the nonvolatile cells and up to 1 million store operations. sram read reading the STK18TA8 via the so (serial output) pin requires the following sequence. after the cs line is pulled low to select a device, the read op-code is transmitted via the si line clocked in on each rising edge of sck followed by a 3 byte address to be read (refer to table 6). all data is sent with the most significant bit first. after the address bytes sck must complete eight cycles. this allows time for the memory to be access and the data to be loaded into the output shift register. on the falling edge of the 32 th clock cycle (after the command, and 3 address bytes) the data at the specified address is shifted out on the so output. every falling edge of sck will generate another data bit to be sampled by the master device on the next rising edge of sck. the read command can be continued by continuously holding the cs line low and supplying additional sck pulses. internally the byte address is automatically incremented and data will continue to be shifted out. the delay byte is only required on first memory access after the read command. all subsequent reads are pipelined and are output on consecutive sck falling edges. when the highest sram address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. when the cs line goes inactive the read command is terminated. please note that the top 16 bytes of the memory space represent the rtc functions. the proper method for reading these registers accurately is described in the ?real time clock operation? section of this document. to logically separate the rtc registers from the sram accesses, read commands wrap back to 0x0000 after accessing 0x1ffef. reads from addresses above 0x1ffef, which represents the rtc address space, do not advance the address counter. only 1 byte is read. as long as cs is held low the same byte will continue be read. figure 7. read command multi-byte example device operation
STK18TA8 april 2005 document control #ml0028 rev 0.8 14 sram fread a fast read command is also provided on the STK18TA8 spi interface. this command operates like the standard read command except that a delay byte is inserted between the last address bit and the first valid data bit. the master spi controller is required to supply 8 delay byte clock cycles. on the rising edge of the 9 th cycle the most significant bit of the memory byte is ready to on the so output. this command is provided for systems that require the maximum clock frequency but are unable to provide the delay required for the sram access prior to valid data on so. so is not driven during the delay byte and data during this time period is considered invalid. figure 8. fast read command multi-byte example sram write writing to the STK18TA8 requires the following sequence. after the cs line is pulled low to select the device, the write op-code is transmitted via the si line (msb first) followed by a three-byte address and the data (d7 - d0) to be programmed (refer to table 6). a single or unlimited number of data bytes may be sent after the first byte and the address will increment after each byte is received. the write command is terminated when cs pin goes inactive. please note that the top 16 bytes of the memory space represent the rtc registers on the chip. the proper method for writing these registers accurately is described in the ?real time clock operation? section of this document. to logically separate the rtc registers from the sram access write commands will wrap back to 0x0000 after writing 0x1ffef. writes targeted for addresses above 0x1ffef which represent the rtc address space, do not advance the address counter. only one data byte is expected in write commands targeted for the rtc. if multiple bytes are sent, later bytes will overwrite bytes sent earlier. figure 9. write command multi-byte example
STK18TA8 april 2005 document control #ml0028 rev 0.8 15 autostore ? operation the STK18TA8 stores data to nvsram using one of three storage operations. t hese three operations are hardware store, activated by hsb , software store, activated by a spi command, and autostore ?, activated on device power down. autostore ? operation is a unique feature of simtek quantumtrap ? technology and is enabled by default on the STK18TA8. during normal operation, the device will draw current from vcc to charge a capacitor connected to the vcap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the vcc pin drops below vswitch, the part will automatically disconnect the vcap pin from vcc. a store operation will be initiated with power provided by the vcap capacitor. figure 10 shows the proper connection of the storage capacitor (vcap) for automatic store operation. refer to the dc characteristics table for the size of vcap. the voltage on the vcap pin is driven to 5v by a charge pump internal to the chip. to reduce unneeded nonvolatile stores, autostore ? and hardware store operations will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. the hsb signal can be monitored by the system to detect a store cycle is in progress. v cc v cap 0.1f v cc v cap figure 10. autostore tm mode
STK18TA8 april 2005 document control #ml0028 rev 0.8 16 hardware store (hsb ) operation the STK18TA8 provides the hsb pin for controlling and monitoring the store operations. the hsb pin can be used to request a hardware store cycle. when the hsb pin is driven low, the STK18TA8 will conditionally initiate a store operation. an actual store cycle will only begin if a write to the sram took place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. the spi controller checks the state of the hsb pin just after the final bit of each byte being written. if hsb is active the write operation is cancelled. however, if hsb goes low after the write operation has been initiated the write will complete before the store operation is started. memory read and incomplete spi commands will be cancel led and/or ignored when hsb is active. during any store operation, regardless of how it was initiated, the STK18TA8 will continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the STK18TA8 will remain disabled until the hsb pin returns high. if hsb is not used, it should be left unconnected. hardware recall (power-up) during power up, or after any low-power condition (v cc < v switch ), an internal recall request will be latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle will automatically be initiated and will take t hrecall to complete. software store data can be transferred from the sram to the nonvolatile memory by using a spi command. the STK18TA8 software store cycle is initiated by issuing a ctlseq command through the spi interface. during the store cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. once a store cycle is initiated, further read and write commands are ignored until the cycle is completed. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. please see table 2 and figure 11 for details on how to issue the appropriate ctlseq. software recall data can be transferred from the nonvolatile memory to the sram by using a spi command. a software recall cycle is initiated by issuing a ctlseq command through the spi interface. internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvolatile information is transferred into the sram cells. once a recall cycle is initiated, further read and write commands are ignored until the cycle is completed. after the t recall cycle time the sram will once again be ready for read and write operations. the recall operation in no way alters the data in the nonvolatile elements. please see table 2 and figure 11 for details on how to issue the appropriate ctlseq. figure 11. control sequence command example
STK18TA8 april 2005 document control #ml0028 rev 0.8 17 preventing autostore tm the autostore ? function can be disabled by initiat- ing an autostore disable ctlseq command. the autostore ? can be re-enabled by initiating an autostore enable ctlseq command. if the autostore ? function is disabled or re-enabled a manual store operation (hardware or software) needs to be issued to save the autostore state through subsequent power down cycles. the part comes from the factory with autostore ? enabled. please see table 2 and figure 11 for details on how to issue the appropriate ctlseq. when autostore ? is disabled as described above the rtc registers are not saved on power down. if the rtc registers are changed during system operation a ctlseq store needs to be issued to update the non-volatile memory. hold operation the hold pin is used to pause serial communications without aborting the command in progress. this can be useful if the spi master is interrupted during a burst read or write to service another device. the hold signal is intended to be asserted while sck is low and to be de-asserted again while sck is low. hold is recognized by the STK18TA8 only when sck is low. if hold changes state while sck is high the hold state will not be recognized until the next falling edge of sck. during the hold state sck can toggle and devices sharing so and si can use these signal lines to communicate without disturbing the command in progress on this device. the STK18TA8 releases the so pin during the duration of the hold operation so that other devices may communicate with the spi master. cs must be held low selecting the device during the hold operation. if the cs goes high while a hold is in progress the command will be terminated. data protection the STK18TA8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated store and write operations. the low- voltage condition is detected when v cc < v switch . noise considerations the STK18TA8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss , using leads and traces that are as short as pos- sible. as with all high-speed cmos ics, careful routing of power, ground and signals will reduce circuit noise. figure 12. hold operation example
STK18TA8 april 2005 document control #ml0028 rev 0.8 18 nvtime operation the STK18TA8 offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. internal double buffering of the clock and the clock/timer information registers prevents accessing transitional internal clock data during a read or write operation. double buffering also cir- cumvents disrupting normal timing counts or clock accuracy of the internal clock while accessing clock data. clock and alarm registers store data in bcd format. clock operations the clock registers maintain time up to 9,999 years in one second increments. the user can set the time to any calendar time and the clock automatically keeps track of days of the week and month, leap years and century transitions. there are eight registers dedicated to the clock functions which are used to set time with a write cycle and to read time during a read cycle. these registers contain the time of day in bcd format. bits defined as ?x? are currently not used and are reserved for future use by simtek. reading the clock while the double-buffered rtc register structure reduces the chance of reading incorrect data from the clock, the user should halt internal updates to the STK18TA8 clock registers before reading clock data to prevent the reading of data in transition. stopping the internal register updates does not affect clock accuracy. the updating process is stopped by writing a ?1? to the read bit ?r? (in the flags register at 0x1fff0), and will not restart until a ?0? is written to the read bit. the rtc registers can then be read while the internal clock continues to run. within 20ms after a ?0? is written to the read bit, all STK18TA8 registers are simultaneously updated. setting the clock setting the write bit ?w? (in the flags register at 0x1fff0) to a ?1? halts updates to the STK18TA8 registers. the correct day, date and time can then be written into the registers in 24-hour bcd format. the time written is referred to as the ?base time.? this value is stored in nonvolatile registers and used in calculation of the current time. resetting the write bit to ?0? transfers those values to the actual clock counters, after which the clock resumes normal operation. backup power the rtc in the STK18TA8 is intended for permanently powered operation. either the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when primary power, v cc , fails and drops below v switch the device will switch to the backup power supply. the clock oscillator uses very little current, which maximizes the backup time available from the backup source. regardless of clock operation with the primary source removed, the data stored in nvsram is secure, having been stored in the nonvolatile elements as power was lost. factors to be considered when choosing a backup power source include: the expected duration of power outages and the cost trade-off of using a battery versus a capacitor. during backup operation the STK18TA8 consumes a maximum of 300 nanoamps at 2 volts. capacitor or battery values should be chosen according to the application. backup time values based on maximum current specs are shown below. nominal times are approximately 3 times longer. capacitor value backup time 0.1 f 72 hours 0.47 f 14 days 1.0 f 30 days using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. real time clock operation
STK18TA8 april 2005 document control #ml0028 rev 0.8 19 if a battery is used, a 3v lithium is recommended and the STK18TA8 will only source current from the bat- tery when the primary power is removed. the battery will not, however, be recharged at any time by the STK18TA8. the battery capacity should be chosen for total anticipated cumulative down-time required over the life of the system. stopping and starting the oscil- lator the oscen bit in calibration register at 0x1fff8 controls the starting and stopping of the oscillator. this bit is nonvolatile and shipped to customers in the "enabled" (set to 0) state. to preserve battery life while system is in storage oscen should be set to a 1. this will turn off the oscillator circuit extending the battery life. if the oscen bit goes from disabled to enabled, it will take approximately 5 seconds (10 seconds max) for the oscillator to start. the STK18TA8 has the ability to detect oscillator failure. this is recorded in the oscf (oscillator failed bit) of the flags register at address 0x1fff0. when the device is powered on (v cc goes above v switch ) the oscen bit is checked for "enabled" status. if the oscen bit is enabled and the oscillator is not active, the oscf bit is set. the user should check for this condition and then write a 0 to clear the flag. it should be noted that in addition to setting the oscf flag bit, the time registers are reset to the ?base time? (see the section ?setting the clock?), which is the value last written to the timekeeping registers. the control/calibration register and the oscen bit are not affected by the oscillator failed condition. if the voltage on the backup supply (either v rtccap or v rtcbat ) falls below their respective minimum level the oscillator may fail, leading to the oscillator failed condition which can be detected when system power is restored. the value of oscf should be reset to 0 when the time registers are written for the first time. this will initialize the state of this bit which may have become set when the system was first powered on. calibrating the clock the rtc is driven by a quartz controlled oscillator with a nominal frequency of 32.768 khz. clock accuracy will depend on the quality of the crystal, usually specified to 35 ppm limits at 25 c. this error could equate to + 1.53 minutes per month. the STK18TA8 employs a calibration circuit that can improve the accuracy to +1/-2 ppm at 25 c. the calibration circuit adds or subtracts counts from the oscillator divider circuit. the number of times pulses are suppressed (sub- tracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibration register at 0x1fff8. adding counts speeds the clock up; subtracting counts slows the clock down. the calibration bits occupy the five lower order bits in the control register 8. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibration and a ?0? indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary ?1? is loaded into the register, only the first 2 minutes of the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles. that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. in order to determine how to set the calibration one may set the cal bit in the flags register at 0x1fff0 to 1, which causes the int pin to toggle at a nominal 512 hz. any deviation measured from the 512 hz will indicate the degree and direction of the required correction. for example, a reading of 512.010124 hz would indicate a +20 ppm error, requiring a -10 (001010) to be loaded into the calibration register. note that setting or changing the calibration register does not affect the frequency test output frequency. alarm the alarm function compares user-programmed val- ues to the corresponding time-of-day values. when a match occurs, the alarm event occurs. the alarm drives an internal flag, af, and may drive the int pin if desired. there are four alarm match fields. they are date, hours, minutes and seconds. each of these fields also has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field will be used in the match process. depending on the match bits, the alarm can occur as specifically as one particular second on one day of the month, or as frequently as once per second
STK18TA8 april 2005 document control #ml0028 rev 0.8 20 continuously. the msb of each alarm register is a match bit. selecting none of the match bits (all 1?s) indicates that no match is required. the alarm occurs every second. setting the match select bit for seconds to ?0? causes the logic to match the seconds alarm value to the current time of day. since a match will occur for only one value per minute, the alarm occurs once per minute. likewise, setting the seconds and minutes match bits causes an exact match of these values. thus, an alarm will occur once per hour. setting seconds, minutes and hours causes a match once per day. lastly, selecting all match values causes an exact time and date match. selecting other bit combinations will not produce meaningful results; however the alarm circuit should follow the functions described. there are two ways a user can detect an alarm event, by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x1fff0 will indicate that a date/time match has occurred. the af bit will be set to 1 when a match occurs. reading the flags/control register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. watchdog timer the watchdog timer is a free running down counter that uses the 32 hz clock (31.25 ms) derived from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the counter consists of a loadable register and a free running counter. on power up, the watchdog time-out value in register 0x1fff7 is loaded into the counter load register. counting begins on power up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to 1. the counter is compared to the terminal value of 0. if the counter reaches this value, it causes an internal flag and an optional interrupt output. the user can prevent the time-out interrupt by setting wds bit to 1 prior to the counter reaching 0. this causes the counter to be reloaded with the watchdog time-out value and to be restarted. as long as the user sets the wds bit prior to the counter reaching the terminal value, the inter- rupt and flag never occurs. new time-out values can be written by setting the watchdog write bit to 0. when the wdw is 0 (from the previous operation), new writes to the watchdog time- out value bits d 5 -d 0 allow the time-out value to be modified. when wdw is a 1, then writes to bits d 5 -d 0 will be ignored. the wdw function allows a user to set the wds bit without concern that the watchdog timer value will be modified. a logical diagram of the watchdog timer is shown below. note that setting the watchdog time-out value to 0 would be otherwise meaningless and therefore disables the watchdog function. the output of the watchdog timer is a flag bit wdf that is set if the watchdog is allowed to time-out. the flag is set upon a watchdog time-out and cleared when the flags/control register is read by the user. the user can also enable an optional interrupt source to drive the int pin if the watchdog time-out occurs. power monitor the STK18TA8 provides a power management scheme with power-fail interrupt capability. it also controls the internal switch to backup power for the clock and protects the memory from low-v cc access. the power monitor is based on an internal band-gap reference circuit that compares the v cc voltage to various thresholds. as described in the autostore ? section previously, when v switch is reached as v cc decays from power loss, a data store operation is initiated from sram to the nonvolatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source no data may be read or written and the clock functions are not available to the user. the clock continues to operate in the background. updated clock data is available to oscillator clock divider counter load register zero compare watchdog register wds wdf wdw 32 hz 1 hz d q q write to watchdog register 32.768kh 2 figure 13. watchdog timer block diagram
STK18TA8 april 2005 document control #ml0028 rev 0.8 21 the user after t hrecall delay (see autostore ? /power-up recall ) after v cc has been restored to the device. interrupts the STK18TA8 provides three potential interrupt sources. they include the watchdog timer, the power monitor, and the clock/calendar alarm. each can be individually enabled and assigned to drive the int pin. in addition, each has an associated flag bit that the host processor can use to determine the cause of the interrupt. some of the sources have additional control bits that determine functional behavior. in addition, the pin driver has three bits that specify its behavior when an interrupt occurs. a functional diagram of the interrupt logic is shown below. the three interrupts each have a source and an enable. both the source and the enable must be active (true high) in order to generate an interrupt output. only one source is necessary to drive the pin. the user can identify the source by reading the flags/control register, which contains the flags associated with each source. all flags are cleared to 0 when the register is read. the cycle must be a complete read cycle ( we high); otherwise the flags will not be cleared. the power monitor has two pro- grammable settings that are explained in the power monitor section. once an interrupt source is active, the pin driver determines the behavior of the output. it has two programmable settings as shown below. pin driver control bits are located in the interrupts register. according to the programming selections, the pin can be driven in the backup mode for an alarm interrupt. in addition, the pin can be an active low (open-drain) or an active high (push-pull) driver. if programmed for operation during backup mode, it can only be active low. lastly, the pin can provide a one-shot function so that the active condition is a pulse or a level condition. in one-shot mode, the pulse width is internally fixed at approximately 200 ms. this mode is intended to reset a host microcontroller. in level mode, the pin goes to its active polarity until the flags/control register is read by the user. this mode is intended to be used as an interrupt to a host microcontroller. the control bits are summarized as follows: watchdog interrupt enable - wie. when set to 1, the watchdog timer drives the int pin as well as an internal flag when a watchdog time-out occurs. when wie is set to 0, the watchdog timer affects only the internal flag. alarm interrupt enable - aie. when set to 1, the alarm match drives the int pin as well as an internal flag. when set to 0, the alarm match only affects to internal flag. power fail interrupt enable - pfe. when set to 1, the power fail monitor drives the pin as well as an internal flag. when set to 0, the power fail monitor affects only the internal flag. high/low - h/l. when set to a 1, the int pin is active high and the driver mode is push-pull. the int pin can drive high only when v cc >v switch . when set to a 0, the int pin is active low and the drive mode is open- drain. active low (open drai n) is operational even in battery backup mode. pulse/level - p/l. when set to a 1 and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/l is set to a 0, the int pin is driven high or low (determined by h/l) until the flags/control register is read. when an enabled interrupt source activates the int pin, an external host can read the flags/control reg- ister to determine the cause. remember that all flags will be cleared when the register is read. if the int pin is programmed for level mode, then the condition will clear and the int pin will return to its inactive state. if the pin is programmed for pulse mode, then reading the flag also will clear the flag and the pin. the pulse will not complete its specified duration if the flags/control register is read. if the int pin is used as a host reset, then the flags/control register should not be read during a reset. figure 14. interrupt block diagram watchdog time r power monito r clock alarm pf pfe vint aie af p/l h/l pin drive r int v cc wie wdf v ss
STK18TA8 april 2005 document control #ml0028 rev 0.8 22 during a power-on reset with no battery, the interrupt register is automatically loaded with the value 24h. this causes power-fail interrupt to be enabled with an active-low pulse. rtc register map bcd format data register d7 d6 d5 d4 d3 d2 d1 d0 function / range 0x1ffff 10s years years years: 00-99 0x1fffe 0 0 0 10s months months months: 01-12 0x1fffd 0 0 10s day of month day of month day of month: 01-31 0x1fffc 0 0 0 0 0 day of week day of week: 01-07 0x1fffb 0 0 10s hours hours hours: 00-23 0x1fffa 0 10s minutes minutes minutes: 00-59 0x1fff9 10s seconds seconds seconds: 00-59 0x1fff8 oscen 0 cal sign calibration calibration values* 0x1fff7 wds wdw wdt watchdog* 0x1fff6 wie aie pfe abe h/l p/l 0 0 interrupts* 0x1fff5 m 0 10s alarm date alarm day alarm, day of month: 01-31 0x1fff4 m 0 10s alarm hours alarm hours alarm, hours: 00-23 0x1fff3 m 10 alarm minutes alarm minutes alarm, minutes: 00-59 0x1fff2 m 10 alarm seconds alarm seconds alarm, seconds: 00-59 0x1fff1 10s centuries cent uries centuries: 00-99 0x1fff0 wdf af pf oscf 0 cal w r flags* * - is a binary value, not a bcd value. 0 - not implemented, reserved for future use.
STK18TA8 april 2005 document control #ml0028 rev 0.8 23 register map detail timekeeping ? years 0x1ffff d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. lower nibble contains the value for years; upper nibble contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0-99. timekeeping ? months 0x1fffe d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. the range for the register is 1-12. timekeeping ? date 0x1fffd d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. the range for the register is 1-31. leap years are automatically adjusted for. timekeeping ? day 0x1fffc d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble contains a value that correlates to day of the week. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, as the day is not integrated with the date. timekeeping ? hours 0x1fffb d7 d6 d5 d4 d3 d2 d1 d0 12/24 0 10s hours hours contains the bcd value of hours in 24 hour format. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0-23. timekeeping ? minutes 0x1fffa d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. the range for the register is 0-59. timekeeping ? seconds 0x1fff9 d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. the range for the register is 0- 59.
STK18TA8 april 2005 document control #ml0028 rev 0.8 24 calibration / control 0x1fff8 d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to 1, the oscillator is halted. when set to 0, the oscillator runs. disabling the oscillator saves battery/capacitor power during storage. on a no-battery power-up, this bit is set to 0. calibration sign determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. calibration these five bits control the calibration of the clock. watchdog timer 0x1fff7 d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to 1 reloads and restarts the watchdog timer. setting the bit to 0 has no affect. the bit is cleared automatically once the watchdog timer is reset. the wds bit is write only. reading it always will return a 0. wdw watchdog write enable. setting this bit to 1 masks the watchdog time-out value (wdt5-wdt0) so it cannot be written. this allows the user to strobe the watchdog without disturbing the time-out value. setting this bit to 0 allows bits 5-0 to be written on the next write to the watchdog register. the new value will be loaded on the next internal watchdog clock after the write cycle is complete. this function is explained in more detail in the watchdog timer section. wdt watchdog time-out selection. the watchdog timer interval is selected by the 6-bit value in this register. it represents a multiplier of the 32 hz count (31.25 ms). the minimum range or time-out value is 31.25 ms (a setting of 1) and the maximum time-out is 2 seconds (setting of 3fh). setting the watchdog timer register to 0 disables the timer. these bits can be written only if the wdw bit was cleared to 0 on a previous cycle. interrupt status / control 0x1fff6 d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfie abe h/l p/l 0 0 wie watchdog interrupt enable. when set to 1 and a watchdog time-out occurs, the watchdog timer drives the int pin as well as the wdf flag. when set to 0, the watchdog time-out affects only the wdf flag. aie alarm interrupt enable. when set to 1, the alarm match drives the int pin as well as the af flag. when set to 0, the alarm match only affects the af flag. pfie power-fail enable. when set to 1, the alarm match drives the int pin as well as the af flag. when set to 0, the power-fail monitor affects only the pf flag. abe alarm battery-backup enable. when set to 1, the alarm interrupt (as controlled by aie) will function even in battery backup mode. when set to 0, the alarm will occur only when v cc >v switch . h/l high/low. when set to a 1, the int pin is driven active high. when set to 0, the int pin is open drain, active low. p/l pulse/level. when set to a 1, the int pin is driven active (determined by h/l ) by an interrupt source for approximately 200 ms. when set to a 0, the int pin is driven to an active level (as set by h/l ) until the flags/control register is read.
STK18TA8 april 2005 document control #ml0028 rev 0.8 25 alarm ? day 0x1fff5 d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to select or deselect the date value. m match. setting this bit to 0 causes the date value to be used in the alarm match. setting this bit to 1 causes the match circuit to ignore the date value. alarm ? hours 0x1fff4 d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the mask bit to select or deselect the hours value. m match. setting this bit to 0 causes the hours value to be used in the alarm match. setting this bit to 1 causes the match circuit to ignore the hours value. alarm ? minutes 0x1fff3 d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm minutes alarm minutes contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. m match. setting this bit to 0 causes the minutes value to be used in the alarm match. setting this bit to 1 causes the match circuit to ignore the minutes value. alarm ? seconds 0x1fff2 d7 d6 d5 d4 d3 d2 d1 d0 m 10s alarm seconds alarm seconds contains the alarm value for the seconds and the mask bit to select or deselect the seconds? value. m match. setting this bit to 0 causes the seconds? value to be used in the alarm match. setting this bit to 1 causes the match circuit to ignore the seconds value. timekeeping ? centuries 0x1fff1 d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s centuries centuries
STK18TA8 april 2005 document control #ml0028 rev 0.8 26 flags 0x1fff0 d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf 0 cal w r wdf watchdog timer flag. this read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags/control register is read. af alarm flag. this read-only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. it is cleared when the flags/control register is read. pf power-fail flag. this read-only bit is set to 1 when power falls below the power-fail threshold v switch . it is cleared to 0 when the flags/control register is read. oscf oscillator fail flag. set to 1 on power-up only if the oscillator is not running in the first 5ms of power-on operation. this indicates that time counts are no longer valid. the user must reset this bit to 0 to clear this condition. the chip will not clear this flag. this bit survives power cycles. cal calibration mode. when set to 1, a 512hz square wave is output on the int pin. when set to 0, the int pin resumes normal operation. this bit defaults to 0 (disabled) on power up. w write time. setting the w bit to 1 freeze updates of the timekeeping registers. the user can then write them with updated values. setting the w bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters. r read time. setting the r bit to 1 copies a static image of the timekeeping registers and places them in a holding register. the user can then read them without concerns over changing values causing system errors. the r bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again.
STK18TA8 april 2005 document control #ml0028 rev 0.8 27 ordering information STK18TA8 ? r f 40 i temperature range blank = commercial (0 to 70o c) i = industrial (-40 to 85oc) maximum clock frequency 40 = 40 mhz lead finish blank = 85% sn / 15% pb f = 100% sn (matte tin) rohs compliant package r = plastic 48-pin 300 mil ssop (25 mil pitch)
STK18TA8 april 2005 document control #ml0028 rev 0.8 28 document revision history revision date summary 0.0 june 2003 publish new datasheet 0.4 november 2004 revised feature set 0.5 january 2005 changed si hold time t h from 0 to 5 ns. 0.6 january 2005 changed t v , sck to data valid from 5ns to 7ns. changed t su, si hold time from 5ns to 3ns. added hold signal to spi interface . 0.7 january 2005 removed rdsr command. 0.8 april 2005 changed rtc register unused bits ?x? to require zero ?0? value when writing values. simtek STK18TA8 data sheet, april 2005 copyright 2005, simtek corporation. all rights reserved. this datasheet may only be printed for the express use of simtek customers. no part of this datasheet may be reproduced in any other form or means without express written permission from simtek corporation. the information contained in this publication is believed to be accurate, but changes may be made without notice. simtek does not assume responsibility for, or grant or imply any warranty, including merch antability or fitness for a particular purpose regarding this information, the product or its use. nothing herein constitutes a license, grant or transfer of any rights to any simtek patent, copyright, trademark or other proprietary right.

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