1 white electronic designs corporation ? (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 2gb- 256mx72, ecc, ddr sdram dimm registered module the WED3EG72256SXX-JD3 is a 256mx72 double data rate sdram memory module based on 1 gigabit ddr sdram components. the module consists of eighteen, 256mx4 ddr sdrams in 66 pin tsop packages mounted on a 184 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. description features january 2004 rev. 0 double data rate architecture; two data transfers per clock cycle clock speeds of 100mhz and 133mhz bi-directional data strobes (dqs) differential clock inputs (ck & ck) dll aligns dq and dqs transition with ck transition programmable read latency 2, 2.5 (clock) programmable burst length (2, 4, 8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh serial presence detect jedec standard 184 pin dimm package power supply: vdd: 2.5v 0.2v, vddq: 2.5v 0.2v operating frequencies 262jd3 265jd3 202jd2 (ddr266@cl=2) (ddr266@cl=2.5) (ddr200@cl=2) speed 133mhz 133mhz 100mhz cl-trcd-trp 2-3-3 2.5-3-3 2-2-2 advance information: speed may not be available. advanced
2 white electronic designs corporation (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 pin configuration (front side/back side) pin description 1 vref 2 dq0 3 vss 4 dq1 5 dqs0 6 dq2 7 vdd 8 dq3 9nc 10 reset 11 vss 12 dq8 13 dq9 14 dqs1 15 vddq 16 nc 17 nc 18 vss 19 dq10 20 dq11 21 cke0 22 vddq 23 dq16 24 dq17 25 dqs2 26 vss 27 a9 28 dq18 29 a7 30 vddq 31 dq19 32 a5 33 dq24 34 vss 35 dq25 36 dqs3 37 a4 38 vdd 39 dq26 40 dq27 41 a2 42 vss 43 a1 44 cb0 45 cb1 46 vdd 47 dqs8 48 a0 49 cb2 50 vss 51 cb3 52 ba1 key 53 dq32 54 vddq 55 dq33 56 dqs4 57 dq34 58 vss 59 ba0 60 dq35 61 dq40 62 vddq 63 we 64 dq41 65 cas 66 vss 67 dqs5 68 dq42 69 dq43 70 vdd 71 nc 72 dq48 73 dq49 74 vss 75 nc 76 nc 77 vddq 78 dqs6 79 dq50 80 dq51 81 vss 82 vddid 83 dq56 84 dq57 85 vdd 86 dqs7 87 dq58 88 dq59 89 vss 90 nc 91 sda 92 scl 93 vss 94 dq4 95 dq5 96 vddq 97 dqs9 98 dq6 99 dq7 100 vss 101 nc 102 nc 103 nc 104 vddq 105 dq12 106 dq13 107 dqs10 108 vdd 109 dq14 110 dq15 111 nc 112 vddq 113 nc 114 dq20 115 a12 116 vss 117 dq21 118 a11 119 dqs11 120 vdd 121 dq22 122 a8 123 dq23 pin front pin front pin front pin back pin back pin back 124 vss 125 a6 126 dq28 127 dq29 128 vddq 129 dqs12 130 a3 131 dq30 132 vss 133 dq31 134 cb4 135 cb5 136 vddq 137 ck0 138 ck0 139 vss 140 dqs17 141 a10 142 cb6 143 vddq 144 cb7 key 145 vss 146 dq36 147 dq37 148 vdd 149 dqs13 150 dq38 151 dq39 152 vss 153 dq44 154 ras 155 dq45 156 vddq 157 cs0 158 nc 159 dqs14 160 vss 161 dq46 162 dq47 163 nc 164 vddq 165 dq52 166 dq53 167 a13 168 vdd 169 dqs15 170 dq54 171 dq55 172 vddq 173 nc 174 dq60 175 dq61 176 vss 177 dqs16 178 dq62 179 dq63 180 vddq 181 sa0 182 sa1 183 sa2 184 vddspd pin name function pin name function vdd power supply (2.5v) vddq power supply for dqs (2.5v) vss ground vref power supply for reference vddspd serial eeprom power/supply (2.3v to 3.6v) sda serial data i/o scl serial clock sa0 ~ 2 address in eeprom nc no connection vddid vdd identification flag reset reset enable a0 ~ a13 address input (multiplexed) ba0 ~ ba1 bank select address dq0 ~ dq63 data input/output dqs0 ~ dqs17 data strobe input/output ck0, ck0 clock input cke0 clock enable input cs0, chip select input ras row address strobe cas column address strobe we write enable cb0 ~ cb7 check bit (data-in/data-out)
3 white electronic designs corporation (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 functional block diagram: vss rs0 dqs1 dqs2 dqs3 dqs4 dqs5 dqs6 dqs7 dqs8 r e g i s t e r dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq48 dq49 dq50 dq51 dq56 dq57 dq58 dq59 cb0 cb1 cb2 cb3 we reset pck pck rs0a i/o 0 i/o 1 i/o 2 i/o3 dqs cs d0 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d1 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d2 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d3 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d4 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d5 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d6 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d7 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d8 dm dqs0 dqs10 dqs11 dqs12 dqs13 dqs14 dqs15 dqs16 dqs17 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq52 dq53 dq54 dq55 dq60 dq61 dq62 dq63 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o3 dqs cs d9 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d10 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d11 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d12 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d13 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d14 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d15 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d16 dm i/o 0 i/o 1 i/o 2 i/o3 dqs cs d17 dm dqs0 v ddspd v dd/ v ddq vref vss spd d0-d17 d0-d17 notes" 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 22 ohms. 4. address and control resistors should be 22 ohms. cs0 rsob rbao - rban bao - ban :sdrams dq0 - d17 rao - ra13 a0 - an :sdrams d0 - d17 ba0-ban a0-a13 ras rras ras : sdrams d0 - d17 cas rcas cas : sdrams dq0 - d17 cke0 rcke0a cke : sdrams d0 - d8 rcke0b cke : sdrams d9 - d17 rwe we: sdrams d0 - d17 serial pd a0 sa0 sa1 sa2 a1 a2 scl sda wp pll cko sdram cko register d0-d17 d0-d17
4 white electronic designs corporation (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, vih (ac) vref+ 0.31 - v 3 input low (logic 0) voltage, vil (ac) -vref - 0.31 v 3 clock input differential voltage, ck and ck inputs vid (ac) 0.7 vddq+0.6 v 1 clock input crossing point voltage, ck and ck inputs vix (ac) 0.5xvddq-0.2 0.5xvddq+0.2 v 2 notes: 1. vid is the magnitude of the difference between the input level on ck and the input on ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the s ame. 3. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulati on. the ac and dc input specifications are relation to vref relation to a vref envelope that has been bandwidth limited 20mhz. recommend operating conditions (voltage referenced to vss = ?v, ta = ? to 70c) power & dc operating conditions (sstl_2 in/out) parameter symbol min max unit note supply voltage (for device with a nominal vdd of 2.5v) vdd 2.3 2.7 ? ? i/o supply voltage vddq 2.3 2.7 v i/o reference voltage vref vddq/2-50mv vddq/2+50mv v 1 i/o termination voltage (system) vtt vref-0.04 vref+0.04 v 2 input logic high voltage vih (dc) vref+0.15 vddq+0.3 v 4 input logic low voltage vil (dc) -0.3 vref-0.15 v 4 input voltage level, ck and ck inputs vin (dc) -0.3 vddq+0.3 v input differential voltage, ck and ck inputs vid(dc) 0.3 vddq+0.6 v 3 input leakage current i -2 2 ua output leakage current ioz -5 5 ua output high current (normal strength driver); vout = vtt + 0.84v ioh -16.8 ma output high current (normal strength driver); vout = vtt - 0.84v iol 16.8 ma output high current (half strength driver); vout = vtt + 0.45v ioh -9 ma output high current (half strength driver); vout = vtt - 0.45v iol 9 ma notes: 1. includes 25mv margin for dc offset on vref, and a combined total of 50mv margin for all ac noise and dc offset on vref, bandwidth limited to 20mhz. the dram must accommodate dram current spikes on vref and internal dram noise coupled to vref, both of which may result in vref noise. vref should be de-coupled with an inductance of 3nh. 2. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equa l to vref, and must track variations in the dc level of vref. 3. vid is the magnitude of the difference between the input level on ck and the input level on ck. 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulati on. the ac and dc input specifications are relative to a vref that has been bandwidth limited to 200mhz.
5 white electronic designs corporation (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 idd specifications and test conditions (recommended operating conditions, ta = 0 to 70c, vddq = 2.5v +\-0.2v, vdd = 2.5v +\-0.2v) note: module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. ddr266@cl=2, 2.5 ddr200@cl=2 parameter symbol conditions max max units operating current idd0 one device bank; active = precharge; trc=trc (min); tck=tck 1957 1900 ma (min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. operating current idd1 one device bank; active-read-precharge; burst = 2; trc=trc (min); tck=tck 2632 2450 ma (min); iout = 0ma; address and control inputs changing once per clock cycle. precharge power-down idd2p all device banks idle; power- down 135 125 ma standby current mode; tck=tck (min); cke=(low) dle standby current idd2f cs# = high; all device 810 750 ma banks idle; tck=tck (min); cke = high; address and other control inputs changing once per clock cycle. vin = vref for dq, dqs and dm. active power-down idd3p one device bank active; power- 405 385 ma standby current down mode; tck (min); cke=(low) active standby current idd3n cs# = high; cke = high; one device bank; active-precharge; 790 700 ma trc=tras (max); tck=tck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. operating current idd4r burst = 2; reads; continuous burst; one device bank active; address 3375 2970 ma and control inputs changing once per clock cycle; tck=tck (min); iout = 0ma. operating current idd4w burst = 2; writes; 3375 3250 ma continuous burst; one device bank active; address and control inputs changing once per clock cycle; tck=tck (min); dq, dm and dqs inputs changing twice per clock cycle. auto refresh current idd5 trc=trc (min) 4455 4300 ma self refresh current idd6 cke 0.2v 121 115 ma operating current idd7a four bank interleaving reads 6682 6550 ma (bl=4) with auto precharge with trc=trc (min); tck=tck (min); address and control inputs change only during active read or write commands.
6 white electronic designs corporation (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 ac timing parameters & specifications parameter symbol (ddr266@cl=2) (ddr266@cl=2.5) (ddr200@cl=2) unit note min max min max min max row cycle time trc 65 65 70 ns refresh row cycle time trfc 75 75 80 ns row active time tras 40 120k 40 120k 48 120k ns ras to cas delay trcd 20 20 20 ns row precharge time trp 20 20 20 ns row active to row active delay trrd 15 15 15 ns write recovery time twr 15 15 15 ns last data in to read command twtr 1 1 1 tck col. address to col. address delay tccd 1 1 1 tck cl=2.0 10 13 10 13 ns 5 cl=2.5 7.5 13 ns 5 clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ck tdqsck -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns output data access time from ck/ck tac -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data strobe edge to output data edge tdqsq 0.5 0.5 0.6 ns 5 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 ns 2 dqs-in hold time twpre 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time (fast) tis 0.9 0.9 1.1 ns i,6 address and control input hold time (fast) tih 0.9 0.9 1.1 ns i,6 address and control input setup time (slow) tis 1.0 1.0 1.1 ns i, 6 address and control input hold time (slow) tih 1.0 1.0 1.1 ns i, 6 data-out high impedance time from ck/ck thz -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data-out low impedance time from ck/ck tlz -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns input slew rate (for input only pins) tsl(i) 0.5 0.5 0.5 v/ns 6 input slew rate (for i/o pins) tsl(io) 0.5 0.5 0.5 v/ns 7 output slew rate (x4,x8) tsl(o) 1.0 4.5 1.0 4.5 1.0 4.5 v/ns 10 output slew rate matching ratio (rise to fall) tslmr 0.67 1.5 0.67 1.5 0.67 1.5 clock cycle time tck 262jd3 265jd3 202jd3
7 white electronic designs corporation (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 system characteristics for ddr sdram the following specification parameters are required in systems using ddr266 & ddr200 devices to ensure proper system performanc e. these characteristics are for system simulation purposes and are guaranteed by design. 262jd3 265jd3 202jd3 parameter symbol (ddr266@cl=2) (ddr266@cl=2.5) (ddr200@cl=2) unit note min max min max min max mode register set cycle time t mrd 15 15 16 ns dq & dm setup time to dqs t ds 0.5 0.5 0.6 ns j, k dq & dm hold time to dqs t dh 0.5 0.5 0.6 ns j, k control & address input pulse width t lpw 2.2 2.2 2.5 ns 8 dq & dm unput pulse width t dipw 1.75 1.75 2 ns 8 power down exit time t pdex 7.5 7.5 10 ns exit self refresh to non-read command t xsnr 75 75 80 ns exit self refresh to read command t xsrd 200 200 200 tck refresh interval time t refl 7.8 7.8 7.8 us 4 output dqs valid window t qh -ns11 clock half period t hp - ns 10, 11 data hold skew factor t qhs 0.75 0.75 0.8 ns 11 dqs write postamble time t qpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 2 active to read with auto precharge command t rap 20 20 20 auto precharge write revovery + precharge time t dal (t wr /t ck )(t wr /t ck )(t wr /t ck ) tck ++ + t hp -t hp -t hp t qhs -t qhs -t qhs t cl min - t cl min - t cl min or t ch min - or t ch min - or t ch min c apacitance (ta = 25c, f = 1mh z , vdd = 2.5v) a bsolute m aximum r atings notes: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol min max unit input capacitance (a0-a13) cin1 - 12 pf input capacitance (ras, cas, we) cin2 - 12 pf input capacitance (cke0) cin3 - 12 pf input capacitance (ck0, ck0) cin4 - 12 pf input capacitance (cs0) cin5 - 11 pf input capacitance (dqm0-dqm8) cin6 - 11 pf input capacitance (ba0-ba1) cin7 - 12 pf data input/output capacitance (dq0-dq63) (dqs) cout - 11 pf data input/output capacitance (cb0-cb7) cout - 11 pf parameter symbol v alue units voltage on any pin relative to vss v in , vout -0.5 ~ 3.6 v voltage on vdd supply relative to vss vdd, vddq -1.0 ~ 3.6 v storage t emperature tstg -55 ~ +150 c power dissipation pd 27 w short circuit current ios 50 ma
8 white electronic designs corporation (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 command truth table notes: 1. op code: operand code. a 0 ~a 13 & ba 0 ~ ba 1 : program keys (@emrs/mrs) 2. emrs/mrs can be issued only at all blanks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatic precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all blanks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued at trp after the end of the burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no operation (nop)" in ddr sdram. (v = valid, x = don't care, h = logic high, l = logic low) command register register refresh bank active & row addr. read & column address write & column address burst stop precharge active power down dm non operation (nop):not defined extended mrs mode register set auto refresh entry exit self refresh cken-1 cken cs ras cas we ba0,1 a10/ap note hxllll hxllll hlllh h l lh lh hh hx xx auto precharge disable auto precharge enable auto precharge disable auto precharge enable bank selection all banks hxllll hxlhlh hxlhll hxlhhl hxllhl entry exit entry exit hx xx lv vv hx xx lh hh hx xx lv vv hx xx lh hh lhxxxx hx hl hl lh a0~a9 a11, a13 op code op code x x v row address (a0~a9, a11,a13) l h l h l h v x v v column address column address 1,2 1,2 4 4 4 4.6 7 x x x x x x 5 8 9 9 hx precharge power down mode 3 3 3 3
9 white electronic designs corporation (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 detailed test conditions for ddr sdram idd1 & idd7a idd1:operating current:one bank 1. typical case : vdd = 2.5v, t = 25'c 2. worst case : vdd = 2.7v, t = 10'c 3. only one bank is accessed with trc (min), burst mode, address and control inputs on nop edge are changing once per clock cycle. iout = 0ma 4. timing patterns - 202jd3, ddr200 (100mhz, cl = 2) : tck = 10ns, cl2, bl = 4, trcd = 2*tck, tras = 5*tck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - 265jd3, ddr266 (133mhz, cl = 2.5) : tck = 7.5ns, cl = 2.5, bl = 4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - 262jd3, ddr266 (133mhz, cl = 2) : tck = 7.5ns, cl = 2, bl = 4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst all dimensions are in inches. package dimensions ordering information part number density s peed organization height wed3eg72256s202jd3-m 2gb 100mhz/cl=2 256m x 72 1.2 in wed3eg72256s262jd3-m 2gb 133mhz/cl=2 256m x 72 1.2 in wed3eg72256s265jd3-m 2gb 133mhz/cl=2.5 256m x 72 1.2 in .250 .250 .070 1.950 .050 .157 min. .050 +/- .004 .150 max. .118 (4x) 1.200 max. typ. 2.550 .394 .700 5.255 max. p1 .157 (4x) m = micron ? die
10 white electronic designs corporation (602) 437-1520 www.whiteedc.com WED3EG72256SXX-JD3 document title 2gb- 256mx72, ecc, ddr sdram dimm registered module revision history rev # history release date status rev 0 initial release january 2004 advanced
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