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1 ? fn8119.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. preliminary x40626 64k, 8k x 8 bit dual voltage cpu supervisor with 64k serial eeprom features ? dual voltage monitoring ?v 2mon operates independent of v cc ? watchdog timer with selectable timeout intervals ?low v cc detection and reset assertion ?four standard reset threshold voltages ?user programmable v trip threshold ?reset signal valid to v cc =1v ? low power cmos ?20a max standby current, watchdog on ?1a standby current, watchdog off ? 64kbits of eeprom ?64 byte page size ? built-in inadvertent write protection ?power-up/power-down protection circuitry ?protect 0, 1/4, 1/2, all or 64, 128, 256 or 512 bytes of eeprom array with programmable block lock ? protection ? 400khz 2-wire interface ?slave addressing supports up to 4 devices on the same bus ? 2.7v to 5.5v power supply operation ? available packages ?14-lead soic ?14-lead tssop description the x40626 combines four popular functions, power-on reset control, watchdog timer, dual supply voltage supervision, and serial eeprom memory in one pack- age. this combination lowers system cost, reduces board space requirements, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset active for a period of time. this allows the power supply and oscillator to stabi- lize before the processor can execute code. the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time- out interval, the device activates the reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. block diagram watchdog timer reset data register command decode & control logic sda scl v cc reset & watchdog timebase power-on and generation v trip + - reset reset low voltage status register protect logic 64kb watchdog transition detector wp v cc threshold reset logic block lock control s0 s1 v2 monitor logic + - v trip2 v2mon v2fail eeprom array data sheet march 28, 2005
2 fn8119.0 march 28, 2005 the device?s low v cc detection circuitry protects the user?s system from low voltage conditions, resetting the system when v cc falls below the set minimum v cc trip point. reset is asserted until v cc returns to proper operating level and stabilizes. four industry standard vtrip thresholds are available. however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. the memory portion of the device is a cmos serial eeprom array with intersil?s block lock ? protection. the array is internally organized as 64 bytes per page. the device features an 2-wire interface and software pro- tocol allowing operation on an i 2 c bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimum endurance of 100,000 page write cycles and a minimum da ta retention of 100 years. pin configuration s 1 v ss v cc v2mon wp 3 2 4 1 12 13 11 14 14 pin soic/tssop s 0 nc reset 6 5 7 9 10 8 nc sda scl v2fail nc nc pin function pin name function 1, 4, 6, 13 nc no internal connections 2s 0 device select input 3s 1 device select input 5 reset reset output . reset is an active low, open drain output which goes active whenever v cc falls below the minimum v cc sense level. it will remain active until v cc rises above the mini- mum v cc sense level for typically 200ms. reset goes active if the watchdog timer is enabled and sda remains either high or low longer than the selectable watchdog time-out period. a falling edge on sda, while scl is high, resets the watchdog timer. reset goes active on power-up and remains active for typically 200ms after the power supply stabilizes. 7v ss ground 8sda serial data. sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. this pin requires a pull up resistor and the input buffer is always active (not gated). watchdog input. a high to low transition on the sda (while scl is high) restarts the watch- dog timer. the absence of a high to low transition within the watchdog time-out period results in reset going active. 9scl serial clock. the serial clock controls the serial bus timing for data input and output. 10 v2fail v2 voltage fail output. this open drain output goes low when v2mon is less than v trip2 and goes high when v2mon exceeds v trip2 . there is no power-up reset delay circuitry on this pin. this circuit works independently from the low v cc reset and battery switch circuits. connect v2fail to vss when not used. 11 v2mon v2 voltage monitor input. when the v2mon input is less than the v trip2 voltage, v2fail goes low. this input can monitor an unregulated power supply with an external resistor divider or can monitor a second power suppl y with no external components. connect v2mon to v ss or v cc when not used. there is no hysteresis in the v2mon comparator circuits. 12 wp write protect. wp high used in conjunction with wpen bit prevents writes to the control reg- ister. 14 v cc supply voltage x40626
3 fn8119.0 march 28, 2005 principles of operation power-on reset application of power to the x40626 activates a power- on reset circuit that pulls the reset pin active. this signal provides several benefits. ? it prevents the system micr oprocessor from starting to operate with insufficient voltage. ? it prevents the processor from operating prior to sta- bilization of the oscillator. ? it allows time for an fpga to download its configura- tion prior to initialization of the circuit. ? it prevents communication to the eeprom, greatly reducing the likelihood of data corruption on power-up. when v cc exceeds the device v trip threshold value for t purst (200ms nominal) the circuit releases reset allowing the system to begin operation. low voltage monitoring during operation, the x40626 monitors the v cc level and asserts reset if supply voltage falls below a pre- set minimum v trip . the reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. watchdog timer the watchdog timer circuit m onitors the microproces- sor activity by monitoring the sda and scl pins. the microprocessor must toggle the sda pin high to low periodically, while scl is high (this is a start bit) prior to the expiration of the watchdog time-out period to prevent a reset signal. the state of two nonvolatile control bits in the status register determine the watch- dog timer period. the microprocessor can change these watchdog bits, or they may be ?locked? by tying the wp pin high. eeprom inadvertent write protection when reset goes active as a result of a low voltage condition or watchdog timer time-out, any in- progress communications are terminated. while reset is active, no new commu nications are allowed and no non-volatile write operation can start. non-vol- atile writes in-progress when reset goes active are allowed to finish. additional protection mechanisms are provided with memory block lock and the write protect (wp) pin. these are discussed elsewhere in this document. v cc /v 2mon threshold reset procedure the x40626 is shipped with a standard v cc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. however, in applica- tions where the standard v trip is not exactly right, or if higher precision is needed in the v trip value, the x40626 threshold may be adjusted. the procedure is described below, and uses the application of a nonvol- atile control signal. setting the v trip voltage this procedure is used to set the v trip to a higher or lower voltage value. it is necessary to reset the trip point before setting the new value. the v cc and v2mon must be tied together during this sequence. to set the new v trip voltage, start by setting the wel bit in the control register, then apply the desired v trip threshold voltage to the v cc pin and the programming voltage, v p , to the wp pin and 2 byte address and 1 byte of ?00? data. the stop bit following a valid write operation initiates the v trip programming sequence. bring wp low to complete the operation. figure 1. set v trip level sequence (v cc /v 2mon = desired v trip values, wp = 12-15v when wel bit set) 01234567 scl sda a0h 01234567 00h wp v p = 12-15v 01234567 xxh* 01234567 00h *for v vtrip2 address is 0dh for v trip address is 01h x40626
4 fn8119.0 march 28, 2005 resetting the v trip voltage this procedure is used to set the v trip to a ?native? voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when v trip is reset, the new v trip is some- thing less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the new v trip voltage start by setting the wel bit in the control register, apply the desired v trip threshold voltage to the v cc pin and the programming voltage, v p , to the wp pin and 2 byte address and 1 byte of ?00? data. the stop bit of a valid write operation initiates the v trip programming sequence. bring wp low to complete the operation. figure 2. reset v trip level sequence (v cc /v 2mon > 3v, wp = 12-15v, wel bit set) figure 3. sample v trip reset circuit 01234567 scl sda a0h 01234567 00h wp v p = 12-15v 01234567 xxh* 01234567 00h *for v trip2 address is 0fh for v trip address is 03h 1 2 5 7 14 12 9 8 x40626 v trip adj. v p reset 4.7k sda scl c adjust run 6 3 13 4 x40626
5 fn8119.0 march 28, 2005 figure 4. v trip programming sequence v tripx programming apply v cc and voltage decrease v x actual v tripx - desired v tripx done set higher v x sequence error < mde ? | error | < | mde | yes no error > mde + > desired v tripx to v x desired present value v tripx execute no yes set v x = desired v tripx execute set higher v tripx sequence new v x applied = old v x applied + | error | new v x applied = old v x applied - | error | execute reset v tripx sequence output switches? let: mde = maximum desired error vx = v cc , v2mon mde + desired value mde ? acceptable error range error = actual - desired x40626
6 fn8119.0 march 28, 2005 control register the control register provides the user a mechanism for changing the block lock and watchdog timer set- tings. the block lock and watchdog timer bits are nonvolatile and do not change when power is removed. the control register is accessed at address ffffh. it can only be modified by performing a byte write opera- tion directly to the address of the register and only one data byte is allowed for each register write operation. prior to writing to the co ntrol register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps. see "writing to the control register" below. the user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores wd1, wd0, bp2, bp1, and bp0. the x40626 will not acknowledge any data bytes written after the first byte is entered. the state of the control re gister can be read at any time by performing a random read at address ffffh. only one byte is read by each register read operation. the x40626 resets itself after the first byte is read. the master should supply a stop condition to be con- sistent with the bus protocol , but a stop is not required to end this operation. rwel: register write enable latch (volatile) the rwel bit must be set to ?1? prior to a write to the control register. wel: write enable latch (volatile) the wel bit controls the access to the memory and to the register during a write operation. this bit is a vola- tile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address, including any control regi sters will be ignored (no acknowledge will be issued after the data byte). the wel bit is set by writing a ?1? to the wel bit and zeroes to the other bits of the control register. once set, wel remains set until eith er it is reset to 0 (by writing a ?0? to the wel bit and zeroes to the other bits of the control register) or until the part powers up again. writes to the wel bi t do not cause a nonvolatile write cycle, so the device is ready for the next opera- tion immediately after the stop condition. bp2, bp1, bp0: block protect bits - (nonvolatile) the block protect bits, bp2 , bp1 and bp0, determine which blocks of the array ar e write protected. a write to a protected block of memory is ignored. the block pro- tect bits will prevent write operations to one of eight segments of the array. wd1, wd0: watchdog timer bits the bits wd1 and wd0 control the period of the watchdog timer. the options are shown below. write protect enable these devices have an ad vanced block lock scheme that protects one of eigh t blocks of the array when enabled. it provides hardw are write protection through the use of a wp pin and a nonvolatile write protect enable (wpen) bit. four of the 8 protected blocks match the original block lock segments and this pro- tection scheme is fully co mpatible with the current devices using 2 bits of block lock control (assuming the bp2 bit is set to 0). the write protect (wp) pin and the write protect enable (wpen) bit in the control register control the programmable hardware write protect feature. hard- ware write protection is enabled when the wp pin and the wpen bit are high and disabled when either the wp pin or the wpen bit is low. when the chip is hardware write protected, nonvolatile writes as well as to the block protected sect ions in the memory array cannot be written. only the sections of the memory array that are not block protected can be written. note that since the wpen bit is wr ite protected, it cannot be changed back to a low stat e; so write protection is enabled as long as the wp pin is held high. 76543210 wpen wd1 wd0 bp1 bp0 rwel wel bp2 bp2 bp1 bp0 protected addresses (size) array lock 0 0 0 none (factory setting) none 0 0 1 1800h - 1fffh (2k bytes ) upper 1/4 (q4) 0 1 0 1000h - 1fffh (4k bytes ) upper 1/2 (q3,q4) 0 1 1 0000h - 1fffh (8k bytes) full array (all) 1 0 0 000h - 03fh (64 bytes) first page (p1) 1 0 1 000h - 07fh (128 bytes) first 2 pgs (p2) 1 1 0 000h - 0ffh (256 bytes) first 4 pgs (p4) 1 1 1 000h - 1ffh (512 bytes) first 8 pgs (p8) wd1 wd0 typ. watchdog time-out period 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled (factory setting) x40626
7 fn8119.0 march 28, 2005 table 1. write protect enable bit and wp pin function writing to the control register changing any of the nonvolat ile bits of the control reg- ister requires the following steps: ? write a 02h to the control register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation pro- ceeded by a start and ended with a stop). ? write a 06h to the control register to set both the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation proceeded by a start and ended with a stop). ? write a value to the control register that has all the control bits set to the desired state. this can be rep- resented as 0xys t 01 r in binary, where xy are the wd bits, and rst are the bp bits. (operation pre- ceeded by a start and ended with a stop). since this is a nonvolatile write cycle it will take up to 10ms to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the non- volatile bits again. if bit 2 is set to ?1? in this third step ( 0xys t 11 r ) then the rwel bit is set, but the wd1, wd0, bp2, bp1 and bp0 bits remain unchanged. writing a second byte to the control register is not allowed. doing so aborts the write operation and returns a nack. ? a read operation occurring between any of the previ- ous operations will not inte rrupt the register write operation. ? the rwel bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. to illustrate, a sequ ence of writes to the device con- sisting of [02h, 06h, 02h] will reset all of the nonvola- tile bits in the control register to 0. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set. serial interface serial interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this fam- ily operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state cha nges during scl high are reserved for indicating start and stop conditions. see figure 5. wp wpen memory array not block protected memory array block protected block protect bits wpen bit protection low x writes ok writes blocked writes ok writes ok software high 0 writes ok writes blocked writes ok writes ok software high 1 writes ok writes blocked writes blocked writes blocked hardware x40626
8 fn8119.0 march 28, 2005 figure 5. valid data changes on the sda bus serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device contin uously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 6. serial stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condi tion is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has rel eased the bus. see figure 6. figure 6. valid start and stop conditions serial acknowledge acknowledge is a software convention used to indi- cate successful data transf er. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during t he ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 7. the device will respond wit h an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generate d by the master, the device will continue to transmit da ta. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. scl sda data stable data change data stable scl sda start stop x40626
9 fn8119.0 march 28, 2005 figure 7. acknowledge response from receiver serial write operations byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condi- tion, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance. see figure 8. figure 8. byte write sequence a write to a protected bl ock of memory will suppress the acknowledge bit. page write the device is capable of a page write operation. it is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transfer red, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the device will respond with an acknowl- edge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to ?0? on the same page. this means that the master can write 64 bytes to the page starting at any location on that page. if the master begins writing at location 60, and loads 12 bytes, then the first 4 bytes are written to locations 60 through 63, and the last 8 bytes are written to locations 0 through 7. after- wards, the address counter would point to location 8 of the page that was just written. if the master supplies more than 64 bytes of data, then new data over-writes the previous data, one byte at a time. data output from data output from receiver 8 1 9 start acknowledge scl from master signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k a c k byte 1 data 1 0 1 0 0 word address byte 0 s p 0 word address s 1 s 0 x40626
10 fn8119.0 march 28, 2005 figure 9. page write operation figure 10. writing 12 bytes to a 64-byte page starting at location 60 (wrap around). the master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. as wi th the byte write operation, all inputs are disabled until completion of the internal write cycle. see figure 9 for the address, acknowledge, and data transfer sequence. stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself withou t performing the write. the contents of the arra y will not be effected. acknowledge polling the disabling of the inputs during nonvolatile cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the master?s byte load operation, the device initiates the internal nonvolatile cycle. acknowl- edge polling can be initiated immediatel y. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the nonvolatile cycle then no ack will be returned. if th e device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to the flow ch art in figure 11. s t a r t s t o p a c k a c k a c k a c k a c k data (0) (n) 0 s p data 1 0 1 0 (i n 63) signals from the master sda bus signals from the slave slave address byte 1 word address byte 0 word address 0 s 1 s 0 address address 60 4 bytes 63 8 bytes address = 7 address pointer ends here addr = 8 x40626
11 fn8119.0 march 28, 2005 figure 11. acknowledge polling sequence serial read operations read operations are initiated in the same manner as write operations with th e exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, ran- dom reads, and sequential reads. current address read internally the device contai ns an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read o peration would access data from address n+1. on power-up, the address in the address counter is 00h. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master terminates the read operati on when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. refer to figure 12 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and th en issue a stop condition. figure 12. current address read sequence ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes nonvolatile cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes s t a r t s t o p slave address data sda bus signals from the slave signals from the master a c k s 0 s 1 1 10100 x40626
12 fn8119.0 march 28, 2005 random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipts of the word address bytes, the master immediately issues another start conditi on and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. refer to figure 13 for the address, acknowledge, and data transfer sequence. figure 13. random address read sequence there is a similar operation, called ?set current address? where the device does no operation, but enters a new address into the address counter if a stop is issued instead of th e second start shown in fig- ure 13. the device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. the next current address read operation reads from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the first data byte is transmitted as with the other modes; however, the master now responds wi th an acknowledge, indicat- ing it requires additional dat a. the device continues to output data for each acknow ledge received. the master terminates the read operation by not responding with an acknowledge and then issu ing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory con- tents to be serially read during one operation. at the end of the address space the counter ?rolls over? to address 0000h and the device continues to output data for each acknowledge received. refer to figure 14 for the acknowledge and data transfer sequence. signals from the master sda bus signals from the slave s t a r t s t o p a c k a c k a c k 0 s t a r t 1 data a c k s p s 1010 slave address byte 1 word address byte 0 word address slave address s 1 s 0 1010 s 1 s 0 0 0 x40626
13 fn8119.0 march 28, 2005 figure 14. sequential read sequence x40626 addressing slave address byte following a start condition, the master must output a slave address byte. this byte consists of several parts: ? a device type identifier that is ?1010? to access the array ? one bit of ?0?. ? next two bits are the device address. (s1 and s0) ? one bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte defines the oper- ation to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. refer to figure 15. ? after loading the entire slave address byte from the sda bus, the device compares the input slave byte data to the proper slave byte. upon a correct compare, the device outputs an acknowledge on the sda line. word address the word address is either supplied by the master or obtained from an internal counter. the internal counter is 00h on a power-up condition. the master must supply t he two word address byte as shown in figure 15. data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) a c k a c k (n is any integer greater than 1) data (1) s 1 s 0 x40626
14 fn8119.0 march 28, 2005 figure 15. x40626 addressing operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? the wel bit is set to ?0?. in this state it is not possi- ble to write to the device. ? sda pin is in the input mode. ? reset signal is active for t purst . data protection the following circuitry has been included to prevent inadvertent writes: ? the wel bit must be set to allow write operations. ? the proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. ? a three step sequence is required before writing into the control register to change watchdog timer or block lock settings. ? the wp pin, when held high , and wpen bit at logic high will prevent all writes to the control register. ? communication to the device is inhibited while reset is active and any in-progress communica- tion is terminated. ? block lock bits can protect sections of the memory array from write operations. symbol table r/w s0 s1 0 1 0 1 slave address byte device identifier device select a8 a9 a10 a11 a12 a13 a14 a15 word address byte 1 high order word address a0 a1 a2 word address byte 0 low order word address a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 data byte 0 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x40626
15 fn8119.0 march 28, 2005 absolute maximum ratings temperature under bias ................... -65c to +135c storage temperature ......... ............... -65c to +150c voltage on any pin with respect to vss... -1.0v to +7v d.c. output current (sink) ................................... 10ma lead temperature (soldering, 10 seconds)........ 300c table 2. recommended operating conditions comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. d.c. operating characteristics (over the recommended operating condit ions unless otherwise specified.) notes: (1) the device enters the active state after any start, and re mains active until: (a) 9 clock cycles later if the device s elect bits in the slave address byte are incorrect; or (b) 200ns after a stop ending a read operation. (2) the device enters the active state afte r any start, and remains active until t wc after a stop ending a write operation. (3) the device goes into standby: (a) 200ns after any stop, exc ept those that initiate a nonvolatile write cycle; or (b) t wc after a stop that initiates a nonvolatile cycle; or 9 clock cyc les after any start that is not followed by the correct device select bits in the slave address byte. temp min. max. commercial 0c 70c industrial -40c +85c symbol parameter v cc = 2.7 to 5.5v unit test conditions min max i cc1 (1) active supply current read 1.0 ma v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 400khz, sda = open i cc2 (2) active supply current write 3.0 ma i sb1 (2) standby current dc (wdt off) 1 av sda =v scl =v cc others=gnd or v cc i sb2 (3) standby current dc (wdt on) 30 av sda =v scl =v cc others=gnd or v cc i li input leakage current 10 av in = gnd to v cc i lo output leakage current 10 av sda = gnd to v cc device is in standby v il input low voltage -1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc +0.5 v v hys schmitt trigger input hysteresis fixed input level v cc related level 0.2 .05 x v cc v v v ol output low voltage 0.4 v i ol = 1.0ma (v cc =3v) i ol = 3.0ma (v cc =5v) x40626
16 fn8119.0 march 28, 2005 capacitance (t a = 25c, f = 1.0 mhz, v cc = 5v) notes: (4) this parameter is periodically sampled and not 100% tested. equivalent a.c. load circuit a.c. test conditions a.c. characteristics (over recommended operating condit ions, unless otherwise specified) notes: (1) typical values are for t a = 25c and v cc = 5.0v (2) cb = total capacitance of one bus line in pf. symbol parameter max. units test conditions c out (4) output capacitance (sda, reset , v2fail )8pfv out = 0v c in (4) input capacitance (scl, wp, s0, s1) 6 pf v in = 0v v2mon 1.53k ? v2fail 30pf sda reset 1533 ? 30pf 5v input pulse levels 0.1v cc to 0.9v cc input rise and fall times 10ns input and output timing levels 0.5v cc output load standard output load symbol parameter min. max. units f scl scl clock frequency 0 400 khz t in pulse width suppression time at inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 s t buf time the bus free before start of new transmission 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 ns t r sda and scl rise time 20 + 0.1cb (2) 300 ns t f sda and scl fall time 20 + 0.1cb (2) 300 ns t su:wp wp setup time 0.6 s t hd:wp wp hold time 0 s cb capacitive load for each bus line 400 pf x40626
17 fn8119.0 march 28, 2005 timing diagrams bus timing wp pin timing write cycle timing nonvolatile write cycle timing notes: (1) t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless ac knowledge polling is used. symbol parameter min. typ. (1) max. units t wc (1) write cycle time 5 10 ms t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r t hd:wp scl sda in wp t su:wp clk 1 clk 9 slave address byte start scl sda t wc 8th bit of last byte ack stop condition start condition x40626
18 fn8119.0 march 28, 2005 power-up and po wer-down timing reset output timing notes: (8) this parameter is periodically sampled and not 100% tested. sda vs. reset timing symbol parameter min. typ. max. units t purst power-up reset timeout 100 200 400 ms t rpd (8) v cc detect to reset /output (falling edge) 500 ns t f (8) v cc /v2mon fall time 100 s t r (8) v cc /v2mon rise time 100 s v rvalid (8) reset valid v cc or v2fail valid v2mon 1.0 v v trip range voltage range over which v trip /v trip2 can be set 2.0 v cc v v cc /v2mon t purst t r t f t rpd 0 volts v trip /v trip2 reset /v2fail v rvalid t purst < t wdo t rst reset sda start t wdo t rst scl timer start t rsp timer restart timer start start x40626
19 fn8119.0 march 28, 2005 reset output timing v trip programming timing diagram (wel = 1) symbol parameter min. typ. max. units t wdo watchdog timeout period, wd1 = 1, wd0 = 1 (factory setting) wd1 = 1, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 0, wd0 = 0 disabled 100 450 1.0 disabled 200 600 1.4 disabled 400 850 2.0 factory setting ms ms sec t rst reset timeout 100 250 400 ms scl sda 0001h*: set v trip 00h v cc /v2mon (v trip /v trip2 ) wp t tsu t thd t vps v p t vpo as 1 s 0 00h 01 2 7 0 7 0 7 0 7 t wc start 000dh: set v trip2 0003h: resets v trip 000fh: resets v trip2 data v cc /v2mon x40626
20 fn8119.0 march 28, 2005 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 14-lead plastic small outline gullwing package type s note: all dimensions in inches (in parentheses in millimeters) 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 0.250" 0.050" typical 0.030" typical 14 places footprint 0.050" typical x40626
21 fn8119.0 march 28, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package code v14 see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) x40626
22 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8119.0 march 28, 2005 ordering information part mark information v cc range v trip range v trip2 range package operating temperature range part number reset (active low) park mark 4.5-5.5v 4.5-4.75 2.85-3.0 14l soic 0c-70c x40626s14-4.5a al -40c-85c x40626s14i-4.5a am 14l tssop 0c-70c x40626v14-4.5a al -40c-85c x40626v14i-4.5a am 4.5-5.5v 4.25-4.5 2.85-3.0 14l soic 0c-70c x40626s14 blank -40c-85c x40626s14i i 14l tssop 0c-70c x40626v14 blank -40c-85c x40626v14i i 2.7-5.5v 2.85-3.0 2.15-2.30 14l soic 0c-70c x40626s14-2.7a an -40c-85c x40626s14i-2.7a ap 14ltssop 0c-70c x40626v14-2.7a bn -40c-85c x40626v14i-2.7a ap 2.7-5.5v 2.55-2.7 2.55-2.7 14l soic 0c-70c x40626s14-2.7 f -40c-85c x40626s14i-2.7 g 14l tssop 0c-70c x40626v14-2.7 f -40c-85c x40626v14i-2.7 g 14-lead soic/tssop x40626 x yywwxx s = soic ww ? workweek yy ? year v = tssop xx ? part mark x40626

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