e1467d rev. a2, 15-jan-01 1 (6) 32-khz clock cmos ic with digital trimming and alarm features 32-khz voltage regulated oscillator 1.1 v to 2.2 v operating-voltage range integrated capacitors for digital trimming suitable for up to 12.5 pf quartz trimming inputs insensitive to stray capacitance output pulse formers mask options for motor period and pulse width low resistance output for bipolar stepping motor alarm function motor-fast-test function pad configuration v dd * v ss ?? 2 ? 8 ? ? 6 ? ? 5 ? 7 e 1467d ?? ?? 1 ? ? 9 ? ? 13 ?? ?? 12 ?? ?? 11 ?? ?? 10 ?? ?? 4 ?? ?? 3 **alin / **mot1l oscin oscout alout mot2 mot1r * sc4 sc3 sc2 sc1 mtest 9611897 *) the pads for v dd and oscout are interchangeable per mask option **) the pads for alin/-mtest and mot1l are inter- changeable per mask-option figure 4. pad configuration general description the e1467d is an integrated circuit in cmos silicon gate technology for analog clocks. it consists of a 32-khz oscillator, frequency divider, output pulse formers, push-pull motor drivers and alarm output. integrated capacitors are mask-selectable to accomodate the external quartz crystal. additional capacitance can be selected through pad bonding for trimming the oscillator frequency. absolute maximum ratings parameters symbol value unit supply voltage v ss 0.3 to 5 v v input voltage range, all inputs v in (v ss 0.3 v) v in (v dd + 0.3 v) v output short circuit duration indefinite power dissipation (dil package) p tot 125 mw mw operating ambient temperature range t amb 20 to +70 c storage temperature range t stg 40 to + 125 c lead temperature during soldering at 2 mm distance, 10 seconds t sld 260 c absolute maximum ratings define parameter limits which, if exceeded, may permanently change or damage the device. all inputs and outputs in atmel wireless & microcontrollers' circuits are protected against electrostatic discharges. however, precautions to minimize the build-up of electro-static charges during handling are recommended. this circuit is protected against supply voltage reversal for typically 5 minutes.
e1467d rev. a2, 15-jan-01 2 (6) functional description oscillator an oscillator inverter with feedback resistor is provided for generation of the 32768 hz clock frequency. values for the fixed capacitors at oscin and oscout are mask-selectable (see note 3 of operating characteristics). four control inputs sc1 to sc4 enable the addition of integrated trimming capacitors to oscin and oscout, providing 15 tuning steps. trimming capacitors a frequency variation of typ. 4 ppm for each tuning step is obtained by bonding the capacitor switch pads to v dd . as none of these pads are bonded, the ic is in an untrimmed state. figure 5 shows the trimming curve characteristic. note: for applications which utilize this integrated trimming feature, atmel wireless & microcontrollers will deter- mine optimum values for the integrated capacitors c oscin and c oscout. motor drive output the e1467d contains two push-pull output buffers for driving bipolar stepping motors. during a motor pulse, the n-channel device of one buffer and the p-channel device of the other buffer will be activated. both n-channel transistor are on and conducting, between output pulses. the outputs are protected against inductive voltage spikes with diodes to both supply pins. the motor output period and pulse width are mask programmable, as listed below: available motor periods (t m ): 125, 250, 500 ms and 2, 16 s available max. pulse widths (t m ): 15, 6, 23.4, 31.25, 46.9 ms available motor periods for motor test (t mt ): 250, 500 ms and 1 s note: the following constraints for combination of motor period and pulse widths have to be considered: t m 4 * t m , t mt 4 * t m or alternatively t m = 2 * t m , t mt = 2 * t m alarm outputs the alarm output driver consists of push-pull stage for driving a speaker via an external bipolar transistor. the output is configured for npn and pnp bipolar capability. the output is an alarm tone modulated by a low frequency. tone frequencies, modulation frequencies, and on/off times are selectable via the metal mask option. alarm input a debounced alarm input is provided. alarm activation is either to v dd or v ss by a mask option. test functions for test purposes the alin/mtest pad is open. with a high resistance probe (r 10 m c 20 pf), a test frequency f test of 128 hz can be measured at the alin/ mtest pad. connecting alin/mtest (for at least 32 ms) to the opposite polarity for alarm activation changes the motor period from the selected value to t mt (mask-selectable) while the pulse width remains unaffected. this feature can be used for testing the mechanical parts of the clock. sc4 sc3 sc2 sc1 ? ? ? ? ? ? ? ? ? e1467d ? ? ? ?? ?? ? ? ? mot1l alin/ oscin oscout alout mot2 mot1r r3 r2 v dd v ss r1 1 2 3 45 6 7 8 9 10 11 12 13 v ss v dd mt 9611896 figure 5. functional test test crystal specification oscillation frequency f osc = 32768 hz series resistance r s = 30 k static capacitance c o = 1.5 pf dynamic capacitance c 1 = 3.0 ff load capacitance c l optionally 10 or 12.5 pf
e1467d rev. a2, 15-jan-01 3 (6) operating characteristics v ss = 0, v dd = 1.5 v, t amb = +25 c, unless otherwise specified all voltage levels are measured with reference to v ss . test crystal as specified below. parameters test conditions / pins symbol min. typ. max. unit operating voltage v dd 1.1 1.5 2.2 v operating temperature t amb 20 +70 c operating current r 1 = , note 2 i dd 1 3 a motor drive output motor output current v dd = 1.2 v, r 1 = 200 i m 4.3 ma motor period t m see option list s motor period during motor test t mt see option list ms motor pulse width t m see option list ms oscillator startup voltage within 2 s v start 1.2 2.2 v frequency stability v dd = 100 mv v dd = 1.1 to 2.2 v f/f 0.1 0.2 ppm integrated input capacitance note 3 c oscin see option list pf integrated output capacitance c oscout see option list pf input current sc1 to sc4 v in = 0.2 v v in = v dd , note 5 i scinl i scinh 1 0.05 5 0.15 25 0.5 a a alarm/output output current for driving npn-transistor v dd = 1.2 v n-channel r 3 = 100 k i ann 1 3 10 a p-channel r 2 = 1 k , note 2, note 4 i anp 0.5 1 ma output current for driving pnp-transistor v dd = 1.2 v n-channel r 3 = 1 k i apn 0.5 1 ma p-channel r 2 = 100 k , note 2, note 4 i app 1 2 10 a alarm options tone frequency f a see option list hz modulation frequency f mod see option list hz on/off time t on /t off see option list s alarm input/motor test input current alin = v dd , peak current i ainh 0.6 3 10 a input current alin = v ss , peak current i ainl 0.6 3 10 a input debounce delay t ain 23.4 31.2 ms note 1: typical parameters represent the statistical mean values note 2: see test circuit note 3: values can be selected in 1 pf steps. a total capacitance (c oscin + c oscout ) of 38 pf is available note 4: npn or pnp driving transistors defined by mask options note 5: i scinh is the peak current of a pulsed current with duty cycle 1:63. average current is always smaller than 10 na
e1467d rev. a2, 15-jan-01 4 (6) motor output signal during normal mode and motortest alin/ mt mot1 v ss v dd v ss v dd v ss v dd mot2 t m t m t mt 1/f test a detail a: 9611898 figure 6. motor output signal during normal operation and during motor test 1/f a 1/f mod v dd v ss detail b: alarm output signal t on t off v dd v ss alout signal on alarm input and alarm output during alarm activation v dd v ss b alin / mtest t < t ain t > t ain t < t v4 t > t v4 9611899 figure 7. alarm operation
e1467d rev. a2, 15-jan-01 5 (6) 1.99991 1.99992 1.99993 1.99994 1.99995 1.99996 1.99997 1.99998 1.99999 2.00000 2.00001 2.00002 2.00003 2.00004 2.00005 2.00006 0123456789101112131415 motorperiod (s) trimming steps c ox = 0.95 1.00 1.05 9611900 figure 8. typical trimming curve characteristic for t m of 2 s c ox means frequency deviation due to production process variations. trimming inputs sc1 ... sc4 are binary weighted, i.e., sc1 ... sc4 = 0 corresponds to trimming step 0 sc1 ... sc4 = 1 corresponds to trimming step 15 lsb = sc1
e1467d rev. a2, 15-jan-01 6 (6) ordering information table 4. option list e1267d option motor alarm load cap. integrated capacitance cycle (t m ) s pulse (t m ) ms test (t mt ) ms frequency hz modulation frequency hz on/ off time s driver type activation polarity pf c oscin *) pf c oscout *) pf b 2 23.4 250 2048 8 0.5/ 0.5 npn v ss 10 17 12 d 2 31.25 250 2048 8 0.5/ 0.5 npn v dd 10 17 12 v2 0.5 23.4 250 2048 8 0.5/ 0.5 npn v ss 12.5 20 16 e2 2 46.9 250 2048 8 1/ 3 npn v ss 12.5 20 16 *) on-chip stray capacitance included option pad designation pad 1 pad 2 pad 3 pad 4 pad 5 pad 6 pad 7 pad 8 pad 9 pad 10 pad 11 pad 12 pad 13 b oscin v dd alout mot2 mot1 mot1 alin/ mtest v ss osc- out sc4 sc3 sc2 sc1 d oscin osc- out alout mot2 mot1 mot1 alin/ mtest v ss v dd sc4 sc3 sc2 sc1 v2 oscin v dd alout mot2 mot1 mot1 alin/ mtest v ss osc- out sc4 sc3 sc2 sc1 d oscin osc- out alout mot2 mot1 alin/ test mot1 v ss v dd sc4 sc3 sc2 sc1 we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use atmel wireless & microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify atmel wireless & microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. data sheets can also be retrieved from the internet: http://www.atmelwm.com atmel germany gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2594, fax number: 49 (0)7131 67 2423
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