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? 2001 fairchild semiconductor corporation ds011657 www.fairchildsemi.com december 1993 revised january 2001 scan182245a non-inverting transceiver with 25 ? series resistor outputs scan182245a non-inverting transceiver with 25 ? series resistor outputs general description the scan182245a is a high performance bicmos bidi- rectional line driver featuring separate data inputs orga- nized into dual 9-bit bytes with byte-oriented output enable and direction control signals. this device is compliant with ieee 1149.1 standard test access port and boundary scan architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of test data input (tdi), test data out (tdo), test mode select (tms), and test clock (tck). features high performance bicmos technology 25 ? series resistors in outputs eliminate the need for external terminating resistors dual output enable control signals 3-state outputs for bus-oriented applications 25 mil pitch ssop (shrink small outline package) ieee 1149.1 (jtag) compliant includes clamp, idcode and highz instructions additional instructions sample-in, sample-out and extest-out power up 3-state for hot insert member of fairchild?s scan products ordering code: devices also available in tape and reel. specify by appending the suffix letter ? x ? to the ordering code. connection diagram pin descriptions order number package number package description scan182245assc ms56a 56-lead shrink small outline package (ssop), jedec mo-118, 0.300 wide SCAN182245AMTD mtd56 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide pin names description a1 (0 ? 8) side a1 inputs or 3-state outputs b1 (0 ? 8) side b1 inputs or 3-state outputs a2 (0 ? 8) side a2 inputs or 3-state outputs b2 (0 ? 8) side b2 inputs or 3-state outputs g1 , g2 output enable pins (active low) dir1, dir2 direction of data flow pins
www.fairchildsemi.com 2 scan182245a truth tables h = high voltage level l = low voltage level x = immaterial z = high impedance note 1: inactive-to-active transition must occur to enable outputs upon power-up. functional description the scan182245a consists of two sets of nine non-invert- ing bidirectional buffers with 3-state outputs and is intended for bus-oriented applications. direction pins (dir1 and dir2) low enables data from b ports to a ports, when high enables data from a ports to b ports. the out- put enable pins (g1 and g2 ) when high disables both a and b ports by placing them in a high impedance condition. block diagrams a1, b1, g1 and dir1 note: bsr stands for boundary scan register. a2, b2, g2 and dir2 note: bsr stands for boundary scan register. tap controller inputs a1 (0?8) b1 (0?8) g1 (note 1) dir1 llh h lll l lhh h lhl l hxzz inputs a2 (0?8) b2 (0?8) g2 (note 1) dir2 llh h ll l l lhh h lh l l hxzz
3 www.fairchildsemi.com scan182245a description of boundary-scan circuitry the scan cells used in the boundary-scan register are one of the following two types depending upon their loca- tion. scan cell type1 is intended to solely observe system data, while type2 has the additional ability to control sys- tem data. scan cell type1 is located on each system input pin while scan cell type2 is located at each system output pin as well as at each of the two internal active-high output enable signals. aoe controls the activity of the a-outputs while boe controls the activity of the b-outputs. each will acti- vate their respective outputs by loading a logic high. the bypass register is a single bit shift register stage identical to scan cell type1. it captures a fixed logic low. bypass register scan chain definition logic 0 scan182245a product idcode (32-bit code per ieee 1149.1) the instruction register is an 8-bit register which cap- tures the default value of 10000001 (sample/preload) during the capture-ir instruction command. the benefit of capturing sample/preload as the default instruction during capture-ir is that the user is no longer required to shift in the 8-bit instruction for sample/preload. the sequence of: capture-ir exit1-ir update-ir will update the sample/preload instruction. for more information refer to the section on instruction definitions. instruction register scan chain definition msb lsb scan cell type1 scan cell type2 versio n entity part manufacture r required number id by 1149.1 0000 111111 000000000 0 00000001111 1 msb msb instruction code instruction 00000000 extest 10000001 sample/preload 10000010 clamp 00000011 high-z 01000001 sample-in 01000010 sample-out 00100010 extest-out 10101010 idcode 11111111 bypass all others bypass
www.fairchildsemi.com 4 scan182245a description of boundary-scan circuitry (continued) boundary-scan register scan chain definition (80 bits in length)
5 www.fairchildsemi.com scan182245a description of boundary-scan circuitry (continued) input boundary-scan register scan chain definition (40 bits in length) when sample in is active
www.fairchildsemi.com 6 scan182245a description of boundary-scan circuitry (continued) output boundary-scan register scan chain definition (40 bits in length) when sample out and extest-out are active
7 www.fairchildsemi.com scan182245a description of boundary-scan circuitry (continued) boundary-scan register definition index bit no. pin name pin no. pin type scan cell type bit no. pin name pin no. pin type scan cell type 79 dir1 3 input type1 control signals 35 b1 0 2 input type1 b1 ? in 78 g1 54 input type1 34 b1 1 4 input type1 77 aoe 1 internal type2 33 b1 2 5 input type1 76 boe 1 internal type2 32 b1 3 7 input type1 75 dir2 26 input type1 31 b1 4 8 input type1 74 g2 31 input type1 30 b1 5 10 input type1 73 aoe 2 internal type2 29 b1 6 11 input type1 72 boe 2 internal type2 28 b1 7 13 input type1 71 a1 0 55 input type1 a1 ? in 27 b1 8 14 input type1 70 a1 1 53 input type1 26 b2 0 15 input type1 b2 ? in 69 a1 2 52 input type1 25 b2 1 16 input type1 68 a1 3 50 input type1 24 b2 2 18 input type1 67 a1 4 49 input type1 23 b2 3 19 input type1 66 a1 5 47 input type1 22 b2 4 21 input type1 65 a1 6 46 input type1 21 b2 5 22 input type1 64 a1 7 44 input type1 20 b2 6 24 input type1 63 a1 8 43 input type1 19 b2 7 25 input type1 62 a2 0 42 input type1 a2 ? in 18 b2 8 27 input type1 61 a2 1 41 input type1 17 a1 0 55 output type2 a1 ? out 60 a2 2 39 input type1 16 a1 1 53 output type2 59 a2 3 38 input type1 15 a1 2 52 output type2 58 a2 4 36 input type1 14 a1 3 50 output type2 57 a2 5 35 input type1 13 a1 4 49 output type2 56 a2 6 33 input type1 12 a1 5 47 output type2 55 a2 7 32 input type1 11 a1 6 46 output type2 54 a2 8 30 input type1 10 a1 7 44 output type2 53 b1 0 2 output type2 b1 ? out 9a1 8 43 output type2 52 b1 1 4 output type2 8 a2 0 42 output type2 a2 ? out 51 b1 2 5 output type2 7 a2 1 41 output type2 50 b1 3 7 output type2 6 a2 2 39 output type2 49 b1 4 8 output type2 5 a2 3 38 output type2 48 b1 5 10 output type2 4 a2 4 36 output type2 47 b1 6 11 output type2 3 a2 5 35 output type2 46 b1 7 13 output type2 2 a2 6 33 output type2 45 b1 8 14 output type2 1 a2 7 32 output type2 44 b2 0 15 output type2 b2 ? out 0a2 8 30 output type2 43 b2 1 16 output type2 42 b2 2 18 output type2 41 b2 3 19 output type2 40 b2 4 21 output type2 39 b2 5 22 output type2 38 b2 6 24 output type2 37 b2 7 25 output type2 36 b2 8 27 output type2
www.fairchildsemi.com 8 scan182245a scan abt live insertion and power cycling characteristics scan abt is intended to serve in live insertion backplane applications. it provides 2nd level isolation 1 which indi- cates that while external circuitry to control the output enable pin is unnecessary, there may be a need to imple- ment differential length backplane connector pins for v cc and gnd. as well, pre-bias circuitry for backplane pins may be necessary to avoid capacitive loading effects dur- ing live insertion. scan abt provides control of output enable pins during power cycling via the circuit in figure 1. it essentially con- trols the g n pin until v cc reaches a known level. during power-up , when v cc ramps through the 0.0v to 0.7v range, all internal device circuitry is inactive, leaving output and i/o pins of the device in high impedance. from approximately 0.8v to 1.8v v cc , the power-on-reset cir- cuitry, (por), in figure 1 becomes active and maintains device high impedance mode. the por does this by pro- viding a low from its output that resets the flip-flop the out- put, q , of the flip-flop then goes high and disables the nor gate from an incidental low input on the g n pin. after 1.8v v cc , the por circuitry becomes inactive and ceases to control the flip-flop. to bring the device out of high imped- ance, the g n input must receive an inactive-to-active transi- tion, a high-to-low transition on g n in this case to change the state of the flip-flop. with a low on the q output of the flip-flop, the nor gate is free to allow propagation of a g n signal. during power-down , the power-on-reset circuitry will become active and reset the flip-flop at approximately 1.8v v cc . again, the q output of the flip-flop returns to a high and disables the nor gate from inputs from the g n pin. the device will then remain in high impedance for the remaining ramp down from 1.8v to 0.0v v cc . some suggestions to help the designer with live insertion issues: the g n pin can float during power-up until the power- on-reset circuitry becomes inactive. the g n pin can float on power-down only after the power-on-reset has become active. the description of the functionality of the power-on-reset circuitry can best be described in the diagram of figure 2. figure 1. 1 section 7, ? design consideration for fault tolerant backplanes ? , application note an-881. scan abt includes additional power-on reset circuitry not otherwise included in abt devices. figure 2.
9 www.fairchildsemi.com scan182245a absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. functional operation under these conditions is not implied. note 3: either voltage limit or current limit is sufficient to protect inputs. dc electrical characteristics note 4: guaranteed not tested. storage temperature ? 65 c to + 150 c ambient temperature under bias ? 55 c to + 125 c junction temperature under bias ? 55 c to + 150 c v cc pin potential to ground pin ? 0.5v to + 7.0v input voltage (note 3) ? 0.5v to + 7.0v input current (note 3) ? 30 ma to + 5.0 ma voltage applied to any output in the disabled or power-off state ? 0.5v to + 5.5v in the high state ? 0.5v to v cc current applied to output in low state (max) twice the rated i ol (ma) dc latchup source current ? 500 ma over voltage latchup (i/o) 10v esd (hbm) min. 2000v free air ambient temperature ? 40 c to + 85 c supply voltage + 4.5v to + 5.5v minimum input edge rate ( ? v/ ? t) data input 50 mv/ns enable input 20 mv/ns symbol parameter v cc min typ max units conditions v ih input high voltage 2.0 v recognized high signal v il input low voltage 0.8 v recognized low signal v cd input clamp diode voltage min ? 1.2 v i in = ? 18 ma v oh output high voltage min 2.5 v i oh = ? 3 ma min 2.0 v i oh = ? 32 ma v ol output low voltage min 0.8 v i ol = 15 ma i ih input high current all others max 5 av in = 2.7v (note 4) max 5 av in = v cc tms, tdi max 5 av in = v cc i bvi input high current breakdown test max 7 av in = 7.0v i bvit input high current breakdown test (i/o) max 100 av in = 5.5v i il input low current all others max ? 5 av in = 0.5v (note 4) max ? 5 av in = 0.0v tms, tdi max ? 385 av in = 0.0v v id input leakage test 0.0 4.75 v i id = 1.9 a all other pins grounded i ih + i ozh output leakage current max 50 av out = 2.7v i il + i ozl output leakage current max ? 50 av out = 0.5v i ozh output leakage current max 50 av out = 2.7v i ozl output leakage current max ? 50 av out = 0.5v i os output short-circuit current max ? 100 ? 275 ma v out = 0.0v i cex output high leakage current max 50 av out = v cc i zz bus drainage test 0.0 100 av out = 5.5v, all others gnd i cch power supply current max 250 av out = v cc ; tdi, tms = v cc max 1.0 ma v out = v cc ; tdi, tms = gnd i ccl power supply current max ma v out = low; tdi, tms = v cc max 65.8 ma v out = low; tdi, tms = gnd i ccz power supply current max 250 a tdi, tms = v cc max 1.0 ma tdi, tms = gnd i cct additional i cc /input all other inputs max 2.9 ma v in = v cc ? 2.1v tdi, tms inputs max 3 ma v in = v cc ? 2.1v i ccd dynamic i cc no load max 0.2 ma/ outputs open mhz one bit toggling, 50% duty cycle
www.fairchildsemi.com 10 scan182245a ac electrical characteristics normal operation: note 5: voltage range 5.0v 0.5v ac electrical characteristics scan test operation note 6: voltage range 5.0v 0.5v note: all propagation delays involving tck are measured from the falling edge of tck. symbol parameter v cc t a = ? 40 c to + 85 c units (v) c l = 50 pf (note 5) min typ max t plh t phl propagation delay 5.0 1.0 3.1 5.2 ns a to b, b to a 1.5 4.4 6.5 t plz disable time 5.0 1.5 4.8 8.6 ns t phz 1.5 5.2 8.9 t pzl enable time 5.0 1.5 5.5 9.1 ns t pzh 1.5 4.6 8.2 symbol parameter v cc t a = ? 40 c to + 85 c units (v) c l = 50 pf (note 6) min typ max t plh t phl propagation delay 5.0 2.9 6.1 10.2 ns tck to tdo 4.2 7.7 12.1 t plz disable time 5.0 2.1 5.9 10.7 ns t phz tck to tdo 3.3 7.4 12.5 t pzl t pzh enable time 5.0 4.6 8.7 13.7 ns tck to tdo 2.8 6.8 11.5 t plh propagation delay 5.0 2.8 6.3 10.7 ns t phl tck to data out during update-dr state 4.5 8.2 13.0 t plh propagation delay 5.0 3.3 7.2 12.2 ns t phl tck to data out during update-ir state 5.0 9.3 14.8 t plh propagation delay 5.0 3.7 8.4 14.0 ns t phl tck to data out during test logic reset state 5.7 10.8 17.2 t plz disable time 5.0 2.8 7.6 13.9 ns t phz tck to data out during update-dr state 3.5 8.4 14.5 t plz disable time 5.0 3.6 8.7 15.1 ns t phz tck to data out during update-ir state 3.8 9.2 15.9 t plz disable time 5.0 4.0 9.8 17.1 ns t phz tck to data out during test logic reset state 4.2 9.9 16.6 t pzl enable time 5.0 4.4 9.3 15.5 ns t pzh tck to data out during update-dr state 3.0 7.5 13.3 t pzl enable time 5.0 5.2 10.7 17.4 ns t pzh tck to data out during update-ir state 3.9 9.0 15.4 t pzl enable time 5.0 5.7 12.0 19.8 ns t pzh tck to data out during test logic reset state 3.0 10.2 17.6
11 www.fairchildsemi.com scan182245a ac operating requirements scan test operation note 7: voltage range 5.0v 0.5v note 8: timing pertains to the type1 bsr and type2 bsr after the buffer (bsr 0 ? 8, 9 ? 17, 18 ? 26, 27 ? 35, 36 ? 44, 45 ? 53, 54 ? 62, 63 ? 71). note 9: timing pertains to bsr 74 and 78 only. note 10: timing pertains to bsr 75 and 79 only. note 11: timing pertains to bsr 72, 73, 76 and 77 only. note: all input timing delays involving tck are measured from the rising edge of tck. capacitance note 12: c i/o is measured at frequency f = 1 mhz, per mil-std-883b, method 3012. symbol parameter v cc t a = ? 40 c to + 85 c units (v) c l = 50 pf (note 7) guaranteed minimum t s setup time 5.0 4.8 ns data to tck (note 8) t h hold time 5.0 2.5 ns data to tck (note 8) t s setup time, h or l 5.0 4.1 ns g1 , g2 to tck (note 9) t h hold time, h or l 5.0 1.7 ns tck to g1 , g2 (note 9) t s setup time, h or l 5.0 4.2 ns dir1, dir2 to tck (note 10) t h hold time, h or l 5.0 2.3 ns tck to dir1, dir2 (note 10) t s setup time 5.0 3.8 ns internal oe to tck (note 11) t h hold time, h or l 5.0 2.3 ns tck to internal oe (note 10) t s setup time, h or l 5.0 8.7 ns tms to tck t h hold time, h or l 5.0 1.5 ns tck to tms t s setup time, h or l 5.0 6.7 ns tdi to tck t h hold time, h or l 5.0 5.0 ns tck to tdi t w pulse width tck: h 5.0 10.2 ns l8.5 f max maximum tck 5.0 50 mhz clock frequency t pu wait time, 5.0 100 ns power up to tck t dn power down delay 0.0 100 ms symbol parameter typ units conditions, t a = 25 c c in input capacitance 5.9 pf v cc = 0.0v (g n , dir n ) c i/o (note 12) output capacitance 13.7 pf v cc = 5.0v (a n , b n )
www.fairchildsemi.com 12 scan182245a physical dimensions inches (millimeters) unless otherwise noted 56-lead shrink small outline package (ssop), jedec mo-118, 0.300 wide package number ms56a
13 www.fairchildsemi.com scan182245a non-inverting transceiver with 25 ? series resistor outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd56 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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