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cy7b9911 roboclock+? programmable skew clock buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07209 rev. *b revised june 20, 2007 features all output pair skew <100 ps typical (250 max) 3.75 to 100 mhz output operation user selectable output functions ? selectable skew to 18 ns ? inverted and non-inverted ? operation at ? and ? input frequency ? operation at 2x and 4x input frequency (input as low as 3.75 mhz) zero input to output delay 50% duty cycle outputs outputs drive 50 terminated lines low operating current 32-pin plcc/lcc package jitter < 200 ps peak-to-peak (< 25 ps rms) functional description the cy7b9911 high speed programmable skew clock buffer (pscb) offers user selectable control over system clock functions. this multiple output clock driver provides the system integrator with functi ons necessary to optim ize the timing of high performance computer systems. each of the eight individual ttl drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50 . they deliver minimal and specified output skews and full swing logic levels. each output is hardwired to one of nine delay or function config- urations. delay increments of 0.6 to 1.5 ns are determined by the operating frequency with outputs able to skew up to 6 time units from their nominal ?zero? skew position. the completely integrated pll allows cancellation of external load and trans- mission line delay effects. when this ?zero delay? capability of the pscb is combined with the sele ctable output skew functions, you can create output-to-output delays of up to 12 time units. divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. when combined with the internal pll, these divide functions enable distribution of a low freque ncy clock that is multiplied by two or four at the clock destinati on. this facility minimizes clock distribution difficulty enabli ng maximum system clock speed and flexibility. logic block diagram test fb ref vco and time unit generator fs select inputs (three level) skew select matrix 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 filter phase freq det
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 2 of 13 pin configuration pin definitions signal name io description ref i reference frequency input. this input supplies the frequency and timing against which all functional variation is measured. fb i pll feedback input (typically connec ted to one of the eight outputs). fs i three level frequency range select. see table 1 . 1f0, 1f1 i three level function select inputs for output pair 1 (1q0, 1q1). see table 2 . 2f0, 2f1 i three level function select inputs for output pair 2 (2q0, 2q1). see table 2 3f0, 3f1 i three level function select inputs for output pair 3 (3q0, 3q1). see table 2 4f0, 4f1 i three level function select inputs for output pair 4 (4q0, 4q1). see table 2 test i three level select. see test mode section under the block diagram descriptions. 1q0, 1q1 o output pair 1. see table 2 . 2q0, 2q1 o output pair 2. see table 2 . 3q0, 3q1 o output pair 3. see table 2 . 4q0, 4q1 o output pair 4. see table 2 . v ccn pwr power supply for output drivers. v ccq pwr power supply for in ternal circuitry. gnd pwr ground. 1 2 3 4323130 17 16 15 14 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3f0 fs v ref gnd test 2f1 fb 2q1 2q0 ccq 2f0 gnd 1f1 1f0 v ccn 1q0 1q1 gnd gnd 3q1 3q0 ccn v ccn v 3f1 4f0 4f1 v ccq v ccn 4q1 4q0 gnd gnd plcc/lcc cy7b9911
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 3 of 13 block diagram description phase frequency detector and filter the phase frequency detector and filter blocks accept inputs from the reference frequency (ref) input and the feedback (fb) input. they generate correction information to control the frequency of the voltage controlled oscillator (vco). these blocks, along with the vco, form a phase locked loop (pll) that tracks the incoming ref signal. vco and time unit generator the vco accepts analog control in puts from the pll filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew select matrix. the operational range of the vco is determined by the fs control pin. the time unit (t u ) is determined by the operating frequency of the device and the le vel of the fs pin as shown in table 1 . skew select matrix the skew select matrix contains four independent sections. each section has two low skew, high fanout drivers (xq0, xq1), and two corresponding three level function select (xf0, xf1) inputs. table 2 shows the nine possible output functions for each section as determined by the function select inputs. all times are measured with respect to the ref input assuming that the output connected to the fb input has 0t u selected. table 1. frequency range select and t u calculation [1] fs [2,3] f nom (mhz) where n = approximate frequency (mhz) at which t u = 1.0 ns min max low 15 30 44 22.7 mid 25 50 26 38.5 high 40 100 16 62.5 t u 1 f nom n ----------------------- - = table 2. programmable skew configurations [1] function selects output functions 1f1, 2f1, 3f1, 4f1 1f0, 2f0, 3f0, 4f0 1q0, 1q1, 2q0, 2q1 3q0, 3q1 4q0, 4q1 low low ?4t u divide by 2 divide by 2 low mid ?3t u ?6t u ?6t u low high ?2t u ?4t u ?4t u mid low ?1t u ?2t u ?2t u mid mid 0t u 0t u 0t u mid high +1t u +2t u +2t u high low +2t u +4t u +4t u high mid +3t u +6t u +6t u high high +4t u divide by 4 inverted notes 1. for all three state inputs, high indicates a connection to vcc, low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to vcc/2. 2. the level to be set on fs is determined by the ?normal? operating frequency (fnom) of the vco and time unit generator (see logic block diagram ). nominal frequency (fnom) always appears at 1q0 and the other outputs when they are operated in their undivided modes (see table 2 ). the frequency appearing at the ref and fb inputs will be fnom when the output connected to fb is un divided. the frequency of the ref and fb inputs will be fnom/2 or fnom/4 when the part is configured for a frequency multiplication by using a divided output as the fb input. 3. when the fs pin is selected high, the ref input must not transition upon power-up until vcc has reached 4.3v.
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 4 of 13 test mode the test input is a three level input. in normal system operation, this pin is connected to ground, enabling the cy7b9911 to operate as explained in the previous section (for testing purposes). any of the three level inputs can have a removable jumper to ground or be tied low through a 100 resistor. this enables an external tester to change the state of these pins. if the test input is forced to its mid or high state, the device operates with its internal phas e locked loop disconnected, and input levels supplied to ref direct ly control all outputs. relative output to output functions are the same as in normal mode. in contrast with normal operatio n (test tied low), all outputs function based only on the con nection of their own function select inputs (xf0 and xf1) and the waveform characteristics of the ref input. maximum ratings operating outside these boundaries may affect the performance and life of the device. these us er guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................ ?55 c to +125 c supply voltage to ground potent ial................?0 .5v to +7.0v dc input voltage ..................... .......................?0.5v to +7.0v output current into outputs (low)............................. 64 ma static discharge voltage....... ........... ............ .............. >2001v (per mil-std-883, method 3015) latch up current ..................................................... >200 ma figure 1. typical outputs with fb connected to a zero-skew output [ 4 ] t 0 ? 6t u t 0 ? 5t u t 0 ? 4t u t 0 ? 3t u t 0 ? 2t u t 0 ? 1t u t 0 t 0 +1t u t 0 t 0 t 0 t 0 t 0 +2t u +3t u +4t u +5t u +6t u fb input ref input ? 6t u ? 4t u ? 3t u ? 2t u ? 1t u 0t u +1t u +2t u +3t u +4t u +6t u divided invert lm lh (n/a) ml (n/a) mm (n/a) mh (n/a) hl hm ll/hh hh 3fx 4fx (n/a) ll lm lh ml mm mh hl hm hh (n/a) (n/a) (n/a) 1fx 2fx note 4. fb connected to an output selected for ?zero? skew (i.e., xf1 = xf0 = mid).
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 5 of 13 operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% electrical characteristics over the operating range cy7b9911 parameter description test conditions min max unit v oh output high voltage v cc = min, i oh = ?16 ma 2.4 v v cc = min, i oh =?40 ma v ol output low voltage v cc = min, i ol = 46 ma 0.45 v v cc = min, i ol = 46 ma v ih input high voltage (ref and fb inputs only) 2.0 v cc v v il input low voltage (ref and fb inputs only) ?0.5 0.8 v v ihh three level input high voltage (test, fs, xfn) [5] min v cc max v cc ? 0.85 v cc v v imm three level input mid voltage (test, fs, xfn) [5] min v cc max v cc /2 ? 500 mv v cc /2 + 500 mv v v ill three level input low voltage (test, fs, xfn) [5] min v cc max 0.0 0.85 v i ih input high leakage current (ref and fb inputs only) v cc = max, v in = max. 10 ma i il input low leakage current (ref and fb inputs only) v cc = max, v in = 0.4v ?500 ma i ihh input high current (test, fs, xfn) v in = v cc 200 ma i imm input mid current (test, fs, xfn) v in = v cc /2 ?50 50 ma i ill input low current (test, fs, xfn) v in = gnd ?200 ma i os output short circuit current [5] v cc = max, v out = gnd (25 c only) ?250 ma i ccq operating current used by internal circuitry v ccn = v ccq = max, all input selects open com?l 85 ma i ccn output buffer current per output pair [6] v ccn = v ccq = max, i out = 0 ma input selects open, f max 14 ma pd power dissipation per output pair [8] v ccn = v ccq = max, i out = 0 ma input selects open, f max 78 mw notes 5. these inputs are normally wired to vcc, gnd, or left unconnect ed (actual threshold voltages vary as a percentage of vcc). int ernal termination resistors hold unconnected inputs at vcc/2. if these inputs are switched , the function and timing of the outputs glitch and the pll requi res an additional tlock time before all datasheet limits are achieved. 6. cy7b9911 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. room tempera ture only. 7. total output current per output pair is approximated by the fo llowing expression that includes device current plus load curre nt: cy7b9911:iccn = [(4 + 0.11f) + [((835 ? 3f)/z) + (.0022fc)]n] x 1.1 where f = frequency in mhz; c = capacitive load in pf; z = line impedance in ohms; n = number of loaded outputs; 0, 1, or 2; fc = f * c. 8. total power dissipation per output pair is approximated by the following expression that includes device power dissipation pl us power dissipation due to the load circuit: cy7b9911:pd = [(22 + 0.61f) + [((1550 ? 2.7f)/z) + (.0125fc)]n] x 1.1.
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 6 of 13 capacitance test conditions assume signal transit ion times unless otherwise specified. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf ac test loads and waveforms ttl ac test load (cy7b9911) ttl input test waveform (cy7b9911) 5v r1 r2 c l 3.0v 2.0v v th =1.5v 0.8v 0.0v 1ns 1ns 2.0v 0.8v v th =1.5v r1=130 r2=91 c l =30pf (includes fixture and probe capacitance)
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 7 of 13 switching characteristics over the operating range [2, 10] cy7b9911?5 cy7b9911?7 parameter description min typ max min typ max unit f nom operating clock frequency in mhz fs = low [1, 2] 15 30 15 30 mhz fs = mid [1, 2] 25 50 25 50 fs = high [1, 2 , 3] 40 100 40 100 t rpwh ref pulse width high 4.0 4.0 ns t rpwl ref pulse width low 4.0 4.0 ns t u programmable skew unit see ta ble 1 see table 1 t skewpr zero output matched pair skew (xq0, xq1) [11, 12] 0.1 0.25 0.1 0.25 ns t skew0 zero output skew (all outputs) [11, 13] 0.25 0.5 0.3 0.75 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [11, 14] 0.6 0.7 0.6 1.0 ns t skew2 output skew (rise-fa ll, nominal-inverted, divided-divided) [11, 14] 0.5 1.2 1.0 1.7 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) [11, 14] 0.5 0.9 0.7 1.4 ns t skew4 output skew (rise-fall, nominal-divided, divided-inverted) [11, 14] 0.5 1.2 1.2 1.9 ns t dev device-to-device skew [10, 15] 1.25 1.65 ns t pd propagation delay, ref rise to fb rise ?0.5 0.0 +0.5 ?0.7 0.0 +0.7 ns t odcv output duty cycle variation [18] ?1.0 0.0 +1.0 ?1.2 0.0 +1.2 ns t pwh output high time deviation from 50% [17, 18] 2.0 2.5 ns t pwl output low time deviation from 50% [17, 18] 2.5 3 ns t orise output rise time [17, 19] 0.15 1.0 1.5 0.15 1.5 2.5 ns t ofall output fall time [17, 19] 0.15 1.0 1.5 0.15 1.5 2.5 ns t lock pll lock time [20] 0.5 0.5 ms t jr cycle-to-cycle output jitter rms [10] 25 25 ps peak-to-peak [10] 200 200 ps notes 9. test conditions assume signal transition times of 2 ns or less and output loading as shown in the ac test loads and waveforms unless otherwise specified. 10. guaranteed by statistical correlation. tested initially and afte r any design or process changes that affect these parameters . 11. skew is defined as the time between the earliest and the latest output transition among all outputs for which the same t u delay is selected when all are loaded with 30 pf and terminated with 50 to 2.06v. 12. t skewpr is defined as the skew between a pair of outputs (xq0 and xq1) when all eight outputs are selected for 0t u . 13. t skew0 is defined as the skew between outputs when they are selected for 0t u . other outputs are divided or inverted but not shifted. 14. there are three classes of outputs: nominal (multiple of t u delay), inverted (4q0 and 4q1 only with 4f0 = 4f1 = high), and divided (3qx and 4qx only in divide-by-2 or divide-by-4 mode). 15. t dev is the output-to-output skew between any two de vices operating under the same conditions (v cc ambient temperature, air flow, and so on). 16. t odcv is the deviation of the output from a 50% duty c ycle. output pulse width variations are included in t skew2 and t skew4 specifications. 17. specified with outputs loaded with 30 pf. devices are terminated through 50 to 2.06v. 18. t pwh is measured at 2.0v. t pwl is measured at 0.8v. 19. t orise and t ofall measured between 0.8v and 2.0v. 20. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at ref or fb until t pd is within specified limits.
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 8 of 13 ac timing diagrams figure 2. ac timing diagrams t odcv t odcv t ref ref fb q other q inverted q ref divided by 2 ref divided by 4 t rpwh t rpwl t pd t skewpr, t skew0, 1 t skewpr, t skew0, 1 t skew2 t skew2 t skew3, 4 t skew3, 4 t skew3, 4 t skew1,3, 4 t skew2, 4 t jr
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 9 of 13 operational m ode descriptions figure 2 shows the pscb configured as a zero skew clock buffer. in th is mode the 7b9911 is used as the basis for a low skew clock distribution tree. when all of the function select inputs (xf0, xf1) are left open, the outputs are aligned and each drive a te rminated transmission line to an independent load. the fb input is tied to any output in this configur ation and the operating frequency range is selected with the fs pin. the low skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), enables efficient printed circuit board design. figure 3 shows a configuration to equalize skew between metal traces of different lengths. in addition to low skew between outputs, the pscb is programmed to stagger the timing of its outputs. the four groups of ou tput pairs are each programmed to different output timing. skew timing is adjusted over a wide range in small increments with t he appropriate strapping of the function select pins. in this co nfiguration the 4q0 output is sent to fb and configured for zero skew. the other three pairs of outputs are programmed to yield different skews relative to the feedback. by advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads receive the clock pulse at the same time. in this illustration the fb input is connected to an output with 0 ns skew (xf1, xf0 = mid) select ed. the internal pll synchro- nizes the fb and ref inputs and aligns their rising edges to make certain that all outputs have precise phase alignment. clock skews is advanced by 6 time units (tu) when using an output selected for zero skew as the feedback. there is a wider figure 3. zero skew and zero delay clock driver system clock l1 l2 l3 l4 length l1 = l2 = l3 = l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0 figure 4. programmable skew clock driver length l1 = l2 l3 < l2 by 6 inches l4 > l2 by 6 inches system clock l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test z 0 load load load load ref z 0 z 0 z 0
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 10 of 13 range of delays, if the output co nnected to fb is also skewed. as ?zero skew?, +tu, and ?tu are defined relative to output groups and the pll aligns the rising e dges of ref and fb, wider output skews are created by proper selection of the xfn inputs. for example, a +10 tu between ref and 3qx is achieved by connecting 1q0 to fb and setting 1f0 = 1f1 = gnd, 3f0 = mid, and 3f1 = high. (since fb aligns at ?4 tu and 3qx skews to +6 tu, a total of +10 tu skew is re alized.) many other configurations are realized by skewing both the ou tput used as the fb input and skewing the other outputs. figure 4 shows an example of the invert function of the pscb. in this example the 4q0 output used as the fb input is programmed for invert (4f0 = 4f 1 = high) while the other three pairs of outputs are programmed for zero skew. when 4f0 and 4f1 are tied high, 4q0 and 4q1 become inverted zero phase outputs. the pll aligns the rising edge of the fb input with the rising edge of the ref. this caus es the 1q, 2q, and 3q outputs to become the ?inverted? output s with respect to the ref input. by selecting the output to connect to fb, you can have two inverted and six non-inverted outputs or six inverted and two non-inverted outputs. the correct configuration is determined by the need for more (or fewer) inverted outputs. 1q, 2q, and 3q outputs is also skewed to compensate for varying trace delays independent of inversion on 4q. figure 5 illustrates the pscb configured as a clock multiplier. the 3q0 output is programmed to di vide by four and is sent back to fb. this causes the pll to increase its frequency until the 3q0 and 3q1 outputs are locked at 20 mhz while the 1qx and 2qx outputs run at 80 mhz. the 4q0 and 4q1 outputs are programmed to divide by two, that results in a 40 mhz waveform at these outputs. no te that the 20 and 40 mhz clocks fall simul- taneously and are out of phase on their rising edge. this enables the designer to use the rising edges of the 1 ? 2 frequency and 1 ? 4 frequency outputs without concern for rising edge skew. the 2q0, 2q1, 1q0, and 1q1 output s run at 80 mhz and are skewed by programming their select inputs accordingly. note that the fs pin is wired for 80 mhz operatio n because that is the frequency of the fastest output. figure 6 demonstrates the pscb in a clock divider application. 2q0 is fed back to the fb input and programmed for zero skew. 3qx is programmed to divide by four. 4qx is programmed to divide by two. note that the falling edges of the 4qx and 3qx outputs are aligned. this enables use of the rising edges of the 1 ? 2 frequency and 1 ? 4 frequency without concern for skew mismatch. the 1qx outputs are programmed to zero skew and are aligned with the 2qx outputs. in this example, the fs input is grounded to configure the device in the 15 to 30 mhz range since the highest frequency output is running at 20 mhz. figure 5. inverted output connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref figure 6. frequency multiplier with skew connections figure 7. frequency divider connections fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 20 mhz 40 mhz 80 mhz fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 20 mhz 5 mhz 10 mhz 20 mhz
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 11 of 13 figure 7 shows some of the functions that are selectable on the 3qx and 4qx outputs. these include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. an inverted output allows the syst em designer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. this function enables each of the two subsystems to clock 180 degrees out of phase, but still stay aligned within the skew specification. the divided outputs offer a zero delay divider for portions of the system that divides the clock by ei ther two or four, and still remain within a narrow skew of the ?1x? clock. without this feature, addition of an external divider is required and the propagation delay of the divider adds to the skew between the different clock signals. these divided outputs, coupled with the phase locked loop, enable the pscb to multiply the clock rate at the ref input by either two or four. this mode enables the designer to distribute a low frequency clock between va rious portions of the system. it also locally multiplies the clock rate to a more suitable frequency, maintaining the low skew characteristics of the clock driver. the pscb performs all of the functions described in this section at the same time. it can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. figure 8. multi-function clock driver figure 9. board-to-board clock distribution 20 mhz distribution clock 80 mhz inverted z 0 20 mhz 80 mhz zeroskew 80 mhz skewed4ns fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref load load load load z 0 z 0 z 0 system clock z 0 l1 l2 l3 l4 fb ref fs 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 test ref 4f0 4f1 3f0 3f1 2f0 2f1 1f0 1f1 4q0 4q1 3q0 3q1 2q0 2q1 1q0 1q1 ref fs fb load load load load load test z 0 z 0 z 0
cy7b9911 roboclock+? document number: 38-07209 rev. *b page 12 of 13 figure 8 shows the cy7b9911 connected in series to construct a zero-skew clock distribution tree between boards. delays of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. cascaded clock buffers accumulate low frequency jitter because of the non-ideal filtering characteristics of the pll filter. do not connect more than two clock buffers in series. ordering information accuracy (ps) ordering code package type operating range 500 cy7b9911?5jc 32-pb plastic leaded chip carrier commercial 500 cy7b9911?5jct 32-pb plastic leaded chip carrier - tape and reel commercial 750 cy7b9911?7jc [21] 32-pb plastic leaded chip carrier commercial note 21. not recommended for the new design. package diagrams figure 10. 32-pin plastic leaded chip carrier j65 51-85002-*b
document number: 38-07209 rev. *b revised june 20, 2007 page 13 of 13 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by phil ips. roboclock+ is a trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7b9911 roboclock+? ? cypress semiconductor corporation, 2001-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy7b9911 roboclo ck+? programmable skew clock buffer document number: 38-07209 rev. ecn no. issue date orig. of change description of change ** 110342 12/21/01 szv change from spec ification number: 38-00623 to 38-07209 *a 1199925 see ecn kvm/aesa add ed tape and reel part in ordering information added note: not recommended for the new design *b 1286064 see ecn aesa change status to final

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