30 n-channel logic level enhancement mode field effect transistor march 1998 features 30v , 20a , r ds(on) =22m @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-251 & to-252 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 20 v drain current-continuous @t j =125 c -pulsed i d 20 a i dm 77 a drain-source diode forward current i s 20 a maximum power dissipation p d w operating and storage temperature range t j ,t stg -55 to 175 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 3 50 /w c /w c ? r ds(on) =40m @v gs =4.5v. ? CED603AL/ceu603al @tc=25 c derate above 25 c 50 0.3 w/ c s g d ceu series to-252aa(d-pak) ced series to-251(l-pak) g g s s d d 6 6-37
CED603AL/ceu603al electrical characteristics (t c =25 c unless otherwise noted) parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss v gs =0v,i d = 250 a 30 v zero gate voltage drain current i dss v ds = 24v, v gs =0v 1 a gate-body leakage i gss v gs = 20v, v ds =0v 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d = 250 a 1 1.6 18 28 3 v drain-source on-state resistance r ds(on) v gs = 10v, i d =20a v gs = 4.5v, i d = 10a 22 40 m ? m ? on-state drain current i d(on) v ds = 10v, v gs =10v 60 35 a s forward transconductance fs g v ds = 10v, i d =25a dynamic characteristics b input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v dd =15v, v gs =0v f = 1.0mh z 770 330 100 15 55 95 100 20 3 5 p f p f p f switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f fall time v dd =15v, i d =20a, v gs =10v, r gen =24 ? 30 ns ns ns ns 110 150 130 total gate charge gate-source charge gate-drain charge q g q gs q gd v ds =24v,i d = 20a, v gs =10v 26 nc nc nc 6-38 6
parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs =0v,is=25a 1.3 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. figure 1. output characteristics figure 2. transfer characteristics figure 4. on-resistance variation with drain current and temperature figure 3. capacitance v ds , drain-to source voltage (v) v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) i d , drain current(a) drain-source, on-resistance i d , drain current (a) i d , drain current (a) [ [ 6-39 r ds(on) , normalized CED603AL/ceu603al 6 1.3 1.2 1.1 1.0 0.9 0.8 0.7 25 c tj=125 c -55 c 01020 3040 v gs =10v c, capacitance (pf) ciss coss crss 1800 1500 1200 900 600 300 0 010 515202530 0.95 -55 c 25 c 40 30 20 10 0 0123456 tj=125 c 40 35 30 25 20 15 10 5 0 0123 4 56 v gs =3v v gs =10,8,7,6,5,4v
CED603AL/ceu603al figure 5. gate threshold variation with temperature figure 6. breakdown voltage variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) v gs , gate to source voltage (v) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) figure 7. transconductance variation with drain current i ds , drain-source current (a) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) i d , drain current (a) 6-40 6 40 10 0.1 1.0 0.4 0.6 0.8 1.0 1.2 1.4 40 30 20 10 50 60 0 0 5 10 15 20 v ds =10v 10 8 6 4 2 0 0 3 6 9 12 15 18 21 24 v ds =24v i d =20a 300 200 100 10 0.5 0.1 1 1103060 v gs =10v single pulse tc=25 c r d s ( on ) limit dc 1s 10 0 ms 10 ms 1ms 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 3 a -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 id=250 3 a
figure 11. switching test circuit figure 12. switching waveforms t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width transient thermal impedance square wave pulse duration (sec) figure 13. normalized thermal transient impedance curve r(t),normalized effective 6-41 6 CED603AL/ceu603al inverted 2 1 0.1 0.01 10 -5 10 -4 10 -3 10 -2 10 -1 110 d=0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 1. r / ja (t)=r (t) * r / ja 2. r / ja =see datasheet 3. t jm- t a =p dm *r / ja (t) 4. duty cycle, d=t 1 /t 2 single pulse v dd r d v v r s v g gs in gen out l
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