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mb86295 s < cor a l p > pci graphics controller specification revision 1. 1 8 th january, 200 3 copyright ? fujitsu limited 200 2 all rights reserved
ii the specifications in this manual are subject to change without notice . contact our sal es department before purchasing the product described in this manual. information and circuit diagrams in this manual are only examples of device application s , they are not intended to be used in actual equipment. also, fujitsu accepts no responsibility f or infringement of patents or other rights owned by third parties caused by use of the information and circuit diagrams. the contents of this manual must not be reprinted or duplicated without permission of fujitsu. fujitsu ? s semiconductor devices are inte nded for standard uses (such as office equipment (computers and oa equipment), industrial/communications/measuring equipment, and personal /home equipment). customers using semiconductor devices for special applications ( including aerospace , nuclear, milit ary and medical applications) in which a failure or malfunction might endanger life or limb and which require extremely high reliability must contact our sales department first. if damage is caused by such use of our semiconductor devices without first co nsulting our sales department, fujitsu will not assume any responsibility for the loss. semiconductor devices fail with a known probability. customers must use safety design (such as redundant design, fireproof design, over - current prevention design, and malfunction prevention design) so that failures will not cause accidents, injury or death). if the products described in this manual fall within the goods or technologies regulated by the f oreign e xchange and foreign trade law, permission must be obtained before exp orting the goods o r technologies. all rights reserved the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams i n this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of thi rd parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weap on system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above - mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, f ire protection, and prevention of over - current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.
MB86295S iii specification manual rev1.1 update history date version page count change 22.8. 2002 0.1 266 first edition (update from coral - lq specification) 26.8.2002 0.2 2 72 video capture description added 12.11.2002 0.3 274 minor updates to host interface description. addition of waveforms/timing. 27.11.2002 0.4 276 refer diff03vs04.txt file. 2.12.2002 0.4a 277 video input register update 6.12.2002 1.0 283 first relea se 26.12.2002 1.0a 282 delete the description of two host interface registers. 8.1.2003 1.1 300 i 2 c interface and pci configuration register description added
MB86295S iv specification manual rev1.1 contents 1. general 1 1.1 preface ................................ ................................ ................................ ................................ 1 1.2 features ................................ ................................ ................................ .............................. 2 1.3 block diagram ................................ ................................ ................................ ...................... 3 1.4 functional overview ................................ ................................ ................................ ............. 4 1.4.1 host cpu interface ................................ ................................ ................................ ......... 4 1.4.2 external memory interface ................................ ................................ ............................... 5 1.4.3 display controller ................................ ................................ ................................ ............ 6 1.4.4 video capture function ................................ ................................ ................................ .... 8 1.4.5 g eometry processing ................................ ................................ ................................ ...... 9 1.4.6 2d drawing ................................ ................................ ................................ .................. 10 1.4.7 3d drawing ................................ ................................ ................................ .................. 12 1.4.8 special effects ................................ ................................ ................................ .............. 13 1.4.9 others ................................ ................................ ................................ .......................... 15 2. pins 16 2.1 signals ................................ ................................ ................................ .............................. 16 2.1.1 signal lines ................................ ................................ ................................ ................... 16 2.2 pin assignment ................................ ................................ ................................ .................. 17 2.2.1 pin assignment diagram ................................ ................................ ................................ 17 2.2.2 pin assignment table ................................ ................................ ................................ ..... 18 2.3 pin function ................................ ................................ ................................ ....................... 26 2.3.1 host cpu interface ................................ ................................ ................................ ....... 26 2.3.2 video output interface ................................ ................................ ................................ ... 28 2.3.3 video capture interface ................................ ................................ ................................ . 29 2.3.4 i 2 c interface ................................ ................................ ................................ ................. 30 2.3.5 graphics memory interface ................................ ................................ ............................ 31 2.3.6 clock input ................................ ................................ ................................ ................... 32 2.3.7 test pins ................................ ................................ ................................ ...................... 33 2.3.8 reset sequence ................................ ................................ ................................ ............ 33 2.3.9 how to switch internal operating frequency ................................ ................................ ..... 33 3. host interface 34 3.1 standard pci slave accesses ................................ ................................ ........................... 34 3.1.1 pci slave write ................................ ................................ ................................ ............ 34 3.1.2 pci slave read ................................ ................................ ................................ ............ 34 3.2 burst controller accesses (including pci master) ................................ ................................ 34 3.2.1 transfer modes ................................ ................................ ................................ ............ 35 3.2.2 burst controller control/status ................................ ................................ ...................... 36 3.3 fifo transfers ................................ ................................ ................................ ................. 37 3.4 gpio/serial interface ................................ ................................ ................................ .......... 37 3.4.1 gpio ................................ ................................ ................................ ............................ 37 3.4.2 serial interface ................................ ................................ ................................ .............. 37 3.5 interrupt ................................ ................................ ................................ ............................. 38 3.5.1 internal bus/fifo timeout ................................ ................................ .............................. 38 3.5.2 address error interrupt ................................ ................................ ................................ ... 39 3.6 memory map ................................ ................................ ................................ ....................... 39 4. i 2 c interface controller 41 4.1 features ................................ ................................ ................................ ............................. 41 4.2 block diagram ................................ ................................ ................................ ..................... 42
MB86295S v specification manual rev1.1 4.2.1 block diagram ................................ ................................ ................................ ............... 42 4.2.2 block function overview ................................ ................................ ................................ 43 4.3 example application ................................ ................................ ................................ ............ 44 4.3.1 connection diagram ................................ ................................ ................................ ...... 44 4.4 function overview ................................ ................................ ................................ ............... 45 4.4.1 start condition ................................ ................................ ................................ ............ 45 4.4.2 stop condition ................................ ................................ ................................ ............. 45 4.4.3 addressing ................................ ................................ ................................ .................... 46 4.4.4 synchronization of scl ................................ ................................ ................................ .. 46 4.4.5 arbitration ................................ ................................ ................................ ..................... 47 4.4.6 acknowledge ................................ ................................ ................................ ................. 47 4.4.7 bus error ................................ ................................ ................................ ....................... 47 4.4.8 initialize ................................ ................................ ................................ ........................ 48 4.4.9 1 - byte transfer from master to slave ................................ ................................ ................ 49 4.4.10 1 - byte transfer from slave to master ................................ ................................ .............. 50 4.4.11 recovery from bus error ................................ ................................ ............................... 51 4.5 note ................................ ................................ ................................ ................................ ... 52 5. display controller 53 5.1 overview ................................ ................................ ................................ ........................... 53 5.2 display function ................................ ................................ ................................ ................. 54 5.2.1 layer configuration ................................ ................................ ................................ ....... 54 5.2.2 overlay ................................ ................................ ................................ ........................ 55 5.2.3 display parameters ................................ ................................ ................................ ....... 57 5.2.4 display position control ................................ ................................ ................................ . 58 5.3 display color ................................ ................................ ................................ ...................... 60 5.4 cursor ................................ ................................ ................................ ............................... 61 5.4.1 cursor display function ................................ ................................ ................................ .. 61 5.4.2 cursor control ................................ ................................ ................................ ............... 61 5.5 display scan control ................................ ................................ ................................ .......... 62 5.5.1 applicable display ................................ ................................ ................................ ......... 62 5.5.2 interlace display ................................ ................................ ................................ ............ 63 5.6 video interface, ntsc/pal output ................................ ................................ ...................... 64 6. video capture 65 6.1 input formats ................................ ................................ ................................ ...................... 65 6.2 itu rbt - 656 input ................................ ................................ ................................ ............... 65 6.2.1 yuv input format ................................ ................................ ................................ ........... 65 6.2.2 synchronous con trol ................................ ................................ ................................ ..... 65 6.2.3 non - interlace transformation ................................ ................................ ......................... 66 6.2.4 area allocation ................................ ................................ ................................ ............. 66 6.3 rgb input ................................ ................................ ................................ ........................... 67 6.3.1. rgb input modes ................................ ................................ ................................ ......... 67 6.3.2. rgb input signals ................................ ................................ ................................ ........ 67 6.3.3. captured range ................................ ................................ ................................ ........... 68 6.3.4. direct input mode operation ................................ ................................ .......................... 69 6.3.5 multiplex input mode operation ................................ ................................ ...................... 69 6.3.6. even/odd field recognition ................................ ................................ ........................... 70 6.3.7. conversion operation ................................ ................................ ................................ ... 70 6.4 scaling ................................ ................................ ................................ ............................... 71 6.4.1 downscaling function ................................ ................................ ................................ ... 71 6.4.2 upscaling function ................................ ................................ ................................ ....... 71
MB86295S vi specification manual rev1.1 7. geometry engine 72 7.1 geometry pipeline ................................ ................................ ................................ .............. 72 7.1.1 processing flow ................................ ................................ ................................ ............ 72 7.1.2 model - view - projection (mvp) transformation (oc ? cc coordinate transformation) ............ 73 7.1.3 3d - 2d transformation (cc ? ndc coordinate transformation) ................................ ........... 73 7.1.4 view port transformation (ndc ? dc coordinate transformation) ................................ ...... 74 7.1.5 view volume clipping ................................ ................................ ................................ ..... 74 7.1.6 back face culling ................................ ................................ ................................ ........... 76 7.2 data format ................................ ................................ ................................ ....................... 77 7.2.1 data format ................................ ................................ ................................ .................. 77 7.3 setup engine ................................ ................................ ................................ ..................... 78 7.3.1 setup processing ................................ ................................ ................................ .......... 78 7.4 log output of device coordinates ................................ ................................ ....................... 78 7.4.1 lo g output mode ................................ ................................ ................................ ........... 78 7.4.2 log output destination address ................................ ................................ ...................... 78 8. drawing processing 79 8.1 coordinate system ................................ ................................ ................................ ............. 79 8.1.1 drawing coordinates ................................ ................................ ................................ ..... 79 8.1.2 texture coordinates ................................ ................................ ................................ ....... 80 8.1.3 frame buffer ................................ ................................ ................................ ................. 80 8.2 figure drawing ................................ ................................ ................................ ................... 81 8.2.1 drawing primitives ................................ ................................ ................................ ........ 81 8.2.2 polygon drawing function ................................ ................................ .............................. 81 8.2.3 drawing parameters ................................ ................................ ................................ ...... 82 8.2.4 anti - aliasing function ................................ ................................ ................................ ..... 83 8.3 bit map processing ................................ ................................ ................................ ............. 84 8.3.1 blt ................................ ................................ ................................ .............................. 84 8.3.2 pattern data format ................................ ................................ ................................ ....... 84 8.4 texture mapping ................................ ................................ ................................ ................. 85 8.4.1 texture size ................................ ................................ ................................ .................. 85 8.4.2 texture memory ................................ ................................ ................................ ............ 85 8.4.3 texture color ................................ ................................ ................................ ................. 85 8.4.4 texture lapping ................................ ................................ ................................ ............. 86 8.4.5 filtering ................................ ................................ ................................ ........................ 87 8.4.6 perspective correction ................................ ................................ ................................ ... 87 8.4.7 texture blending ................................ ................................ ................................ ........... 88 8.4.8 bi - linear high - speed mode ................................ ................................ ............................. 88 8.5 rendering ................................ ................................ ................................ .......................... 90 8.5.1 tiling ................................ ................................ ................................ ............................ 90 8.5.2 alpha blending ................................ ................................ ................................ .............. 90 8.5.3 logic operation ................................ ................................ ................................ ............. 91 8.5.4 hidden plane management ................................ ................................ ............................ 91 8.6 drawing attributes ................................ ................................ ................................ .............. 92 8.6.1 line drawing attributes ................................ ................................ ................................ .. 92 8.6.2 triangle drawing attributes ................................ ................................ ............................ 92 8.6.3 texture attributes ................................ ................................ ................................ .......... 92 8.6.4 blt attributes ................................ ................................ ................................ ............... 93 8.6.5 character pattern drawing attribu tes ................................ ................................ .............. 93 8.7 bold line ................................ ................................ ................................ ........................... 94 8.7.1 starting and ending points ................................ ................................ ............................. 94
MB86295S vii specification manual rev1.1 8.7.2 b roken line pattern ................................ ................................ ................................ ........ 95 8.7.3 edging ................................ ................................ ................................ ......................... 96 8.7.4 interpolation of bold line joint ................................ ................................ ......................... 96 8.8 display list ................................ ................................ ................................ .................... 97 8.8.1 overview ................................ ................................ ................................ ...................... 97 8.8.2 header format ................................ ................................ ................................ .............. 98 8.8.3 parameter format ................................ ................................ ................................ .......... 98 8.8.4 geometry command list ................................ ................................ ................................ 99 8.8.5 explanation of geometry commands ................................ ................................ ............ 102 8.9 rendering command ................................ ................................ ................................ ......... 112 8.9.1 command list ................................ ................................ ................................ .............. 112 8.9.2 details of rendering commands ................................ ................................ .................... 116 9. pci configuration registers 127 9.1 pci configuration register list ................................ ................................ ............................. 127 9.2 pci configuration registers descriptions ................................ ................................ ............ 128 10 local memory registers 131 10.1 local memory register list ................................ ................................ ................................ 131 10.1.1 host interface register list ................................ ................................ .......................... 131 10.1.2 i 2 c interface register list ................................ ................................ ............................ 133 10.1.3 graphics memory interface register list ................................ ................................ ....... 133 10.1.4 display controller register list ................................ ................................ ..................... 134 10.1.5 video capture register lis t ................................ ................................ .......................... 139 10.1.6 drawing engine register list ................................ ................................ ........................ 141 10.1.7 geometry engine register list ................................ ................................ ..................... 147 10.2 explanation of local memory registers ................................ ................................ ............ 148 10.2.1 host interface registers ................................ ................................ ............................. 149 10.2.2 i 2 c interface regist ers ................................ ................................ .............................. 162 10.2.3 graphics memory interface registers ................................ ................................ .......... 168 10.2.4 display control register ................................ ................................ .............................. 171 10.2.5 video capture registers ................................ ................................ .............................. 219 10.2.6 drawing control registers ................................ ................................ ........................... 231 10.2.7 drawing mode registers ................................ ................................ ............................. 234 10.2.8 triangle drawing registers ................................ ................................ .......................... 250 10.2.9 line drawing registers ................................ ................................ ............................... 253 10.2.10 pixel drawing registers ................................ ................................ ............................ 254 10.2.11 rectangle drawing registers ................................ ................................ ..................... 254 10.2.12 blt registers ................................ ................................ ................................ ............ 256 10.2.13 high - speed 2d line drawing registers ................................ ................................ ....... 257 10.2.14 high - speed 2d triangle drawing registers ................................ ................................ . 258 10.2.15 geometry control register ................................ ................................ ........................ 259 10.2.16 geometry mode registers ................................ ................................ ........................ 261 10.2.17 display list fifo registers ................................ ................................ ........................ 268 11. timing diagram 269 11.1 host interface ................................ ................................ ................................ ................. 269 11.1.1 pci interface ................................ ................................ ................................ ............. 269 11.1.2 eeprom timing ................................ ................................ ................................ ....... 270 11.1.3 serial interface timing ................................ ................................ ............................... 271 11.2 i 2 c interface ................................ ................................ ................................ ................... 272 11.3 graphics memory interface ................................ ................................ .............................. 273 11.3.1 timing of read access to same row address ................................ ................................ 273
MB86295S viii specification manual rev1.1 11.3.2 timing of read access to different row addresses ................................ ........................ 274 11.3.3 timing of write access to same row address ................................ ............................... 275 11.3.4 timing of write access to different row addresses ................................ ........................ 276 11.3.5 timing of read/write access to same row address ................................ ........................ 277 11.3.6 delay between actv commands ................................ ................................ ............... 278 11.3.7 delay between refresh command and next actv command ................................ ....... 2 78 11.4 display tim ing ................................ ................................ ................................ ................ 279 11.4.1 non - interlace mode ................................ ................................ ................................ ... 279 11.4.2 interlace video mode ................................ ................................ ................................ . 280 11.4.3 composite synchronous signal ................................ ................................ ................... 281 12. electrical characteristics 282 12.1 introduction ................................ ................................ ................................ .................... 282 12.2 maximum rating ................................ ................................ ................................ ............. 282 12.3 recommended operating conditions ................................ ................................ ............... 283 12.3.1 recommended operating co nditions ................................ ................................ .......... 283 12.3.2 note at power - on ................................ ................................ ................................ ...... 283 12.4 dc characteristics ................................ ................................ ................................ .......... 284 12.5 ac characteristics ................................ ................................ ................................ .......... 285 12.5.1 host interface ................................ ................................ ................................ ........... 285 12.5.2 i 2 c interface ................................ ................................ ................................ .............. 287 12.5.3 video interface ................................ ................................ ................................ .......... 288 12.5.4 graphics memory interface ................................ ................................ ........................ 289 12.5.5 pll specifications ................................ ................................ ................................ ..... 296 12.6 ac characteristics measuring conditions ................................ ................................ ......... 297 12.7 timing diagram ................................ ................................ ................................ .............. 298 12.7.1 host inter face ................................ ................................ ................................ ........... 298 12.7.2 video interface ................................ ................................ ................................ .......... 299 12.7.3 graphics memory interface ................................ ................................ ........................ 300
fujistu limited prel iminary and confiden tial MB86295S 1 specification manual rev1.1 1. general 1.1 prefac e the mb8629 5s < coral p> is a graphics controller with pci host interface. note: this device has a i 2 c interface. purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent right to use these components in an i 2 c system, provided t hat the system conforms to the i 2 c standard specification as defined by philips.
fujistu limited prel iminary an d confidential MB86295S 2 specification manual rev1.1 1. 2 features geometry engine geometry engine supports the geometry processing that is compatible**1 with orchid (mb86292). using the display list created by orchid enables drawing. heavy processing of geometric operations such as coordinates conversions or clipping performed by this device can reduce the cpu loads dramatically. **1( floating point setup command is tbd ) 2d and 3d drawing the mb86295 has a drawing function t hat is compatible with the cremson ( mb86290a ) . it can draw data using the display list created for cremson . the mb86295 also supports 3d rendering, such as texture mapping with perspective collection and gouraud shading, alpha b l ending, and anti - aliasing for drawing smooth lines. digital video capture the digital video capture function can store digital video data such as tv in graphics memory; it can display drawn images and video images on the same screen. display controller the mb86295 has a display con troller that is compatible with orchid . in addition to the traditional xga (1024 768 pixels) display, 4 - layer overlay, left/right split display, wrap - around scrolling, double buffers, and translucent display, function of 6 - layer overlay, 4 - siding for pal ette are expanded. host cpu interface the mb86295 has a 32 bit, 33mhz pci interface fully compliant to pci version 2.1. external memory interface sdram and fcram can be connected. optional function final device can be selected from the combination of geome try high - /low - speed version and video capture function provided / not provided. others cmos technology 0. 18 m bga256 package supply voltage:1. 8 v (internal operation) /3.3 v (i/o)
fujistu limited prel iminary and confiden tial MB86295S 3 specification manual rev1.1 1. 3 block diagram coral general block diagram is shown below: fig.1. 1 coral p block diagram ad0-31 host interface external memory controller display controller geometry engine 2d/3d rendering engine capture controller d rgb yuv/rgb pixel bus md0-31/63 ma0-14 sdram or fcram pci bus
fujistu limited prel iminary an d confidential MB86295S 4 specification manual rev1.1 1. 4 functional overview 1. 4 .1 host cpu interface supported cpu the mb8629 5 can be connected to any cpu with a 32mhz 32 - bit pci v2.1 host interface . configuration eeprom configuration supported serial interface for ext ernal device control through pci interface pci slave supports burst reads/writes of up to 8 double words (32 bytes). supports multi - burst transfers with automatic pre - fetch. pci master supports transfers of up to 2 24 - 1 double words in bursts of between 1 a nd 8 double words. supports all combinations of transfer (pci - >pci, pci - >internal, internal - >pci) host notification on burst complete and/or transfer complete optional external burst initiation control internal dma supports transfers of up to 2 24 - 1 double words in bursts of between 1 and 8 double words. interrupt vertical (frame) synchronous detection field synchronous detection external synchronous error detection drawing command error drawing command execution end burst/transfer complete
fujistu limited prel iminary and confiden tial MB86295S 5 specification manual rev1.1 1. 4 . 2 external memory interface sdram or fcram can be connected. 64 bits or 32 bits can be selected for data bus. max. 133 mhz is available for operating frequency. connectable memory configuration is as shown below. external memory configuration type data bus width use count total capacity fcram 16 m b it s (x 3 2 bit s ) 32 bit s 2 4 m bytes fcram 16 mbit s (x32 bit s ) 64 bit s 4 8 m bytes sdram 64 mbit s (x32 bit s ) 32 bit s 1 8 m bytes sdram 64 mbit s (x32 bit s ) 64 bit s 2 16 m bytes sdram 64 mbit s (x16 bit s ) 32 bit s 2 16 m bytes sd ram 64 mbit s (x16 bit s ) 64 bit s 4 32 m bytes sdram 128 mbit s (x32 bit s ) 32 bit s 1 16 m bytes sdram 128 mbit s (x32 bit s ) 64 bit s 2 32 m bytes sdram 128 mbit s (x16 bit s ) 32 bit s 2 32 m bytes sdram 128 mbit s (x16 bit s ) 64 bit s 4 64 m bytes sdram 256 mbit s (x1 6 bit s ) 32 bit s 2 64 m bytes
fujistu limited prel iminary an d confidential MB86295S 6 specification manual rev1.1 1. 4 . 3 display c ontroller video data output each 6 - /8 - bit digital video output is provided. when selecting each 8 bits output, usable external memory bus width is 32 bits only. screen resolution lcd panels with wide range of resolutions are supported by using a programmable timing generator as follows: screen resolutions resolution s 1024 768 1024 600 800 600 854 480 640 480 480 234 400 234 320 234 hardware cursor mb8629 x supports two hardware cursor functions. each of these hardware cursors is specified as a 64 64 - pixel area. each pixel of these hardware cursors is 8 bits and uses the same look - up table as indirect color mode . double buffer method double buffer method in which drawing window and d isplay window is switched in units of 1 frame enables the smooth animation. flipping (switching of display window area) is performed in synchronization with the vertical blanking period using program. scroll method independent setting of drawing and displa y windows and their starting position enables the smooth scrolling. display colors supports indirect color mode which uses the look - up table (color pale t t e ) in 8 bits/pixels. entry for look - up table (color palette) corresponds to color code for 8 bits, in other words, 256 . color data is each 6 bits of rgb. consequently, 256 colors can be displayed out of 260,000 colors. supports direct color mode which specifies rgb with 16 bits/pixels. supports direct color mode which specifies rgb with 24 bits/pixels.
fujistu limited prel iminary and confiden tial MB86295S 7 specification manual rev1.1 overlay compatibility mode up to four extra layers (c, w, m and b) can be displayed overlaid. the overla y position for the hardware cursors is above/below the top layer (c). the transparent mode or the blend mode can be selected for overlay. the m - and b - layers can be split into separate windows. window display can be performed for the w - layer. two palettes are provided: c - layer and m - /b - layer. the w - layer is used as the video input layer. window mode up to six screens (l0 to 5) can be displa yed overlaid. the overlay sequence of the l0 - to l5 - layers can be changed arbitrarily. the overla y position for the hardware cursors is above/below the l0 - layer. the transparent mode or the blend mode can be selected for overlay. the l5 - layer can b e used as the blend coefficient plane (8 bits/pixel). window display can be performed for all layers. four palettes corresponded to l0 to 3 are provided. the l1 - layer is used as the video input layer. background color display is supported in window display for all layers. l0, l2, l4 ( 0,0 ) l3, l5 ( hdb + 1 , 0) l1 ( wx, wy ) l0 ( l0wx, l0wy ) l2 ( l2wx, l2wy ) l1 ( l1wx, l1wy ) l5 ( l5wx, l5wy ) l4 ( l4wx, l4wy ) l3 ( l3wx, l3wy )
fujistu limited prel iminary an d confidential MB86295S 8 specification manual rev1.1 1. 4 .4 video c apture function video input the input format is either itu rbt - 656 or rgb . the 8 - bit video input pin and the external digital video decoder can be connected. video data is stored in graphics memory once an d then displayed on the screen in synchronization with the display scan. scaling a scale - up factor 1 to 2 can be used. pal or ntsc images can be displayed on a wide screen. a scale - down factor 1 to 1/32 can be used. picture - in - picture can be used to displ ay drawn images and video images on the same screen.
fujistu limited prel iminary and confiden tial MB86295S 9 specification manual rev1.1 1. 4 .5 geometry p rocessing the mb8629 5 has a geometry engine for performing the numerical operations required for graphics processing. the geometry engine uses the floating - point format for highly p recise operations. it selects the required geometry processing according to the set drawing mode and primitive type and executes processing to the final drawing. primitives point , line , line strip , independent triangle , triangle strip , triangle fan , and a rbitrary polygon are supported. mvp transformation mvp transformation setting a 4 4 transformation matrix enables transformation of a 3d model view projection. two - dimensional affine transformation is also possible. clipping clipping stops drawing of fi gures outside the window (field of view). polygons (including concave shapes) can also be clipped. culling triangles on the back are not drawn. 3d - 2d transformation this functions transforms 3d coordinates (normalization) into 2d coordinates in orthogonal or perspective projections. view port transformation this function transforms normalized 2d coordinates into drawing (device) coordinates. primitive setup this function automatically performs a variety of slope computations, etc., based on transforming ve rtex data into coordinates and prepares for rendering (setup) . log output of device coordinates the view port conversion results are output to the local memory.
fujistu limited prel iminary an d confidential MB86295S 10 specification manual rev1.1 1. 4 .6 2d d rawing 2d primitives mb8629 x can perform 2d drawing for graphics memory (drawing p lane) in direct color mode or indirect color mode. bold lines with width and broken lines can be drawn. with anti - aliasing smooth diagonal lines also can be drawn. a triangle can be tiled in a single color or 2d pattern (tiling), or mapped with a texture pattern by specifying coordinates of the 2d pattern at each vertex (texture mapping). at texture mapping, drawing/non - drawing can be set in pixel units. moreover, transparent processing can be performed using alpha blending. when drawing in single color or tiling without gouraud shading or texture mapping, high - speed 2d line and high - speed 2dtriangle can be used. only vertex coordinates are set for these primitives. high - speed 2d t riangle is also used to draw polygons. 2d primitives primitive type descri ption point plots point line draws line bold line strip (provisional name) draws continuous bold line this primitive is used when interpolating the bold line joint. triangle draws triangle high - speed 2dline draws lines compared to line, this reduce s the host cpu processing load. arbitrary polygon draws arbitrary closed polygon containing concave shapes consisting of vertices arbitrary polygon draw ing using this function , arbitrary closed polygon containing concave shapes consisting of vertices can be drawn . ( there is no restriction on the count of vertices, however, the polygon with its sides crossed are not supported. ) in this case, as a work area for drawing, polygon draw ing flag buffer is used on the graphics memory . in drawing polygon, draw t riangle for polygon drawing flag buffer using high - speed 2dtriangle. decide any vertex as a starting point to draw triangle along the periphery. it enables you to draw final polygon form in singl e color or with tiling in a draw ing frame.
fujistu limited prel iminary and confiden tial MB86295S 11 specification manual rev1.1 blt/rectangle d rawing this function draws a rectangle using logic operations . it is used to draw pattern and copy the image pattern within the drawing frame . it is also used for clearing drawing frame and z buffer . blt attributes attribute description raster operation selects two source logical operation mode transparent processing performs blt without drawing pixel consistent with the transparent color. alpha blending the alpha map and source in the memory is subjected to alpha blending and then copied to the destin ation. pattern (text) drawing this function draws a binary pattern (text) in a specified color. pattern (text) drawing attributes attribute description enlarge vertically 2 2 horizontally 2 vertically and horizontally 2 shrink vertically 1/2 1 /2 horizontally 1/2 vertically and horizontally 1/2 drawing clipping this function sets a rectang le frame in drawing frame to prohibit the drawing of the outside the frame .
fujistu limited prel iminary an d confidential MB86295S 12 specification manual rev1.1 1. 4 .7 3d d rawing 3d primitives this function draws 3d objects in drawing memo ry in the direct color mode. 3d primitives primitive description point plots 3d point line draws 3d line triangle draws 3d triangle arbitrary polygon draws arbitrary closed polygon containing concave shapes consisting of vertexes 3d drawing attribute s texture mapping with bi - linear filtering/automatic perspective correction and gouraud shading provides high - quality realistic 3d drawing. a built - in texture mapping unit performs fast pixel calculations. this unit also delivers color blending between t he shading color and texture color. hidden plane management mb8629 x supports the z buffer for hidden plane management.
fujistu limited prel iminary and confiden tial MB86295S 13 specification manual rev1.1 1. 4 .8 special e ffects anti - aliasing anti - aliasing manipulates line borders of polygons in sub - pixel units and blend the pre - drawing pix el color with color to make the jaggies be seen smooth . it is used as a functional option for 2d drawing (in direct color mode only). bold line and broken line drawing this function draws lines of a specific width and a broken line . line draw ing attribute s attribute description line width selectable from 1 to 32 pixels broken line set by 32 bit or 24 bit of broken line pattern supports the verticality of starting and ending points. supports the verticality of broken line pattern. interpolation of bold line joint supports the following modes: ( 1) broken line pattern reference address fix mode ? the same broken line pattern is kept referencing for the period of some pixels starting from the joint and the starting point for the next line. ( 2) no interpola tion supports the equalization of the width of bold lines. supports the bold line edging. not support the anti - aliasing of dashed line patterns. for a part overlaid due to connection of bold lines, natural overlay can be represented by providing depth info rmation. (z value). shading supports the shading primitive. drawing is performed to the body primitive coordinates (x, y) with an offset as a shade. at this drawing, the z buffer is used in order to differentiate between the body and shade.
fujistu limited prel iminary an d confidential MB86295S 14 specification manual rev1.1 alpha blend ing alpha blending blends two image colors to provide a transparent effect. coral supports two types of blending; blending two different colors at drawing, and blending overlay planes at display. transparent color is not used for these blending options. there are two ways of specifying alpha blending for drawing: ( 1) set a transparent coefficient to the register; the transparent coefficient is applied for transparency processing of one plane. ( 2) set a transparent coefficient for each vertex of the plane; as with gouraud shading, the transparent coefficient is linear - interpolated to perform transparent processing in pixel units. in addition to the above, the following setting s can be performed at texture mapping . w hen the most significant bit of each text ure cell is 1, drawing or transparency can be set. w hen the most significant bit of each texture cell is 0, non - drawing can be set. alpha blending type description drawing transparent ratio set in particular register while one primitive (polygon, pattern , etc.), being drawn, registered transparent ratio applied a transparent coefficient set for each vertex. a l inear - interpolated transparent coefficient applied. overlay display blends top layer pixel color with lower layer pixel color transparent coeffic ient set in particular register registered transparent coefficient applied during one frame scan shading gouraud shading can be used in the direct color mode to provide 3d object real shading and color gradation.
fujistu limited prel iminary and confiden tial MB86295S 15 specification manual rev1.1 texture mapping mb86295 supports texture mapping to map a image pattern onto the surface of plane . for 2d pattern texture mapping, mb86295 has a built - in pattern memory for a field of up to 64 64 pixels (at 16 - bit color), which performs high - speed texture mapping . the texture pattern can als o be laid out in the graphics memory. in this case, max. 4096 4096 pixels can be used. d rawing of 8 - /16 - /24 - bit direct color is supported for the texture pattern. for drawing 8 - bit direct color, only point sampling can be specified for texture interpol ation; only de - curl can be specified for the blend mode. texture mapping function description filtering point sample bi - linear filter coordinate s correction linear perspective blend de - curl modulate stencil alpha blend normal stencil stencil alpha wra p repeat cramp border 1. 4 .9 other s direct color 24 - bit direct color is supported in addition to 16 - bit direct color as a drawing input data. the 24 - bit direct color data is laid out on the memory by 32 - bit - aligned. top - left rule non - applicable mode in addition to the top - left rule applicable mode in which the triangle borders are compatible with cremson, the top - left rule non - applicable mode can be used. caution: use perspective correct mode when use texture at the top - left rule non - applicable mode. top - left rule non - applicable primitives cannot use geometry clip function. non - top - left - part ? s pixel quality is less than body. ( using approximate calculation )
fujistu limited prel iminary an d confidential MB86295S 16 specification manual rev1.1 2. pins 2.1 signals 2.1.1 signal lines fig. 2 .1 coral lp signal lines devsel pclk coral lp graphics controller testh host cpu interface bga256 a d0 - 31 cbe0 - 3 par frame trdy irdy stop idsel perr serr req xrst gnt clk s clock ckm dclko dckli hsync vsync gv r2 - 7 video output interface dispe xrgben g2 - 7 b2 - 7 cclk csync sda scl clksel0 - 1 video capture interface md0 - 63 mcas mwe mras mclki mdqm0 - 7 mclko ma0 - 14 graphics memory interface test xint burstc transc bursten eeprom0 - 4 gpio0 - 4 sbusy vi0 - 7 ri0 - 5 gi0 - 5 bi0 - 5 xre rgbclk colsel
fujistu limited prel iminary and confiden tial MB86295S 17 specification manual rev1.1 2.2 pin assignmen t 2.2.1 pin a ssignment d iagram index top view bga256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a nc comr vro comg avs xtst dact vl md60 md59 vl md57 md54 md53 md50 md46 md44 md41 md38 vs b vsyn gi3 gi0 avs aor aog aob smck cclk md61 md56 vh vl md49 md45 md42 md40 md35 md34 dqm7 c gv gi4 gi2 gi1 vref avd avd avd mst md62 md55 md52 md48 vh vl md39 md36 md33 vh dqm4 d bc de dcki vs xre comb avs vs xsm md63 md58 md51 vs md43 md47 md37 vs md32 dqm5 mras e req dcko hsyn vh vs dqm6 mcas ma12 f eck edo csyn xint ma11 mwe ma13 vh g rst vs sb vl vl ma14 ma9 ma6 h ee ecs vh vs vs ma10 ma8 ma4 j pclk edi vl tc thermal balls vl ma7 ma5 ma0 k vs gnt ben vl ma3 ma2 ma1 vl l vh ad29 ad30 ad31 in order to reduce heat, dqm2 mcko dqm0 dqm3 m ad27 vh ad28 vl please connect to gnd vs vl vs dqm1 n ad25 ad26 vs vs vs md28 md31 vh p idsl cbe3 ad24 vl md23 vl md29 mcki r ad22 ad23 vh vh md27 md21 md25 md30 t ad19 ad20 ad21 vs md16 md18 md22 md26 u ad17 ad18 vh vs vs vs vl vs vl vs vh pvd vs vl vh md10 vs vh md19 md24 v cbe2 ad16 dsel serr vh ad14 ad11 ad08 ad07 ad04 vl s csl1 md2 md5 md8 md12 md13 md15 md20 w frm irdy stop par cbe1 ad13 ad10 vh ad06 vh ad02 pvs vl csl0 md1 md4 md7 md11 md14 md17 y vs trdy perr vh ad15 ad12 ad09 cbe0 ad05 ad03 ad01 ad00 ckm clk vs md0 md3 md6 md9 vs pci interface pins memory i/f pins dac pins clock pins other host i/f pins muxed memory i/f pins disp pins capture pins test pins
fujistu limited prel iminary an d confidential MB86295S 18 specification manual rev1.1 2.2.2 pin a ssignment t able jedec number pin name i/o function b 2 gi3 input rgb input green[3]. may also be configured as gpio input. c 2 gi4 input rgb input green[4]. may also be configured as gpio input. d 3 dcki input video output interface dot clock input. e 4 vh - vddh - 3.3v power supply. b 1 vsyn i/o video output interface vertical sync output. vertical sync input in external sync mode. e 3 hsyn i/o video output interface horizontal sync output. horizontal sync input in external sync mode. d 2 de output video output interface display enable period. c 1 gv output video output interface graphics/video switch. f 3 csyn output video output interface composite sync output. e 2 dcko output video output interf ace dot clock signal for display. d 4 vs - vss - ground. g 4 vl - vddl 1.8v power supply. g 3 sb i/o host interface slave busy signal. may also be configured as gpio input/output. in addition this signal is used as rgb input green[5] and serial interfac e strobe depending on configuration. d 1 bc i/o host interface burst complete signal. may also be configured as gpio input/output. in addition this signal is used as rgb input red[0] and serial interface strobe depending on configuration. f 2 edo i/o pci configuration eeprom data output. may also be configured as gpio input/output. in addition this signal is used as rgb input red[1] and serial interface data out depending on configuration. e 1 req output pci request. f 4 xint output (open drain) externa l interrupt. by default (and pci standard) it is active low. however it may be configured as active high if desired. h 3 vh - vddh 3.3v power supply. g 2 vs - vss - ground. f 1 eck i/o pci configuration eeprom clock output. may also be configured as gpi o input/output. in addition this signal is used as rgb input red[2] and serial interface clock out depending on configuration. h 2 ecs i/o pci configuration eeprom select output. may also be configured as gpio input/output. in addition this signal is used as rgb input red[3] depending on configuration. j 4 tc i/o host interface transfer complete. may also be configured as gpio input/output. note that the state of this pin is latched at external reset to help provide initial i/o configuration. if it is in an active high state then the eeprom enable register bit is set. j 3 vl - vddl 1.8v power supply. g 1 xrst input device reset.
fujistu limited prel iminary and confiden tial MB86295S 19 specification manual rev1.1 h 4 vs - vss - ground. j 2 edi i/o pci configuration eeprom data input. may also be configured as gpio input/output. in addit ion this signal is used as rgb input red[4] and serial interface data in depending on configuration. h 1 ee i/o pci configuration eeprom enable. may also be configured as gpio input/output. in addition this signal is used as rgb input red[5] depending on configuration. k 3 ben i/o host interface burst enable used as an external trigger of the host interface burst controller. may also be configured as gpio input/output. note that the state of this pin is latched at external reset to help provide initial i/ o configuration. if it is in an active high state then the rgb input enable register bit is set. k 2 gnt output pci grant. j 1 pclk input pci clock (33mhz). k 4 vl - vddl 1.8v power supply. k 1 vs - vss - ground. l 1 vh - vddh 3.3v power supply. m 1 ad27 i/o pci address/data bit 27. l 2 ad29 i/o pci address/data bit 29. l 3 ad30 i/o pci address/data bit 30. l 4 ad31 i/o pci address/data bit 31. n 1 ad25 i/o pci address/data bit 25. m 2 vh - vddh 3.3v power supply. n 4 vs - vss - ground. p 1 ids l input pci initialisation device select (idsel). m 3 ad28 i/o pci address/data bit 28. m 4 vl - vddl 1.8v power supply. n 2 ad26 i/o pci address/data bit 26. r 1 ad22 i/o pci address/data bit 22. p 2 cbe3 i/o pci command/byte enable 3. n 3 vs - vss - ground. r 4 vh - vddh 3.3v power supply. t 1 ad19 i/o pci address/data bit 19. r 2 ad23 i/o pci address/data bit 23. p 3 ad24 i/o pci address/data bit 24. u 1 ad17 i/o pci address/data bit 17. p 4 vl - vddl 1.8v power supply. y 1 vs - vss - ground . t 2 ad20 i/o pci address/data bit 20. r 3 vh - vddh 3.3v power supply. v 1 cbe2 i/o pci command/byte enable 2. u 2 ad18 i/o pci address/data bit 18. t 3 ad21 i/o pci address/data bit 21. w 1 frm i/o pci frame. t 4 vs - vss - ground. v 2 ad16 i/o pci address/data bit 16.
fujistu limited prel iminary an d confidential MB86295S 20 specification manual rev1.1 u 3 vh - vddh 3.3v power supply. v 3 dsel i/o pci device select (devsel). w 2 irdy i/o pci initiator ready. w 3 stop i/o pci stop. v 4 serr output (open drain) pci system error. u 5 vs - vss - ground. y 2 trdy i/o pci target ready. v 5 vh - vddh 3.3v power supply. w 4 par i/o pci parity. y 3 perr i/o pci parity error. v 6 ad14 i/o pci address/data bit 14. w 5 cbe1 i/o pci command/byte enable 1. u 4 vs - vss - ground. u 7 vl - vddl 1.8v power supply. v 7 ad11 i/o pci a ddress/data bit 11. y 4 vh - vddh 3.3v power supply. w 6 ad13 i/o pci address/data bit 13. y 5 ad15 i/o pci address/data bit 15. u 6 vs - vss - ground. v 8 ad08 i/o pci address/data bit 8. w 7 ad10 i/o pci address/data bit 10. y 6 ad12 i/o pci addre ss/data bit 12. w 8 vh - vddh 3.3v power supply. u 9 vl - vddl 1.8v power supply. v 9 ad07 i/o pci address/data bit 7. y 7 ad09 i/o pci address/data bit 9. u 8 vs - vss - ground. w 9 ad06 i/o pci address/data bit 6. y 8 cbe0 i/o pci command/byte ena ble 0. v 10 ad04 i/o pci address/data bit 4. w 10 vh - vddh 3.3v power supply. y 9 ad05 i/o pci address/data bit 5. u 10 vs - vss - ground. y 10 ad03 i/o pci address/data bit 3. y 11 ad01 i/o pci address/data bit 1. y 12 ad00 i/o pci address/data bi t 0. w 11 ad02 i/o pci address/data bit 2. v 11 vl - vddl 1.8v power supply. u 11 vh - vddh 3.3v power supply. y 13 ckm input clock mode. if low then the output from the internal pll is used as the internal clock. if high then the pci clock is used. w 12 pvs - pll ground. u 13 vs - vss - ground. y 14 clk input clock input. v 12 s input pll reset. u 12 pvd - pll 1.8v power supply. w 13 vl - vddl 1.8v power supply.
fujistu limited prel iminary and confiden tial MB86295S 21 specification manual rev1.1 y 15 vs - vss - ground. w 14 csl0 input clock rate selection 0. v 13 csl1 input cl ock rate selection 1. u 15 vh - vddh 3.3v power supply. y 16 md0 i/o graphics memory data bit 0. w 15 md1 i/o graphics memory data bit 1. v 14 md2 i/o graphics memory data bit 2. y 17 md3 i/o graphics memory data bit 3. u 14 vl - vddl 1.8v power supp ly. y 20 vs - vss ? ground. w 16 md4 i/o graphics memory data bit 4. v 15 md5 i/o graphics memory data bit 5. y 18 md6 i/o graphics memory data bit 6. w 17 md7 i/o graphics memory data bit 7. v 16 md8 i/o graphics memory data bit 8. y 19 md9 i/o gra phics memory data bit 9. u 16 md10 i/o graphics memory data bit 10. w 18 md11 i/o graphics memory data bit 11. v 17 md12 i/o graphics memory data bit 12. v 18 md13 i/o graphics memory data bit 13. w 19 md14 i/o graphics memory data bit 14. v 19 md15 i/o graphics memory data bit 15. u 18 vh - vddh 3.3v power supply. t 17 md16 i/o graphics memory data bit 16. w 20 md17 i/o graphics memory data bit 17. t 18 md18 i/o graphics memory data bit 18. u 19 md19 i/o graphics memory data bit 19. v 20 md20 i /o graphics memory data bit 20. r 18 md21 i/o graphics memory data bit 21. t 19 md22 i/o graphics memory data bit 22. u 17 vs - vss - ground. p 17 md23 i/o graphics memory data bit 23. p 18 vl - vddl 1.8v power supply. u 20 md24 i/o graphics memory d ata bit 24. r 19 md25 i/o graphics memory data bit 25. t 20 md26 i/o graphics memory data bit 26. r 17 md27 i/o graphics memory data bit 27. n 18 md28 i/o graphics memory data bit 28. p 19 md29 i/o graphics memory data bit 29. r 20 md30 i/o graphics memory data bit 30. n 19 md31 i/o graphics memory data bit 31. m 17 vs - vss - ground. m 18 vl - vddl 1.8v power supply. p 20 mcki input graphics memory clock input. n 17 vs - vss - ground. m 19 vs - vss - ground. n 20 vh - vddh 3.3v power supply. l 18 mcko output graphics memory clock output.
fujistu limited prel iminary an d confidential MB86295S 22 specification manual rev1.1 l 19 dqm0 output graphics memory data mask 0. m 20 dqm1 output graphics memory data mask 1. l 17 dqm2 output graphics memory data mask 2. l 20 dqm3 output graphics memory data mask 3. k 20 vl - vddl 1.8v power supply. j 20 ma0 output graphics memory address bit 0. k 19 ma1 output graphics memory address bit 1. k 18 ma2 output graphics memory address bit 2. k 17 ma3 output graphics memory address bit 3. h 20 ma4 output graphics memory address bit 4. j 19 ma5 output graphics memory address bit 5. h 17 vs - vss - ground. g 20 ma6 output graphics memory address bit 6. j 18 ma7 output graphics memory address bit 7. j 17 vl - vddl 1.8v power supply. h 19 ma8 output graphics memory address bit 8. f 20 vh - vddh 3.3v power supply. g 19 ma9 output graphics memory address bit 9. h 18 ma10 output graphics memory address bit 10. f 17 ma11 output graphics memory address bit 11. e 20 ma12 output graphics memory address bit 12. f 19 ma13 output graphics me mory address bit 13. g 18 ma14 output graphics memory address bit 14. d 20 mras output graphics memory row address strobe. g 17 vl - vddl 1.8v power supply. a 20 vs - vss - ground. e 19 mcas output graphics memory column address strobe. f 18 mwe outp ut graphics memory write enable. c 20 dqm4 output graphics memory data mask 4. d 19 dqm5 output graphics memory data mask 5. e 18 dqm6 output graphics memory data mask 6. may also be configured as blue[0] for the rgb output. b 20 dqm7 output graphics m emory data mask 7. may also be configured as blue[1] for the rgb output. e 17 vs - vss - ground. c 19 vh - vddh 3.3v power supply. d 18 md32 i/o graphics memory data bit 32. may also be configured as blue[2] for the rgb output. c 18 md33 i/o graphics m emory data bit 32. may also be configured as blue[3] for the rgb output. b 19 md34 i/o graphics memory data bit 32. may also be configured as blue[4] for the rgb output. b 18 md35 i/o graphics memory data bit 32. may also be configured as blue[5] for the rgb output. c 17 md36 i/o graphics memory data bit 32. may also be configured as blue[6] for the rgb output. d 16 md37 i/o graphics memory data bit 32. may also be configured as blue[7] for the rgb output. a 19 md38 i/o graphics memory data bit 32. may also be configured as green[0] for the rgb output.
fujistu limited prel iminary and confiden tial MB86295S 23 specification manual rev1.1 c 16 md39 i/o graphics memory data bit 32. may also be configured as green[1] for the rgb output. b 17 md40 i/o graphics memory data bit 32. may also be configured as green[2] for the rgb output. a 18 md41 i/o graphics memory data bit 32. may also be configured as green[3] for the rgb output. c 15 vl - vddl 1.8v power supply. b 16 md42 i/o graphics memory data bit 32. may also be configured as green[4] for the rgb output. d 17 vs - vss - ground. d 1 4 md43 i/o graphics memory data bit 32. may also be configured as green[5] for the rgb output. c 14 vh - vddh 3.3v power supply. a 17 md44 i/o graphics memory data bit 32. may also be configured as green[6] for the rgb output. b 15 md45 i/o graphics mem ory data bit 32. may also be configured as green[7] for the rgb output. a 16 md46 i/o graphics memory data bit 32. may also be configured as red[0] for the rgb output.r0 d 15 md47 i/o graphics memory data bit 32. may also be configured as red[1] for the rgb output.r1 c 13 md48 i/o graphics memory data bit 32. may also be configured as red[2] for the rgb output.r2 b 14 md49 i/o graphics memory data bit 32. may also be configured as red[3] for the rgb output.r3 a 15 md50 i/o graphics memory data bit 32. may also be configured as red[4] for the rgb output.r4 b 13 vl - vddl 1.8v power supply. d 12 md51 i/o graphics memory data bit 51. may also be configured as red[5] for the rgb output.r5 c 12 md52 i/o graphics memory data bit 52. may also be configured as red[6] for the rgb output.r6 a 14 md53 i/o graphics memory data bit 53. may also be configured as red[7] for the rgb output. r7 d 13 vs - vss - ground. b 12 vh - vddh 3.3v power supply. a 13 md54 i/o graphics memory data bit 54. may also be configu red as i 2 c serial data (sda). c 11 md55 i/o graphics memory data bit 55. may also be configured as i 2 c serial clock (scl). b 11 md56 i/o graphics memory data bit 56. may also be configured as itu - rbt - 656 video capture data input bit 0 (vi0). when the rgb input is enabled this pin acts as blue[0]. a 12 md57 i/o graphics memory data bit 57. may also be configured as itu - rbt - 656 video capture data input bit 1 (vi1). when the rgb input is enabled this pin acts as blue[1]. d 11 md58 i/o graphics memory data bit 58. may also be configured as itu - rbt - 656 video capture data input bit 2 (vi2). when the rgb input is enabled this pin acts as blue[2].
fujistu limited prel iminary an d confidential MB86295S 24 specification manual rev1.1 a 11 vl - vddl 1.8v power supply. a 10 md59 i/o graphics memory data bit 59. may also be configured as itu - rbt - 656 video capture data input bit 3 (vi3). when the rgb input is enabled this pin acts as blue[3]. a 9 md60 i/o graphics memory data bit 60. may also be configured as itu - rbt - 656 video capture data input bit 4 (vi4). when the rgb input is enabled this pin act s as blue[4]. b 10 md61 i/o graphics memory data bit 61. may also be configured as itu - rbt - 656 video capture data input bit 5 (vi5). when the rgb input is enabled this pin acts as blue[5]. c 10 md62 i/o graphics memory data bit 62. may also be configured as itu - rbt - 656 video capture data input bit 6 (vi6). when the rgb input is enabled this pin acts as hsync. d 10 md63 i/o graphics memory data bit 63. may also be configured as itu - rbt - 656 video capture data input bit 7 (vi7). when the rgb input is enable d this pin acts as vsync. a 8 vl - vddl 1.8v power supply. b 9 cclk input itu - rbt - 656 video capture clock input. d 8 vs - vss - ground. a 7 dact input test signal. c 9 mst input test signal. d 9 xsm input test signal. b 8 smck input test signal. a 6 xtst input test signal. b 7 aob output analog signal (b) output c 8 avd2 - analog power supply(3.3v) d 6 comb output analog b signal compensation pin a 5 avs2 - analog ground b 6 aog output analog singnal (g) output c 7 avd1 - analog power supply(3 .3v) a 4 comg output analog g signal compensation pin d 7 avs1 - analog ground a 1 nc - not connected. b 5 aor output analog singnal (r) output c 6 avd0 - analog power supply(3.3v) a 3 vro output analog reference current output b 4 avs0 - analog gro und c 5 vref input analog reference voltage input a 2 comr output analog r signal compensation pin d 5 xre input rgb output/video input/i 2 c enable. b 3 gi0 gi0 rgb input green[0]. may also be configured as gpio input. c 4 gi1 gi1 rgb input green[1]. m ay also be configured as gpio input. c 3 gi2 gi2 rgb input green[2]. may also be configured as gpio input.
fujistu limited prel iminary and confiden tial MB86295S 25 specification manual rev1.1 notes v ss /pllv ss : ground v ddh : 3.3 - v power supply v ddl /pllv dd : 1. 8 - v power supply pllv dd : pll power supply (1.8 v) open : do not connect anything. testh : input a 3.3 v - power supply . avs : analog ground avd : analog power supply (3.3 v) - it is recommended that pllv dd should be isolated on the pcb. - it is recommended that avd should be isolated on the pcb. - insert a bypass capacitor with good high frequency characteristics between the power supply and ground. place the capacitor as near as possible to the pin.
fujistu limited prel iminary an d confidential MB86295S 26 specification manual rev1.1 2.3 pin function 2.3.1 host cpu i nterfa ce table 2 - 1 host cpu interface pins pin name i/o description ad0 - 31 in/out pci address/data cbe0 - 3 in/out pci bus command/byte enable par in/out pci parity frm in/out pci cycle frame trdy in/out pci target ready irdy in/out pci initiator ready sto p in/out pci stop dsel in/out pci device select idsel input pci initialisation device select perr in/out pci parity error serr output (open drain) system error req output pci bus master request gnt input pci bus grant pclk input pci clock ? 33mhz x rst input system reset (including pci) xint output (open drain) interrupt bc output burst complete. indicates a burst is complete when using the dma/burst controller. this pin may also be configured as a gpio input/output and acts as ri0 (red input 0) wh en the rgb input is enabled. tc output transfer complete. indicates that a whole transfer is complete when using the dma/burst controller. this may also be configured as a gpio input/output. in addition this pin may be used to automatically enable the eep rom at the reset phase. to do this a pull up should be applied. ben input enables the burst controller to start/continue execution. this pin may also be configured as a gpio input/output. in addition this pin may be used to automatically enable the rgb in put pins as rgb inputs. to do this a pull up should be applied. sb output slave busy. indicates that the pci slave is busy completing a write transfer. this pin may also be configured as a gpio input/output, the serial interface strobe output and acts as gi5 (green input 5) when the rgb input is enabled.
fujistu limited prel iminary and confiden tial MB86295S 27 specification manual rev1.1 ee input eeprom enable. enables the pci eeprom configuration. this pin may also be configured as a gpio input/output and acts as ri5 (red input 5) when the rgb input is enabled. ecs output eeprom chip s elect . this pin may also be configured as a gpio input/output and acts as ri3 (red input 3) when the rgb input is enabled. eck output eeprom clock. this pin may also be configured as a gpio input/output, the serial interface data input and acts as ri2 (r ed input 2) when the rgb input is enabled. edo output eeprom data out. this pin may also be configured as a gpio input/output, the serial interface data output and acts as ri1 (red input 1) when the rgb input is enabled. edi input eeprom data in. this pi n may also be configured as a gpio input/output, the serial interface data input and acts as ri4 (red input 4) when the rgb input is enabled. gi0 - 4 input gpio inputs. these pins also act as gi0 - 4 (green inputs 0 - 4) when the rgb input is enabled. the ee, eck, ecs, edo, edi, bc, tc, sb and ben signals can all be configured as gpio inputs/outputs and default to gpio inputs at reset unless otherwise specified by the reset control pins (tc, ben) which can be used to enable the eeprom or the rgb input. the gi0 - 4 signals can be gpio inputs only, which is their default state unless the rgb input is enabled in which case they are used as green[0 - 4]. the host interface also has a serial interface function built in. this uses the edi/edo signals as data in/out, the eck pin as a serial clock output and the sb pin as a strobe output. the serial interface may only be used when neither the eeprom nor the rgb input is in use. once the device has been reset all configuration of the host interface related pins is done using the io mode register (iom). note that to enable the rgb input the xre signal must be active low and also the appropriate register in the capture engine must be configured.
fujistu limited prel iminary an d confidential MB86295S 28 specification manual rev1.1 2.3.2 video output i nterface table 2 - 2 video output interface pins pin name i/o description dcko output dot clock signal for display dcki input dot clock signal input hsyn i/o horizontal sync signal output horizontal sync input < in external sync mode > vsyn i/o vertical sync signal output vertical sync input < in external sync mode > csyn output composite sync signal output de output display enable period signal gv output graphics/video switch r 7 - 0 output d i gital picture (r) output . . these pins are multiplexed md53 - 46. these pins are available when xre=0. g 7 - 0 output d i gital pi cture (g) output . . these pins are multiplexed md45 - 38. these pins are available when xre=0. b 7 - 0 output d i gital picture (b) output . these pins are multiplexed md37 - 32 and dqm7 - 6. these pins are available when xre=0. xre input signal to switch between digital rgb output, capture signals /memory bus (md 63 - 32, dqm7 - 6) aor analog output analog signal (r) output aog analog output analog signal ( g ) output aob analog output analog signal ( b ) output comr analog analog (r) compensation output comg analog analog (g) compensation output comb analog analog (b) compensation output vref analog analog voltage reference input vro analog analog reference current output it is possible to output digital rgb when xre = 0 (memory bus = 32bit). additional setting of external circuits can generate composite video signal . synchronous to external video signal display can be performed. either mode which is synchronous to dclki signal or one which is synchronous to dot clock, as for normal display can be selected. sinc e hsync and vsync signals are set to input state after reset , these signals must be pulled up lsi externally. the gv signal switches graphics and video at chroma key operation. when video is selected, the ?l ow ? level is output. aor, aog and aob must be te rminated at 75 ohm. 1.1 v is input to vref. a bypass capacitor ( with good high - frequency characteristics ) must be inserted between vref and avs. comr, comg and comb are tied to analog vdd via 0.1 uf ceramic capacitors. vro must be pulled down to analog g round by a 2.7 k ohm resister.
fujistu limited prel iminary and confiden tial MB86295S 29 specification manual rev1.1 2.3.3 video c apture i nterface 1 . itu - 656 input signals table 2 - 3 video c apture interface pin s pin name i/o description cclk input digital video input clock signal input vi 7 - 0 input itu656 digital video data input . the se pins are multiplexed md63 - md56. inputs itu - rbt - 656 format digital video signal digital video data input can be used only when the xre pin is ? 0 ? . md63 - md56 are assigned as the digital video data input pins. when video capture is not used and the xre pin is 0, input the ?h igh ? level to md63 - md56. 2. rgb input signals the signals used for video capture are not assigned on dedicated pins but share the same pins with other functions. there is a set of signals corresponding to the rgb capture modes. (1) direct input mode name io function rgbclk in clock for rgb input. this pin is multiplexed cclk. ri5 - 0 in red component value. these pins are multiplexed ee, edi, ecs, eck, edo and bc. gi5 - 0 in green component value. these pins are multiplexed sb and gp i4 - gpi0. bi5 - 0 in blue component value. these pins are multiplexed md61 - md56. vsynci in vertical sync for rgb capture. this pin is multiplexed md63. hsynci in horizontal sync for rgb capture. this pin is multiplexed md63. note : - the rgb bit of vcm (video capture mode) register enables rgb input mode of video capture.
fujistu limited prel iminary an d confidential MB86295S 30 specification manual rev1.1 2.3. 4 i 2 c i nterface pin name i/o description sda i/o i 2 c or video capture test signal. this pin is multiplexed md54. scl i/o i 2 c or video capture test signal. this pin is multipl exed md55. i 2 c interface signals can be used only when the xre pin is ? 0 ? . md55 - md54 are assigned as the i 2 c interface pins. when i 2 c interface is not used and the xre pin is 0, input the ?h igh ? level to md63 - md56. note) input voltage level is 3.3 v. please be careful, it does not support to 5v input. (the device whose output voltage is 5v is not connectable.)
fujistu limited prel iminary and confiden tial MB86295S 31 specification manual rev1.1 2.3. 5 graphics memory interface graphics memory interface pins pin name i/o description md31 - md0 i/o graphics memory bus data md53 - md32 i/o graphics memory bus data or digital r7 - 0, g7 - 0, b7 - 2 output (when xre = 0) md55 - md54 i/o graphics memory bus data or scl, sda (when xre=0) md63 - md56 i/o graphics memory bus data or video input (when xre=0) ma0 to 14 output graphics memory b us data mras output row address strobe mcas output column address strobe mwe output write enable dqm5 - dqm0 output data mask dqm7 - dqm6 output data mask or digital b1 - 0 output (when xre = 0) mclk0 output graphics memory clock output mclk1 input gr aphics memory clock input connect the interface to the external memory used as memory for image data. the interface can be connected to 64 - /128 - /256 - mbit sd ram ( 16 - or 32 - bit length data bus ) without using any external circuit. 64 bits or 32 bits can b e selected for the memory bus data. . connect mclki to mclk0. when xre is fixed at ? 1 ? , md63 - md32 and dqm7 - dqm6 can be used as graphics memory interface. when xre is fixed at ? 0 ? , these signals can be used as digital rgb output and digital video data input.
fujistu limited prel iminary an d confidential MB86295S 32 specification manual rev1.1 2.3. 6 clock input table 2 - 4 clock input pin s pin name i/o description clk input clock input signal s input pll reset signal ckm input clock mode signal csl [1:0] input clock rate select signal inputs source clock for internal operation cloc k and display dot clock. normally, 4 fsc (= 14.31818 mhz: ntsc) is input. an internal pll generates the internal operation clock of 166 mhz/133 mhz and the display base clock of 4 00 mhz. ckm clock mode l output from internal pll selected h pci bus clo ck selected when ckm = l, selects input clock frequency when built - in pll used according to setting of csl pins csl1 csl 0 input clock frequency multiplication rate display reference clock l l inputs 13.5 - mhz clock frequency 29 391.5 mhz l h inputs 14.32 - mhz clock frequency 28 400.96 mhz h l inputs 17.73 - mhz clock frequency 22 390.06 mhz h h reserved
fujistu limited prel iminary and confiden tial MB86295S 33 specification manual rev1.1 2.3.7 test pin s table 2 - 5 test pin s pin name i/o description testh input input 3.3 - v power. 2.3.8 reset sequence see section 10.3.2 . 2 .3.9 how to switch internal operating frequency switch the operating frequency immediately after a reset (before rewriting mmr mode register of external memory interface). any operating frequency can be selected from the five combinations shown in table 2 - 6 . table 2 - 6 frequency setting combinations clock for geometry engine clock for other than geometry engine 166 mhz 133 mhz 166 mhz 100 mhz 133 mhz 133 mhz 133 mhz 100 mhz 100 mhz 100 mhz the following relationship is disabled: clock for geometry e ngine < clock for other than geometry engine
fujistu limited prel iminary an d confidential MB86295S 34 specification manual rev1.1 3. host interface the coral lp has a 33mhz, 32 - bit pci host interface compliant to pci version 2.1. it includes both pci master and pci slave functions and an internal dma/burst controller for multi - burst transfers of large quantities of data between all combinations of pci data space and coral lp internal data space. pci eeprom configuration is also supported. additional functions provided by the host interface are optional host interface status/control signals whi ch may aid in the reduction of pci retries, the provision of general purpose io (gpio) signals for control of external devices via the pci interface including support for a simple serial interface. 3.1 standard pci slave accesses an external pci master will a ccess the coral lp as a pci slave. 3 .1.1 pci slave write for a pci slave write, data will be ?posted? into a temporary buffer from where it is written to the target internal client. this temporary buffer is 8 dwords deep. pci slave writes of any size are supported but typically a retry will occur after each 8 dword burst. note that when writing to the display list fifo a burst should be no more than 16 dwords (64 bytes) due to fifo address space limitations. when the write from the temporary buffer to the internal client is being performed the slave busy (sb) signal becomes active. while this is happening pci accesses will be rejected. if the sb signal is used then pci retries may be reduced. 3 .1.2 pci slave read for a pci slave read the read requested wil l be passed to an internal client from where data will be fetched into the temporary buffer (8 dwords deep). typically a retry will occur to actually fetch the data. in order to fetch the correct number of words from the read address the burst size must be specified. this is done by writing to the slave burst read size (srbs) register. bursts of between 1 and 8 dwords are supported. if the pci master retries and reads less than the specified burst size then the remaining dwords will be discarded. this means that the slave burst read size can be permanently configured as 8 dwords. however there will be an increased latency on the pre - fetch stage if this is done. 3.2 burst controller accesses (including pci master) the coral lp host interface includes a burst con troller which can be used for transferring large quantities of contiguous data between all combinations (source/destination) of pci data space and coral lp internal data space. control/status monitoring is done through internal registers with the optional aid of external signals ? burst complete (bc), transfer complete (tc) and burst enable (ben). a transfer can be any number of dwords from 1 to 16777215 (2 24 - 1) dwords, split up into a number of individual bursts of size from 1 to 8 dwords. if the transfer size is not an integer multiple of the burst size then the final burst of the transfer will be less than the configured burst size. a transfer is from a source address to a destination address with the source/destination being in either pci or coral lp dat a space as appropriate to the transfer mode. after each burst of a transfer the source and/or the destination address may be incremented (or not) by the burst size enabling transfers both to/from
fujistu limited prel iminary and confiden tial MB86295S 35 specification manual rev1.1 memory and also fifo - like sources/destinations. note that wh en writing to the display list fifo, the destination address should be configured to not increment between bursts. 3.2.1 transfer modes there are 6 transfer modes configurable through the burst setup register (bsr). these are: mode function 000b slave mode pci to coral lp. in this mode a pci master writes bursts of data directly into a temporary buffer from where it is transferred to the destination address by the burst controller. while this can also be accomplished using simple pci slave writes there are bene fits in using this mode when transferring large quantities of data. for a normal pci write the coral lp pci slave interface is blocked until the write to the destination address has completed. depending on the destination there may be some delay in doing t his. using the burst controller the data is transferred out of the pci interface into the temporary buffer from where it is transferred to the destination. in this case the pci slave interface is quickly cleared and so other operations can take place or th e next burst can be written in. 001b slave mode coral lp to pci. in this mode the burst controller reads data from a coral lp internal address into its temporary buffer and then waits for the data to be read using a pci slave read from this buffer?s addre ss. while this can also be accomplished using simple pci slave reads there are benefits in using this mode when transferring large quantities of data. a normal pci read will typically be accomplished by a pci read request followed by a retry to fetch the d ata. using this mode the burst controller can be used to automatically fetch the next data to be read. depending on internal latencies this should reduce the number of retries. 010b coral lp to coral lp. in this mode data is read from a source address int ernal to coral lp into a temporary buffer, from where it is written to a destination, also internal to coral lp. an example of where this mode may be used is to transfer display list data from graphics memory to the display list fifo. 011b reserved. 100b pci to coral lp (pci master read). in this mode the source address is in pci data space and the destination address internal to coral lp. for each burst of the transfer ?burst size? dwords of data are read as a pci master read into a temporary buffer, fro m where they are written to the internal destination address. an example of where this mode will be used is display list transfer to the fifo/graphics memory. 101b coral lp to pci (pci master write). in this mode the source address is internal to coral lp and the destination address is in pci data space. for each burst of the transfer ?burst size? dwords of data are fetched from an internal address into a temporary buffer, from where they are written to the destination address using a pci master write. an example of where this mode may be used is to transfer graphics memory data to external pci memory. 110b pci to pci (pci master read/write). this mode is effectively a pci to pci dma. data is read from a source address in pci data space into a temporary bu ffer from where it is written to the destination address, also in pci data space. 111b reserved.
fujistu limited prel iminary an d confidential MB86295S 36 specification manual rev1.1 the figure below illustrates a pci to coral (master read) transfer. the host cpu will program up the bcu registers (using normal pci slave writes) and tr igger the transfer. the coral then reads data from the source memory as a pci master and writes to the destination inside the coral. all other bcu transfers use the bcu ram in a similar way but with source/destination dependent on transfer type. 3.2.2 burst con troller control/status all setup/control and status for the burst controller can be done through registers. these provide ways of specifying the parameters for a burst (source/destination address, address increment (or not) and burst/transfer size. in addi tion, a transfer can be started/paused/aborted and also its progress monitored using the enable and status registers. the key status indicators are burst complete and transfer complete, which become active at the end of each burst/transfer respectively. th ese may either be active high or toggle state at the end of each burst/transfer. when active high they will have to be cleared after each burst/transfer. this may be done using a clear on read mode (default) or by manually writing to the appropriate regist er. the burst/transfer complete indications are also available though the main interrupt status register (ist) and can trigger the main external interrupt (xint). if being used for this they must be configured as active high (ie. not toggle mode). in addit ion burst/transfer complete can be made available as external signals (bc/tc) for connection directly to an external device (eg. through some form of gpio or interrupt). normally a transfer will be configured and enabled using internal registers. however i t is possible to configure the transfer but not actually start it. an external signal (ben) can then be used to trigger the transfer and pause it between bursts. this may be useful, for example, when doing pci master reads from a client which takes time to pre - fetch more data for the next burst. coral lp host cpu (pci master) memory (pci slave) bcu ram 1) slave write to setup transfer 2) master read from source 3) onward transfer to destination pci bus internal bus
fujistu limited prel iminary and confiden tial MB86295S 37 specification manual rev1.1 3.3 fifo transfers unlike coral lq/coral lb there are no specific transfer mechanisms to write data into the display list fifo. a write to the fifo interface occurs automatically when it is specified as a destination a ddress either for a pci slave write or in a burst controller transfer. if this is not desired, and the main internal bus should be used, then the override fifo use register may be set. under normal circumstances there should be no need to use this feature. as previously stated when the fifo address is specified as the destination in the burst controller the destination should not be incremented after each burst. this will not happen automatically and must be specifically configured. in addition when writing to the fifo using a pci slave write the fifo address space is limited to 16 dwords (64 bytes). this means that a pci slave write burst to the fifo must not be more than 16 dwords, otherwise data will be written to invalid locations for retries after 2 bur sts of 8 dwords. in normal mode when writing to the fifo, data is written to the geometry engine fifo from where it is transferred either directly to the draw engine fifo or to the geometry engine, depending on the command. if the geometry engine is not in use then a direct write to the draw engine fifo can be accomplished by setting cremson mode (cm register). when the burst controller is used to transfer data to the fifo the rate of bursts us controlled using the current fifo status. when the fifo is near ly full the next burst will not occur until data is processed by the geometry/draw engine. this guarantees that there will always be space for the next burst of data. if this feature is not required then it can be disabled using the fifo burst mode (fbm) r egister. 3.4 gpio/serial interface the host interface supports optional register mapped general purpose io (gpio) and serial interface functions. 3.4.1 gpio depending on configuration there are up to 14 gpio signals. 5 of these (gi0, gi1, gi2, gi3, gi4) are inputs only. the remainder (ben,sb,tc,bc,ee,ecs,eck,edi, edo) may be either input or output. all reset to gpio inputs unless otherwise configured using the reset configuration mechanism to enable the eeprom/rgb input. operation of the gpio is simply th rough the reading of the gpio data (gd) register for gpio inputs and writing to this register (with write mask) for the gpio outputs. gpio inputs may be configured selectively to trigger an external interrupt (via the interrupt status register (ist)) when they change state (0 - >1 or 1 - >0 transition). 3.4.2 serial interface a simple serial interface is available depending on configuration. this uses the edi/edo pins as serial data input/output, the eck as the serial clock output and sb as the serial interface strobe. the serial data out signal may be tri - stated when not in use. up to 8 bits of data is shifted out/in based on the serial clock. this may be 1 / 16 , 1 / 32 , 1 / 64 or 1 / 128 of the main internal clock. the clock polarity may be specified to be high/low an d it may be gated when the serial interface is inactive.
fujistu limited prel iminary an d confidential MB86295S 38 specification manual rev1.1 the strobe signal has configurable polarity and may be active only for the first cycle of a transfer or the complete transfer. it may also be disabled completely. configured strobe settings may be ov erridden on a transfer by transfer basis if required. an interrupt may be generated when a transfer is complete. 3 . 5 interrupt the coral lp mb8629 5 issues interrupt requests to the host cpu. the following interrupt triggers may enabled/disabled using the interrupt mask register (imask). vertical synchronization detect field synchronization detect external synchronization error detect drawing command error drawing command execution end internal bus/fifo timeout serial interface transfer complete gpio inpu t change burst complete transfer complete host interface fatal (pci error) address error (invalid address accessed) in addition the i 2 c interface can trigger an interrupt, but this is non - maskable through the imask register. by default the external interru pt is active low (pci standard) and is open drain. if required it may be configured to be active high using the interrupt polarity (ip) register. once an interrupt is detected by the host it can read the interrupt status register (ist) to determine the sou rce of the interrupt. the exception to this is the i 2 c interrupt. once read the interrupt status register must be cleared by writing 0 to the appropriate bit/bits (selective clearing is possible). note that the burst complete/transfer complete interrupts m ust be cleared by writing to the burst status (bst) register. 3.5.1 internal bus/fifo timeout when accessing an internal client through the internal bus or writing to the fifo it is possible that an unacceptable delay (possibly a lockup situation) occurs. this should not normally happen, but as a safety feature a timeout is available to allow for graceful termination of the offending access. separate timeout periods for the internal bus and fifo can be programmed and enabled (using the btv, ftv and tcs regi sters). when an access is made to a client and no response is obtained within the specified timeout period then the access is terminated and an interrupt generated. the timeout control/status (tcs) register may be read to determine the offending client. de pending on circumstance a soft or firm reset may then be issued (through the srst or frst register) to clear the problem.
fujistu limited prel iminary and confiden tial MB86295S 39 specification manual rev1.1 3.5.2 address error interrupt certain addresses are invalid depending on operation. for example the burst controller cannot access the host interface internal registers. if an attempt is made to do this then the access will be terminated and an address error interrupt triggered. 3.6 memory map the local memory base address of coral - lp is determined by memory base address register 0 (pci byte address=0x10) in pci configuration registers. the following shows the local memory map of c oral lp to the host cpu memory space . fig. 3 .1 memory map table 3 - 4 address space size resource base address (name) 3 2 m b to 25 6 kb graphics memory 00000000 64 kb host interface registers (i 2 c interface registers) 01fc0000 (01fcc000) (hostbase) (i 2 cbase) 32 kb display registers 01fd0000 (displaybase) 32 kb video capture registers 01fd8000 (capturebase) 64 kb internal texture memory 01fe0000 (texturebase) 32 kb drawing registers 01ff0000 (drawbase) 32 kb geometry engine registers 01ff8000 (geometrybase) 32 mb graphics memory 02000000 register area graphics memory area 32 mb to 256 kb 256 kb 0000000 to 1fbffff 1fc0000 to 1ffffff 2000000 to 3ffffff 64 mb space 32 mb graphics memory area
fujistu limited prel iminary an d confidential MB86295S 40 specification manual rev1.1 if required t he register area can be moved by writing 1 to bit 0 at hostbase + 005ch (rs w: register location switch). in the initial state, the register space is at the center (1fc0000) of the 64 mb space. c oral lp may be accessed after about 20 bus clocks after writing 1 to rsw. fig. 3 . 2 alternate memory map table 3 - 5 altern ate address mapping size resource base address (name) 64 mb to 256 kb graphics memory 0 0000000 64 kb host interface registers (i 2 c interface registers) 0 3f c0000 (03fcc000) (hostbase) (i 2 cbase) 32 kb display registers 0 3f d0000 (displaybase) 32 kb video capture registers 0 3f d8000 (capturebase) 64 kb internal texture memory 0 3f e0000 (texturebase) 32 kb drawing registers 0 3f f0000 (drawbase) 32 kb geometry engine registers 0 3f f8000 (geometrybase) register area graphics memory area 32 mb to 256 kb 256 kb 0000000 to 1ffffff 3fc0000 to 3ffffff 2000000 to 3fbffff 64 mb space 32 mb graphics memory area
fujistu limited prel iminary and confiden tial MB86295S 41 specification manual rev1.1 4. i 2 c interface controller 4.1 features - master transmiss ion and receipt - slave transmission and r eceipt - arbitration - clock synchronization - detection of slave address - detection of general call address - detection of transfer direction - repeated generation and detection of start condition - detection of bus error - correspondence to standard - mode (100kbit/s ) / high - speed - mode (400kbit/s)
fujistu limited prel iminary an d confidential MB86295S 42 specification manual rev1.1 4.2 block diagram 4.2.1 block diagram noise filter start condition/stop condition detecting circuit adr comparater dar bsr bcr ccr arbitration lost detecting circuit start condition/stop condition generating circuit shift clock generating circuit host bus sda scl host if i2c unit
fujistu limited prel iminary and confiden tial MB86295S 43 specification manual rev1.1 4.2.2 block function overview start condition / stop condition detecting circuit this circuit performs detection of start co ndition and stop condition from the state of sda and scl. start condition / stop condition generating circuit this circuit performs generation of start condition and stop condition by changing the state of sda and scl. arbitration lost detecting circuit this circuit compares the data output to sda line with the data input into sda line at the time of data transmission, and it checks whether these data is in agreement. when not in agreement, it generates arbitration lost. shift clock generating circuit th is circuit performs generating timing count of the clock for serial data transfer, and output control of scl clock by setup of a clock control register. comparater comparater compares whether the received address and the self - address appointed to be the address register is in agreement, and whether the received address is a global address. adr adr is the 7 - bit register which appoints a slave address. dar dar is the 8 - bit register used by serial data transfer. bsr bsr is the 8 - bit register for the state of i2c bus etc. this register has following functions: - detection of repeated start condition - detection of arbitration lost - storage of acknowledge bit - data transfer direction - detection of addressing - detection of general call address - detection of the 1st byte bcr bcr is the 8 - bit register which performs control and interruption of i2c bus. this register has following functions: - request / permission of interruption - generation of start condition - selection of master / slave - permission to generate acknowledge
fujistu limited prel iminary an d confidential MB86295S 44 specification manual rev1.1 ccr ccr is the 7 - bit register used by serial data transfer. this register has following functions: - permission of operation - setup of a serial clock frequency - selection of standard - mode / high - speed - mode noise filter this noise filter consists of a 3 step shift register. when all three value that carried out the continuation sampling of the scl/sda input signals is ?1?, the filter output is ?1?. conversely when all three value is ?0?, the filter output is ?0?. to other samplings it holds the state before 1 clock. 4.3 example application 4.3.1 connection diagram sda scl sda scl slave device coral 3.3v
fujistu limited prel iminary and confiden tial MB86295S 45 specification manual rev1.1 4.4 function overview two bi - directional buses, serial data line (sda) and serial clock line (scl), carry information at i2c - bus. scarlet i2c interface has sda input (sdai) and sda output (sdao) for sda and is connected to sda line via open - drain i/o cell. and this interface also has scl input (scli) and scl output (sclo) for scl line and is connected to scl line via open - drain i/o cell. the wired theory is used when the i nterface is connected to sda line and scl line. 4.4.1 start condition if ? 1 ? is written to mss bit while the bus is free, this module will become a master mode and will generate start condition simultaneously. in a master mode, even if a bus is in a u se state (bb=1), start condition can be generated again by writing ? 1 ? to scc bit. there are two conditions to generate start condition. - ? 1 ? writing to mss bit in the state where the bus is not used (mss=0 & bb=0 & int=0 & al=0) - ? 1 ? writing to scc bit in the interruption state in a master mode (mss=1 & bb=1 & int=1 & al=0) if ? 1 ? writing is performed to mss bit in an idol state, al bit will be set to ? 1 ? . ? 1 ? writing to mss bit other than the above is disregarded. 4.4.2 stop condition if ? 0 ? is wri tten to mss bit in a master mode (mss=1), this module will generate stop condition and will become a slave mode. there is a condition to generate stop condition. - ? 0 ? writing to mss bit in the interruption state in a master mode (mss=1 & bb=1 & int=1 & a l=0) ? 0 ? writing to mss bit other than the above is disregarded. start condition sda scl stop condition sda scl
fujistu limited prel iminary an d confidential MB86295S 46 specification manual rev1.1 4.4.3 addressing in a master mode, it is set to bb= ? 1 ? and trx= ? 0 ? after generation of start condition, and the contents of dar register are output from msb. when this module receives ackn owledge after transmission of address data, the bit - 0 of transmitting data (bit - 0 of dra register after transmission) is reversed and it is stored in trx bit. - transfer format of slave address a transfer format of slave address is shown below: msb lsb a6 a5 a4 a3 a2 a1 a0 r/w ack slave address - map of slave address a map of slave address is shown below: slave address r/w description 0 0 0 0 0 0 0 0 general call address 0 0 0 0 0 0 0 1 start byte 0 0 0 0 0 0 1 x cbus a ddress 0 0 0 0 0 1 0 x reserved 0 0 0 0 0 1 1 x reserved 0 0 0 0 1xx x reserved 0 0 0 1 xxx ----- - x available slave address 1 1 1 0 xxx 1 1 1 1 0 xx x 10 - bit slave addressing*1 1 1 1 1 1 xx x reserved *1 this module does n o t support 10 - bit slave address. 4.4.4 synchronization of scl when two or more i2c devices turn into a master device almost simultaneously and drive scl line, each devices senses the state of scl line and adjusts the drive timing of scl line automatical ly in accordance with the timing of the latest device.
fujistu limited prel iminary and confiden tial MB86295S 47 specification manual rev1.1 4.4.5 arbitration when other masters have transmitted data simultaneously at the time of master transmission, arbitration takes places. when its own transmitting data is ? 1 ? and the data on sda line is ? 0 ? , the master considers that the arbitration was lost and sets ? 1 ? to al. and if the master is going to generate start condition while the bus is in use by other master , it will consider that arbitration was lost and will set ? 1 ? to al. when the start condition which other masters generated is detected by the time the master actually generated start condition, even when it checked the bus is in nonuse state and wrote in mss= ? 1 ? , it considers that the arbitration was lost and sets ? 1 ? to al. when al bit is set to ? 1 ? , a master will set mss= ? 0 ? and trx= ? 0 ? and it will be a slave receiving mode. when the arbitration is lost (it has no royalty of a bus), a master stops a drive of sda. however, a drive of scl is not stopped until 1 byte transfer is complete d and interruption is cleared. 4.4.6 acknowledge acknowledge is transmitted from a reception side to a transmission side. at the time of data reception, acknowledge is stored in lrb bit by ack bit. when the acknowledge from a master reception side is not r eceived at the time of slave transmission, it sets trx= ? 0 ? and becomes slave receiving mode. thereby, a master can generate stop condition when a slave opens scl. 4.4.7 bus error when the following conditions are satisfied, it is judged as a bus error, an d this interface will be in a stop state. - detection of the basic regulation violation on i2c - bus under data transfer (including ack bit) - detection of stop condition in a master mode - detection of the basic regulation violation on i 2c - bus at the time of bus idol sda changed under data transmission (scl=h). it becomes bus error. sda scl start 3 1 2 d7 d6 d5
fujistu limited prel iminary an d confidential MB86295S 48 specification manual rev1.1 4.4.8 initialize start setup of slave address setup of clock frequency setup of macro enable setup of interruption end adr: write ccr: write cs[4:0]: write en: 1write bcr: write ber: 0write beie: 1write int: 0write inte: 1write
fujistu limited prel iminary and confiden tial MB86295S 49 specification manual rev1.1 4.4.9 1 - byte transfer from master to slave start start condition transfer of address data end dar: write mss: 1write lrb reset int set, trx set dar: write int: 0write master bb set,trx set acknowledge interruption data transfer acknowledge inte rruption stop condition lrb reset int set mss: 0write int reset bb reset, trx reset slave bb set,trx reset aas set int set,trx reset ack: 1write int: 0write int set dar: read int: 0write bb reset,trx reset aas reset
fujistu limited prel iminary an d confidential MB86295S 50 specification manual rev1.1 4.4.10 1 - byte transfer from slave to master start start condition transfer of address data end dar:write mss:1write lrb reset int set, trx set ack: 0write int: 0write master bb set, trx set acknowledge iterruption data transfer negative acknowle dge interruption stop condition int set dar: read mss: 0write int reset bb reset, trx reset slave bb set, trx reset aas set int set, trx reset dar: write int: 0write int set bb reset, trx reset aas reset lrb set, rtx set int: 0write
fujistu limited prel iminary and confiden tial MB86295S 51 specification manual rev1.1 4.4.11 recovery from bus error start cancellation of error flag setup of clock frequency setup of macro enable setup of interruption end ccr: write cs[4:0]: write en: 1write bcr: write ber: 0write beie: 1write int: 0write inte: 1w rite bcr: write ber: 0write beie: 1write
fujistu limited prel iminary an d confidential MB86295S 52 specification manual rev1.1 4.5 note a ) about a 10 - bit slave address this module does not support the 10 - bit slav e address. therefore, please do not specify the slave address of from 78h to 7bh to this module. if it is specified by mistake, a normal transfer cannot be performed although acknowledge bit is returned at the time of 1 byte reception. b ) about competiti on of scc, mss, and int bit competition of the following byte transfer, generation of start condition, and generation of stop condition happens by the simultaneous writing of scc, mss, and int bit. at this time the priority is as follows. 1) the following byte transfer and generation of stop condition if ? 0 ? is written to int bit and ? 0 ? is written to mss bit, priority will be given to ? 0 ? writing to mss bit and stop condition will be generated. 2) the following byte transfer and generation of start conditi on if ? 0 ? is written to int bit and ? 1 ? is written to scc bit, priority will be given to ? 1 ? writing to scc bit and start condition will be generated . 3) generation of start condition and generation of stop condition the simultaneous writing of ? 1 ? in scc bit and ? 0 ? to mss bit is prohibition. c ) about setup of s serial transfer clock when the delay of the positive edge of scl terminal is large or when the clock is extended by the slave device, it may become smaller than setting value (calculation value) because of generation of overhead.
fujistu limited prel iminary and confiden tial MB86295S 53 specification manual rev1.1 5 . display controller 5 .1 overview display control window display can be performed for six layers. window scrolling, etc. , can also be performed. back ward compatibility back ward compatibility with previous product s is supported in the four - layer display mode or in the left/right split display mode. video timing generator the video display timing is generated according to the display resolution (from 320 240 to 1024 768). color look - up there are two sets of colo r look - up tables by palette ram for the indirect color mode (8 bits/pixel). cursor two sets of hardware cursor patterns (8 bits/pixel, 64 64 pixels each) can be used.
fujistu limited prel iminary an d confidential MB86295S 54 specification manual rev1.1 5 .2 display function 5 .2.1 layer configuration six - layer window display is performed . layer overlay sequence can be set in any order. a four - layer display mode and left/right split display mode are also provided, supporting backward compatibility with previous products. configuration of display layers the correspondenc e between the display layers for this product and for previous products is shown below. coordinates of starting point width/height layer correspondence window mode compatibility mode window mode compatibility mode l0 c (l0wx, l0wy) (0, 0) (l0ww, l0wh + 1) (hdp + 1, vdp + 1) l1 w (l1wx, l1wy) (wx, wy) (l1ww, l1wh + 1) (ww, wh + 1) l2 ml (l2wx, l2wy) (0, 0) (l2ww, l2wh + 1) (hdb + 1, vdp + 1) l3 mr (l3wx, l3wy) (hdb, 0) (l3ww, l3wh + 1) (hdp - hdb, vdp + 1) l4 bl (l4wx, l4wy) (0, 0) (l4ww, l4wh + 1) (h db + 1, vdp + 1) l5 br (l5wx, l5wy) (hdb, 0) (l5ww, l5wh + 1) (hdp - hdb, vdp + 1) c, w, ml, mr, bl, and br above mean layers for previous products. the window mode or the compatibility mode can be selected for ea ch layer. it is possible to use new fun ctions through minor program changes by allowing the coexistence of display modes instead of separating them completely. however, if high resolutions are displayed, the count of layers that can be displayed simultaneously and pixel data may be restricted according to the graphics memory ability to supply data. l0 ( l0wx,l0wy ) l2 ( l2wx,l2wy ) l1 ( l1wx,l1wy ) l5 ( l5wx,l5wy ) l4 ( l4wx,l4wy ) l3 ( l3wx,l3wy ) (a) six layerd window display l0,l2,l4 ( 0,0 ) l3,l5 ( hdb+1 , 0 ) l1 ( wx,wy ) (b) four la yered display for downward compatibility background color
fujistu limited prel iminary and confiden tial MB86295S 55 specification manual rev1.1 5 .2.2 overlay (1) overview image data for the six layers (l0 to l5) is processed as shown below. the fundamental flow is : palette ? layer selection ? blending. the palettes co nvert 8 - bit color codes to the rgb format. the layer selector exchanges the layer overlay sequence arbitrarily. the blender performs blending using the blend coefficient defined for each layer or overlays in accordance with the transparent - color definiti on. the l0 layer corresponds to the c layer for previous products and shares the palettes with the cursor. as a result, the l0 layer and cursor are overlaid before blend operation. the l1 layer corresponds to the w layer for previous products. to implemen t back ward compatibility with previous products, the l1 layer and lower layers are overlaid before blend operation. the l2 to l5 layers have two paths; in one path, these layers are input to the blender separately and in the other, these layers and the l1 layer are overlaid and then are input to the blender. when performing processing using the extended mode, select the former; when performing the same processing as previous products, select the latter. it is possible to specify which one to select for ea ch layer. pallet - 1 yuv/rgb pallet - 2 pallet - 3 pallet - 0 layer selector l0(c) data l2(ml) data cursor0 data l2 data l3 data l4 data l5 data blender overlay cursor1 data l1(w) data l4(bl) data l3(mr) data l5(br) data
fujistu limited prel iminary an d confidential MB86295S 56 specification manual rev1.1 (2) overlay mode image layer overlay is performed in two modes: simple priority mode , and blend mode. in the simple priority mode, processing is performed according to the transparent color defined for each layer. when the color is a transpar ent color, the value of the lower layer is used as the image value for the next stage; when the color is not a transparent color, the value of the layer is used as the image value for the next stage. d view = d new (when d new does not match transparent colo r) = d lower (when d new matches transparent color) when the l1 layer is in the ycbcr mode, transparent color checking is not performed for the l1 layer; processing is always performed assuming that transparent color is not used. in the blend mode, the ble nd ratio ? r ? defined for each layer is specified using 8 - bit tolerance, and the following operation is performed: d view = d new *r + d lower* (1 ? r) blending is enabled for each layer by mode setting and a specific bit of the pixel is set to ? 1 ? . for 8 bit s/pixel, the msb of ram data enable s blending; for 16 bits/pixel, the msb of data of the relevant layer enable s blending; for 24 bits/pixel, the msb of the word enable s blending. (3) blend coefficient layer in the normal blend mode, the blend coefficient is fixed for each layer. however , in the blend coefficient layer mode, the l5 layer can be used as the blend coefficient layer. in this mode, the blend coefficient can be specified for each pixel, providing gradation, for example. when using this mode, set the l5 layer to 8 bits/pixel.
fujistu limited prel iminary and confiden tial MB86295S 57 specification manual rev1.1 5 .2.3 display p arameters the display area is defined according to the following parameters. each parameter is set independently at the respective register. fig. 5 .1 display parameters htp horizontal to tal pixels hsp horizontal synchronize pulse position hsw horizontal synchronize pulse width hdp horizontal display period hdb horizontal display boundary vtr vertical total raster vsp vertical synchronize pulse position vsw vertical synchronize puls e width vdp vertical display period ln wx layer n window position x ln wy layer n window position y ln ww layer n window width ln wh layer n window height when not splitting the window , set hdp to hdb and display only the left side of the window . the se ttings must meet the following relationship: 0 < hdb hdp < hsp < hsp + hsw + 1 < htp 0 < vdp < vsp < vsp + vsw + 1 < vtr htp h s p h db h dp ln wy ln wx ln ww ln wh v dp v s p v tr v sw h sw
fujistu limited prel iminary an d confidential MB86295S 58 specification manual rev1.1 5 .2.4 display p osition c ontrol the graphic image data to be displayed is located in the logical 2d coordinate s space (logical graph ics space ) in the graphics memory. there are six logical graphics spaces as follows: l0 layer l1 layer l2 layer l3 layer l4 layer l5 layer the relation between the logical graphics space and display position is defined as follows: fig. 5 . 2 display position parameters oa origin address origin address of logical graphics space . memory address of top left edge pixel in logical frame origin w stride width of logical graphics space . defined in 64 - byte unit h height height of logical graph ics space . total raster (pixel) count of field da display address display origin address. top left position address of display frame origin dx dy display position display origin coordinate s . coordinate s in logical frame space of display frame origin stride (w) height (h) origin address (oa) display address (da) display position x,y ( dx , dy ) v dp logical frame display frame h dp
fujistu limited prel iminary and confiden tial MB86295S 59 specification manual rev1.1 mb8629 x scans the logical graphics space as if the entire space is rolled over in both the horizontal and vertical directions. using this function, if the display frame crosses the border of the logical graphics space , the part outside the border is cover ed with the other side of the logical graphics space , which is assumed to be connected cyclically as shown below: fig. 5 .3 wrap around of display frame the expression of the x and y coordinates in the frame and their corresponding linear add resses (in bytes) is shown below. a(x,y) = x bpp/8 + 64wy (bpp = 8 or 16) the origin of the displayed coordinates has to be within the frame. to be more specific, the parameters are subject to the following constraints: 0 dx < w 64 8/bpp (bpp = 8 or 16) 0 dy < h dx, dy, and da have to indicate the same point within the frame. in short , the following relationship must be satisfied . da = oa + dx bpp/8 + 64w dy (bpp = 8 or 16) 64 w l logical frame o rigin additionally drawn area new display origin previo u s display origin
fujistu limited prel iminary an d confidential MB86295S 60 specification manual rev1.1 5 .3 display color color data is displayed in the following modes : indirect color (8 bits/pixel) in this mode, the index of the palette ram is displayed. data is converted to image data consisting of 6 bits for r, g, and b via the palette ram and is then displayed. direct color (16 bits/pixel) each level of r, g, and b is represented using 5 bits. direct color (24 bits/pixel) each level of r, g, and b is represented using 8 bits. ycbcr color (16 bits/pixel) in this mode, image data is displayed with ycbcr = 4:2:2. data is converted to image data consisting of 8 bits f or r, g, and b using the operation circuit and is then displayed. the display color s for each layer are shown below. layer compatibility mode extended mode l0 direct color (16, 24), indirect color (p0) direct color (16, 24), indirect color (p0) l1 dire ct color (16, 24), indirect color (p1), ycbcr direct color (16, 24), indirect color (p1), ycbcr l2 direct color (16, 24), indirect color (p1) direct color (16, 24), indirect color (p2) l3 direct color (16, 24), indirect color (p1) direct color (16, 24), indirect color (p3) l4 direct color (16, 24), indirect color (p1) direct color (16, 24) l5 direct color (16, 24), indirect color (p1) direct color (16, 24) ? pn ? stands for the corresponding palette ram. four palettes are used as follow s : palette 0 (p0 ) this palette corresponds to the c - layer palette for previous products. this palette is used for the l0 layer. this palette can also be used for the cursor. palette 1 (p1) this palette corresponds to the m/b layer palette for previous products. in the compatibility mode, this palette is common to layers l1 to 5. in the extended mode, this palette is dedicated to the l1 layer. palette 2 (p2) this palette is dedicated to the l2 layer. this palette can be used only for the extended mode. palette 3 (p3) t his palette is dedicated to the l2 layer. this palette can be used only for the extended mode.
fujistu limited prel iminary and confiden tial MB86295S 61 specification manual rev1.1 5 .4 cursor 5 .4.1 cursor d isplay function coral can display two hardware cursors. each cursor is specified as 64 64 pixels, and the cursor pattern is set i n the graphics memory. the indirect color mode (8 bits/pixel) is used and the l0 layer palette is used. however, transparent color control ( handling of transparent color code and code 0) is independent of l0 layer . blending with lower layer is not perfo rmed. 5 .4.2 cursor control the display priority for hardware cursors is programmable. the cursor can be displayed either on upper or lower the l0 layer using this feature. a separate setting can be made for each hardware cursor. if part of a hardware c ursor crosses the display frame border, the part outside the border is not shown. usually, cursor 0 is preferred to cursor 1. however, with cursor 1 displayed upper the l0 layer and cursor 0 displayed lower the l0 layer, the cursor 1 display is preferred to the cursor 0.
fujistu limited prel iminary an d confidential MB86295S 62 specification manual rev1.1 5 . 5 display scan control 5 .5.1 applicable d isplay the following table shows typical display resolutions and their synchronous signal frequencies. the pixel clock frequency is determined by setting the division rate of the display refer ence clock. the display reference clock is either the internal pll (400. 9 mhz at input frequency of 14.318 mhz), or the clock supplied to the dclki input pin. the following table gives the clock division rate used when the internal pll is the display ref erence clock: table 4 - 1 resolution and display f requency resolution division rate of reference clock pixel frequency horizontal total pixel count horizontal frequency vertical total raster count vertical frequency 320 240 1/ 6 0 6.7 mhz 424 15.76 khz 263 59.9 hz 400 240 1/ 48 8.4 mhz 530 15.76 khz 263 59.9 hz 480 240 1/ 4 0 10.0 mhz 636 15.76 khz 263 59.9 hz 640 480 1/ 16 25.1 mhz 800 31.5 khz 525 59.7 hz 854 480 1/ 12 33.4 mhz 1062 31.3 khz 525 59.9 hz 800 600 1/10 40.1 mhz 1056 38.0 khz 633 60 .0 hz 1024 768 1/6 66.8 mhz 1389 48.1 khz 806 59.9 hz pixel frequency = 14.318 mhz 28 reference clock division rate (when internal pll selected) = dclki input frequency reference clock division rate (when dclki selected) horizontal frequency = pixel frequency/horizontal total pixel count vertical frequency = horizontal frequency/vertical total raster count
fujistu limited prel iminary and confiden tial MB86295S 63 specification manual rev1.1 5 .5.2 interlace d isplay coral can perform both a non - interlace display and an interlace display. when the dcm register synchronization mode is set to interlace video (11), images in memory are output in odd and even rasters alternately to each field, and one frame (odd + even fields) forms one screen. when the dcm register synchronization mode is set to interlace (10), images in memory are ou tput in raster order. the same image data is output to odd fields and even fields. consequently, the count of rasters on the screen is half of that of interlace video. however, unlike the non - interlace mode, there is a distinction between odd and even f ields depending on the phase relationship between the horizontal and vertical synchronous signal s . fig. 5.4 display difference between synchronization modes odd eve n non - interlace interlace video interlace
fujistu limited prel iminary an d confidential MB86295S 64 specification manual rev1.1 5 . 6 video interface, ntsc/pal output to achieve ntsc/pal signals, a ntsc/pal encode r must be connected externally as shown below: fig. 5 . 6 example of ntsc/pal encoder connection the digital ntsc /pal encoder can also be used, but in general, the usable pixel frequency/resolution are limited. for details, refer to the spec ifications for each company ? s digital ntsc /pal encoder. c sync r7-0 coral mb3516a video-out g7-0 b7-0 dclko csync-in r-in g-in b-in fsc-in mb 86029 rout gout bout r7-0 g7-0 b7-0 clk 1 / 4 c lk 14.318 mhz xrgben
fujistu limited prel iminary and confiden tial MB86295S 65 specification manual rev1.1 6 . video capture 6 .1 input formats the video capture unit of mb86295 ? coral - p ? accepts yuv422 video data primarily, but rgb video data is also accepted via an internal rgb preprocessor which converts rgb to yuv422. captured pixels are stored in ycbcr format in graphics memory, 16 bits per pixel. the video data is converted to rgb when it is displayed. 3 1 2 4 2 3 1 6 1 5 8 7 0 y1 cr y0 cb 7 6 5 4 3 2 1 0 y0,y1 y7 y6 y5 y4 y 3 y2 y1 y0 cr,cb c7 c6 c5 c4 c3 c2 c1 c0 6 .2 itu rbt - 656 input 6 .2.1 yuv input format the itu rbt - 656 format is widely used for digital transmission of ntsc and pal signals . the format corresponds to yuv422. interlaced video display signal s can be captured and displayed non - interlace d with linear interpolation. when the vie bit of the video capture mode register (vcm) is 1, coral is able to capture video stream data from the 8 - bit vi pin in synchronization with the cclk clock. in this m ode, only a digital video stream conforming to itu - rbt656 can be processed. for this reason, a y,cb,cr 4:2:2 format to which timing reference codes are added is used. the video stream is captured according to the timing reference codes; coral automatical ly supports both ntsc and pal. however, to detect error codes, set ntsc/pal in the vs bit of vcm. if ntsc is not set, reference the number of data in the capture data count register (cdcn). if pal is not set, reference the number of data in the capture d ata counter register (cdcp). if the reference data does not match the stream data, bit 4 to bit 0 of the video capture status register (vcs) will be values other than 0000. 6 .2.2 synchronous control writing video data in memory and scanning for display ar e executed simultaneously. the m emory of the video capture unit is controlled by a ring buffer controller . if the frame rate of video capture is
fujistu limited prel iminary an d confidential MB86295S 66 specification manual rev1.1 different from the display frame rate , frame s are skip ped or the same frame is continuously displayed automatic ally to match the two frame rates. when the expected control code in input video stream is not detected, an error is generated . the error status is returned in an register. when control code is not detected, pictures are taken in continuously by predicting the timing by code input previously. 6 .2.3 non - interlace transformation captured video graphics can be displayed in non - interlaced format. two modes (bob and weave) can be selected at non - interlace transformation. - bob mode in odd fields, the even - fiel d rasters generated by average interpolation are added to produce one frame. in even fields, the odd - field rasters generated by average interpolation are added to produce one frame. - weave mode odd and even fields are merged in the video capture buffer to produce one frame. vertical resolutions in the weave mode are higher than those in the bob mode but raster dislocation appears at moving places. when the vi bit of the video capture mode register (vcm) is ?0?, data in the same field is used to interp olate the interlace screen vertically. the interlace screen is doubled in the vertical direction. when the vi bit is ?1?, the interlace screen is not interpolated vertically. 6 .2.4 area allocation allocate an area of about 2.2 frames to the video captu re buffer. the size of this area is equivalent to the size that considers the margin equivalent to the double buffer of the frame. set the starting address and upper - limit address of the area in the cboa/cbla registers. here, specify the raster start po sition as the upper - limit address. to allocate n rasters as the video capture buffer, set the upper - limit value as follows: cbla = cboa + 64n x cbs if cbla does not match the head of a raster, video capture data is written beyond the upper limit by only 1 raster (max.). note that if other meaningful data is held in the area, the user - intended operation is hindered by overwriting. for reduced display, allocate the buffer area of the reduced frame size.
fujistu limited prel iminary and confiden tial MB86295S 67 specification manual rev1.1 6 .3 rgb input 6 .3.1. rgb input modes rgb video dat a is accepted via an internal rgb preprocessor which converts rgb to yuv422. there are two rgb modes : direct input mode and multiplex input mode. one pixel is transferred in one clock in direct input mode while one pixel is transferred in two clocks in mu ltiplex input mode. the direct mode is suitable for relatively high speed non - interlaced video signal s but the de - interlacing operation is not available in this mode . the maximum input rate is 40mpixel/sec. rgb component data is 6bit. the multiplex mode i s suitable for interlaced or relatively low speed video signal and de - interlac ing operation is available. rgb component data is 8bit. the mode will be controlled by the rgb bit of vcm(video capture mode) register . 6 .3. 2. rgb input signals the signals used for rgb video capture are not assigned dedicated terminals but share same pins with other functions. there are two set of signals corresponding to two modes. direct input mode : name io function rgbclk in clock for rgb input ri5 - 0 in red component valu e gi5 - 0 in green component value bi5 - 0 in blue component value vsynci in vertical sync for rgb capture hsynci in horizontal sync for rgb capture multiplex input mode : name io function rgbclk in clock for rgb input rbi7 - 0 in red and blue component v alue gi7 - 0 in green component value colsel in select red and blue vsynci in vertical sync for rgb capture hsynci in horizontal sync for rgb capture note : - input pins are shared with the itu656 input and memory data bus. - the mpx bit of the vcm(v ideo capture mode) register selects which mode is used.
fujistu limited prel iminary an d confidential MB86295S 68 specification manual rev1.1 6 .3. 3. captured range instead of embedded sync code method used in itu656 mode , the capture range in rgb mode is specified by the following register parameters : 1) rgb input mode of capture : set r gb666 input flag in vcm . 2) hsync cycle : s et the number of hsync cycles in rgbhc . 3) horizontal enable area : set enable area start position and enable picture size into rgbhst and rgbhen . 4) vertical enable area : set enable area start position and enable picture size into rgbvst and rgbven . for example, if input picture size is 800x400 , then parameters for each register are decided as follow : 5)convert matrix coefficient in order to change the color conversion matrix, set up rgbcmy ,rgbcb,r gbcr and rgbcmb . vsync hsync rgb hst(20) rgbvst (10) ) rgb hen(800) rgbven (400) captured rgbhc(840)
fujistu limited prel iminary and confiden tial MB86295S 69 specification manual rev1.1 6 .3. 4. direct input mode operat i on 6. 3.5 multiplex input mode operation rgbclk hsynci ri5-0 gi5-0 bi5-0 rgbhst captured rgbclk hsynci gi7-0 rbi7-0 colsel g r b g r b rgbhst captured
fujistu limited prel iminary an d confidential MB86295S 70 specification manual rev1.1 6 .3. 6. even/odd field recognition in multiplex input mode, interlaced rgb video data can be accepted and de - interlaced. a field is recognized as even or odd by the relativ e pulse position of h - sync and v - sync. 6 .3. 7. conversion operation rgb input data is converted to ycrcb by the following matrix operation : y = a11*r + a12*g + a13*b + b1 cr= a21*r + a22*g + a23*b + b2 a ij : 10bit signed real ( lower 8bit is fraction ) cb= a31*r + a32*g + a33*b + b3 b i : 8bit unsigned integer note : - each coefficient can be defined by registers. - c b and cr components are reduced to half after this operation to form in 4:2:2 format. vsync i hsync i start to capture ( even field) rgbvst vsync i hsync i start to capture (odd field) rgbvst
fujistu limited prel iminary and confiden tial MB86295S 71 specification manual rev1.1 6 .4 scaling 6 .4.1 downscaling fun ction when the cm bits of the video capture mode register (vcm) are 11, coral reduces the video screen size. the reduction can be set independently in the vertical and horizontal scales. the reduction is set per line in the vertical direction and in 2 - pi xel units in the horizontal direction. the scale setting value is defined by an input/output value. it is a 16 - bit fixed fraction where the integer is represented by 5 bits and the fraction is represented by 11 bits. valid setting values are from 0800 h to ffff h . set the vertical direction at bit 31 to bit 16 of the capture scale register (csc) and the horizontal direction at bits 15 to bit 00. the initial value for this register is 08000800 h (once). an example of the expressions for setting a reductio n in the vertical and horizontal directions is shown below. reduction in vertical direction 576 ? 490 lines 576/490 = 1.176 1.176 2048=2408 ? 0968 h reduction in horizontal direction 720 ? 648 pixels 720/648 = 1.111 1.111 2048=2275 ? 08e3 h therefore, 096 808e3 h is set in csc. the capture horizontal pixel register (chp) and capture vertical pixel register (cvp) are used to limit the number of pixels processed during scaling. they are not used to set scaling values. clamp processing is performed on the vid eo streaming data outside the values set in chp and cvp. usually, the defaults for these registers are used. 6 .4.2 upscaling function coral is able to enlarge the size of a video capture picture by the factor of 2 in both the horizontal and vertical dire ctions. this feature can be used to realize full - screen modes of video input streams which have a resolution less than actual display size. in order to use magnify (up - scaling) mode, the horizontal and vertical factor must be less than one. do not specify different scaling ways (reduction/enlargement) for horizontal and vertical factors ! also initialize the following registers as follows : set the magnify flag in the l1 - layer mode register of the display controller. set the picture source size (before m agnification) into cmshp and cmsvl. set the final picture size (after magnification) into cmdhp and cmdvl. an example of the expressions for setting an enlargement in the vertical and horizontal directions is shown below : if the input picture size is 480x 360 and the display picture size is 640x480, then the parameters for each register are as follows. hscale=(480/640)*2048=0x0600 vscale=(360/480)*2048=0x0600 cmshp=0x00f0 cmsvl=0x0168 cmdhp=0x0140 cmdvl=0x01e0 l1ww=0x0280 l1wh=0x01df
fujistu limited prel iminary an d confidential MB86295S 72 specification manual rev1.1 7 . geo metry engine 7 .1 geometry pipeline 7 .1.1 processing f low the flow of geometry is shown below. object coordinates (oc) clip coordinates (cc) normalized device coordinates (ndc) drawing (device) coordinates (dc) mvp t ransformation clipping 3d - 2d t ransformation view port transformation back face carling
fujistu limited prel iminary and confiden tial MB86295S 73 specification manual rev1.1 7 .1.2 model - v iew - p rojection (mvp) t ransformation (oc ? cc c oordinate t ransformation) the geometry engine transforms the vertex of the ?oc? coordinate system specified by the g_vertex packet to the ?cc? coordinate system according to the coordinate transformation matrix (oc ? cc matrix) specified by the g_loadmatrix packet. the ?oc ? cc matrix? is a ?4 4? matrix consisting of a modelview ma trix and a projection matrix. if ?zoc? is not contained in the input parameter of the g_vertex packet (z - bit of gmdr0 is off), (oc ? cc) coordinate transformation is processed as ?zoc = 0?. when gmdr0[0] is 0 (orthogonal projection transformation), oc ? cc coordinate transformation is processed as ?wcc = 1.0?. oc: object coordinates cc: clip coordinates ma0 to md3: oc ? cc matrix xoc to zoc: x, y, and z of oc coordinate system xcc to woc: x, y, z, and w of cc coordinate system 7 .1.3 3d - 2d trans formation (cc ? ndc c oordinate t ransformation) the geometry engine divides ?xyz? of the ?cc? coordinate system by ?wcc? (perspective division). ndc: normalized device coordinates xndc to zndc: x, y, and z of ?ndc? coordinate system ma0 mb0 mc0 md0 ma1 mb1 mc1 md1 ma2 mb2 mc2 md2 ma3 mb3 mc3 md3 xcc ycc zcc wcc xoc yoc zoc 1 = xndc yndc zndc = 1/wcc xcc ycc zcc
fujistu limited prel iminary an d confidential MB86295S 74 specification manual rev1.1 7 .1.4 view p ort t ransformation (ndc ? dc c oordinate t ransformation) the geometry engine transforms ?xyz? of the ?ndc? coordinate system to the ?dc? coordinate system according to the transformation coefficient specified by g_viewport and g_depthrange. ?x_scaling,x_offset? a nd ?y_scaling,y_offset? are coefficients to be mapped finally to frame buffer. xdc and ydc must be included within the drawing input range ( - 4096 to 4095). ?z_scaling? and ?z_offset? are coefficients to be mapped finally to ?z buffer?. ?zdc? must be inc luded within the ?z buffer? range (0 to 65535). dc: device coordinates xdc = x_scaling*xndc + x_offset ydc = y_scaling*yndc + y_offset zdc = z_scaling*zndc + z_offset 7 .1.5 view v olume c lipping expression for determination the expression for determining the coral view volume clipping is shown below. w clipping is intended to prevent the overflow caused by 1/w. xmin*wcc xcc xmax*wcc ymin*wcc ycc ymax*wcc zmin*wcc zcc zmax*wcc wmin wcc note: xmin, xmax, ymin, ymax, zmin, zmax, and wmin are the clip boundary values set by the g_viewvolumexyclip/zclip/wclip packet. clipping - on/ - off view volume clipping - on/ - off can be switched by using the clip boundary values set by the g_viewvolumexyclip/zclip/wclip packet. to switch view volume clipping to off, set the maximum and minimum values of the geometry data format (ieee single - precision floating point(*1)) in the ?clip.max? value(*2) and ?clip.min? value(*3), respectively. in this case, ?all coordinate transformation results? can be evaluated as w ithin view volume range , making it possible to obtain the effect of view volume clipping - off. this method is valid only when w clipping does not occur . when a clip boundary value (wmin) that causes w clipping to occur is set, clipping is also performed fo r each clip area. consequently, set an appropriate clip boundary value for clip. max value. and clip. min value . , respectively. if other values are set in ?clip.max? and clip.min, view volume clipping - on operates. the coordinate transformation result is always compared with the values set in ?clip.max? and ?clip.min?. *1: maximum value = 0x7f7fff f f, minimum value = 0xff7fff f f *2: xmin,ymin, zmin, wmin *3: xmax, ymax, zmax
fujistu limited prel iminary and confiden tial MB86295S 75 specification manual rev1.1 an example of the g_viewvolumezclip packet is shown below. 0xf1012010 //setting of gmdr0 0x00000000 //data format: floating point data format 0x45000000 //g_viewvolumezclip packet 0xff7ffff f //zmin.float setting value (minimum value of ieee single - precision floating point) 0x7f7f f fff //zmax.float setting value (maximum value of i eee single - precision floating point) example of g_viewvolumezclip packet when z clipping off ?w? clipping at orthogonal projection transformation ?w? at orthogonal projection transformation (gmdr0[0] = 0) is treated as ?wcc=1.0?. for this reason, to supp ress ?w? clipping, the set ?wmin? value must be larger than 0 and 1.0 or less. relationship with drawing clip frame for the following reasons, the clip boundary values of the view volume should be set so that the values after dc coordinate transformation w ill be larger than the drawing clip frame (2 pixels or more). (1) ?xy? on the view volume clip frame of the ?cc? coordinate system may be drawn one pixel outside or inside the frame due to an operation error when it is finally mapped to the ?dc? coordinate system. (2) when the end point of a line overlaps the view volume frame mapped to the ?dc? coordinate system, there are two cases, where the dots on the frame are drawn, and not drawn depending on the specifying of the line drawing attribute (end point dr awing/non - drawing). (3) when the start point of a line overlaps the view volume frame mapped to the ?dc? coordinate system, the dots on the frame are always drawn. when the line drawing attribute is ?end point non - drawing,? the dots on the frame are drawn at the starting point, but they may not be drawn at the end point. (4) when applying to triangle and polygon drawing the rasterizing rule ?dots containing center of pixel drawn. dots on right side and base of triangle not drawn.? depending on the value o f the fraction, a gap may be produced between the right side and base of the frame. drawing clip frame drawing area a space of two pixels or more is required . ? dc ? c oordinates image of view volume clip frame
fujistu limited prel iminary an d confidential MB86295S 76 specification manual rev1.1 7 .1.6 back face culling in coral , a triangle direction can be defined and a mode in which drawing for the back face is inhibited (back face culling) is supported . the on/off operation is controlled by the gmdr2[0] setting. gmdr2[0] must be set to 1 only when back face carling is required. when back face culling is not required such as in ?line,? ?point,? and ?polygon primitive,? gmdr2[0] must be set to 0.
fujistu limited prel iminary and confiden tial MB86295S 77 specification manual rev1.1 7 .2 data format 7 .2.1 data format the supported data formats are 32 - bit single - precision floating - point format, 32 - bit fixed - point format, integer packed format, and rgb packed format. all internal processing is performed in the floating - point format. for this reason, the integer packed format, fixed - point format, and rgb packed format must be converted to the floating - point format. the processing speeds in these formats are slightly lower than in the 32 - bit single - precision floating - point format. the dat a format to use is selected by setting the gmdr0 register. (1) 32 - bit single - precision floating - point format 31 30 23 22 0 s e f s: sign bit (1 bit) e: exponent part (8 bits) f: mantissa (23 bits) : ?1.f? shows the fraction. ?1? is a hidden bit. the numerical value of the floating - point format becomes ( - 1) s (1.f)2 (e - 127) (0 < e < 255). (2) signed fixed - point format (sfix16.16) 31 30 16 15 0 s int frac s: sign bit (1 bit) int: integer (15 bits) frac: fraction (16 bits) (3) signed integer packed format (sint16.sint16) 31 30 16 15 14 0 s y.int s x.int s: sign bit (1 bit) int: integer (15 bits) (4) rgb packed format 31 24 23 16 15 8 7 0 reser ved r g b r, g, b: color bits (8 bits) ( 5 ) a rgb packed format 31 24 23 16 15 8 7 0 a r g b a : alpha bits (8 bits) r, g, b: color bits (8 bits)
fujistu limited prel iminary an d confidential MB86295S 78 specification manual rev1.1 7 .3 setup engine 7 .3.1 setup processing the vertex data transformed by the geom etry engine is transferred to the setup engine. coral has a drawing interface that is compatible with the mb86290a. it operates parameters for various slope calculations, etc., with the setup engine. when the obtained parameters are set in the drawing e ngine, the final drawing processing starts. 7 . 4 log output of device coordinates a function is provided to output device coordinates (dc) data obtained by view port conversion to local memory (graphics memory). 7 . 4 .1 log output mode drawing & log outp ut command log output of drawing coordinates (device coordinates) can be performed concurrently with nclip_points.int primitive drawing. log output can be controlled using the command with log output on/off attribute; log output is performed only when the log output on attribute is specified. log output dedicated command when the log output dedicated command is used, log output of the device coordinates can be performed. 7 . 4 . 2 log output destination address the log output destination address is controlled using the device coordinates log pointer. log pointer is auto - increment - pointer, increment with log output.
fujistu limited prel iminary and confiden tial MB86295S 79 specification manual rev1.1 8 . drawing processing 8 .1 coordinate system 8 .1.1 drawing coordinate s after the calculation of coordinates by the geometry engine, coral draws data in the drawing frame in the graphics memory that finally uses the drawing coordinates (device coordinates). drawing frame is treated as 2d coordinate s with the origin at the top left as shown in the figure below . the maximum coordinate s is 4096 40 96. each drawing frame is located in the graphics memory by setting the address of the origin and resolution of x direction (size ). although the size of y direction does not need to be set , y coordinates which are max. at drawing must not be overlapped w ith other area . in addition , at drawing, specifying the clip frame (top left and bottom right coordinates) can prevent the drawing of images outside the clip frame . x (max. 4096 ) y (max. 4096) origin drawing frame size x drawing frame size y (xmin, ymin) (xmax, ymax) clip frame
fujistu limited prel iminary an d confidential MB86295S 80 specification manual rev1.1 8 .1.2 texture c oordinate s texture coordinate is a 2d coordinate system represen ted as s and t (s: horizontal, t: vertical). any integer in a range of - 8192 to + 8191 can be used as the s and t coordinates. the texture coordinate s is correlated to the 2d coordinate s of a vertex. one texture pattern can be applied to up to 4096 4 096 pixels. the pattern size is set in the register. when the s and t coordinate s exceed the maximum pattern size, the repeat, cramp or border color option is selected. 8 .1.3 frame b uffer for drawing, the following area must be assigned to th e graphics memory. the frame size ( count of pixels on x direction ) is common for these areas. drawing frame the results of drawing are stored in the graphical image data area. both the direct and indirect color mode are applicable. z buffer z buffer is r equired for eliminating hidden surfaces . in 16 bits mode, 2 bytes and in 8 bits mode, 1 byte are required per 1 pixel. polygon draw ing flag buffer this area is used for polygon drawing. 1 bit is required per 1 pixel . s (max. 8192) t (max. 8192) origin max. 4096 pixels max. 4096 pixels texture pattern
fujistu limited prel iminary and confiden tial MB86295S 81 specification manual rev1.1 8 .2 figure drawing 8 .2.1 drawing p rimitives coral has a drawing interface that is compatible with the mb86290a graphics controller which does not perform geometry processing. the following types of figure drawing primitives are compatible with the mb86290a. point line triangle high - speed 2dline high - speed 2dtriangle polygon 8 .2.2 polygon d rawing function an irregular polygon (including concave shape) is drawn by hardware in the following manner: 1. execute polygonbegin command. initialize polygon draw ing hardware. 2. draw vertices. draw outline of polygon and plot all vertices to polygon draw flag buffer using high - speed 2dtriangle primitive. 3. execute polygonend command. copy shape in polygon draw flag buffer to drawing frame and fill shape with color or specified tiling pattern.
fujistu limited prel iminary an d confidential MB86295S 82 specification manual rev1.1 8 .2.3 drawing p arameters the mb86290a - compatible interface uses the following parameters for draw ing : the triangles (right triangle and left triangle) are distinguished according to the locations of three vertices as follows (not used for high - speed 2dtriangle ): the following parameters are required for drawing triangles (for high - speed 2dtriangle, x and y coordinates of each vertex are specified). note: be careful about the positional relationship between coordinates xs, xus, and xls. fo r example, in the above diagram, when a right - hand triangle is drawn using the parameter that shows the coordinates positional relationship xs (upper edge start y coordinate s ) > xus or xs (lower edge start y coordinate s ) > xls, the appropriate picture may not be drawn. v0 upper edge long edge v1 lower edge v2 upper triangle lower triangle v1 v0 v2 upper edge lower edge long edge upper triangle lower triangle right - hand triangle left - hand triangle xus xls ys xs,zs,rs,gs,bs,ss,ts ,qs upper edge start y coordinates dxdy dzdy drdy dgdy dbdy dsdy dtdy dqdy dxudy dxldy lower edge start y coordinates dzdx ,drdx,dgdx,dbdx, dsdx,dtdx,dqdx usn l sn
fujistu limited prel iminary and confiden tial MB86295S 83 specification manual rev1.1 ys y coordinate s start position of long edge in drawing triangle xs x coordinate s start position of long edge corresponding to ys xus x coordinate s start position of upper edge xls x coordinate s start position of lower edge zs z coordin ate s start position of long edge corresponding to ys rs r color value of long edge corresponding to ys gs g color value of long edge corresponding to ys bs b color value of long edge corresponding to ys ss s coordinate of texture s of long edge correspo nding to ys ts t coordinate of texture s of long edge corresponding to ys qs q perspective correction value of texture of long edge corresponding to ys dxdy x dda value of long edge direction dxudy x dda value of upper edge direction dxldy x dda value of lower edge direction dzdy z dda value of long edge direction drdy r dda value of long edge direction dgdy g dda value of long edge direction dbdy b dda value of long edge direction dsdy s dda value of long edge direction dtdy t dda value of long e dge direction dqdy q dda value of long edge direction usn count of spans of upper triangle lsn count of spans of lower triangle dzdx z dda value of horizontal direction drdx r dda value of horizontal direction dgdx g dda value of horizontal direction dbdx b dda value of horizontal direction dsdx s dda value of horizontal direction dtdx t dda value of horizontal direction dqdx q dda value of horizontal direction 8 .2.4 anti - aliasing function coral performs anti - aliasing to make jaggies less notic eable and smooth on line edges. to use this function at the edges of primitives, redraw the primitive edges with anti - alias lines.
fujistu limited prel iminary an d confidential MB86295S 84 specification manual rev1.1 8 .3 bit map processing 8 .3.1 blt a rectangular shape in pixel units can be transferred . there are following types of tr ansfer : 1. transfer from host cpu to drawing frame memory 2. transfer between graphics memories including drawing frame 3. transfer from host cpu to internal texture memory 4. transfer from graphics memory to internal texture memory concerning 1 and 2 above, 2 - term lo gic operation is performed between source and destination data and its result can be stored. setting a transparent color enables a drawing of a specific pixel with transmission . if part of the source and destination of the blt field are physically overlapp ed in the display frame, the start address (from which vertex the blt field to be transferred) must be set correctly . 8 .3.2 pattern data format coral can handle three bit map data formats: indirect color mode (8 bits/pixel), direct color mode (16 bits/pi xel , 24 bits/pixel), and binary bit map (1 bit/pixel). the binary bit map is used for character/font patterns, where foreground color is used for bitmap = 1 pixel, and background color (background color can be set to be transparent by setting) is applied f or bitmap = 0 pixels.
fujistu limited prel iminary and confiden tial MB86295S 85 specification manual rev1.1 8 .4 texture mapping 8 .4.1 texture size coral reads texcel corresponding to the specified texture coordinate s (s, t), and draws that data at the correlated pixel position of the polygon. for the s and t coordinates, the selectable texture data size is any value in the range from 16 to 4096 pixels represented as an exponent of 2. 8 .4.2 texture memory texture pattern data is stored in either coral internal texture ram or external ly connected graphics memory. the coral texture ram ca n store up to 64 64 pixels of texture (at 16 - bit color) . if the texture pattern size is smaller than 64 64 pixels, it is best to store it in the internal texture buffer because the texture mapping speed is faster. note the following point when using t he texture: when access ( e.g., cpu read/write) is made to the internal texture ram other than the display list during drawing, the drawing results are not as sured. 8.4.3 texture color drawing of 8 - /16 - /24 - bit direct color is supported for the texture patt ern. for drawing 8 - bit direct color, only point sampling can be specified for texture interpolation; only de - curl can be specified for the blend mode.
fujistu limited prel iminary an d confidential MB86295S 86 specification manual rev1.1 8 .4. 4 texture lapping if a negative or larger than the specified texture pattern size is specified as the texture coordinate s (s, t), according to the setting, one of these options (repeat, cramp or border) is selected for the ?out - of - range? texture mapping. the mapping image for each case is shown below: repeat this just simply masks the upper bi ts of the applied (s, t) coordinate s . when the texture pattern size is 64 64 pixels, the lower 6 bits of the integer part of (s, t) coordinate s are used for s and t coordinates . cramp when the applied (s, t) coordinate s is either negative or larger than the specified texture pattern size, cramp the (s, t) coordinate as follows instead of texture : s < 0 s = 0 s > texture x size - 1 s = texture x size - 1 border when the applied (s, t) coordinate is either negative or larger than the specified texture p attern size, the outside of the specified texture pattern is rendered in the ?border? color. repeat cramp border
fujistu limited prel iminary and confiden tial MB86295S 87 specification manual rev1.1 8 .4. 5 filtering coral supports two texture filtering modes: point filtering, and bi - linear filtering. point filtering this mode uses the texture pixel specifie d by the (s, t) coordinate s as they are for drawing . the nearest pixel in the texture pattern is chosen according to the calculated (s, t) coordinate s . bi - linear filtering the four nearest pixels specified with (s, t) coordinate are blended a ccording to the distance from specified point and used in drawing . 8 .4. 6 perspective correction this function corrects the distortion of the 3d perspective in the texture mapping. for this correction , the ?q? component of the texture coordina te s (q = 1/w) is set based on the w component of 3d coordinate s of the vertex. when the texture coordinates are large values, the texture may not be drawn correctly when perspective correction is performed. this phenomenon occurs due to the precision limi tation of the arithmetical unit for perspective correction. the coordinates for the texture that cannot be drawn normally vary with the value of the q component ; as a guide , when this value is smaller than ? 2048 or larger than 2048, normal drawing results are less likely to be obtained. 0.0 0.5 1.0 1.5 2.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0 0.5 1.0 1.5 2.0 c 00 c 10 c 01 c 11
fujistu limited prel iminary an d confidential MB86295S 88 specification manual rev1.1 8 .4. 7 texture blending coral supports the following three blend modes for texture mapping: de - curl this mode displays the selected texture pixel color regardless of the polygon color. modulate this mode multiplies the nat ive polygon color (c p ) and selected texture pixel color (c t ) and the result is used for drawing . rendering color is calculated as follows (c o ): c 0 = c t c p stencil this mode select s the display color from the texture color with msb as a flag . msb = 1: t exture color msb = 0: polygon color 8.4.8 bi - linear high - speed mode bi - linear filtering is performed at high speed by creating normal texture data in advance with four - pixel redundancy for one pixel. one pixel requires information of about four pixels, so an area of four times the normal area is used. this data format can only be used only for the bi - linear filtering mode; it cannot be used for the point sampling mode. the wrapping mode is limited to repeat and the color mode is limited to 16 - bit color.
fujistu limited prel iminary and confiden tial MB86295S 89 specification manual rev1.1 normal texture layout (8 8 pixels ) texture layout in bi - linear mode (8 8 pixels ) 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 42 43 44 45 46 47 41 49 50 51 52 53 54 55 48 57 58 59 60 61 62 63 56 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 00 01 08 09 01 02 09 10 08 09 16 17 12 13 14 15 16 17 24 25 17 18 25 26 24 25 32 33 25 26 33 34 32 33 40 41 33 34 41 42 40 48 49 41 42 49 50 41 49 56 57 49 50 57 58 48 57 00 01 57 58 01 02 56 0 1 to 6 7 0 1 2 3 4 5 6 7 06 07 14 15 07 00 15 08 09 10 17 18 23 16 15 08 to 30 31 22 23 31 24 23 16 to 38 39 30 31 39 32 31 24 to 54 55 46 47 to 38 39 46 47 39 32 47 40 55 48 47 40 to 62 63 54 55 63 56 55 48 to 06 07 62 63 07 00 63 56 to
fujistu limited prel iminary an d confidential MB86295S 90 specification manual rev1.1 8 .5 rendering 8 .5.1 tiling tiling reads the pixel color from the correlated tiling pattern and maps it onto the polygon. the tiling determine s the pixel on the pattern read by pixel coordinate s to be drawn, irrespective of position and size of primitive . since the tiling pattern is stored in the texture memory , this function and texture mapping cannot be used at the same time. also, the tilin g pattern size is limited to within 64 64 pixels. (at 16 - bit color ) example of tiling 8 .5.2 alpha blending alpha blending blends the drawn in frame buffer to - be - drawn pixel or pixel already according to the alpha value set in the alpha register. this function cannot be used simultaneously with logic operation drawing . it can be used only when the direct color mode (16 bits/pixel , 24 bits/pixel) is used. the blended color c is calculated as shown below when the color of the pixel to be drawn is c p , the color of frame buffer is c f , and the alpha value is a: c = c p a + (1 - a) c f the alpha value is specified as 8 - bit data. 00h means alpha value 0% and ffh means alpha value 100%. when the texture mapping function is enabled, the following blendin g modes can be selected : normal blends post texture mapping color with frame buffer color stencil uses msb of texcel color for on/off control : msb = 1: texcel color msb = 0: frame buffer color stencil alpha uses msb of texcel color for a /off control : ms b = 1: alpha blend texcel color and current frame buffer color msb = 0: frame buffer color
fujistu limited prel iminary and confiden tial MB86295S 91 specification manual rev1.1 8 .5.3 logic operation this mode executes a logic operation between the pixel to be drawn and the one already drawn in frame buffer and its result is drawn . alph a blending cannot be used when this function is specified . type id operation type id operation clear 0000 0 and 0001 s & d copy 0011 s or 0111 s | d nop 0101 d nand 1110 ! (s & d) set 1111 1 nor 1000 ! (s | d) copy inverted 1100 !s xor 0110 s xor d invert 1010 !d equiv 1001 ! (s xor d) and reverse 0010 s & !d and inverted 0100 !s & d or reverse 1011 s | !d or inverted 1101 !s | d 8 .5.4 hidden plane management coral supports the z buffer for hidden plane management. this function compares the z va lue of a new pixel to be drawn and the existing z value in the z buffer. display/not display is switched according to the z - compare mode setting. define the z - buffer access options in the zwritemask mode. the z compare operation type is determined by the z compare mode. either 16 or 8 bits can be selected f or the z - value. 1 compare z values, no z value write overwrite zwritemask 0 compare z values , z value write z compare mode code condition never 000 never draw always 001 always draw less 010 dra w if pixel z value < current z buffer value lequal 011 draw if pixel z value current z buffer value equal 100 draw if pixel z value = current z buffer value gequal 101 draw if pixel z value 3 current z buffer value greater 110 draw if pixel z value > current z buffer value notequal 111 draw if pixel z value ! = current z buffer value
fujistu limited prel iminary an d confidential MB86295S 92 specification manual rev1.1 8 .6 drawing attributes 8 .6.1 line draw ing attributes in drawing line s , the following attributes apply: line draw ing attributes drawing attribute description line w idth line width selectable in range of 1 to 32 pixels broken line specify broken line pattern in 32 - bit data anti - alias line edge smoothed when anti - aliasing enabled 8 .6.2 triangle draw ing attributes in drawing triangle s, the following attributes apply (these attributes are disabled in high - speed 2dtriangle) . texture mapping and tiling have separated texture attributes: triangle draw ing attributes drawing attribute description shading gouraud shading or flat shading selectable alpha blending set alph a blend ing enable /disable per polygon alpha blending coefficient set color blend ing ratio of alpha blend ing 8 .6.3 texture attributes in texture mapping , the following attributes apply: texture attributes drawing attribute description texture mode selec t either texture mapping or tiling texture memory mode select either internal texture buffer or external graphics memory to use in texture mapping texture filter select either point sampling or bi - linear filtering texture coordinate s correction select e ither linear or perspective correction texture wrap select either repeat or cramp of texture pattern texture blend mode select either decal or modulate bi - linear high - speed mode texture data is created in a dedicated format to perform high - speed bi - line ar filtering.
fujistu limited prel iminary and confiden tial MB86295S 93 specification manual rev1.1 8 .6.4 blt attributes in blt draw ing , the following attributes apply: blt attributes drawing attribute description logic operation mode specify two source logic operation mode transparency mode set transparent copy mode and transparent c olor 8 .6.5 character pattern drawing attributes character pattern drawing drawing attribute description character pattern enlarge/shrink 2 2, 2 horizontal, 1/2 1/2, 1/2 horizontal character pattern color set character color and background colo r transparency/non - transparency set background color to transparency/non - transparency
fujistu limited prel iminary an d confidential MB86295S 94 specification manual rev1.1 8.7 bold line 8.7.1 starting and ending points in the cremson bold line mode, the starting and ending point s are vertical to the principal axis. in the coral bold l ine mode, the starting and ending point s are vertical to the theoretical line. caution: coral line is generated by different algorithm. thus drawing position is little bit different form other primitive. cremson bold line mode coral bold line mode
fujistu limited prel iminary and confiden tial MB86295S 95 specification manual rev1.1 8.7.2 broken line pattern the broken line pattern vertical to the theoretical line (the coral broken line pattern) is supported. in the cremson bold line mode, lines can be drawn using the broken line pattern vertical to the cremson - compatible principal axis (the cremson broken line pattern) , and can also be drawn using the coral broken line pattern. in the coral bold line mode, only the coral broken line pattern is supported. interpolation of broken line pattern two types of interpolation modes are supported: no interpolation mo de: interpolation is not performed. broken line pattern reference address fix mode: the same broken line pattern is referenced for several pixels before and after the joint of the bold line. any pixel count can be set by the user. coral bold and broken lines (1) (2) broken line pattern made vertical starting point made vertical; ending point made vertical edging not performed interpolation of bold line joint not performed interpolation of broken line pattern reference performed (1) (2) (1) (2) edging not performed interpolation of bold line jo int not performed broken line pattern reference address fixed
fujistu limited prel iminary an d confidential MB86295S 96 specification manual rev1.1 8.7.3 e dging the edging line is supported. the line body and edging section can have depth information (z offset). this mechanics makes it possible to easily represent a good connection of the overlaid part of the edging line. for example, when the line body de pth information and edging section depth information are the same, the drawing result of the edging line is like the intersection shown in the figure below. also, when the line body depth information and edging section depth information are different, the drawing result of the edging line is like the solid intersection shown in the figure below. 8.7.4 interpolation of bold line joint in the bold line joint interpolation mode, the bold line joint is interpolated using a triangle as shown in the figure below. the edging line joint is also interpolated using a triangle, but the said depth information makes it possible to represent a good connection as shown in the figure below. caution: sometime joint shape looks not perfect. ( using approximate calculation ) edging intersection solid intersection control by depth information interpolation of bold line joint interpolation using triangle edging interpolation can also be performed.
fujistu limited prel iminary and confiden tial MB86295S 97 specification manual rev1.1 8. 8 display list 8 .8.1 overview display list is a set of display list commands, parameters and pattern data. all display list commands stored in a display list are executed consequently . the display list is transferred to the d isplay list fifo by one of the following methods: write to display fifo by cpu transfer from main memory to display fifo by external dma transfer from graphics memory to display fifo by register set ting display list command - 1 data 1 - 1 data 1 - 2 data 1 - 3 display list command - 2 data 2 - 1 data 2 - 2 data 2 - 3 display list
fujistu limited prel iminary an d confidential MB86295S 98 specification manual rev1.1 8 .8.2 header format the format of the display list header is shown below. format list format 31 24 23 16 15 0 format 1 type reserved reserved format 2 t ype count address format 3 type reserved reserved vertex format 4 type reserved reserved flag vertex format 5 type command reserved format 6 type command count format 7 type command reserved vertex format 8 type command reserved flag vertex format 9 type reserved reserved flag format 10 type reserved count description of each field type display list type command command count count of data excluding header address address value used at data transfer vertex vertex number flag attribute flag pe culiar to display list command vertex number specified in vertex code vertex vertex number (line) vertex number (triangle) 00 v0 v0 01 v1 v1 10 setting prohibited v2 11 setting prohibited setting prohibited 8 .8.3 parameter format the parameter forma t of the geometry command depends on the value set in the d field of gmdr0. when the d field is ?00?, all parameters are handled in the floating - point format. when the d field is ?01?, colors are handled as the packed rgb format, and others are handled a s the fixed - point format. when the d field is ?11?, xy is handled as the packed integer format, colors are handled as the packed rgb format, and others are handled as the fixed - point format. in the following text, the floating - point format is suffixed by .float , the fixed point format is suffixed by .fixed , and the integer format is suffixed by .int . set gmdr0 properly to match parameter suffixes. rendering command parameters conform to the mb86290a data format.
fujistu limited prel iminary and confiden tial MB86295S 99 specification manual rev1.1 8 .8.4 geometry command list coral geometr y commands and each command code are shown in the table below. type command description g_nop ? no operation g_begin see geometry command code table . specifies primitive type and pre - processes g_begincont ? specifies primitive type (vertex processing i n same mode as previous mode) g_begin e see geometry command code table . specifies primitive type and pre - processes this command is used at execution of the coral extended function. g_begin e cont ? specifies primitive type (vertex processing in same mode a s previous mode) this command is used at execution of the coral extended function. g_end ? ends primitive this command is used at execution of g_begin or g_begincont g_end e ? ends primitive this command is used at execution of g_begine or g_beginecont. g_vertex ? sets vertex parameter and draws g_vertex log ? sets vertex parameter and draws outputs device coordinates g_vertex noplog ? only outputs device coordinates g_init ? initialize geometry engine g_viewport ? scale to screen coordinates (x, y) and set origin offset g_depthrange ? scale to screen coordinate s (z) and set origin offset g_loadmatirix ? load geometri c transformation matrix g_viewvolumexyclip ? set boundary value (x, y) of view volume clip g_viewvolumezclip ? set boundary value (z) o f view volume clip g_viewvolumewclip ? set boundary value (w) of view volume clip overlapxyofft see command table . sets xy offset at shading overlapzofft see command table . sets z offset of shade primitive; sets z offset of edge primitive; sets z offset of interpolation primitive at 2d drawing with top - left non - applicable dc_logoutaddr ? sets starting address of device coordinates output setmoderegister see command table . sets drawing extended mode register setgmoderegister see command table . sets geo metry extended mode register setcolorregister see command table . sets body color, shade color, and edge color setlvertex2i ? pass through high - speed 2dline drawing register setlvertex2ip ? pass through high - speed 2dline drawing register
fujistu limited prel iminary an d confidential MB86295S 100 specification manual rev1.1 type code tabl e type code g_nop 0010_0000 g_begin 0010_0001 g_begincont 0010_0010 g_end 0010_0011 g_vertex 0011_0000 g_vertex log 0011_0010 g_vertex noplog 0011_0011 g_init 0100_0000 g_viewport 0100_0001 g_depthrange 0100_0010 g_loadmatirix 0100_0011 g_viewvol umexyclip 0100_0100 g_viewvolumezclip 0100_0101 g_viewvolumewclip 0100_0110 setlvertex2i 0111_0010 setlvertex2ip 0111_0011 setmoderegister 1100_0000 setgmoderegister 1100_0001 overlapxy0fft 1100_1000 overlapz0fft 1100_1001 dc _ logoutaddr 1100_1100 setcolorregister 1100_1110 g_begin e 11 1 0_0001 g_begin conte 11 1 0_0010 g_ende 11 1 0_0011
fujistu limited prel iminary and confiden tial MB86295S 101 specification manual rev1.1 geometry command code table (1) floating point setup type ? integer setup type this function is deleted. (coral series) command code points 0000_0000 lines 0000 _0001 polygon 0000_0010 triangles 0000_0011 line_strip 0000_0101 triangle_strip 0000_0111 triangle_fan 0000_1000 (2) integer setup type in setup processing, ?xy? is calculated in the integer format and other parameters are calculated in the floating - point format. command code points.int 0001_0000 lines.int 0001_0001 polygon.int 0001_0010 triangles.int 0001_0011 line_strip.int 0001_0101 triangle_strip.int 0001_0111 triangle_fan.int 0001_1000 (3) ?unclipped? integer setup type this command does not clip the view volume. only ?xy? is enabled as the input parameter. in setup processing, ?xy? is calculated in the integer format. the screen projection (gmdr0[0]=1) performed using this command is not assured. command code nclip_points.int 0011_0000 nclip_lines.int 0011_0001 nclip_polygon.int 0011_0010 nclip_triangles.int 0011_0011 nclip_line_strip.int 0011_0101 nclip_triangle_strip.int 0011_0111 nclip_triangle_fan.int 0011_1000
fujistu limited prel iminary an d confidential MB86295S 102 specification manual rev1.1 8 .8.5 explanation of geometry commands g_nop (format 1) 31 24 23 16 15 0 g_nop reserved reserved no operation g_init (format 1) 31 24 23 16 15 0 g_init reserved reserved the g _ init command initializes geometry engine. execute this command before processing. g_end (format 1) 31 24 23 16 15 0 g_end reserved reserved the g_end command ends one primitive. the g_vertex command must be specified between the g_begin or g_begincont command and g_end command.
fujistu limited prel iminary and confiden tial MB86295S 103 specification manual rev1.1 g_begin (format 5) 31 24 23 16 15 0 g_begin command reserved the g_begin command sets types of primitive for geometry processing and drawing. a vertex is set and drawn by the g_vertex command. the g_vertex command must be specified between the g_begin or g_begincont command and g_end command. command: points* handles primitive as point lines* handles primitive as independent line polygon* handles primitive as polygon triangles* handles primitive as independent triangle line_strip* handles primitive as li ne strip triangle_strip* handles primitive as triangle strip triangle_fan* handles primitive as triangle fan usable combinations of gmdr0 mode setting and primitives are as follows: unclipped primitives (nclip*) (st,z,c) point line triangle polygon (0,0, 0) ? ? ? ? other than above primitives other than unclipped primitives (st,z,c) point line triangle polygon (0,0,0) ? ? ? ? (0,0,1) ? (0,1,0) ? ? ? ? (0,1,1) ? (1,x,x) ? ? (*1) *1: shading is not assured. g_begincont (for mat 1) 31 24 23 16 15 0 g_begincont reserved reserved when the primitive type set by the g_begin command the last time and drawing mode are not changed , the g_begincont command is used instead of the g_begin command. the g_begi ncont command is processed faster than the g_begin command. the packet that can be set between the g_end packet set just before and the g_begincont packet is only ?foreground color setting by the setregister packet.? the g_vertex command must be specified between the g_begin or g_begincont command and g_end command. no primitive type need be specified in the g_begincont command.
fujistu limited prel iminary an d confidential MB86295S 104 specification manual rev1.1 g_begin e (format 5) 31 24 23 16 15 0 g_begin command reserved this is the extended g_begin command. when using the following functions, this command must be executed instead of g_begin . mode register mdr1s/mdr1b/mdr1tl/mdr2s/mdr2tl/gmdr1e/gmdr2e log output of device coordinates g_vertexlog/g_vertexnoplog the g_begine command sets types of primitive for geometry processing and drawing. vertex setting/drawing using the above extended function is performed using the g_vertex* command. the g_vertex* command must be set between the g_begine command (or the g_beginecont command) and the g_ende command. com mand: points* handles primitive as point lines* handles primitive as independent line interpolation of the joint and broken line pattern is not supported. polygon* handles primitive as polygon triangles* handles primitive as independent triangle line_stri p* handles primitive as line strip triangle_strip* handles primitive as triangle strip triangle_fan* handles primitive as triangle fan usable combinations of gmdr0 mode setting and primitives are as follows: unclipped primitives (nclip*) (st,z,c) point li ne triangle polygon (0,0,0) ? ? ? ? other than above primitives other than unclipped primitives (st,z,c) point line triangle polygon *2 (0,0,0) ? ? ? ? (0,0,1) ? (0,1,0) ? ? ? ? (0,1,1) ? (1,x,x) ? ? (*1) *1: shading is no t assured. *2: texture and depth quality is less than triangle
fujistu limited prel iminary and confiden tial MB86295S 105 specification manual rev1.1 g_begin e cont (format 1) 31 24 23 16 15 0 g_begincont reserved reserved when the primitive type set by the g_begin e command the last time and drawing mode are not ch anged , the g_begin e cont command is used instead of the g_begin e command. the g_begin e cont command is processed faster than the g_begin e command. the packet that can be set between the g_end packet set just before and the g_begincont packet is only ?foregr ound color setting by the setregister packet.? the g_vertex command must be specified between the g_begin or g_begincont command and g_end command. no primitive type need be specified in the g_begincont command.
fujistu limited prel iminary an d confidential MB86295S 106 specification manual rev1.1 g_vertex / g_vertex log/ g_vertex noplog (for mat 1) when data format is floating - point format 31 24 23 16 15 0 g_vertex reserved reserved x.float y.float z.float r.float g.float b.float s.float t.float when data format is fixed - point format 31 24 23 16 15 0 g_vertex reserved reserved x.fixed y.fixed z.fixed r.int g.int b.int s.fixed t.fixed when data format is packed integer format 31 24 23 16 15 0 g_vertex reserved reserved y.int x.int z.fixed r.in g g.int b.int s.fixed t.fixed the g_vertex command sets vertex parameters and processes and draws the geometry of the primitive specified by the g_begin * command. note the following when using this command: required parameters depend on the setting of the gmdr0 register. proper values must be set as the mode values of the mdr0 to mdr4 registers to be finally reflected at drawing. that is, when ?z? comparison is made (zc bit of mdr1 or mdr2 = 1), the z bit of the gmdr0 register must be set to 1. when gouraud shading is performed (sm bit of mdr2 = 1), the c bit of the gmdr0 register must be set to 1. when texture mapping is performed (tt bits of mdr2 = 10), the st bit of the gmdr0 register must be set to 1. when the z bit of the gmdr0 register is 0, in put ?z? (zoc) is treated as ?0?. use values normalized to 0 and 1 as texture coordinates (s, t). when the color rgb is floating - point format, use values normalized to 0 and 1 as the 8 - bit color value. for the packed rgb, use the 8 - bit color value directly . the gmdr1 register is valid only for line drawing; it is ignored in primitives other than line. the gmdr2 register matters only when a triangle ( excluding a polygon) is drawn. at primitives other than triangle, set ?0?.
fujistu limited prel iminary and confiden tial MB86295S 107 specification manual rev1.1 g_viewport (format 1) 31 2 4 23 16 15 0 g_viewport reserved reserved x_scaling.float/fixed x_offset.float/fixed y_scaling.float/fixed y_offset.float/fixed the g_viewport command sets the ?x,y? scale/offset value used when normalized device coordinate s (ndc) is transformed into device coordinate s (dc). g_depthrange (format 1) 31 24 23 16 15 0 g_depthrange reserved reserved z_scaling.float/fixed z_offset.float/fixed the g_depthrange command sets the ?z? scale/offset value used wh en an ndc is transformed into a dc. g_loadmatrix (format 1) 31 24 23 16 15 0 g_loadmatrix reserved reserved matrix_a0.float/fixed matrix_a1.float/fixed matrix_a2.float/fixed matrix_a3.float/fixed matrix_b0.float/fixed matr ix_b1.float/fixed matrix_b2.float/fixed matrix_b3.float/fixed matrix_c0.float/fixed matrix_c1.float/fixed matrix_c2.float/fixed matrix_c3.float/fixed matrix_d0.float/fixed matrix_d1.float/fixed matrix_d2.float/fixed matrix_d3.float/fixed the g_l oadmatrix command sets the transformation matrix used when object coordinate s (oc) is transformed into clip coordinate s (cc).
fujistu limited prel iminary an d confidential MB86295S 108 specification manual rev1.1 g_viewvolumexyclip (format 1) 31 24 23 16 15 0 g_viewvolumexyclip reserved reserved xmin.float/fixed xmax.float/fixed ymin.float/fixed ymax.float/fixed the g_viewvolumexyclip command sets the x,y coordinates of the clip boundary value in view volume clipping. g_viewvolumezclip (format 1) 31 24 23 16 15 0 g_viewvolumezclip r eserved reserved zmin.float/fixed zmax.float/fixed the g_viewvolumezclip command sets the z coordinate s of the clip boundary value in view volume clipping. g_viewvolumewclip (format 1) 31 24 23 16 15 0 g_viewvolumewclip reser ved reserved wmin.float/fixed the g_viewvolumewclip command sets the w coordinate s of the clip boundary value in view volume clipping (minimum value only).
fujistu limited prel iminary and confiden tial MB86295S 109 specification manual rev1.1 overlapxyofft (format5) 31 24 23 16 15 0 overlapxyofft command reserve d y offset x offset the overlapxyofft command sets the xy offset of the shade primitive relative to the body primitive at shading drawing. shadow shape is same as body. command: command code explanation shadow xy 0000_0000 shadowxy command sets the xy o ffset of the shade primitive relative to the body primitive. shadowxycompsition 0000_0001 shadowxycomposition command sets the xy offset of the shade synthetic primitive relative to the body primitive. it command synthesizes a shade from the relationship between the xy offset set using shadowxy and this xy offset. this command is enabled for only lines. overlapzofft (format5) 31 24 23 16 15 0 overlapzofft command reserved don ? t care z offset note: when mdr0 zp = 1, only low er 8 bits are enabled. 31 24 23 16 15 0 overlapzofft packed_onbs reserved s _ z offset b _ z offset n _ z offset o _ z offset the overlapzofft command sets the z offset of the shade primitive relative to the body primitive, sets the z - offset of the edge primitive relative to the body primitive , and sets the z offset of the interpolation primitive relative to the body primitive, with the top - left rule non - applicable in effect. at this time, the following relationship must be satisfied w hen, for example, greater is specified for the z value comparison mode: body primitive > top - left rule non - applicable interpolation primitive > edge primitive > shade primitive command: command code explanation origin 0000_0000 origin command sets the z offset of the body primitive. when drawing one primitive below the other primitive (for example, when drawing a solid intersection), this z offset is changed. when drawing an ordinary intersection, set the same z offset as other primitives. nontopleft 0000_0001 nontopleft command sets the z offset of the interpolation primitive, with the top - left non - applicable. border 0000_0010 border command sets the z offset of the edge primitive. shadow 0000_0011 shadow command sets the z offset of the shade primi tive. packed_onbs 0000_0111 packed_onbs command sets the above four types of z offsets.
fujistu limited prel iminary an d confidential MB86295S 110 specification manual rev1.1 dc_logoutaddr (format5) 31 24 23 16 15 0 overlapxyofft command reserved 000000 logoutaddr the dc_logoutaddr command sets the starting ad dress of the log output destination of the device coordinates. setmoderegister (format5) 31 24 23 16 15 0 setmoderegister command reserved mdr1*/mdr2* the setmoderegister command sets the mode register for shade primitive, for edge primitive, and for top - left non - applicable primitive. at drawing of these primitives, also set the mode register (mdr1/mdr2) for the body primitive, using this packet. command: command code explanation mdr1 0000_0000 mdr1 command sets mdr1 for the body primitive. mdr1s 0000_0010 mdr1s command sets mdr1 for the shade primitive. mdr1b 0000_0100 mdr1b command sets mdr1 for the edge primitive. mdr2 0000_0001 mdr2 command sets mdr2 for the body primitive. mdr2s 0000_0011 mdr2s command sets mdr2 for the shade primitive. mdr2lt 0000_0111 mdr2lt command sets mdr2 for the top - left non - applicable primitive. setgmoderegister (format5) 31 24 23 16 15 0 set g moderegister command reserved gmdr1e/gmdr2e the setgmoderegister comma nd sets the geometry extended mode register. command: command code explanation gmdr1e 0001_0000 gmdr1e command sets gmdr1e and at the same time, updates gmdr1. gmdr2e 0010_0000 gmdr2e command sets gmdr2e and at the same time, updates gmdr2.
fujistu limited prel iminary and confiden tial MB86295S 111 specification manual rev1.1 setcolorr egister (format5) 31 24 23 16 15 0 setcolorregister command reserved fgc8/16/24 the setcolorregister command sets the foreground color and background color of the body primitive, shade primitive, and edge primitive. command s : command code explanation forecolor 0000_0000 forecolor command sets the foreground color for the body primitive. backcolor 0000_0001 backcolor command sets the background color for the body primitive. forecolor shadow 0000_0010 forecolor shadow command se ts the foreground color for the shade primitive. backcolor shadow 0000_0011 backcolor shadow command sets the background color for the shade primitive. forecolor border 0000_0100 forecolor border command sets the foreground color for the edge primitive. bac kcolor border 0000_0101 backcolor border command sets the background color for the edge primitive. setregister (format 2) 31 24 23 16 15 0 setregister count address (val 0) (val 1) ? (val n) the setregister command is upper compatible with cremson setregister . it can specify the address of a register in the geometry engine. setlvertex2i (format 1) 31 24 23 16 15 0 setlvertex2i reserved reserved lx0dc ly0dc the setlvertex2i command issues the se tregister_lxodc/lyodc command (mb86290a command to set starting vertex at line drawing) in the geometry fifo interface. this performs processing faster than when the setregister_lxodc/lyodc command is input directly to the geometry fifo. setlvertex2ip (f ormat 1) 31 24 23 16 15 0 setlvertex2ip reserved reserved ly0dc lx0dc the setlvertex2ip command supports packed xy of setlvertex21.
fujistu limited prel iminary an d confidential MB86295S 112 specification manual rev1.1 8 .9 rendering command 8 .9.1 command list the following table lists coral rendering commands and their command codes. type command description nop ? no operation interrupt ? interrupt request to host cpu sync ? synchronization with events setregister ? set s data to register normal set s data to high - speed 2dtriangle vertex registe r setvertex2i polygonbegin initializes border rectangle calculation of multiple vertices random shape polygonend clear s polygon flag after drawing pol y gon draw flush_fb/z flushes drawing pipelines drawpixel pixel draws point drawpixelz pixelz draws point with z xvector draw s line ( principal axis x) yvector draw s line ( principal axis y) antixvector draw s line with anti - alias option ( principal axis x) drawline antiyvector draw s line with anti - alias option ( principal axis y) zerovecto r draw s high - speed 2dline ( with vertex 0 as starting point ) drawline2i drawline2ip onevector draw s high - speed 2dline ( with vertex 1 as starting point ) trapright draw s right triangle drawtrap trapleft draw s left triangle trianglefan draw s high - spe ed 2dtriangle drawvertex2i drawvertex2ip flagtrianglefan draw s high - speed 2dtriangle for multiple vertices random shape bltfill draws rectangle with single color drawrectp clearpolyflag clear s polygon flag buffer bltdraw draw s blt drawbitmapp bitmap draw s binary bit map (ch aracter) topleft blt transfer from top left coordinates topright blt transfer from top right coordinates bottomleft blt transfer from bottom left coordinates bltcopyp bltcopy - alternatep bottomright blt transfer from bottom right coordinates loadtexture load s texture pattern loadte xturep loadtile load s tile pattern loadtexture load s texture pattern from local memory blttexturep loadtile load s tile pattern from local memory bltcopyalt - alphablendp ? alpha blending is supported (see the alpha ma p). bltcopyalternatep
fujistu limited prel iminary and confiden tial MB86295S 113 specification manual rev1.1 type code table type code drawpixel 0000_0000 drawpixelz 0000_0001 drawline 0000_0010 drawline2i 0000_0011 drawline2ip 0000_0100 drawtrap 0000_0101 drawvertex2i 0000_0110 drawvertex2ip 0000_0111 drawrectp 0000_1001 drawbit mapp 0000_1011 bitcopyp 0000_1101 bitcopyalternatep 0000_1111 loadtexturep 0001_0001 blttexturep 0001_0011 bltcopyalt alphablend p 0001 _1111 setvertex2i 0111_0000 setvertex2ip 0111_0001 draw 1111_0000 setregister 1111_0001 sync 1111_1100 interrupt 1111_1101 nop 1111_1111
fujistu limited prel iminary an d confidential MB86295S 114 specification manual rev1.1 command code table (1) command code pixel 000_00000 pixelz 000_00001 xvector 001_00000 yvector 001_00001 xvectornoend 001_00010 yvectornoend 001_00011 xvectorblpclear 001_00100 yvectorblpclear 001_00101 xvectornoendblp clear 001_00110 yvectornoendblpclear 001_00111 antixvector 001_01000 antiyvector 001_01001 antixvectornoend 001_01010 antiyvectornoend 001_01011 antixvectorblpclear 001_01100 antiyvectorblpclear 001_01101 antixvectornoendblpclear 001_01110 antiyve ctornoendblpclear 001_01111 zerovector 001_10000 onevector 001_10001 zerovectornoend 001_10010 onevectornoend 001_10011 zerovectorblpclear 001_10100 onevectorblpclear 001_10101 zerovectornoendblpclear 001_10110 onevectornoendblpclear 001_10111 ant izerovector 001_11000 antionevector 001_11001 antizerovectornoend 001_11010 antionevectornoend 001_11011 antizerovectorblpclear 001_11100 antionevectorblpclear 001_11101 antizerovectornoendblpclear 001_11110 antionevectornoendblpclear 001_11111
fujistu limited prel iminary and confiden tial MB86295S 115 specification manual rev1.1 c ommand code table (2) command code bltfill 010_00001 bltdraw 010_00010 bitmap 010_00011 topleft 010_00100 topright 010_00101 bottomleft 010_00110 bottomright 010_00111 loadtexture 010_01000 loadtile 010_01001 trapright 011_00000 trapleft 011_000 01 trianglefan 011_00010 flagtrianglefan 011_00011 flush_fb 110_00001 flush_z 110_00010 polygonbegin 111_00000 polygonend 111_00001 clearpolyflag 111_00010 normal 111_11111
fujistu limited prel iminary an d confidential MB86295S 116 specification manual rev1.1 8 .9.2 details of rendering commands all parameters belonging to their c ommand are stored in relevant registers. the definition of each parameter is explained in the section of each command. nop (format1) 31 24 23 16 15 0 nop reserved reserved no operation interrupt (format1) 31 24 23 16 15 0 interrupt reserved reserved the interrupt command generates interrupt request to host cpu . sync (format9) 31 24 23 16 15 4 0 sleep reserved reserved flag the sync command suspends all subsequent display l ist processing until event set in flag detected . flag: bit number 4 3 2 1 0 bit field name reserved reserved reserved reserved vblank bit 0 vblank vblank synchronization 0 no operation 1 wait for vsync detection
fujistu limited prel iminary and confiden tial MB86295S 117 specification manual rev1.1 setregister (format2) 31 2 4 23 16 15 0 setregister count address (val 0) (val 1) (val n) the setregister command sets data to sequential registers . count: data word count (in double - word unit) address: register address set the value of the address fo r setregister given in the register list. when transferring two or more data, set the starting register address. setvertex2i (format8) 31 24 23 16 15 4 3 2 1 0 setvertex2i command reserved flag vertex xdc ydc the setvertex2i co mmand sets vertices data for high - speed 2dline or high - speed 2dtriangle to registers . commands: normal set s vertex data (x, y). polygonbegin start s calculation of circumscribed rectangle for random shape to be drawn. calculate vertices of rectangle incl uding all vertices of random shape defined between polygonbegin and polygonend . flag: not used setvertex2ip (format8) 31 24 23 16 15 4 3 2 1 0 setvertex2i command reserved flag vertex ydc xdc the setvertex2ip command sets vertice s data for high - speed 2dline or high - speed 2dtriangle to registers . only the integer (packed format) can be used to specify these vertices. command s : normal set s vertices data. polygonbegin start s calculation of circumscribed rectangle of random shape to be drawn. calculate vertices of rectangle including all vertices of random shape defined between polygonbegin and polygonend . flag: not used
fujistu limited prel iminary an d confidential MB86295S 118 specification manual rev1.1 draw (format5) 31 24 23 16 15 0 draw command reserved the draw command executes dra w ing command . all parameters required for draw ing command execution must be set at their appropriate registers. commands: polygonend draw s polygon end . fill s random shape with color according to flags generated by flagtrianglefan command and information of circumscribed rectangle generated by polygonbegin command. flush_fb flushes drawing data in the drawing pipeline into the graphics memory. place this command at the end of the display list. flush_z flushes z value data in the drawing pipeline into th e graphics memory. when using the z buffer, place this command together with the flush_fb command at the end of the display list. drawpixel (format5) 31 24 23 16 15 0 deawpixel command reserved pxs pys the drawpixel comma nd draws pixel . command: pixel draws pixel without z value. drawpixelz (format5) 31 24 23 16 15 0 deawpixel command reserved pxs pys pzs the drawpixelz command draws pixel with z value. command: pixelz draws pixel with z value.
fujistu limited prel iminary and confiden tial MB86295S 119 specification manual rev1.1 drawline (format5) 31 24 23 16 15 0 drawline command reserved lpn lxs lxde lys lyde the drawline command draws line . it start s drawing after setting all parameters at line draw registers. commands: xvector draw s line (principal axis x). yvector draw s line (principal axis y). xvectornoend draw s line (principal axis x, and without end point drawing ). yvectornoend draw s line (principal axis y , and without end point drawing ). xvectorblpclear draw s line (principa l axis x, and prior to drawing, broken line pattern reference position cleared) . yvectorblpclear draw s line (principal axis y, and prior to drawing, broken line pattern reference position cleared) . xvectornoendblpclear draw s line (principal axis x, witho ut end point drawing and prior to drawing, broken line pattern reference position cleared) . yvectornoendblpclear draw s line (principal axis y, without end point drawing and prior to drawing, broken line pattern reference position cleared) . antixvector dr aw s anti - alias line (principal axis x). antiyvector draw s anti - alias line (principal axis y). antixvectornoend draw s anti - alias line (principal axis x, and without end point drawing ). antiyvectornoend draw s anti - alias line (principal axis y , and without end point drawing ). antixvectorblpclear draw s anti - alias line (principal axis x and prior to drawing, broken line pattern reference position cleared) . antiyvectorblpclear draw s anti - alias line (principal axis y and prior to drawing, broken line pattern reference position cleared) . antixvectornoendblpclear draw s anti - alias line (principal axis x, without end point drawing and prior to drawing, broken line pattern reference position cleared) . antiyvectornoendblpclear draw s anti - alias line (principal axis y, without end point drawing and prior to drawing, broken line pattern reference position cleared) .
fujistu limited prel iminary an d confidential MB86295S 120 specification manual rev1.1 drawline2i (format7) 31 24 23 16 15 0 drawline2i command reserved vertex lfxs 0 lfys 0 the drawline2i command draws high - s peed 2d l ine . it start s drawing after setting parameters at the high - speed 2dline draw ing registers. integer data can only be used for coordinates . commands: zerovector draw s line from vertex 0 to vertex 1. onevector draw s line from vertex 1 to vertex 0. zerovectornoend draw s line from vertex 0 to vertex 1 ( without drawing end point ) . onevectornoend draw s line from vertex 1 to vertex 0 ( without drawing end point ) . zerovectorblpclear draw s line from vertex 0 to vertex 1 (principal axis x, and prior to d rawing, broken line pattern reference position cleared) . onevectorblpclear draw s line from vertex 1 to vertex 0 (principal axis y, and prior to drawing, broken line pattern reference position cleared) . zerovectornoendblpclear draw s line from vertex 0 to vertex 1 (principal axis x, without end point drawing and prior to drawing, broken line pattern reference position cleared) . onevectornoendblpclear draw s line from vertex 1 to vertex 0 (principal axis y, without end point drawing and prior to drawing, bro ken line pattern reference position cleared) . antizerovector draw s anti - alias line from vertex 0 to vertex 1. antionevector draw s anti - alias line from vertex 1 to vertex 0. antizerovectornoend draw s anti - alias line from vertex 0 to vertex 1 ( without end point ) . antionevectornoend draw s anti - alias line from vertex 1 to vertex 0 ( without end point ) . antizerovectorblpclear draw s anti - alias line from vertex 0 to vertex 1 (principal axis x and prior to drawing, broken line pattern reference position cleared ) . antionevectorblpclear draw s anti - alias line from vertex 1 to vertex 0 (principal axis y and prior to drawing, broken line pattern reference position cleared) . antizerovectornoendblpclear draw s anti - alias line from vertex 0 to vertex 1 (principal axis x, without end point drawing and prior to drawing, broken line pattern reference position cleared) . antionevectornoendblpclear draw s anti - alias line from vertex 1 to vertex 0 (principal axis y, without end point drawing and prior to drawing, broken line p attern reference position cleared) .
fujistu limited prel iminary and confiden tial MB86295S 121 specification manual rev1.1 drawline2ip (format7) 31 24 23 16 15 0 drawline2ip command reserved vertex lfys lfxs the drawline2ip command draws high - speed 2d l ine . it start s drawing after setting parameters at high - sp eed 2dl i ne draw ing registers. only packed integer data can be used for coordinates . commands: zerovector draw s line from vertex 0 to vertex 1. onevector draw s line from vertex 1 to vertex 0. zerovectornoend draw s line from vertex 0 to vertex 1 ( without drawing end point ) . onevectornoend draw s line from vertex 1 to vertex 0 ( without drawing end point ) . zerovectorblpclear draw s line from vertex 0 to vertex 1 (principal axis x, and prior to drawing, broken line pattern reference position cleared) . onevec torblpclear draw s line from vertex 1 to vertex 0 (principal axis y, and prior to drawing, broken line pattern reference position cleared) . zerovectornoendblpclear draw s line from vertex 0 to vertex 1 (principal axis x, without end point drawing and prior to drawing, broken line pattern reference position cleared) . onevectornoendblpclear draw s line from vertex 1 to vertex 0 (principal axis y, without end point drawing and prior to drawing, broken line pattern reference position cleared) . antizerovector dr aw s anti - alias line from vertex 0 to vertex 1. antionevector draw s anti - alias line from vertex 1 to vertex 0. antizerovectornoend draw s anti - alias line from vertex 0 to vertex 1 ( without end point ) . antionevectornoend draw s anti - alias line from vertex 1 to vertex 0 ( without end point ) . antizerovectorblpclear draw s anti - alias line from vertex 0 to vertex 1 (principal axis x and prior to drawing, broken line pattern reference position cleared) . antionevectorblpclear draw s anti - alias line from vertex 1 to vertex 0 (principal axis y and prior to drawing, broken line pattern reference position cleared) . antizerovectornoendblpclear draw s anti - alias line from vertex 0 to vertex 1 (principal axis x, without end point drawing and prior to drawing, broken line p attern reference position cleared) . antionevectornoendblpclear draw s anti - alias line from vertex 1 to vertex 0 (principal axis y, without end point drawing and prior to drawing, broken line pattern reference position cleared) .
fujistu limited prel iminary an d confidential MB86295S 122 specification manual rev1.1 drawtrap (format5) 31 24 23 16 15 0 drawtrap command reserved ys 0 xs dxdy xus dxudy xls dxldy usn 0 lsn 0 the drawtrap command draws triangle . it start s drawing after setting parameters at the triangle draw ing registers (coordinates) . command s: trapright draw s right triangle. trapleft draw s left triangle. drawvertex2i (format7) 31 24 23 16 15 0 drawvertex2i command reserved vertex xdc 0 ydc 0 the drawvertex2i command draws high - speed 2d t riangle it start s triang le drawing after setting parameters at 2dtriangle draw ing registers. commands: trianglefan draw s high - speed 2d t riangle. flagtrianglefan draw s high - speed 2dtriangle for polygon drawing in the flag buffer . drawvertex2ip (format7) 31 24 23 16 1 5 0 drawvertex2ip command reserved vertex ydc xdc the drawvertex2ip command draws high - speed 2d t riangle it start s drawing after setting parameters at 2dtriangle draw ing registers only the packed integer format can be used for vertex coordi nates. commands: trianglefan draw high - speed 2d t riangle. flagtrianglefan draw s high - speed 2dtriangle for polygon drawing in the flag buffer .
fujistu limited prel iminary and confiden tial MB86295S 123 specification manual rev1.1 drawrectp (format5) 31 24 23 16 15 0 drawrectp command reserved rys rxs rsizey rsi zex the drawrectp command fills rectangle . the rectangle is filled with the current color after setting parameters at the rectangle registers. commands: bltfill fill s rectangle with current color (single). clearpolyflag fill s polygon drawing flag buffer area with 0. the size of drawing frame is defined in rsizex,y. drawbitmapp (format6) 31 24 23 16 15 0 drawbitmapp command count rys rxs rsizey rsizex (pattern 0) (pattern 1) (pattern n) the drawbitmapp command draw s rectangle patterns. commands: bltdraw draw s rectangle of 8 bits/pixel or 16 bits/pixel. drawbitmap draw s binary bitmap character pattern. bit 0 is drawn in transparent or background color, and bit 1 is drawn in foreground color.
fujistu limited prel iminary an d confidential MB86295S 124 specification manual rev1.1 bltcopyp (format5) 3 1 24 23 16 15 0 bltcopyp command reserved srys srxs drys drxs brsizey brsizex the bltcopyp command copies rectangle pattern within drawing frame . commands: topleft start s bitblt transfer from top left coordinates . topright s tart s bitblt transfer from top right coordinates . bottomleft start s bitblt transfer from bottom left coordinates . bottomright start s bitblt transfer from bottom right coordinates . bltcopyalternatep (format5) 31 24 23 16 15 0 b ltcopyalternatep command reserved saddr sstride srys srxs daddr dstride drys drxs brsizey brsizex the bltcopyalternatep command copies rectangle between two separate drawing frames . command: topleft start s bitblt transfer from top left coordinates .
fujistu limited prel iminary and confiden tial MB86295S 125 specification manual rev1.1 loadtexturep (format6) 31 24 23 16 15 0 loadtexturep command count (pattern 0) (pattern 1) (pattern n) the loadtexturep command loads texture or tile pattern into internal texture buffer . it stores a texture pattern in to the texture buffer based on the current pattern size (txs/tis) and offset address (xbo). commands: loadtexture stores texture pattern into internal texture buffer. loadtile stores tile pattern into internal texture buffer. blttexturep (format5) 31 24 23 16 15 0 blttexturep command reserved srcaddr srcstride srcrectys srcrectxs brsizey brsizex destoffset the blttexturep command loads texture or tile pattern into texture buffer from graphics memory . it stores a texture pattern in to the texture buffer current pattern size (txs/tis) and offset address (xbo). for destoffset, specify the word - aligned byte address (16 bits) (bit 0 is always 0). commands: loadtexture stores texture pattern into internal texture buffer. loadti le stores tile pattern into internal texture buffer.
fujistu limited prel iminary an d confidential MB86295S 126 specification manual rev1.1 blt copyaltalphablend p (format5) 31 24 23 16 15 0 bltcopyalternatep command reserved saddr sstride srys srxs blendstride blendrys blendrxs drys drxs brsizey brsizex the blt copyaltalphablend p command performs alpha blending for the source (specified using saddr, sstride, srxs, srxy) and the alpha map (specified using abr (alpha base address), blendstride, blendrxs, blendrys) and then copies the result of the alpha blen ding to the destination (specified using fbr (frame buffer base address), xres (x resolution), drxs, and drys). command: reserved set 0000_0000 to maintain future compatibility.
fujistu limited prel iminary and confiden tial MB86295S 127 specification manual rev1.1 9. pci configuration register s for the coral - lp, the pci configuration re gisters are divided into two subgroups: 1. device specific registers (eg. vendor id). these should not normally be modified by the user. these registers can be loaded from eeprom. 2. application specific registers (eg. pci command register). these can be m odified by the user and must be programmed using pci configuration cycles as they can not be loaded from the eeprom. however an eeprom loadable 32 bit register is available for the user. for the eeprom loadable configuration registers, the coral - lp uses by te addresses which are used on the pci bus. however, when in 16 bit data mode the eeprom requires word addresses. the eeprom preloaded using the 16 bit word addresses shown in the below. 9.1 pci configuration register list 31:24 23:16 15:8 7:0 pci byte address eeprom word address device id vender id 00 01 00 status commnd 04 - - class code revision id 08 05 04 bist header type master latency timer cacheline size 0c 07 - base address register0 10 - - reserved 14 - - reserved 18 - - reserved 1c - - reserved reserved reserved reserved 20 - - reserved reserved reserved reserved 24 - - reserved reserved reserved reserved 28 - - subsystem id subsystem vendor id 2c 17 16 reserved reserved reserved reserved 30 - - reserved 34 - - reserved 38 - - max lat min gnt interrupt pin interrupt line 3c 1f 1e reserved retry time out trdy time out 40 - - user register 44 23 22
fujistu limited prel iminary an d confidential MB86295S 128 specification manual rev1.1 9.2 pci configuration registers descriptions in the following sections, the following abbreviations in the ? type ? field apply: ro : register is read - only, not loadable via eeprom. er : register is read - only, loadable via eeprom. rw : register is read/writable using pci configuration transactions; not loadable via eeprom. for further information about these fields, please refer to the pci specification v2.1, section6. vendor id register bit type reset value description 15 - 0 er 10cfh identifies the vendor of the ic. the reset value represents the vendor id of fujitsu limited. device id register bit type reset value desc ription 15 - 0 er 2019h id of fujitsu limited pci device (coral device id). pci command register bit type reset value description 15 - 10 - 0 reserved 9 rw 0 fast back - to - back master enable. this is not supported by the coral - lp and should be set to ? 0 ? 8 rw 0 system error enable. this is supported by the coral - lp. 7 - 0 reserved 6 rw 0 parity error enable. this is supported by the coral - lp. 5 - 0 reserved 4 rw 0 memory write and invalidate enable. this feature is not supported in master mode, but in slave mode the coral - lp will convert any memory write and invalidate commands to memory write commands. this bit should be set to ? 0 ? . 3 - 0 reserved 2 rw 0 bus master enable. this bit must be set to ? 1 ? by the user for correct operation. 1 rw 0 memory access enable. this bit must be set to ? 1 ? by the user for correct operation. 0 rw 0 i/o access enable. the coral - lp does not do i/o accesses.
fujistu limited prel iminary and confiden tial MB86295S 129 specification manual rev1.1 pci status register bit type reset value description 15 status 0 parity error has been detected by the cor al - lp. 14 status 0 system error has been signaled by the coral - lp. 13 status 0 received master abort. set to ? 1 ? when a pci master terminates a user to the coral - lp transaction with master abort. 12 status 0 received target abort. set to ? 1 ? when the co ral - lp has initiated a transaction that has been terminated by target abort. 11 status 0 target abort has been signaled by the coral - lp. 10 - 9 ro 01 device select timing. indicates the timing of the devsel# signal when the coral - lp responds as a pci targe t. 8 status 0 data parity error detected. 7 ro 1 fast back - to - back capable status flag. 6 - 0 reserved 5 ro 0 66mhz capable flag. 4 - 0 - - reserved revision id register bit type reset value description 7 - 0 er 01h revision id of the coral - lp. pci c lass code register bit type reset value description 23 - 0 er 038000h class code of the coral - lp. the reset value means ? display controller ? of non - specific type. casheline size register bit type reset value description 7 - 0 rw 0 casheline size. master latency timer register bit type reset value description 7 - 2 rw 0 master latency timer count value. this register sets the minimum number of pci clocks the coral - lp is guaranteed access to the pci bus. after the count has expired, the coral - lp releases the pci bus as soon as another pci master is granted the bus by the bus arbiter. 1 - 0 - 0 reserved header type register bit type reset value description 7 - 0 er 0 as defined in the pci specification, section 6.2.1. bist register bit type reset value desc ription 7 - 0 - 0 this field is not used by the coral - lp, so it is hard - wired to zero.
fujistu limited prel iminary an d confidential MB86295S 130 specification manual rev1.1 memory base address register bit type reset value description 31 rw 0 memory base address. this determines the address of the first coral - lp non pci register. the cora l - lp will respond as a target to accesses in the address range: (memory_base_address) to (memory_base_address + 3ff0000h) subsystem vendor id register bit type reset value description 15 - 0 er 0 subsystem vendor id. this register can be loaded from eepr om. subsystem id register bit type reset value description 15 - 0 er 0 subsystem id. this register can be loaded from eeprom interrupt line register bit type reset value description 7 - 0 rw 0 interrupt line register. used to convey interrupt line routin g information . interrupt pin register bit type reset value description 7 - 0 rw 1 identifies which pci interrupt pin the coral - lp is connected to. the default value of this indicate that the coral - lp is connected to the inta line, which is the usual setti ng for this field. min grant register bit type reset value description 7 - 0 er 0 identifies the maximum length of pci burst period the coral - lp needs. this should be left at the reset setting. max latency register bit type reset value description 7 - 0 er 0 specifies how often the coral - lp needs to access the bus. this should be left at the reset settings. trdy timeout value register bit type reset value description 7 - 0 rw 80h sets the number of pci clocks the coral - lp will wait for trdy, when acting as a bus master. retry timeout value register bit type reset value description 7 - 0 rw 80h sets the number of retries of the coral - lp will perform when acting as a bus master. user programmable register bit type reset value description 31 - 0 er 0 user programmable register
fujistu limited prel iminary and confiden tial MB86295S 131 specification manual rev1.1 10 local memory register s 10.1 local memory register list 10.1.1 host interface register list base = hostbase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mro 0 01c mro ist 0 020 ist ist ist ist imask 0 024 imask imask imask imask srst 0 02c srst ccf 0 038 cge cot rsw 0 05c rsw ip 0070 ip btv 0074 btv ftv 0078 ftv ofu 007c ofu frst 00a0 frst srbs 00a4 srbs
fujistu limited prel iminary an d confidential MB86295S 132 specification manual rev1.1 iom 00a8 gim gd ser rgb bee sbe tce bce eee gd 00ac gwe gd sic 00b0 ckp ckg ckd doe sd sp sl sid 00b4 fsl fs tls rwd cid 00f0 cn ver bsa 8000 sa bda 8004 da bcr 8008 strt nda nsa bsize tsize bsr 80 0c xcor imode tcm bcm exten mode ber 8010 abort extst ben bst 8014 tc bc tcnt bcb 8040 ? 805c rwdata * 8
fujistu limited prel iminary and confiden tial MB86295S 133 specification manual rev1.1 10.1.2 i 2 c interface register list base = i 2 c base offset 31 30 29 28 27 2 6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 reserved bsr 004 reserved bcr 008 reserved ccr 00c reserved adr 010 reserved dar 014 access prohibitation 018 access prohibitation 01c access prohibitation 10.1.3 graphics memory interface register list base = hostbase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dtc fffc twr id trrd trc trp tras trcd lowd rts saw asw cl
fujistu limited prel iminary an d confidential MB86295S 134 specification manual rev1.1 10.1.4 display controller register list base = displaybase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dce (display controller enable) dcm (display control mode) 000 den l45e l23e l1e l0e cks dcs sc eeq ede eof eod sf esy sync dcee (display controller extend enable) 100 den l5e l4e l3e l2e l1e l0e cks dcs sc eeq ede eof eod sf esy sync 004 htp (h total pixels) 008 hdb (h display boundary) hdp (h display period) 00c vsw hsw hsp (h sync pul se position) 010 vtr (v total rasters) 014 vdp (v display period) vsp (v sync pulse position) 018 wy (window y) wx (window x) 01c wh (window height) ww (window width) l0m (l0 mode) 020 l0c l0s (l0 s tride) l0h (l0 height) 024 l0oa (l0 origin address) 028 l0da (l0 display address) 02c l0dy (l0 display y ) l0dx (l0 display x) l0em (l0 extend mode) 110 l0ec l0pb l0wp 114 l0wy (l0 window y) l0wx (l0 window x) 118 l0wh (l0 window height) l0ww (l0 window width) l1m (l1 mode) 030 l1c l1yc l1cs l1im l1s (l1 stride) 034 l1da (l1 display address) l1em (l1 extend mode) 120 l1ec l1pb l2m (l2 mode) 040 l2c l2flp l2s (l2 stride) l2h (l2 height) 044 l2oa0 (l2 origin address 0) 048 l2da0 (l2 display address 0) 04c l2oa1 (l2 origin address 1) 050 l2da1 (l2 display address 1) 054 l2dy (l2 display y ) l2dx (l2 display x) l2em (l2 extend mode) 130 l2ec l2pb l2om l2wp 134 l2wy (l2 window y) l2wx (l2 window x) 138 l2wh (l2 window height) l2ww (l2 window width)
fujistu limited prel iminary and confiden tial MB86295S 135 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 2 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 l3m (l3 mode) 058 l3c l3flp l3s (l3 stride) l3h (l3 height) 05c l3oa0 (l3 origin address 0) 060 l3da0 (l3 display address 0) 064 l3oa1 (l3 origin address 1) 068 l3 da1 (l3 display address 1) 06c l3dy (l3 display y ) l3dx (l3 display x) l3em (l3 extend mode) 140 l3ec l3pb l3om l3wp 144 l3wy (l3 window y) l3wx (l3 window x) 148 l3wh (l3 window height) l3ww (l3 window width) l4m (l4 mode) 070 l4c l4flp l4s (l4 stride) l4h (l4 height) 074 l4oa0 (l4 origin address 0) 078 l4da0 (l4 display address 0) 07c l4oa1 (l4 origin address 1) 080 l4da1 (l4 display address 1) 084 l4dy (l4 display y ) l4dx (l4 display x) l4em (l4 extend mode) 150 l4ec l4om l4wp 154 l4wy (l4 window y) l4wx (l4 window x) 158 l4wh (l4 window height) l4ww (l4 window width) l5m (l5 mode) 088 l5c l5flp l 5s (l5 stride) l5h (l5 height) 08c l5oa0 (l5 origin address 0) 090 l5da0 (l5 display address 0) 094 l5oa1 (l5 origin address 1) 098 l5da1 (l5 display address 1) 09c l5dy (l5 display y ) l5x (l5 display x) l5em ( l5 extend mode) 110 l5ec l5om l5wp 164 l5wy (l5 window y) l5wx (l5 window x) 168 l5wh (l5 window height) l5ww (l5 window width)
fujistu limited prel iminary an d confidential MB86295S 136 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 csize cpm cutc (cursor transparent control) 0a0 csiz1 csiz0 cue1 cue0 cuo1 cuo0 cuzt cutc 0a4 cuoa0 (cursor0 origin address) 0a8 cuy0 (cursor0 position y) cux0 (cursor0 position x) 0ac cuoa1 (curs or1 origin address) 0b0 cuy1 (cursor1 position y) cux1 (cursor1 position x) dls (display layer select) 180 dls5 dls4 dls3 dls2 dls1 dls0 184 dbgc (display back ground color) l0bld (l0 blend) 0b4 l0be l0bs l0bi l0bp l0br l1bld (l1 blend) 188 l1be l1bs l1bi l1bp l1br l2bld (l2 blend) 18c l2be l2bs l2bi l2bp l2br l3bld (l3 blend) 190 l3be l3bs l3bi l3bp l3br l4bld (l4 blend) 194 l4be l4bs l4bi l4bp l4br l5bld (l5 blend) 198 l5be l5bs l5bi l5br
fujistu limited prel iminary and confiden tial MB86295S 137 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 l0tc (l0 transparent control) 0bc l0zt l0tc (l0 transparent color) l2tr (l2 transparent control) l3tr (l3 transparent control) 0c0 l2zt l2tc (l2 transparent color) l3zt l3tr (l3 transparent color) l0tec (l0 extend transparency control) 1a0 l0ezt l0etc (l0 extend tra nsparent color) l1tec (l1 transparent extend control) 1a4 l1ezt l1etc (l1 extend transparent color) l2tec (l2 transparent extend control) 1a8 l2ezt l2etc (l2 extend transparent color) l3tec (l3 transparent extend control) 1ac l3ezt l3etc (l3 extend transparent color) l4etc (l4 extend transparent control) 1b0 l4ezt l4etc (l4 extend transparent color) l5etc (l5 extend transparent control) 1b4 l5ezt l5etc (l5 extend transparent color)
fujistu limited prel iminary an d confidential MB86295S 138 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 l0pal0 400 a r g b 404 l0pal1 : : 7fc l0pal255 l1pal0 800 a r g b 804 l1pal1 : : bfc l1pal255 l2pal0 1000 a r g b 1004 l2pal1 : : 13fc l2pal255 l3pal0 1400 a r g b 1404 l3pal1 : : 17fc l3pal255
fujistu limited prel iminary and confiden tial MB86295S 139 specification manual rev1.1 10.1.5 video c apture r egister list base = capturebase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vcm (video cap ture mode) 000 vie cm vi vs csc(capture scale) 004 vsci vscf hsci hscf vcs(video capture status) 008 ce cbm(capture buffer mode) 010 oo cbw cboa(capture bauffer origin address) 014 cboa cbla(capture buffer limit address) 018 cbla 01c civstr cihstr 020 civend cihend chp(capture horizontal pixel) 028 chp cvp(capture vertical pixel) 02c cvpp cvpn clpf(capture low pass filter) 040 cvlpf chlpf cmss(capture magnify source size) 048 cmshp cmsvl cmds(capture magnify display size) 04c cmdhp cmdvl rgbhc(rgb input hsync cycle) 0 80 rgbhc rgbhen(rgb input horizontal enable area) 084 rgbhst rgbhen rgbven(rgb input vertical enable area) 088 rgbvst rgbven rgbs(rgb input sync) 090 rm hp vp
fujistu limited prel iminary an d confidential MB86295S 140 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rgbcmy(rgb color convert matrix y coefficient) 0c0 a11 a11 a11 rgbcmcb(rgb color convert matrix cb coefficient) 0c4 a21 a22 a23 rgbcmcr(rgb color convert matrix cr coefficient) 0c8 a31 a32 a33 rgbcmb(rgb color convert matrix b coefficient) 0cc b1 b2 b3 cdcn(capture data count for ntsc) 4000 bdcn vdcn cdcp(capture data count for pal) 4004 bdcp v dcp
fujistu limited prel iminary and confiden tial MB86295S 141 specification manual rev1.1 10.1.6 drawing engine register list the parenthesized value in the offset field denotes the absolute address used by the setregister command. base = drawbase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ys 000 (000) s s s s int 0 xs 004 (001) s s s s int frac dxdy 008 (002) s s s s int frac xus 00c (003) s s s s int frac dxudy 010 (004) s s s s int frac xls 014 (005) s s s s int frac dxldy 018 (006) s s s s int frac us n 01c (007) 0 0 0 0 int 0 lsn 020 (008) 0 0 0 0 int 0 rs 040 (010) 0 0 0 0 0 0 0 0 int frac drdx 044 (011) s s s s s s s s int frac drdy 048 (012) s s s s s s s s int frac gs 04c (013) 0 0 0 0 0 0 0 0 int frac dgdx 050 (014) s s s s s s s s int f rac dgdy 054 (015) s s s s s s s s int frac bs 058 (016) 0 0 0 0 0 0 0 0 int frac dbdx 05c (017) s s s s s s s s int frac dbdy 060 (018) s s s s s s s s int frac
fujistu limited prel iminary an d confidential MB86295S 142 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 zs 080 (020) 0 int frac dzdx 084 (021) s int frac dzdy 088 (022) s int frac ss 0c0 (030) s s s int frac dsdx 0c4 (031) s s s int frac dsdy 0c8 (032) s s s int frac ts 0cc (033) s s s int frac dtdx 0d0 (034) s s s int f rac dtdy 0d4 (035) s s s int frac qs 0d8 (036) 0 0 0 0 0 0 0 int frac dqdx 0dc (037) s s s s s s s int frac dqdx 0e0 (038) s s s s s s s int frac lpn 140 (050) 0 0 0 0 int 0 lxs 144 (051) s s s s int frac lxde 148 (052) s s s s s s s s s s s s s s s int frac lys 14c (053) s s s s int frac lyde 150 (054) s s s s s s s s s s s s s s s int frac lzs 154 (055) s int frac lzde 158 (056) s int frac
fujistu limited prel iminary and confiden tial MB86295S 143 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pxdc 180 (060) s s s s int frac pydc 184 (061) s s s s int frac pzdc 188 (062) s int frac rxs 200 (080) s s s s int 0 rys 204 (081) s s s s int 0 rsizex 208 (082) s s s s int 0 rsizey 20c (083) s s s s int 0 sadd r 240 (090) 0 0 0 0 0 0 0 address sstride 244 (091) 0 0 0 0 int 0 srxs 248 (092) 0 0 0 0 int 0 srys 24c (093) 0 0 0 0 int 0 daddr 250 (094) 0 0 0 0 0 0 0 address dstride 254 (095) 0 0 0 0 int 0 drxs 258 (096) 0 0 0 0 int 0 drys 25c (097) 0 0 0 0 int 0 brsizex 250 (098) 0 0 0 0 int 0 brsizey 254 (099) 0 0 0 0 int 0 tcolor 258 (09a) 0 color blpo 3e0 (0f8) bcr
fujistu limited prel iminary an d confidential MB86295S 144 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ctr 400 (100) fd fe ce fcnt nf ff fe ss ds ps ifsr 404 ( - ) fd fe ce ifcnt 408 ( - ) fcnt sst 40c ( - ) ss ds 410 ( - ) ds pst 414 ( - ) ps est 418 ( - ) fd pe ce mdr0 420 (108) zp cf cy cx bsv bsh mdr1/mdr1s/mdr1b/mdr1tl 424 (109) lw bp bl log bm zw zcl zc as sm md r2/mdr2s/mdr2tl 428 (10a) tt log bm zw zcl zc as sm mdr3 42c (10b) ba tab tbl tws twt tf tc tbu mdr4 430 (10c) log bm te
fujistu limited prel iminary and confiden tial MB86295S 145 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1 0 9 8 7 6 5 4 3 2 1 0 fbr 440 (110) fbase xres 444 (111) xres zbr 448 (112) zbase tbr 44c (113) tbase pfbr 450 (114) pfbase cxmin 454 (115) clipxmin cxmax 458 (116) clipxmax cymin 45c (117) clipymin cymax 460 (118) clipymax txs 464 (119) txsn txsm tis 468 (11a) tisn tism toa 46c (11b) xbo sho 470 (11c) shoffs abr 474 (11d) abase fc 480 (120) fgc8/16/24 bc 484 (121) bgc8/16/24 alf 488 (122) a 48c (123) blp tbc 494 (129) bc16/24
fujistu limited prel iminary an d confidential MB86295S 146 specification manual rev1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lx0dc 540 (150) 0 0 0 0 int 0 ly0dc 544 (151) 0 0 0 0 int 0 lx1dc 548 (150) 0 0 0 0 int 0 ly1dc 54c (151) 0 0 0 0 int 0 x0dc 580 (160) 0 0 0 0 int 0 y0dc 584 (161) 0 0 0 0 int 0 x 1dc 588 (162) 0 0 0 0 int 0 y1dc 58c (163) 0 0 0 0 int 0 x2dc 590 (164) 0 0 0 0 int 0 y2dc 594 (165) 0 0 0 0 int 0
fujistu limited prel iminary and confiden tial MB86295S 147 specification manual rev1.1 10.1.7 geometry engine register list the parenthesized value in the offset field denotes the absolute address used by the setregister co mmand. base = geometrybase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gctr 000 ( - ) fo fcmt nf ff fe gs ss ps gmdr0 040 (2010) cf df st z c f gmdr1 044 (2011) bo ep aa gmdr1e - tc bc uw bm tm bp sp bo ep aa gmdr2 048 (2012) fd cf gmdr2e - tl sp fd cf 400 ( - ) dfifog
fujistu limited prel iminary an d confidential MB86295S 148 specification manual rev1.1 10 . 2 explanation of loca l memory register s terms appeared in this chapter are explained below: 1. register address indicates address of register 2. bit number indicates bit number 3. bit field name indicates name of each bit field included in register 4. r/w indicates access attribute ( read/write) of each field each symbol shown in this section denotes the following: r0 ?0? always read at read. write access is don?t care. w0 only ?0? can be written . r read enable d w write enable d rx read enable d (read values undefined) rw read and wr ite enable d rw0 read and write 0 enable d 5. initial value indicates initial value of immediately before the reset of each bit field. 6. handling of reserved bits ? 0 ? is recommended for the write value so that compatibility can be maintained with future prod ucts.
fujistu limited prel iminary and confiden tial MB86295S 149 specification manual rev1.1 10 .2 . 1 host interface registers mro (mirror register override) register address hostbaseaddress + 001c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved mro r/w r0 rw init ial value 0 0 writing a ?1b? to this register overrides use of the geometry/draw engine mirror registers which reside in the host interface. access to the mirror registers is faster than the source registers in the geometry/draw engines. for normal operat ion this register need not be used and should be kept as ?0b?. ist (interrupt status) register address hostbaseaddress + 20 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ist *1 ist rese rved resv reserved ist ist r/w rw0 r rw0 r0 rw0 r0 r 0w0 r0 rw0 r w0 initial value 0 0 0 0 0 0 0 0 0 0 *1 reserved this register indicates the current interrupt status. it shows that an interrupt request is issued when ? 1 ? is set to this register. the i nterrupt status is cleared by writing ?0? to this register. bit 0 cerr (command error flag) indicates drawing command execution error interrupt bit 1 cend (command end) indicates drawing command end interrupt bit 2 vsync (vertical sync.) indicates verti cal interrupt synchronization bit 3 fsync (frame sync.) indicates frame synchronization interrupt bit 4 syncerr (sync. error) indicates external synchronization error interrupt bit 17 and 16 reserved this field is provided for testing. normally, the rea d value is ? 0 ? , but note that it may be ? 1 ? when a drawing command error (bit 0) has occurred. bit 24 tim (timeout) indicates that an internal fifo or bus timeout has occurred. the tcs (timeout control/status) register may be read to determine the cause o f the timeout. bit 26 sii (serial interface interrupt) indicates a serial interface write/read has completed. bit 27 gi (gpio interrupt) indicates that a gpio input has changed state (0 - >1 or 1 - >0)
fujistu limited prel iminary an d confidential MB86295S 150 specification manual rev1.1 bit 28 bc (burst complete) indicates that a burst has c ompleted (as part of a burst control unit transfer). note that this bit is cleared by writing to the bst (burst status) register, not the ist. bit 29 tc (transfer complete) indicates that a transfer is complete (as controlled by the burst control unit). n ote that this bit is cleared by writing to the bst (burst status) register, not the ist. bit 30 hf (hif fatal) indicates that a fatal error occurred in a pci transfer. bit 31 ae (address error) indicates that an invalid address was specified for an acces s (eg. host interface registers as a bcu source address). im ask (interrupt mask) register address hostbaseaddress + 24 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name imask *1 imask rese rved resv reserved imask imask r/w rw r0 rw r0 r0 w0 r0 rw rw initial value 0 0 0 0 0 0 0 0 *1 reserved this register masks interrupt requests. even when the interrupt request is issued for the bit to which ? 0 ? is written, interrupt signal is not assert ed for cpu. bit 0 cerrm (command error interrupt mask) masks drawing command execution error interrupt bit 1 cendm (command interrupt mask) masks drawing command end interrupt bit 2 vsyncm (vertical sync. interrupt mask) masks vertical synchronization i nterrupt bit 3 fsynch (frame sync. interrupt mask) ma s ks frame synchronization interrupt bit 4 syncerrm ( sync error mask ) masks external synchronization error interrupt bit 24 timm (timeout mask) masks timeout interrupt. bit 26 siim (serial interface i nterrupt) masks serial interface interrupt. bit 27 gim (gpio interrupt) masks gpio interrupt. bit 28 bcm (burst complete) masks burst complete interrupt. bit 29 tcm (transfer complete) masks transfer complete interrupt.
fujistu limited prel iminary and confiden tial MB86295S 151 specification manual rev1.1 bit 30 hfm (hif fatal) masks hif fatal interrupt. bit 31 aem (address error) masks address error interrupt. srst (software reset) register address hostbaseaddress + 2c h bit number 7 6 5 4 3 2 1 0 bit field name reserved srst r/w r0 w1 initial value 0 0 this register controls sof tware reset. when ?1? is set to this register, a software reset is performed . ccf (change of clock frequency) register address hostbaseaddress + 00 38 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cge cot reserved r/w rw0 rw rw rw0 initial value 0 10 01 0 this register change s the operating frequency. bit 19 and 18 cge (clock select for geometry engine ) selects the clock for the geometry engine 11 reserved 10 166 mhz 01 133 mhz 00 100 mhz bit 17 and 16 cot (clock select for the others except - geometry engine) selects the clock for other than the geometry engine 11 reserved 10 reserved 01 133 mhz 00 100 mhz notes: 1. write ? 0 ? to the bit field other t han the above ([31:20], [15:00]). 2. operation is not as sured when the clock setting relationship is cge < cot.
fujistu limited prel iminary an d confidential MB86295S 152 specification manual rev1.1 rsw (register location switch) register address hostbaseaddress + 5c h bit number 7 6 5 4 3 2 1 0 bit field name reserved rsw r/w r0 rw i nitial value 0 0 setting this register will move the register area from the center (1fc0000) to the end of the coral area (3fc0000). this move can be performed when ? 1 ? is written to this register. set this register at the first access after reset. acce ss coral a fter about 20 bus clocks after setting the register. ip (interrupt polarity) register address hostbaseaddress + 0070 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved ip r/w r0 rw initial value 0 0 in normal mode (with ip ?0b?) the interrupt polarity is low (pci standard). if an active high interrupt is required then this may be configured by setting this register to ?1b?. ofu (override fifo use) register address hostb aseaddress + 007c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved ofu r/w r0 rw initial value 0 0 in normal mode (with ofu ?0b?) any write to the fifo address will use the fifo interface. setting this bit to ?1b? will override this and a standard bus access will be used. under normal circumstances this register should be kept as ?0b?. frst (firm reset) register address hostbaseaddress + 00a0 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved frst r/w r0 rw initial value 0 0 writing a ?1b? to this register will trigger a firm reset. this resets the complete device (as far as possible) including the pci int erface. srbs (slave burst read size)
fujistu limited prel iminary and confiden tial MB86295S 153 specification manual rev1.1 register address hostbaseaddress + 00a4 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved srbs r/w r0 rw initial value 0 0 this register sp ecifies the length of a burst read through the pci slave interface as srbs+1. by default this register is set to ?000b? indicating a burst read length of 1 dword. the maximum setting is 7 (?111b?) and indicates a burst read length of 8 dwords. iom (io mode ) register address hostbaseaddress + 00a8 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name resv. gim gd ser rgb bee sbe tce bce eee r/w r0 rw rw rw rw rw rw rw rw rw initial value 0 0 0 0 *1 0 0 0 0 *2 *1 ? initial reset value specified by burst enable pin state at reset. *2 ? initial reset value specified by transfer complete pin state at reset. this register determines the function of those coral lp pins under the control of the host in terface. it also defines the direction (input/output) of any gpio. bit 0 eee (eeprom enable) if set then the pci eeprom configuration function is enabled. this field takes it?s reset value from the transfer complete pin at system reset. note that if the r gb input is enabled then the eeprom interface us disabled regardless of the value of this register. if this field is ?0b? (and the rgb input is not enabled) then the eeprom pins operate either as serial interface pins or gpio as determined by the ser field . bit 1 bce (burst complete enable) if set to ?1b? then the burstc pin operates as burst complete. otherwise if set to ?0b? it operates as a gpio. if the rgb input is enabled this field is ignored and the burstc pin operates as an rgb input pin. bit 2 tc e (transfer complete enable) if set to ?1b? then the transc pin operates as transfer complete. otherwise if set to ?0b? it operates as gpio. bit 3 sbe (slave busy enable) if set to ?1b? then the sbusy pin operates as slave busy. otherwise if set to ?0b? i t operates as a gpio. if the rgb input is enabled this field is ignored and the sbusy pin operates as an rgb input pin. bit 4 bee ( burst enable enable ) if set to ?1b? then the bursten pin operates as burst enable. otherwise if set to ?0b? it operates as g pio. bit 5 rgb (rgb input enable) if set to ?1b? then the rgb input is enabled. this field takes its reset value from the burst enable pin at system reset and overrides all other io enable fields. bit 6 ser (serial interface enable) if set to ?1b? then t he serial interface is enabled. this field is ignored if either the rgb input or eeprom is enabled. for the serial interface strobe signal to be used the sbe field must also be clear (?0b?).
fujistu limited prel iminary an d confidential MB86295S 154 specification manual rev1.1 bit 15 to bit 7 gd (gpio direction) specifies the direction of p ins acting as gpio. if a bit is ?0b? then the pin acts as an input. otherwise if set to ?1b? it operates as an output. the mapping to pins is: bit 7: edo bit 8: edi bit 9: eck bit 10: ecs bit 11: ee bit 12: burstc bit 13: transc bit 14: sbusy bit 15: burst en bit 29 to bit 16 gim (gpio interrupt mask) masks (enables) interrupt triggering on a gpio pin by pin basis. if a bit is set to ?1b? then a change in stage of that pin (0 - >1 or 1 - >0) can trigger an interrupt via the ist register. otherwise if set to ?0b ? no interrupt will be triggered. care should be taken to disable interrupts on pins not operating as gpio inputs, otherwise unwanted interrupts may occur. the mapping to pins is: bit 16: edo bit 17: edi bit 18: eck bit 19: ecs bit 20: ee bit 21: burstc bi t 22: transc bit 23: sbusy bit 24: bursten bit 25: gi1 bit 26: gi2 bit 27: gi3 bit 28: gi4 bit 29: gi5
fujistu limited prel iminary and confiden tial MB86295S 155 specification manual rev1.1 gd (gpio data) register address hostbaseaddress + 00ac h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved gwe resv gd r/w r0 w r0 rw initial value 0 0 0 0 (*1) *1 ? initial value will be affected by state of gpio pins this register contains the gpio read/write data field and the write mask when setting gpio outputs. bit 13 to bit 0 gd (gpio data) this field is used for both reading the value of gpio inputs and specifying the value for gpio outputs. when writing to this field only those pins with the corresponding bit set in the gwe field will be changed. the bit positions refer to the following pins: bit 0: edo bit 1: edi bit 2: eck bit 3: ecs bit 4: ee bit 5: burstc bit 6: transc bit 7: sbusy bit 8: bursten bit 9: gi1 bit 10: gi2 bit 11: gi3 bit 12: gi4 bit 13: gi5 bit 24 to bit 16 gwe (gpio write enable) when writing values t o the gpio outputs using the gd field, this field specifies those bits which are being written to. if a bit in this field is ?1b? then the corresponding bit will be written to. otherwise if a bit it ?0b? the corresponding bit will remain unchanged. the bit positions refer to the following pins: bit 16: edo bit 17 edi bit 18: eck bit 19: ecs bit 20: ee bit 21: burstc bit 22: transc bit 23: sbusy bit 24: bursten
fujistu limited prel iminary an d confidential MB86295S 156 specification manual rev1.1 sic (serial interface control) register address hostbaseaddress + 00b0 h bit number 31 30 29 2 8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved ckp ckg ckd reserved doe reserved sd sp sl r/w r0 rw rw rw r0 rw r0 rw rw rw initial value 0 0 0 0 0 0 0 0 0 0 this register provides control for the se rial interface protocol and clock. bit 0 sl (strobe length) if set to ?0b? then the strobe signal is only active for one cycle at the start of a transfer. otherwise if set to ?1b? it is active for the duration of the cycle. note that this field may be ove rridden for a single transaction using the fs/fsl fields in the sid register. bit 1 sp (strobe polarity) if set to ?0b? then strobe is active low. otherwise if set to ?1b? it is active high. bit 2 sd (strobe disable) if set to ?1b? then the serial interf ace strobe is disabled. note that this field may be overridden foe a single transaction using the fs field in the sid register. bit 8 doe (data output enable control) if set to ?0b? then the data out signal is driven permanently even when transactions are not in progress. if set to ?1b? then the data out is driven only during active cycles. bit 17 to bit 16 ckd ( clock divisor ) this field specifies the serial interface clock divisor. the main system clock is divided down by one of the following factors: 00 b: 16 01b: 32 10b: 64 11b: 128 based on a 133mhz internal clock these yield frequencies of approximately 8.3mhz, 4.1mhz, 2.0 mhz and 1.0mhz respectively. bit 18 ckg (clock gating) when set to ?1b? the serial interface clock is only active during active tr ansfers. otherwise if set to ?0b? it is active continuously. note that the ckp field specifies the inactive value when the clock is static. bit 19 ckp (clock polarity) when set to ?0b? data/strobe are clocked out on a falling edge of the serial interface clock and data in is clocked in on the next falling edge. when clock gating is enabled (by setting the ckg field) the static level is low. when set to ?1b? data/strobe are clocked out on a rising edge of the serial interface clock and data in is clocked in on the next falling edge. when clock gating is enabled (by setting the ckg field) the static level is high.
fujistu limited prel iminary and confiden tial MB86295S 157 specification manual rev1.1 sid (serial interface data) register address hostbaseaddress + 00b4 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved fsl fs tls rwd r/w r0 rw rw rw rw initial value 0 0 0 0 0 this register is used to write/read serial interface data, enable a transfer and monitor a transfers progress. bit 0 to bit 7 rwd (read/write d ata) when written to specifies the serial output data. when read it contains the serial interface input data. note that data will be shifted out top bit (bit 7) first down to the bottom bit (bit 0) last. read data will be shifted in to the bottom bit and s hifted up by by each bit of the transfer. for transfer of length 8 this will yield consistent read/write data. for transfers of less than 8 bits then identical read and write data will appear different. bit 15 to bit 8 tls (transfer length/status) specifi es the length of a transfer and can be used to monitor its status. for each bit of a transfer this field is shifted up by one until it is ?00000000b?. for example, to specify a transfer of 8 bits ?00000001b? should be written. to specify a transfer of 3 bi ts ?00100000? should be written. bit 16 fs (force strobe) for a single transfer this field can be used to override settings in the sic register. if set to ?1b? then a strobe will be done with a length specified in the fsl field. bit 17 fsl (force strobe length) for a single transfer if the fs field is set this field overrides the sl field in the sic register and specifies the strobe length for the transfer. a value of ?0b? specifies a strobe only for the first active cycle of the transfer. a value of ?1b? specifies a strobe active for the whole transfer. cid (chip id register) register address hostbaseaddress + 00 f0 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cn ver r/w r0 r r initial value 0 0000_0011 0 000_0110 this is the chip identification register. bit 7 to 0 ver ( version ) this field indicates the chip ? s unique version number. note that the unique version number for the es version and that of the mass - produced ve rsion are different. 0000_0000 es 0000_0001 reserved 0000_0010 reserved for lq 0000_0011 reserved 0000_0100 reserved for lb
fujistu limited prel iminary an d confidential MB86295S 158 specification manual rev1.1 0000_0101 reserved 0000_0110 reserved for lp (coral lp value) others reserved bit 15 to 8 cn ( chip name ) this field indicates the chip name. 0000_0000 reserved 0000_0001 reserved 0000_0010 reserved 0000_0011 coral others reserved bsa ( burst source address ) register address hostbaseaddress + 8000 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name sa r/w rw initial value 0 this register specifies the initial source address for a transfer controlled by the burst control unit . its interpretation (internal coral/external pci) will depend on the transfer mode specified in the bsr register. bda ( burst destination address ) register address hostbaseaddress + 8004 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name da r/w rw initia l value 0 this register specifies the initial destination address for a transfer controlled by the burst control unit . its interpretation (internal coral/external pci) will depend on the transfer mode specified in the bsr register. bcr ( burst control regi ster ) register address hostbaseaddress + 8008 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name strt nda nsa *1 bsize tsize r/w rw rw rw r0 rw rw initial value 0 0 0 0 0 0 *1 - reserved t his register specifies the length and address manipulation performed for a transfer. it can also be used to start a transfer. bit 23 to 0 tsize this field specifies the overall transfer length as a number of dwords. a transfer will be split up into a numb er of bursts whose length is specified by the bsize field.
fujistu limited prel iminary and confiden tial MB86295S 159 specification manual rev1.1 bit 27 to 24 bsize (burst size) this field specifies the length of a bcu controlled burst as a number of dwords. one or more bursts will make up an overall transfer. note that if tsize is not an e xact multiple of bsize the final burst of a transfer will be less than bsize. bit 29 nsa (new source address) if this bit is set to ?1b? then after each burst the source address is incremented by the burst size. this means that a large continuous section of memory can be transferred. if this bit is ?0b? then successive bursts will always be from the initial specified start address. this mode could be used if transferring data from a fifo like interface. bit 30 nda (new destination address) if this bit is set to ?1b? then after each burst the destination address is incremented by the burst size. this means that data can be transferred into a large continuous section of memory. if this bit is ?0b? then successive bursts will always be to the initial specifie d destination address. this mode should be used when transferring data to the fifo. bit 31 strt (start transfer) when set to ?1b? a transfer is started. otherwise the transfer will wait until triggered wither through the burst enable register (ber) or via the external burst enable signal. bsr ( burst setup register ) register address hostbaseaddress + 800c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved xcor imode tcm bcm exten mo de r/w r0 rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 this register specifies the type of a transfer (interpretation of the addresses) and specifies the setup of control signals/status bits. bit 2 to 0 mode (transfer mode) this field specifies the mo de of the transfer and thus the interpretation of the source/destination addresses. 000b: slave mode pci to coral 001b: slave mode coral to pci 010b: coral to coral (internal transfer) 011b: reserved 100b: pci to coral (pci master read) 101b: coral to pci (pci master write) 110b: pci to pci (pci master read/write external dma transfer) 111b: reserved refer to chapter 3 for a detailed explanation of these modes. bit 3 exten (external enable) if set to ?1b? then the external bursten (burst enable) signal may be used to initiate and pause a transfer. otherwise if set to ?0b? the external bursten signal is ignored. bit 4 bcm (burst complete mask) if set to ?1b? then the external burstc signal will be active. otherwise if set to ?0b? it will remain inactive low . note that this bit does not affect the burst complete indication in the main interrupt status register (ist) or the triggering of the main external interrupt. bit 5 tcm (transfer complete mask) if set to ?1b? then the external transc signal will be acti ve. otherwise if set to ?0b? it will remain inactive low. note that this bit does not affect the transfer complete indication in the main interrupt status register (ist) or the triggering of the main external interrupt.
fujistu limited prel iminary an d confidential MB86295S 160 specification manual rev1.1 bit 6 imode (interrupt mode) this b it controls how the external burstc/transc signals operate. if set to ?0b? they are active high. otherwise if set to ?1b? they toggle at each change of state removing the need for the host to read/write the status register to clear them down. note that whe n using the burst complete/transfer complete indications via the main interrupt status register this field should always be ?0b?. bit 7 xcor ( not clear on read) if set to ?0b? then the burst complete/transfer complete fields in the burst status register a re clear on read. otherwise if set to ?1b? they must be manually written. ber ( burst enable register ) register address hostbaseaddress + 8010 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field n ame reserved abort *1 reserved reserved extst ben r/w r0 w r0 rx r0 r rw initial value 0 0 0 don?t care 0 0 0 *1 - reserved this register can be used to enable/pause/abort a transfer. it can also be used to monitor the state of the external burst enable signal. bit 0 ben (burst enable) when set to ?1b? a transfer is enabled. this bit will also become set if the strt bit in the bcr register is set. during a transfer this may be cleared to ?0b? to pause/halt a transfer at the next boundary between bursts. setting it back to ?1b? will re - enable the transfer from the position it had reached. bit 1 extst (external status) provided the state of the external burst enable signal. bit 16 abort under some circumstances clearing the ben field may not halt a trans fer. this will happen if the burst controller is waiting for an external pci master to take some action. in this case writing ?1b? to the abort field will cancel the transfer. the transfer will not be able to be re - started. bst ( burst status ) register ad dress hostbaseaddress + 8014 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name tc bc reserved tcnt r/w r r r0 r initial value 0 0 0 0 this register is used to monitor the state of the cur rent transfer. bit 23 to 0 tcnt (transfer count) gives the current transfer count as a number of dwords remaining to be transferred. bit 30 bc (burst complete) indicates the state of a burst. note that when in active high mode this field will remain high following a burst unless it is cleared either by a clear on read or by writing 0 to it.
fujistu limited prel iminary and confiden tial MB86295S 161 specification manual rev1.1 bit 31 tc (transfer complete) indicates the state of the current transfer. when set to ?1b? the transfer is complete. bcb ( burst controller buffer ) register address hostbaseaddress + 8040 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name rwdata * 8 r/w rw initial value 0 this buffer is used by the burst controller as a temporary store while executin g transfers. the user should only need to access it when using modes ?000b? and ?001b? ? the pci slave modes. these can be used to transfer large quantities of data to/from the coral lp in pci slave mode with automatic pre - fetch/write of data with address incrementing.
fujistu limited prel iminary an d confidential MB86295S 162 specification manual rev1.1 10.2.2 i 2 c interface registers bsr (bus status register) register address i2c base address + 000h bit no 7 6 5 4 3 2 1 0 bit field name bb rsc al lrb trx aas gca fbt r/w r r r r r r r r default 0 0 0 0 0 0 0 0 all bits on this reg ister are cleared while bit en on ccr register is ? 0 ? . bit7 bb (bus busy) indicate state of i2c - bus 0: stop condition was detected. 1: start condition (the bus is in use.) was detected. bit6 rsc (repeated start condition) indicate repeated start con dition this bit is cleared by writing ? 0 ? to int bit, the case of not addressed in a slave mode, the detection of start condition under bus stop, and the detection of stop condition. 0: repeated start condition was not detected. 1: start condition was dete cted again while the bus was in use. bit5 al(arbitration lost) detect arbitration lost this bit is cleared by writing ? 0 ? to int bit . 0: arbitration lost was not detected. 1: arbitration occurred during master transmission, or ? 1 ? writing was performed to mss bit while other systems were using the bus. bit4 lrb (last received bit) store acknowledge this bit is cleared by detection of start condition or stop condition. bit3 trx (transmit / receive ) indicate data receipt and data transmission. 0: rec eipt 1: transmission bit2 aas (address as slave) detect addressing this bit is cleared by detection of start condition or stop condition. 0: addressing was not performed in a slave mode. 1: addressing was performed in a slave mode. bit1 gca (general ca ll address) detect general call address (00h) this bit is cleared by detection of start condition or stop condition. 0: general call address was not received in a slave mode. 1: general call address wad received in a slave mode. bit0 fbt (first byte tra nsfer) detect the 1st byte even if this bit is set to ? 1 ? by detection of start condition, it is cleared by writing ? 0 ? on int bit or by not being addressed in a slave mode. 0: received data is not the 1st byte. 1: received data is the 1st byte (address data).
fujistu limited prel iminary and confiden tial MB86295S 163 specification manual rev1.1 bcr (bus control register) register address i2c base address + 0004h bit no 7 6 5 4 3 2 1 0 bit field name ber beie scc mss ack gcaa inte int r/w r/w0 r/w r0/w1 r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit7 ber (bus error) flag bit for request of bus error interruption when this bit is set, en bit on ccr register will be cleared, this module will be in a stop state and data transfer will be discontinued. write case 0: a request of buss error interruption is cleared. 1: don ? t care. read case 0: a bus error was not detected. 1: undefined start condition or stop condition was detected while data transfer. bit6 beie (bus error interruption enable) permit bus error interruption when both this bit and ber bit are ? 1 ? , the interruption is ge nerated. 0: prohibition of bus error interruption 1: permission of bus error interruption bit5 scc (start condition continue) generate start condition write case 0: don ? t care. 1: start condition is generated again at the time of master transmission. bit4 mss (master slave select) select master / slave mode when arbitration lost is generated in master transmission, this bit is cleared and this module becomes a slave mode. 0: this module becomes a slave mode after generating stop condition and complet ing transfer. 1: this module becomes a master mode, generates start condition and starts transfer. bit3 ack (acknowledge) permit generation of acknowledge at the time of data reception this bit becomes invalid at the time of address data reception in a slave mode. 0: acknowledge is not generated. 1: acknowledge is generated. bit2 gcaa(general call address acknowledge) permit generation of acknowledge at the time of general call address reception 0: acknowledge is not generated. 1: acknowledge is gener ated. bit1 inte (interrupt enable) permit interruption when this bit is ? 1 ? interruption is generated if int bit is ? 1 ? . 0: prohibition of interrupt 1: permission of interrupt bit0 int (intrrupt) flag bit for request of interruption for transfer end when this bit is ? 1 ? scl line is maintained at ? l ? level. if this bit is cleared by being written ? 0 ? , scl line is released and the following byte transfer is started. moreover, it is
fujistu limited prel iminary an d confidential MB86295S 164 specification manual rev1.1 written ? 0 ? , scl line is released and the following byte transfer is started. moreover, it is reset to ? 0 ? by generating of start condition or stop condition at the t ime of a master. write case 0: the flag is cleared. 1: don ? t care. read case 0: the transfer is not ended. 1: it is set when 1 byte transfer including the acknowledge bit is completed and it corresponds to the following conditions. - it is a bus master. - it is an addressed slave. - it was going to generate start condition while other systems by which arbitration lost happened used the bus. competition of scc, mss and int bit competition of the following byte transfer, generation of start condition and ge neration of stop condition happens by the simultaneous writing of scc, mss and int bit. the priority at this case is as follows. 1) the following byte transfer and generation of stop condition if ? 0 ? is written to int bit and ? 0 ? is written to mss bit, pr iority will be given to ? 0 ? writing to mss bit and stop condition will be generated. 2) the following byte transfer and generation of start condition if ? 0 ? is written to int bit and ? 1 ? is written to scc bit, priority will be given to ? 1 ? writing to scc b it and start condition will be generated. 3) generation of start condition and stop condition the simultaneous writing of ? 1 ? to scc bit and ? 0 ? to mss bit is prohibition.
fujistu limited prel iminary and confiden tial MB86295S 165 specification manual rev1.1 ccr (clock control register) register address i2c base address + 0008h bit no 7 6 5 4 3 2 1 0 bit field name - hsm en cs4 cs3 cs2 cs1 cs0 r/w r1 r/w r/w r/w r/w r/w r/w r/w default 1 0 0 - - - - - bit7 nonuse ? 1 ? is always read at read. bit6 hsm (high speed mode) select standard - mode / high - speed - mode 0: standard - mode 1: hig h - speed - mode bit5 en (enable) permission of operation when this bit is ? 0 ? , each bit of bsr and bcr register (except ber and beie bit) is cle a red. this bit is cleared when ber bit is set. 0: prohibition of operation 1: permission of operation bit4 cs4 - 0 (clock period select4 - 0) set up the frequency of a serial transfer clock frequency fscl of a serial transfer clock is shown as the following formula. please set up fscl not to exceed the value shown below at the time of master operation. standar d - mode: 100khz high - speed - mode: 400khz standard - mode a fscl = (2 x m)+2 high - speed - mode a fscl = int(1.5 x m)+2 a: i2c system clock = 16.6mhz +2 cycles are minimum overhead to confirm that the output level of scl terminal changed. wh en the delay of the positive edge of scl terminal is large or when the clock is extended by the slave device, it becomes larger than this value. the value of m becomes like the following page to the value of cs 4 - 0.
fujistu limited prel iminary an d confidential MB86295S 166 specification manual rev1.1 m cs4 cs3 cs2 cs1 cs0 standa rd high - speed 0 0 0 0 0 65 inhibited 0 0 0 0 1 66 inhibited 0 0 0 1 0 67 inhibited 0 0 0 1 1 68 inhibited 0 0 1 0 0 69 inhibited 0 0 1 0 1 70 inhibited 0 0 1 1 0 71 inhibited 0 0 1 1 1 72 inhibited 0 1 0 0 0 73 9 0 1 0 0 1 74 10 0 1 0 1 0 75 11 0 1 0 1 1 76 12 0 1 1 0 0 77 13 0 1 1 0 1 78 14 0 1 1 1 0 79 15 0 1 1 1 1 80 16 1 0 0 0 0 81 17 1 0 0 0 1 82 18 1 0 0 1 0 83 19 1 0 0 1 1 84 20 1 0 1 0 0 85 21 1 0 1 0 1 86 22 1 0 1 1 0 87 23 1 0 1 1 1 88 24 1 1 0 0 0 89 25 1 1 0 0 1 90 26 1 1 0 1 0 91 27 1 1 0 1 1 92 28 1 1 1 0 0 93 29 1 1 1 0 1 94 30 1 1 1 1 0 95 31 1 1 1 1 1 96 32
fujistu limited prel iminary and confiden tial MB86295S 167 specification manual rev1.1 address register(adr) register address i2c base address + 000ch bit no 7 6 5 4 3 2 1 0 bit field name - a6 a5 a4 a3 a2 a1 a0 r/w r1 r/w r/w r/w r/w r/w r/w r/w default 1 - - - - - - - bit7 nonuse ? 1 ? is always read at read. bit6 - 0 a6 - 0 (address6 - 0) store slave address in a slave mode it is compared with dar register after address data reception, and when in agreement, acknowledge is transmitted to a master. data register(dar) register address i2c base address + 0010h bit no 7 6 5 4 3 2 1 0 bit field name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default - - - - - - - - bit7 - 0 d7 - 0 (data7 - 0) store se rial data this is a data register for serial data transfer. the data is transferred from msb. at the time of data reception (trx=0) the data output is set to ? 1 ? . the writing side of this register is a double buffer. when the bus is in use (bb=1), the writ e data is loaded to the register for serial transfer for every transfer. at the time of read - out, the receiving data is effective only when int bit is set because the register for serial transfer is read directly at this time.
fujistu limited prel iminary an d confidential MB86295S 168 specification manual rev1.1 10.2.3 graphics memory in terface registers mmr (memory i/f mode register) register address hostbaseaddress + fffc h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name *1 twr reserved *1 *1 trrd trc trp tras trcd lowd r ts raw asw cl r/w rw rw r r1 w0 r rw rw rw rw rw rw rw rw rw rw initial value 0 0 don ? t care 1 0 00 0000 00 000 00 00 000 000 0 000 *1: reserved this register sets the mode of the graphics memory interface. a value must be written to this register afte r a reset. ( when default setting is performed, a value must also be written to this register.) only write once to this register; do not change the written value during operation. this register is not initialized at a software reset. bit 2 to 0 cl (cas l atency) sets the cas latency. write the same value as this field, to the mode register for sdram 011 cl3 010 cl2 other than the above setting disabled bit 3 asw (attached sdram bit width) sets the bit width of the data bus (memory bus width mode) 1 64 bit 0 32 bit bit 6 to 4 saw (sdram address width) sets the bit width of the sdram address 001 15 bit bank 2 bit row 13 bit col 9 bit sdram 111 14 bit bank 2 bit row 12 bit col 9 bit sdram 110 14 bit bank 2 bit row 12 bit col 8 bi t sdram 101 13 bit bank 2 bit row 11 bit col 8 bit sdram 100 12 bit bank 1 bit row 11 bit col 8 bit fcram other than the above setting disabled bit 9 to 7 rts (refresh timing setting) sets the refresh interval 000 refresh is performed every 3 84 internal clocks. 111 refresh is performed every 1552 internal clocks. 001 to 110 refresh is performed every ? 64 n ? internal clocks in the 64 to 384 range.
fujistu limited prel iminary and confiden tial MB86295S 169 specification manual rev1.1 bit 11 and 10 lowd sets the count of clocks secured for the period from the instant th e ending data is output to the instant the write command is issued. 10 2 clocks other than the above setting disabled bit 13 and 12 trcd sets the wait time secured from the bank active to cas. the clock count is used to express the wait time. 11 3 clocks 10 2 clocks 01 1 clock 00 0 clock bit 16 to 14 tras sets the minimum time for 1 bank active. the clock count is used to express the minimum time. 111 7 clocks 110 6 clocks 101 5 clocks 100 4 clocks 011 3 clocks 010 2 cl ocks other than the above setting disabled bit 18 and 17 trp sets the wait time secured from the pre - charge to the bank active. the clock count is used to express the wait time. 11 3 clocks 10 2 clocks 01 1 clock bit 22 to 19 trc this field sets the wait time secured from the refresh to the bank active. the clock count is used to express the wait time. 1010 10 clocks 1001 9 clocks 1000 8 clocks 0111 7 clocks 0110 6 clocks 0101 5 clocks 0100 4 clocks
fujistu limited prel iminary an d confidential MB86295S 170 specification manual rev1.1 0011 3 clocks othe r than the above setting disabled bit 24 and 23 trrd sets the wait time secured from the bank active to the next bank active. the clock count is used to express the wait time. 11 3 clocks 10 2 clocks bit 26 reserved always write ? 0 ? at wr ite . ? 1 ? is always read at read. bit 30 twr sets the write recovery time (the time from the write command to the read or to the pre - charge command). 1 2 clocks 0 1 clock
fujistu limited prel iminary and confiden tial MB86295S 171 specification manual rev1.1 10.2.4 display control register dcm (display control mode) register address displaybaseaddress + 00 h (displaybaseaddress + 100 h ) bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name cks reserve d reserve d sc eeq ode reserve d reserve d sf esy sync r/w rw rw0 rx rw rw rw rx rx rw rw rw initial value 0 0 x 11110 0 0 x x 0 0 00 this register controls the display count mode. it is not initialized by a software reset. this register is mapped to two addresses. the difference between the two registers is the format of the frequency division rate setting ( sc ) . bit 1 to 0 sync (synchronize) set synchronization mode x0 non - interlace mode 10 interlace mode 11 interlace video mode bit 2 esy (external synchronize) sets external synchronization mode 0: external synchronization disable d 1: external synch ronization enable d bit 3 sf (synchronize signal output format) sets format of synchronization (vsync, hsync) signals 0: negative logic output 1: positive logic output bit 7 eeq (enable equalizing pulse) sets ccync signal mode 0: does not insert equalizing pulse into ccync signal 1: inserts equalizing pulse into ccync signal bit 13 to 8 sc (scaling) divides display reference clock by the preset ratio to generate dot clock offset = 0 offset = 100 h x 00000 frequency not divided 000 000 frequency not divided x 00001 frequency division rate = 1/ 4 000001 frequency division rate = 1/2 x 00010 frequency division rate = 1/ 6 000010 frequency division rate = 1/3 x00011 frequency division rate = 1/8 000011 frequency division rate = 1/4 : : x 11111 frequency division rate = 1/64 111111 frequency division rate = 1/64
fujistu limited prel iminary an d confidential MB86295S 172 specification manual rev1.1 when n is set, with offset = 0, the frequency division rate is 1/(2n + 2). when m is set, with offset = 100h, the frequency division rate is 1/(m + 1). basically , the se are setting parameters with the same function ( 2n + 2 = m + 1 ) . because of this, m = 2n + 1 is established. when n is set to the sc field with offset = 0, 2n + 1 is reflected with offset = 100h. also, when pll is selected as the reference clock, fre quency division rates 1/1 to 1/5 are non - functional even when set; other frequency division rates are assigned. bit 15 cks (clock source) selects reference clock 0: internal pll output clock 1: dclki input
fujistu limited prel iminary and confiden tial MB86295S 173 specification manual rev1.1 dce (display controller enable) regis ter address displaybaseaddress + 02 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name den reserved l45e l23e l1e l0e r/w rw r0 rw rw rw rw initial value 0 0 0 0 0 0 this register controls enabling the video signal output and display of each layer. layer enabling is specified in four - layer units to maintain backward compatibility with previous products. bit 0 l0e ( l0 layer enable ) enables display of the l0 layer. the l0 layer corresponds to the c layer for previous products. 0: do es not display l0 layer 1: displays l0 layer bit 1 l1e ( l1 layer enable ) enables display of the l1 layer. the l1 layer corresponds to the w layer for previous products. 0: does not display l1 layer 1: displays l1 layer bit 2 l23e ( l2 & l3 layer enable ) enables simultaneous display of the l2 and l3 layers. these layers correspond to the m layer for previous products. 0: does not display l2 and l3 layer 1: displays l2 and l3 layer bit 3 l45e ( l4 & l5 layer enable ) enables simulta neous display of the l4 and l5 layers. these layers correspond to the b layer for previous products. 0: does not display l4 and l5 layer 1: displays l4 and l5 layer bit 15 den (display enable) enables display 0: does not output display signal 1: outputs display signal
fujistu limited prel iminary an d confidential MB86295S 174 specification manual rev1.1 dce e (display controller extend enable) register address displaybaseaddress + 1 02 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name den reserved l5e l4e l3e l2e l1e l0e r/w rw r0 rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register controls enabling the video signal output and display of each layer. this register has the same function as dce. bit 0 l0e ( l0 layer enable ) enables l0 layer display 0: does not display l0 layer 1: displays l0 l ayer bit 1 l1e ( l1 layer enable ) enables l1 layer display 0: does not display l1 layer 1: displays l1 layer bit 2 l2e ( l2 layer enable ) enables l2 layer display 0: does not display l2 layer 1: displays l2 layer bit 3 l3e ( l3 layer e nable ) enables l3 layer display 0: does not display l3 layer 1: displays l3 layer bit 4 l4e ( l4 layer enable ) enables l4 layer display 0: does not display l4 layer 1: displays l4 layer bit 5 l5e ( l5 layer enable ) enables l5 layer disp lay 0: does not display l5 layer 1: displays l5 layer bit 15 den ( display enable ) enables display 0: does not output display signal 1: outputs display signal
fujistu limited prel iminary and confiden tial MB86295S 175 specification manual rev1.1 htp (horizontal total pixels) register address displaybaseaddress + 06 h bit numb er 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved htp r/w r0 rw initial value 0 don?t care this register controls the horizontal total pixel count. setting value + 1 is the total pixel count. hdp (horizontal display period) register add ress displaybaseaddress + 08 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved hdp r/w r0 rw initial value 0 don?t care this register controls the total horizontal display period in unit of pixel clock s . setting value + 1 is the pixel count for the display period. hdb (horizontal display boundary) register address displaybaseaddress + 0a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved hdb r/w r0 rw initial value 0 don?t care this register contro ls the display period of the left part of the window in unit of pixel clocks. setting value + 1 is the pixel count for the display period of the left part of the window . when the window is not divided into right and left before display, set the same valu e as hdp. hsp (horizontal synchronize pulse position) register address displaybaseaddress + 0c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved hsp r/w r0 rw initial value 0 don?t care this register controls the pulse positio n of the horizontal synchronization signal in unit of pixel clock s . when the clock count since the start of the display period reaches s etting value + 1, the horizontal synchronization signal is asserted. hsw (horizontal synchronize pulse width) register address displaybaseaddress + 0e h bit number 7 6 5 4 3 2 1 0 bit field name hsw r/w rw initial value don?t care this register controls the pulse width of the horizontal synchronization signal in unit of pixel clock s . setting value + 1 is the pulse wi dth clock count.
fujistu limited prel iminary an d confidential MB86295S 176 specification manual rev1.1 vsw (vertical synchronize pulse width) register address displaybaseaddress + 0f h bit number 7 6 5 4 3 2 1 0 bit field name reserved vsw r/w r0 rw initial value 0 don?t care this register controls the pulse width of vertical synchron ization signal in unit of raster. setting value + 1 is the pulse width raster count. vtr (vertical total rasters) register address displaybaseaddress + 12 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved vtr r/w r0 rw initial value 0 don?t care this register controls the vertical total raster count. setting value + 1 is the total raster count. for the interlace display, setting value + 1.5 is the total raster count for 1 field; 2 setting value + 3 is the total raster coun t for 1 frame (see section 8.3.2 ). vsp (vertical synchronize pulse position) register address displaybaseaddress + 14 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved vsp r/w r0 rw initial value 0 don?t care this register con trols the pulse position of vertical synchronization signal in unit of raster. the vertical synchronization pulse is asserted starting at the s etting value + 1 st raster relative to the display start raster. vdp (vertical display period) register address displaybaseaddress + 16 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved vdp r/w r0 rw initial value 0 don?t care this register controls the vertical display period in unit of raster. setting value + 1 is the count of raster to be displayed.
fujistu limited prel iminary and confiden tial MB86295S 177 specification manual rev1.1 l0m ( l0 layer mode ) register address displaybaseaddress + 20 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l0c reserved reserved cw reserved ch r/w rw r0 r0 rw r0 rw i nitial value 0 0 0 don?t care 0 don?t care bit 11 to 0 l0h ( l0 layer height ) specifies the height of the logic frame of the l0 layer in pixel units. setting value + 1 is the height bit 23 to 16 l0w ( l0 layer memory width ) sets the memory width ( stride) of the logic frame of the l0 layer in 64 - byte units bit 31 l0c ( l0 layer color mode ) sets the color mode for l0 layer 0 indirect color (8 bits/pixel) mode 1 direct color (16 bits/pixel) mode l0em ( l0 - layer extended mode ) register address displaybaseaddress + 110 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ----- 4 3 2 1 0 bit field name l0ec reserved l0pb reserved l0wp r/w rw r0 rw r0 rw initial value 0 0 0 bit 0 l0 wp ( l0 layer window position ena ble ) selects the display position of l0 layer 0 compatibility mode display (c layer supported) 1 window display bit 23 to 20 l0pb ( l0 layer palette base ) shows the value added to the index when subtracting palette of l0 layer. 16 times of sett ing value is added. bit 31 and 30 l0ec ( l0 layer extended color mode ) sets extended color mode for l0 layer 00 mode determined by l0c 01 direct color (24 bits/pixel) mode 1x reserved
fujistu limited prel iminary an d confidential MB86295S 178 specification manual rev1.1 l0oa ( l0 layer origin address ) register address displaybas eaddress + 24 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0oa r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 0 layer. since lower 4 bits are fixed at ? 0 ? , address 16 - byte - aligned. l0da ( l0 - layer display address ) register address displaybaseaddress + 28 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field n ame reserved l0da r/w r0 rw initial value 0 don?t care this register sets the display origin address of the l0 layer. for the direct color mode (16 bits/pixel), the lower 1 bit is ? 0 ? , and this address is treated as being aligned in 2 byte s. l0dx ( l0 - l ayer display position x ) register address displaybaseaddress + 2c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0dx r/w r0 rw initial value 0 don?t care this register sets the display starting position (x coordinates) of t he l0 layer on the basis of the origin of the logic frame in pixel s. l0dy ( l0 - layer display position y ) register address displaybaseaddress + 2e h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0dy r/w r0 rw initial value 0 do n?t care this register sets the display starting position (y coordinates) of the l0 layer on the basis of the origin of the logic frame in pixel s.
fujistu limited prel iminary and confiden tial MB86295S 179 specification manual rev1.1 l0wx ( l0 layer window position x ) register address displaybaseaddress + 114 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0wx r/w r0 rw initial value 0 this register sets the x coordinates of the display position of the l0 layer window. l0wy ( l0 layer window position y ) register address displaybaseaddress + 116 h bit number 1 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0wy r/w r0 rw initial value 0 this register sets the y coordinates of the display position of the l0 layer window. l0 ww ( l0 layer window width) register address displaybaseaddress + 118 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0 ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l0 layer w indow. do not specify ?0?. l0 wh ( l0 layer window h eight) register address displaybaseaddress + 1 1a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of the l0 layer w indow. setting value + 1 is the height.
fujistu limited prel iminary an d confidential MB86295S 180 specification manual rev1.1 l1m (l1 - layer mode) register address displaybaseaddress + 30 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 5 4 3 2 1 0 bit field name l1c l1yc l1cs l1im reserve d l1w reserve d r/w r0 initial value 0 bit 23 to 16 l1 w ( l1 layer memory width) set s the memory width (stride) of the logic frame of the w layer in unit of 64 byte s bit 28 l1 im ( l1 layer interlace mode) sets video capture mode when l1 cs in captur e mode 0: normal mode 1: for non - interlace display, displays captured video graphics in weave mode for interlace and video display, buffers are managed in frame units (pair of odd field and even field). bit 29 l1 cs ( l1 layer capture synchronize ) sets whether the layer is used as normal display layer or as video capture 0: normal mode 1: capture mode bit 30 l1 yc ( l1 layer yc mode) sets color format of l1 layer the yc mode must be set for video capture. 0: rgb mode 1: yc mode l1 c ( l1 layer color mode) sets color mode for l1 layer 0: indirect color (8 bits/pixel) mode bit 3 1 1: direct color (16 bits/pixel) mode
fujistu limited prel iminary and confiden tial MB86295S 181 specification manual rev1.1 l1em ( l1 layer extended mode ) register address displaybaseaddress + 120 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 4 3 2 1 0 bit field name l0ec reserved l0pb reserved r/w rw r0 rw r0 initial value 0 0 bit 23 to 20 l1pb ( l1 layer palette base ) shows the value added to the index when subtracting palette of l1 layer. 16 t imes of setting value is added. bit 31 to 30 l1ec ( l1 layer extended color mode ) sets extended color mode for l1 layer 00 mode determined by l0c 01 direct color (24 bits/pixel) mode 1x reserved l1da ( l1 layer display address ) register address displaybaseaddress + 34 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0da r/w r0 rw initial value 0 don?t care this register sets the display origin address of the l1 layer. for the direct color mode (16 bits/pixel), the lower 1 bit is ? 0 ? , and this register is treated as being aligned in 2 byte s. wraparound processing is not performed for the l1 layer, so the frame origin linear address and display position (x coordinates, and y coordinates) are not specified. l1wx ( l1 layer window position x ) register address displaybaseaddress + 124 h (dispplaybaseaddress + 18 h ) bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0wx r/w r0 rw initial value 0 don? t care this register sets the x coordinates of the display position of the l1 layer window. this register is placed in two address spaces. the parenthesized address is the register address to maintain compatibility with previous products. the same appl ies to l1wy, l1ww, and l1wh. l1wy ( l1 layer window position y ) register address displaybaseaddress + 126 h (dispplaybaseaddress + 1a h ) bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0wy r/w r0 rw initial value 0 don?t care t his register sets the y coordinates of the display position of the l1 layer window.
fujistu limited prel iminary an d confidential MB86295S 182 specification manual rev1.1 l1ww ( l1 layer window width ) register address displaybaseaddress + 128 h (dispplaybaseaddress + 1c h ) bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name rese rved l0ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l1 layer w indow. do not specify ?0?. l1 wh ( l1 layer window height) register address displaybaseaddress + 1 2a h (( displaybaseaddre ss + 1 e h ) bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of the l1 layer window. setting value + 1 is the height.
fujistu limited prel iminary and confiden tial MB86295S 183 specification manual rev1.1 l2m ( l2 layer mode ) register address displaybaseaddress + 40 h bit number 31 30 29 28 27 - - 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l2c l2flp reserved l2w reserved l2h r/w rw rw r0 rw r0 rw initial value 0 do n?t care 0 don?t care bit 11 to 0 l2h ( l2 layer height ) specifies the height of the logic frame of the l2 layer in pixel units. setting value + 1 is the height bit 23 to 16 l2w ( l2 layer memory width ) set s the memory width (stride) of the logic frame of the l2 layer in 64 - byte units bit 30 and 29 l2flp (l2 layer flip mode) set s flipping mode for l2 layer 00 display s frame 0 01 display s frame 1 10 switch es frame 0 and 1 alternately for display 11 reserved bit 31 l2c ( l2 layer col or mode ) sets the color mode for l2 layer 0 indirect color (8 bits/pixel) mode 1 direct color (16 bits/pixel) mode
fujistu limited prel iminary an d confidential MB86295S 184 specification manual rev1.1 l2em ( l2 layer extended mode ) register address displaybaseaddress + 130 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ----- 4 3 2 1 0 bit field name l2ec reserved l2pb reserved l2om l0wp r/w rw r0 rw r0 rw rw initial value 00 0 0 0 0 bit 0 l2 wp ( l2 layer window position enable ) selects the display position of l2 layer 0 compatibility mode dis play (ml layer supported) 1 window display bit 1 l2om (l2 layer overlay mode) selects the overlay mode for l2 layer 0 compatibility mode 1 extended mode bit 23 to 20 l2pb ( l2 layer palette base ) shows the value added to the index when sub tracting palette of l2 layer. 16 times of setting value is added. bit 31 and 30 l2ec ( l2 layer extended color mode ) sets extended color mode for l2 layer 00 mode determined by l2c 01 direct color (24 bits/pixel) mode 1x reserved
fujistu limited prel iminary and confiden tial MB86295S 185 specification manual rev1.1 l 2 oa0 ( l2 l ayer origin address 0) register address displaybaseaddress + 44 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d l 2 oa0 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 2 layer in frame 0 . since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. l 2 da0 (l 2 layer display address 0) register address displaybaseaddress + 48 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d l 2 da0 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 2 layer in frame 0. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l 2 oa1 (l 2 layer origin address 1) register address displaybaseaddress + 4c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d l 2 oa1 r/ w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 2 layer in frame 1 . since lower 4 - bits are fixed to ?0?, this address is 16 - byte aligned. l 2 da1 (l 2 layer display address 1) register address di splaybaseaddress + 50 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d l 2 da1 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 2 layer in frame 1 . for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l 2 dx (l 2 layer display position x) register address displaybaseaddress + 54 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d l 2 dx r/w r0 rw initial value 0 don?t care this register sets the display starting position (x coordinates) of the l2 layer on the basis of the origin of the logic frame in pixel s.
fujistu limited prel iminary an d confidential MB86295S 186 specification manual rev1.1 l 2 dy (l 2 layer display position y) register address displaybaseaddres s + 56 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l 2 dy r/w r0 rw initial value 0 don?t care this register sets the display starting position (y coordinates) of the l2 layer on the basis of the origin of the logic frame i n pixel s. l2wx ( l2 layer window position x ) register address displaybaseaddress + 134 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l2wx r/w r0 rw initial value 0 don?t care this register sets the x coordinates of the disp lay position of the l2 layer window. l2wy ( l2 layer window position y ) register address displaybaseaddress + 138 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l2wy r/w r0 rw initial value 0 don?t care this register sets th e y coordinates of the display position of the l2 layer window. l2 ww ( l2 layer window width) register address displaybaseaddress + 13a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l2 ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l2 layer window. do not specify ?0?. l2 wh ( l2 layer window height) register address displaybaseaddress + 1 3c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name r eserved l2 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of the l2 layer window. setting value + 1 is the height.
fujistu limited prel iminary and confiden tial MB86295S 187 specification manual rev1.1 l3 m (l 3 layer mode) register address displaybaseaddress + 58 h bit number 3 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l 3 c l 3 flp reserve d l 3 w reserve d l 3 h r/w rw r0 r0 rw r0 rw initial value 0 0 0 don?t care 0 don?t care bit 11 to 0 l3 h ( l3 layer height) specifies the height of the logic frame of the l3 layer in pixel units. setting value + 1 is the height bit 23 to 16 l3 w ( l3 layer memory width) set s the memory width (stride) of the logic frame of the l3 layer in 64 - byte units bit 30 and 29 l3 flp ( l3 layer flip mode) set s flipping mode for l3 layer 00 display s frame 0 01 display s frame 1 10 switch es frame 0 and 1 alternately for display 11 reserved bit 31 l3 c ( l3 layer color mode) sets the color mode for l3 layer 0 indirect color (8 bits/pi xel) mode 1 direct color (16 bits/pixel) mode
fujistu limited prel iminary an d confidential MB86295S 188 specification manual rev1.1 l3em ( l3 layer extended mode ) register address displaybaseaddress + 140 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 4 3 2 1 0 bit field name l3ec reserved l3pb res erved l3om l3wp r/w rw r0 rw r0 rw rw initial value 00 0 0 0 0 bit 0 l3 wp ( l3 layer window position enable ) selects the display position of l3 layer 0 compatibility mode display (mr layer supported) 1 window display bit 1 l3om (l3 layer ove rlay mode) selects the overlay mode for l3 layer 0 compatibility mode 1 extended mode bit 23 to 20 l3pb ( l3 layer palette base ) shows the value added to the index when subtracting palette of l3 layer. 16 times of setting value is added. bi t 31 and 30 l3ec ( l3 layer extended color mode ) sets extended color mode for l3 layer 00 mode determined by l3c 01 direct color (24 bits/pixel) mode 1x reserved
fujistu limited prel iminary and confiden tial MB86295S 189 specification manual rev1.1 l3oa0 ( l3 layer origin address 0 ) register address displaybaseaddress + 5c h bit num ber 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3oa0 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 3 layer in frame 0 . s ince lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. l3da0 ( l3 layer display address 0 ) register address displaybaseaddress + 60 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field n ame reserved l3da0 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 3 layer in frame 0. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l3oa1 ( l3 layer origin addre ss 1 ) register address displaybaseaddress + 64 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3oa1 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin a ddress of the logic frame of the l 3 layer in frame 1 . since lower 4 - bits are fixed to ?0?, this address is 16 - byte aligned. l3oa1 ( l3 layer display address 1 ) register address displaybaseaddress + 68 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3da1 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 3 layer in frame 1. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l3dx ( l3 layer display position x ) register address displaybaseaddress + 6c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3dx r/w r0 rw initial value 0 don?t care this register set s the display start ing position (x coordinate s ) of the l 3 layer on the basis of the origin of the logic frame in pixels .
fujistu limited prel iminary an d confidential MB86295S 190 specification manual rev1.1 l3dy ( l3 layer display position y ) register address displaybaseaddress + 6e h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reser ved l3dy r/w r0 rw initial value 0 don?t care this register sets the display starting position (y coordinates) of the l3 layer on the basis of the origin of the logic frame in pixel s. l3wx ( l3 layer window position x ) register address displaybaseaddres s + 140 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3wx r/w r0 rw initial value 0 don?t care this register sets the x coordinates of the display position of the l3 layer window. l3wy ( l3 layer window position y ) register address displaybaseaddress + 142 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3wy r/w r0 rw initial value 0 don?t care this register sets the y coordinates of the display position of the l3 layer window. l3 ww ( l3 layer window width) register address displaybaseaddress + 144 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3 ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l3 layer window. do not specify ?0?. l3 wh ( l3 - layer window height) register address displaybaseaddress + 1 46 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of the l3 layer window. setting value + 1 is the height.
fujistu limited prel iminary and confiden tial MB86295S 191 specification manual rev1.1 l4m ( l4 layer mode ) register address displaybaseaddress + 70 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l4c l4flp reserved l4w reserved l4h r/w rw rw r0 rw r0 rw initial value 0 don?t care 0 don?t care bit 11 to 0 l4h ( l4 layer height ) specifies the height of the logic frame of the l4 layer in pixel units. setting value + 1 is t he height bit 23 to 16 l4w ( l4 layer memory width ) set s the memory width ( stride ) logic frame of the l4 layer in 64 - byte units bit 30 and 29 l4flp (l4 layer flip mode) set s flipping mode for l4 layer 00 display s frame 0 01 display s frame 1 10 switch es frame 0 and 1 alternately for display 11 reserved bit 31 l4c ( l4 layer color mode ) sets the color mode for l4 layer 0 indirect color (8 bits/pixel) mode 1 direct color (16 bits/pixel) mode
fujistu limited prel iminary an d confidential MB86295S 192 specification manual rev1.1 l4em ( l4 layer extended mode ) register address displaybaseaddress + 150 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 4 3 2 1 0 bit field name l4ec reserved l4pb reserved l4om l4wp r/w rw r0 rw r0 rw rw initial value 00 0 0 0 0 bit 0 l4 wp ( l4 layer window position enable ) selects the display position of l4 layer 0 compatibility mode display (bl layer supported) 1 window display bit 1 l4om (l4 layer overlay mode) selects the overlay mode for l4 layer 0 compatibility mode 1 extended mo de bit 23 to 20 l4pb ( l4 layer palette base ) shows the value added to the index when subtracting palette of l4 layer. 16 times of setting value is added. bit 31 and 30 l4ec ( l4 layer extended color mode ) sets extended color mode for l4 layer 00 mode determined by l4c 01 direct color (24 bits/pixel) mode 1x reserved
fujistu limited prel iminary and confiden tial MB86295S 193 specification manual rev1.1 l4oa0 ( l4 layer origin address 0 ) register address displaybaseaddress + 74 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4oa0 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 4 layer in frame 0 . since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. l4da0 ( l4 layer disp lay address 0 ) register address displaybaseaddress + 78 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4da0 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 4 layer in frame 0. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l4oa1 ( l4 layer origin address 1 ) register address displaybaseaddress + 7c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4oa1 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 4 layer in frame 1 . since lower 4 - bits are fixed to ?0 ?, this address is 16 - byte aligned. l4oa1 ( l4 layer display address 1 ) register address displaybaseaddress + 80 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4da1 r/w r0 rw in itial value 0 don?t care this register sets the origin address of the l 4 layer in frame 1. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l4dx ( l4 layer display position x ) register address displayba seaddress + 84 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4dx r/w r0 rw initial value 0 don?t care this register set s the display start ing position (x coordinate s ) of the l 4 layer on the basis of the origin of the logic frame in pixels .
fujistu limited prel iminary an d confidential MB86295S 194 specification manual rev1.1 l4dy ( l4 layer display position y ) register address displaybaseaddress + 86 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4dy r/w r0 rw initial value 0 don?t care this register sets the display starting position (y coordinates) of the l4 layer on the basis of the origin of the logic frame in pixel s. l4wx ( l4 layer window position x ) register address displaybaseaddress + 154 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4wx r/w r0 rw initial value 0 don?t care this register sets the x coordinates of the display position of the l4 layer window. l4wy ( l4 layer window position y ) register address displaybaseaddress + 156 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bi t field name reserved l4wy r/w r0 rw initial value 0 don?t care this register sets the y coordinates of the display position of the l4 layer window. l4 ww ( l4 layer window width) register address displaybaseaddress + 158 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4 ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l4 layer window. do not specify ?0?. l4 wh ( l4 layer window height) register address displ aybaseaddress + 1 5a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of the l4 layer window. setting value + 1 is t he height.
fujistu limited prel iminary and confiden tial MB86295S 195 specification manual rev1.1 l5m ( l5 layer mode ) register address displaybaseaddress + 88 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l5c l5flp reserved l5w reserved l5h r/w rw rw r0 rw r0 rw initial value 0 don?t care 0 don?t care bit 11 to 0 l5h ( l5 layer height ) specifies the height of the logic frame of the l5 layer in pixel units. setting value + 1 is the height bit 23 to 16 l5w ( l5 layer memory width ) set s the memory width ( stride ) l ogic frame of the l5 layer in 64 - byte units bit 30 and 29 l5flp (l5 layer flip mode) set s flipping mode for l5 layer 00 display s frame 0 01 display s frame 1 10 switch es frame 0 and 1 alternately for display 11 reserved bit 31 l5c ( l5 laye r color mode ) sets the color mode for l5 layer 0 indirect color (8 bits/pixel) mode 1 direct color (16 bits/pixel) mode
fujistu limited prel iminary an d confidential MB86295S 196 specification manual rev1.1 l5em ( l5 layer extended mode ) register address displaybaseaddress + 110 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 4 3 2 1 0 bit field name l5ec reserved l5pb reserved l5om l5wp r/w rw r0 rw r0 rw rw initial value 00 0 0 0 0 bit 0 l5 wp ( l5 layer window position enable ) selects the display position of l5 layer 0 compatibility mod e display (br layer supported) 1 window display bit 1 l5om (l5 layer overlay mode) selects the overlay mode for l5 layer 0 compatibility mode 1 extended mode bit 23 to 20 l5pb ( l5 layer palette base ) shows the value added to the index whe n subtracting palette of l5 layer. 16 times of setting value is added. bit 31 to 30 l5ec ( l5 layer extended color mode ) sets extended color mode for l5 layer 00 mode determined by l5c 01 direct color (24 bits/pixel) mode 1x reserved
fujistu limited prel iminary and confiden tial MB86295S 197 specification manual rev1.1 l5oa0 ( l5 layer origin address 0 ) register address displaybaseaddress + 8c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved broa0 r/w r0 rw r0 initial value 0 don?t care 0000 this regis ter sets the origin address of the logic frame of the l 5 layer in frame 0 . since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. l5da0 ( l5 layer display address 0 ) register address displaybaseaddress + 90 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5da0 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 5 layer in frame 0. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l5oa1 ( l5 layer origin address 1 ) register address displaybaseaddress + 94 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5oa1 r /w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 5 layer in frame 1 . since lower 4 - bits are fixed to ?0?, this address is 16 - byte aligned. l5oa1 ( l5 layer display address 1 ) register address di splaybaseaddress + 98 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5da1 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 5 layer in frame 1 . for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l5dx ( l5 layer display position x ) register address displaybaseaddress + 9c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5dx r/w r0 rw initial value 0 don?t care this register set s the display start ing position (x coordinate s ) of the l 5 layer on the basis of the origin of the logic frame in pixels .
fujistu limited prel iminary an d confidential MB86295S 198 specification manual rev1.1 l5dy ( l5 layer display position y ) register address displaybaseaddress + 9e h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5dy r/w r0 rw initial value 0 don?t care this register sets the display starting position (y coordinates) of the l5 layer on the basis of the origin of the logic frame in pixel s. l5wx ( l5 layer window position x ) register address displaybaseaddress + 164 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5wx r/w r0 rw initial value 0 don?t care this register sets the x coordinates of the displa y position of the l5 layer window. l5wy ( l5 layer window position y ) register address displaybaseaddress + 166 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5wy r/w r0 rw initial value 0 don?t care this register sets the y coordinates of the display position of the l5 layer window. l5 ww ( l5 layer window width) register address displaybaseaddress + 168 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5 ww r/w r0 rw initial value 0 don?t care t his register controls the horizontal direction display size ( width ) of the l5 layer window. do not specify ?0?. l5 wh ( l5 layer window height) register address displaybaseaddress + 1 6a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name res erved l5 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of the l5 layer window. setting value + 1 is the height.
fujistu limited prel iminary and confiden tial MB86295S 199 specification manual rev1.1 cutc (c u rsor transparent control) register address displaybaseaddress + a0 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cuzt cutc r/w r0 rw rw initial value 0 don?t care don?t care bit 7 to 0 cutc (cursor transparent code) set s color code handled as transparent code bit 8 cuzt (cursor zero t ransparency) defines handling of color code 0 0 code 0 as transparency color 1 code 0 as non - transparency color cpm (cursor priority mode) register address displaybaseaddress + a2 h bit number 7 6 5 4 3 2 1 0 bit field name reserved cen1 cen0 rese rved cuo1 cuo0 r/w r0 rw rw r0 rw rw initial value 0 0 0 0 0 0 this register controls the display priority of cursors. cursor 0 is always preferred to cursor 1. bit 0 cuo0 (cursor overlap 0) sets display priority between cursor 0 and pixels of conso le layer 0 put s cursor 0 at lower than l0 layer. 1 pu ts cursor 0 at higher than l0 layer. bit 1 cuo1 (cursor overlap 1) sets display priority between cursor 1 and c layer 0 put s cursor 1 at lower than l0 layer. 1 put s cursor 1 at lower than l 0 layer. bit 4 cen0 (cursor enable 0) sets enabling display of cursor 0 0 disable d 1 enable d bit 5 cen1 (cursor enable 1) sets enabling display of cursor 1 0 disable d 1 enable d
fujistu limited prel iminary an d confidential MB86295S 200 specification manual rev1.1 cuoa0 (cursor - 0 origin address) register address display baseaddress + a4 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d cuoa0 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the start address of the cursor 0 pattern. since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. cux0 (cursor - 0 x position) register address displaybaseaddress + a8 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cux0 r/w r0 rw initial value 0 don?t care this register sets the display position (x coordinates) of the cursor 0 in pixels . the reference position of the coordinate s is the top left of the cursor pattern. cuy0 (cursor - 0 y position) register address displaybaseaddress + aa h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cuy0 r/w r0 rw initial value 0 don?t care this register sets the display position (y coordinates) of the cursor 0 in pixels . the reference position of the coordinate s is the top left of the cu rsor pattern.
fujistu limited prel iminary and confiden tial MB86295S 201 specification manual rev1.1 cuoa1 (cursor - 1 origin address) register address displaybaseaddress + ac h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d cuoa1 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the start address of the cursor 1 pattern. since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. cux1 (cursor - 1 x position) register address displaybaseaddress + b0 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cux1 r/w r0 rw initial value 0 don?t care this register sets the display position (x coordinates) of the cursor 1 in pixels . the reference position of the coordinate s is the top left of the cursor pattern. cuy1 (cursor - 1 y position) register address displaybaseaddress + b2 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cuy1 r/w r0 rw initial value 0 don?t care this register sets the display position (y coordinates) of the cursor 1 in pixe ls . the reference position of the coordinate s is the top left of the cursor pattern.
fujistu limited prel iminary an d confidential MB86295S 202 specification manual rev1.1 dls ( display layer select ) register address displaybaseaddress + 180 h bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bi t field name reserved dls5 dls4 dls3 dls2 dls1 dsl0 r/w r0 r0 rw r0 rw r0 rw r0 rw r0 rw r0 rw initial value 101 100 011 010 001 000 this register defines the blending sequence. bit 3 to 0 dsl0 ( display layer select 0 ) selects the top layer su bjected to blending. 0000 l0 layer 0001 l1 layer : : 0101 l5 layer 0110 reserved : : 0110 reserved 0111 not selected bit 7 to 4 dsl1 ( display layer select 1 ) selects the second layer subjected to blending. the bit values are the same as dsl0. bit 11 to 8 dsl2 ( display layer select 2 ) selects the third layer subjected to blending. the bit values are the same as dsl0. bit 15 to 12 dsl3 ( display layer select 3 ) selects the fourth layer subjected to blending. the bit val ues are the same as dsl0. bit 19 to 16 dsl4 ( display layer select 4 ) selects the fifth layer subjected to blending. the bit values are the same as dsl0. bit 23 to 20 dsl5 ( display layer select 5 ) selects the bottom layer subjected to blending. the bit values are the same as dsl0.
fujistu limited prel iminary and confiden tial MB86295S 203 specification manual rev1.1 dbgc ( display background color ) register address displaybaseaddress + 184 h bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved dbgr dbgg dbgb r/ w r0 initial value this register specifies the color to be displayed in areas outside the display area of each layer on the window. bit 7 to 0 dbgb ( display background blue ) specifies the blue level of the background color. bit 15 to 8 dbgg ( display background green ) specifies the green level of the background color. bit 23 to 16 dbgr ( display background red ) specifies the red level of the background color.
fujistu limited prel iminary an d confidential MB86295S 204 specification manual rev1.1 l0bld ( l0 blend ) register address displaybaseaddress + b4 h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0be l0bs l0bi l0bp reserved l0br r/w initial value this register specifies the blend parameters for the l0 layer. this register corresponds to bratio or bmode for previous products. bit 7 to 0 l0br ( l0 layer blend ratio ) sets the blend ratio. basically, the blend ratio is setting value/256. bit 13 l0bp (l0 layer blend plane ) specifies that the l5 layer is the blend plane. 0 value of l 0br used as blend ratio 1 pixel of l5 layer used as blend ratio bit 14 l0bi (l0 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l0bs ( l0 layer blend select ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l0be (l0 layer blend enable) this b it enables blending. 0 overlay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l0be, and alpha must also be enabled for l0 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujistu limited prel iminary and confiden tial MB86295S 205 specification manual rev1.1 l1bld ( l1 blend ) register address displaybaseaddress + 188 h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l1be l1bs l1bi l1bp reserved l1br r/w initial value this register specifies the blend parameters for the l1 layer. bit 7 to 0 l1br ( l1 layer blend ratio ) sets the blend ratio. basically, the blend ratio is setting value/256. bit 13 l1bp (l1 layer blend plane ) specifies that the l5 layer is the blend plane. 0 value of l1br used as blend ratio 1 pixel of l5 layer used as blend ratio bit 14 l1bi (l1 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l1bs ( l1 layer blend select ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l1be (l1 layer blend enable) this bit enables blending. 0 overlay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l1be, and alpha must also be enabled for l1 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujistu limited prel iminary an d confidential MB86295S 206 specification manual rev1.1 l2bld ( l2 blend ) register address displaybaseaddress + 18c h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l2be l2bs l2bi l2bp reserved l2br r/w initial value this register specifies the blend parameters for the l2 layer. bit 7 to 0 l2br ( l2 layer blend ratio ) sets the blend ratio. basically, the blend ratio is setting value/256. bit 13 l2bp (l2 layer blend plane ) specifies that the l5 layer is the blend plane. 0 value of l2br used as blend ratio 1 pixel of l5 layer used as blend ratio bit 14 l2bi (l2 laye r blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l2bs ( l2 layer blend select ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l2be (l2 layer blend enable) this bit enables blending. 0 overlay via transparent color 1 overlay via blending before bl ending, the blend mode must be specified using l2be, and alpha must also be enabled for l2 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujistu limited prel iminary and confiden tial MB86295S 207 specification manual rev1.1 l3bld ( l3 bl end ) register address displaybaseaddress + 190 h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3be l3bs l3bi l3bp reserved l3br r/w initial value this register specifies the bl end parameters for the l3 layer. bit 7 to 0 l3br ( l3 layer blend ratio ) sets the blend ratio. basically, the blend ratio is setting value/256. bit 13 l3bp (l3 layer blend plane ) specifies that the l5 layer is the blend plane. 0 value of l3br us ed as blend ratio 1 pixel of l5 layer used as blend ratio bit 14 l3bi (l3 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l3bs ( l3 layer blend select ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l3be (l3 layer blend enable) this bit ena bles blending. 0 overlay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l3be, and alpha must also be enabled for l3 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujistu limited prel iminary an d confidential MB86295S 208 specification manual rev1.1 l4bld ( l4 blend ) register address displaybaseaddress + 194 h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4be l4bs l4bi l4bp reserved l4br r/w initial value this register specifies the blend parameters for the l4 layer. bit 7 to 0 l4br ( l4 layer blend ratio ) sets the blend ratio. basically, the blend ratio is setting value/256. bit 13 l4bp (l4 layer blend plane ) specifies that the l5 layer is the blend plane. 0 value of l4br used as blend ratio 1 pixel of l5 layer used as blend ratio bit 14 l4bi (l4 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l4bs ( l4 layer blend select ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio ) + lower image blend ratio bit 16 l4be (l4 layer blend enable) this bit enables blending. 0 overlay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l4be, and alpha must also be enabled for l4 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujistu limited prel iminary and confiden tial MB86295S 209 specification manual rev1.1 l5bld ( l5 blend ) register address displaybaseaddress + 198h bit number 31 30 29 28 ----- 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5be l5bs l5bi reserved l5br r/w r0 rw rw rw r0 rw initial value 0 0 0 this register specifies the blend parameters for the l5 layer. bit 7 to 0 l5br ( l5 layer blend ratio ) se ts the blend ratio. basically, the blend ratio is setting value/256. bit 14 l5bi (l5 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l5bs ( l5 layer blend select ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l5be (l5 layer blend enable) th is bit enables blending. 0 overlay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l5be, and alpha must also be enabled for l5 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujistu limited prel iminary an d confidential MB86295S 210 specification manual rev1.1 l0tc ( l0 layer transparency control) register address displaybaseaddress + bc h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l0zt l0tc r/w rw rw initial value 0 don?t care this register sets the transparent color for the l0 layer. color set by this register is transparent in blend mode. when l0tc = 0 and l0zt = 0, color 0 is displayed in black (transparent). this register corresponds to the ctc register for previous products. bit 14 to 0 l0tc ( l0 layer transparent color ) set s transparent color code for the l0 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 15 l0zt ( l0 layer zero transparency ) sets handling of color code 0 in l0 layer 0: code 0 as transparency color 1: code 0 as non - transparency color l2tc ( l2 layer transparency control ) register address displaybaseaddress + c2 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l2zt l2tc r/w rw rw in itial value 0 don?t care this register sets the transparent color for the l2 layer. when l2tc = 0 and l2zt = 0, color 0 is displayed in black (transparent). this register corresponds to the mltc register for previous products. bit 14 to 0 l2tc (l2 layer transparent color) set s transparent color code for the l2 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 15 l2zt (l2 layer zero transparency) sets handling of color code 0 in l2 layer 0 code 0 as transparency color 1 co de 0 as non - transparency color
fujistu limited prel iminary and confiden tial MB86295S 211 specification manual rev1.1 l3tc ( l3 layer transparency control ) register address displaybaseaddress + c0 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l3zt l3tc r/w rw rw initial value 0 don?t care this register sets the tran sparent color for the l3 layer. when l3tc = 0 and l3zt = 0, color 0 is displayed in black (transparent). this register corresponds to the mltc register for previous products. bit 14 to 0 l3tc (l3 layer transparent color) set s transparent color code for the l3 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 15 l3zt (l3 layer zero transparency) sets handling of color code 0 in l3 layer 0 code 0 as transparency color 1 code 0 as non - transparency color l0e tc ( l0 layer ext end transparency control) register address displaybaseaddress + 1a0 h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l0etz reserved l0tec r/w rw r0 rw initial value 0 0 this register sets th e transparent color for the l0 layer. the 24 bits/pixel transparent color is set using this register. the lower 15 bits of this register are physically the same as l0tc. also, l0etz is physically the same as l0tz. when l0etc = 0 and l0ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l0etc (l0 layer extend transparent color) set s transparent color code for the l0 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 31 l0ezt (l0 layer extend zero transparency) se ts handling of color code 0 in l0 layer 0 code 0 as transparency color 1 code 0 as non - transparency color
fujistu limited prel iminary an d confidential MB86295S 212 specification manual rev1.1 l1etc ( l1 layer extend transparency control ) register address displaybaseaddress + 1a4 h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l1etz reserved l1tec r/w rw r0 rw initial value this register sets the transparent color for the l1 layer. when l1etc = 0 and l1ezt = 0, color 0 is displayed in black (transparent). for ycbcr di splay, transparent color checking is not performed; processing is always performed assuming that transparent color is not used. bit 23 to 0 l1etc (l1 layer extend transparent color) set s transparent color code for the l1 layer. in indirect color mode ( 8 bits/pixel) bits 7 to 0 are used. bit 31 l1ezt (l1 layer extend zero transparency) sets handling of color code 0 in l1 layer 0 code 0 as transparency color 1 code 0 as non - transparency color l2etc ( l2 layer extend transparency control ) regist er address displaybaseaddress + 1a8 h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l2etz reserved l2tec r/w rw r0 rw initial value this register sets the transparent color for the l2 lay er. the 24 bits/pixel transparent color is set using this register. the lower 15 bits of this register are physically the same as l2tc. also, l2etz is physically the same as l2tz. when l2etc = 0 and l2ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l2etc (l2 layer extend transparent color) set s transparent color code for the l2 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 31 l2ezt (l2 layer extend zero transparency) sets handling of color code 0 in l2 layer 0 code 0 as transparency color 1 code 0 as non - transparency color
fujistu limited prel iminary and confiden tial MB86295S 213 specification manual rev1.1 l3etc ( l3 layer extend transparency control ) register address displaybaseaddress + 1ac h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l3etz reserved l3tec r/w rw r0 rw initial value 0 0 this register sets the transparent color for the l3 layer. the 24 bits/pixel transparent color is set using this register. the lower 15 bits of this register are physically the s ame as l3tc. also, l3etz is physically the same as l3tz. when l3etc = 0 and l3ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l3etc (l3 layer extend transparent color) set s transparent color code for the l3 layer. in indirect color m ode (8 bits/pixel) bits 7 to 0 are used. bit 31 l3ezt (l3 layer extend zero transparency) sets handling of color code 0 in l3 layer 0 code 0 as transparency color 1 code 0 as non - transparency color l4etc ( l4 layer extend transparency control ) r egister address displaybaseaddress + 1b0 h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l4etz reserved l4tec r/w rw r0 rw initial value 0 0 this register sets the transparent color for the l4 layer. this register sets the transparent color for the l4 layer. when l4etc = 0 and l4ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l4etc (l4 layer extend transparent color) set s transparent color code for the l4 layer. in in direct color mode (8 bits/pixel) bits 7 to 0 are used. bit 31 l4ezt (l4 layer extend zero transparency) sets handling of color code 0 in l4 layer 0 code 0 as transparency color 1 code 0 as non - transparency color
fujistu limited prel iminary an d confidential MB86295S 214 specification manual rev1.1 l5etc ( l5 layer extend transpar ency control ) register address displaybaseaddress + 1b4 h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l5etz reserved l5tec r/w rw r0 rw initial value 0 0 this register sets the transparen t color for the l5 layer. this register sets the transparent color for the l5 layer. when l5etc = 0 and l5ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l5etc (l5 layer extend transparent color) set s transparent color code for the l 5 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 31 l5ezt (l5 layer extend zero transparency) sets handling of color code 0 in l5 layer 0 code 0 as transparency color 1 code 0 as non - transparency color
fujistu limited prel iminary and confiden tial MB86295S 215 specification manual rev1.1 l0 pal0 - 255 ( l0 l ayer palette 0 - 255) register address displaybaseaddress + 400 h -- displaybaseaddress + 7ff h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r g b r/w rw r0 rw r0 rw r0 rw r0 initial val ue don?t care 0000000 don?t care 00 don?t care 00 don?t care 00 these are color palette registers for l0 layer and cursors. in the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. this register corresponds to the cpaln register for previous products. bit 7 to 2 b (blue) set s blue color component bit 15 to 10 g (green) set s green color component bit 23 to 18 r (red) set s red color component bit 31 a (alpha) specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 blending not performed even when blending mode enabled overlay is performed via transparent c olor. 1 blending performed
fujistu limited prel iminary an d confidential MB86295S 216 specification manual rev1.1 l1 pal0 - 255 ( l1 layer palette 0 - 255) register address displaybaseaddress + 8 00 h -- displaybaseaddress + b ff h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r g b r/w rw r0 rw r0 rw r0 rw r0 initial value don?t care 0000000 don?t care 00 don?t care 00 don?t care 00 these are color palette registers for l1 layer and cursors. in the indirect color mode, a color code in the display frame indicates the palett e register number, and the color information set in that register is applied as the display color of that pixel. this register corresponds to the mbpaln register for previous products. bit 7 to 2 b (blue) set s blue color component bit 15 to 10 g (g reen) set s green color component bit 23 to 18 r (red) set s red color component bit 31 a (alpha) specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 blending not performed even when blending mo de enabled overlay is performed via transparent color. 1 blending performed
fujistu limited prel iminary and confiden tial MB86295S 217 specification manual rev1.1 l2 pal0 - 255 ( l2 layer palette 0 - 255) register address displaybaseaddress + 10 00 h -- displaybaseaddress + 13 ff h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r g b r/w rw r0 rw r0 rw r0 rw r0 initial value don?t care 0000000 don?t care 00 don?t care 00 don?t care 00 these are color palette registers for l2 layer and cursors. in the indirect color mode, a c olor code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. bit 7 to 2 b (blue) set s blue color component bit 15 to 10 g (green) set s green col or component bit 23 to 18 r (red) set s red color component bit 31 a (alpha) specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 blending not performed even when blending mode enabled overlay is performed via transparent color. 1 blending performed
fujistu limited prel iminary an d confidential MB86295S 218 specification manual rev1.1 l3 pal0 - 255 ( l3 layer palette 0 - 255) register address displaybaseaddress + 1 400 h -- displaybaseaddress + 1 7ff h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r g b r/w rw r0 rw r0 rw r0 rw r0 initial value don?t care 0000000 don?t care 00 don?t care 00 don?t care 00 these are color palette registers for l3 layer and cursors. in the indirect color mode, a color code in the displ ay frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. bit 7 to 2 b (blue) set s blue color component bit 15 to 10 g (green) set s green color component bit 2 3 to 18 r (red) set s red color component bit 31 a (alpha) specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 blending not performed even when blending mode enabled overlay is performed via transpar ent color. 1 blending performed
fujistu limited prel iminary and confiden tial MB86295S 219 specification manual rev1.1 10.2.5 video c apture r egisters vcm (video capture mode) register address caputurebaseaddress + 00 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name vie vis | reserve d cm reserve d vi reserve d vs rsv r/w rw rw | rx rw rx rw rx rw rx initial value 0 x 00 x 0 x 0 x this register sets the video capture mode. bit 31 vie (video input enable) enables video capture function 0: does not capture video 1 : captures video vis (video input select) 0 rbt656 bit 30 1 rgb666 bit 25 to 24 cm (capture mode) set s video capture mode to capture vides, set these bits to ?11?. 00: initial value 01: reserved 10: reserved 11: capture bit 20 vi (verti cal interpolation) sets whether to perform vertical interpolation 0: performs vertical interpolation the graphics are enlarged vertically by two times 1: does not perform vertical interpolation bit 1 vs (video select) selects ntsc or pal 0: n tsc 1: pal
fujistu limited prel iminary an d confidential MB86295S 220 specification manual rev1.1 csc (capture scale) register address caputurebaseaddress + 04 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name vsci vscf hsci hscf r/w rw rw rw rw initial value 00001 00000000000 00001 00000000000 this register sets the video capture enlargement/reduction ratio. bit 31 to 27 vsci (vertical scale integer) set s integer part of vertical enlargement/reduction ratio bit 26 to 16 vscf (vertical scale fraction) set s fraction part of vertical enlargement/reduction ratio bit 15 to 11 hsci (horizontal s c ale integer) set s integer part of horizontal enlargement/reduction ratio bit 10 to 0 hscf (horizontal scale fraction) set s fraction part of horizontal enlarge ment/reduction ratio note : simultaneous upscaling and downscaling is not possible (eg hscale=0x1000,vscale=0x0600) . no scaling ( hscale= 0x0800 , vscale=0x800 ) is the default setting. vcs (video capture status) register address caputurebaseaddress + 08 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d ce r/w rx rw initial value don?t care 00000 this register indicates the itu - rbt656 sav and eav status. to detect error codes, s et ntsc/pal in the vs bit of vcm. if ntsc is set, reference the number of data in the capture data count register (cdcn). if pal is set, reference the number of data in the capture data counter register (cdcp). if the reference data does not match the stre am data , or undefined fourth word of sav/eav codes are detected, bits 4 to 0 of the video capture status register (vcs) will be values as follows. bits 4 - 0 ce (capture error) indicates error occurred during video capture bit4 1 : rbt.656 h code error ( end) 0 : true bit3 1 : rbt.656 h code error (start) 0 : true bit2 1 : rbt.656 undefined error (code bit7 - 0) 0 : true bit1 1 : rbt.656 undefined error (code bit7 - 4) 0 : true bit0 1 : rbt.656 undefined error (code bit7) 0 : true
fujistu limited prel iminary and confiden tial MB86295S 221 specification manual rev1.1 cbm (vide capture buffer mode) register address caputurebaseaddress + 10 h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name 00 reserved cbw reserved r/w rw rx rw rx initial value don?t care don?t care do n?t care bit 23 to 16 cbw (capture buffer memory width) set s memory width (stride) of capture buffer in 64 byte s bit 31 oo (odd only mode) specifies whether to capture odd fields only 0: normal mode 1: odd only mode cboa (video capture buf fer origin address) register address caputurebaseaddress + 14 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cboa r/w rx rw r0 initial value don?t care don?t care 0 this regis ter specifies the starting (origin) address of the video capture buffer. cbla (video capture buffer limit address) register address caputurebaseaddress + 18 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cbla r/w rx rw r0 initial value don?t care don?t care 0 this register specifies the end (limit) address of the video capture buffer. cbla must be larger than cboa.
fujistu limited prel iminary an d confidential MB86295S 222 specification manual rev1.1 cihstr (capture image horizontal start) register address cap uturebaseaddress + 1c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cihstr r/w rx rw initial value don?t care don?t care this register sets the range of the images to be written (captured) to the video capture buffer. spec ify the x coordinate s located in the top left of the image range as the count of pixels from the top left of the image. for reduction, apply this setting to the post - reduction image coordinate s . civstr (capture image vertical start) register address capu turebaseaddress + 1e h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved civstr r/w rx rw initial value don?t care don?t care this register sets the range of the images to be written (captured) to the video capture buffer. speci fy the y coordinate s located in the top left of the image range as the count of pixels from the top left of the image. for reduction, apply this setting to the post - reduction image coordinate s . cihend (capture image horizontal end) register address caput urebaseaddress + 20 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cihend r/w rx rw initial value don?t care don?t care this register sets the range of the images to be written (captured) to the video capture buffer. specif y the x coordinate s located in the bottom right of the image range as the count of pixels from the top left of the image. for reduction, apply this setting to the post - reduction image coordinate s . if the pixel at the right end of the image is not aligned on 64 bits/word boundary, extra data is written before 64 bits/word boundary. if the width of the input image is less than the range set by this command, data is written only at the size of input image. civend (capture image vertical end) register address caputurebaseaddress + 22 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved civend r/w rx rw initial value don?t care don?t care this register sets the range of the images to be written (captured) to the video capture buffer. specify the y coordinate s located in the bottom right of the image range as the count of pixels from the top left of the original image to be input. for reduction, apply this setting to the post - reduction image coordinate s . if the count of rasters of the input image is less than the range set by this command, data is written only at the size of the input image.
fujistu limited prel iminary and confiden tial MB86295S 223 specification manual rev1.1 chp (capture horizontal pixel) register address caputurebaseaddress + 28 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved chp r/w rx rw initial value x 168 h (360 d ) this register sets the count of horizontal pixels of the image output after scaling. specify the count of horizontal pixels in 2 pixel s . cvp (capture vertical pixel) register address caputurebaseaddress + 2c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cvpp reserved cvpn r/w rx rw rx rw initial value x 271 h (625 d ) x 20d h (525 d ) t his register sets the count of vertical pixels of the image output after scaling. the fields to be used depend on the video format to be used . bit 25 to 16 cvpp (capture vertical pixel for pal) set count of vertical pixels of output image in pal format used bit 9 to 0 cvpn (capture vertical pixel for ntsc) set count of vertical pixels of output image in ntsc format used
fujistu limited prel iminary an d confidential MB86295S 224 specification manual rev1.1 c l p f (capture low pass filter ) register address caputurebaseaddress + 40 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 1 9 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve cvlpf reserve chlpf reserve r/w r0 r/w r0 r/w r0 initial value 0 0 0 0 0 this register sets the low pass filter coefficient. it specifies independently in 2 - bit coefficient code wi th a luminance signal (y) and a color - difference signal (c). a coefficient is a right - and - left symmetrical coefficient. a vertical low path filter consists of fir filters of three taps. a coefficient is specified in the following register. bit 27 to 26 c vlpf_y ( capture vert ical lpf coefficient y ) set s y part of vertical lpf coefficient code cvlpf_y k0 k1 k2 2 ? b00 0 1 0 2 ? b01 1/4 2/4 1/4 2 ? b10 3/16 10/16 3/16 2 ? b11 reserve bit 25 to 24 c v lpf_c ( capture vert ical lpf coefficient c ) set s c par t of vertical lpf coefficient code cvlpf_c k0 k1 k2 2 ? b00 0 1 0 2 ? b01 1/4 2/4 1/4 2 ? b10 3/16 10/16 3/16 2 ? b11 reserve a horizontal low path filter consists of fir filters of five taps. a coefficient is specified in the following register. bit 1 9 to 18 chlpf_y i ( capture horizontal lpf coefficient y ) set s y part of horizontal coefficient code chlpf_y k0 k1 k2 k3 k4 2 ? b00 0 0 1 0 0 2 ? b01 0 1/4 2/4 1/4 0 2 ? b10 0 3/16 10/16 3/16 0 2 ? b11 3/32 8/32 10/32 10/32 3/32 bit 17 to 16 chlpf_c ( c apture horizontal lpf coefficient c ) set s c pa rt of horizontal coefficient code chlpf_c k0 k1 k2 k3 k4 2 ? b00 0 0 1 0 0 2 ? b01 0 1/4 2/4 1/4 0 2 ? b10 0 3/16 10/16 3/16 0 2 ? b11 3/32 8/32 10/32 10/32 3/32 lpf will be turned off if coefficient cod e 2'b00 are set up.
fujistu limited prel iminary and confiden tial MB86295S 225 specification manual rev1.1 cdcn (capture data count for ntsc) register address caputurebaseaddress + 4000 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved bdcn reserved vdcn r/w rx rw rx rw initial value x 10f h (271 d ) x 5a3 h (1443) this register sets the count of data of the input video stream in ntsc format. bit 25 to 16 bdcn (blanking data count for ntsc) set s count of data processed during blanking period in ntsc format bit 10 to 0 vdcn (valid data count for ntsc) set s count of data processed during valid period in ntsc format cdcp (capture data count for pal) register address caputurebaseaddress + 4004 h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved bdcp reserved vdcp r/w rx rw rx rw initial value x 11b h (283 d ) x 5a3 h (1443) this register sets the count of data of the input video stream in pal format. bit 25 to 16 bdcp (blanking data count for pal) set s count of data processed during blanking period in pal format bit 10 to 0 vdcp (valid data count for pal) set s count of data processed during valid period in pal format
fujistu limited prel iminary an d confidential MB86295S 226 specification manual rev1.1 cmss (capture magnify source size) register address caputurebaseaddres s +48 h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cm s hp reserved cm s vl r/w r r/w r r/w initial value 0 x h 0 x bit 2 7 to 16 cm s hp(capture magnify source horizontal pixel) this register sets the number of horizontal pixels of the image input before magnify scaling. specify the number of horizontal pixels in 2 - pixel units. bit 1 1 to 0 cm s vl(capture magnify source vertical line) this register sets the number of vertical lines of the image input before magnify scaling. cmds (capture magnify display size) register address caputurebaseaddress + 4c h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cmdhp reserv ed cmdvl r/w r r/w r r/w initial value 0 x 0 x bit 2 7 to 16 cmdhp(capture magnify display horizontal pixel) this register sets the number of horizontal pixels of the image output after magnify scaling. specify the number of horizontal pixels in 2 - pix el units. bit 1 1 to 1 0 cmdvl(capture magnify display vertical line) this register sets the number of vertical lines of the image output after magnify scaling.
fujistu limited prel iminary and confiden tial MB86295S 2 27 specification manual rev1.1 rgb hc ( rgb input hsync cycle ) register address caputurebaseaddress +80 h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved rgb hc r/w r r/w initial value 0 x bit 1 1 to 0 rgbhc ( rgb input hsync cycle ) this register sets the number of hsync cycles of the rgb input . rgbhe n (rgb input horizontal enable area ) register address caputurebaseaddress + 84 h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved rgbh st reserved rgb hen r/w r r/w r r/w initial value 0 x 0 x bit 2 7 to 16 rgbhst ( rgb input horizontal enable area start position ) this register sets the position of horizontal active area start position . setting - 4 is the line count for the start position . bit 10 to 0 rgb h en ( rgb input horizontal enabl e area size ) this register sets the number of horizontal active area size of the rgb input . specify the number of horizontal pixels in 2 - pixel units. rgbven (rgb input vertical enable area ) register address caputurebaseaddress + 88 h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved rgbv st reserved rgbven r/w r r/w r r/w initial value 0 x 0 x bit 2 7 to 16 rgbvst ( rgb input vertical enable area start position ) this register sets t he position of vertical active area start position . setting - 1 is the line count for the start position . bit 9 to 0 rgbven ( rgb input vertical enable area size ) this register sets the number of vertical active area size .
fujistu limited prel iminary an d confidential MB86295S 228 specification manual rev1.1 rgbs ( rgb input sync ) regi ster address caputurebaseaddress + 90 h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved rm reserved hp vp r/w r r/ w r r/w initial value 0 1 0 0 0 bit 16 rm ( rgb input mode select ) sets direct rgb input mode 0: reserved 1: rgb666 direct input mode hp (hsync polarity) 0 negedge is set to hsync bit 1 1 posedge is set to hsync bit 0 v p ( vsync polarity ) 0: negedge is set to vsync 1: posedge is set to vsunc
fujistu limited prel iminary and confiden tial MB86295S 229 specification manual rev1.1 c onversion ope ration rgb data is converted to yuv by the following matrix expression : y = a11*r + a12*g + a13*b + b1 cb= a21*r + a22*g + a23*b + b2 a ij 10bit signed real ( lower 8bit is fraction ) cr= a31*r + a32*g + a33*b + b3 b i 8bit unsigned integer each coeffi cients can be defined by following registers. cb and cr components are reduced half after this operation to form the 4:2:2 format. rgbcmy (rgb color convert matrix y coefficient ) register address caputurebaseaddress + c0 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a1 1 re a1 2 re a1 3 r/w rw r rw r rw initial value 0001000010 b 0 0010000000 b 0 0000011001 b this register sets the rgb color convert matrix coefficient . bit 31 to 22 a1 1 10bit signed real (lower8bit is fraction) bit 20 to 11 a12 10bit signed real (lower8bit is fraction) bit 9 to 0 a13 10bit signed real (lower8bit is fraction) rgbcmcb (rgb color convert matrix cb coefficient ) register address caputurebase address + c 4 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a2 1 re a2 2 re a2 3 r/w rw r rw r rw initial value 1111011010 b 0 1110110110 b 0 0001110000 b this register sets the rgb color convert matrix coefficient . bit 31 to 22 a2 1 10bit signed real (lower8bit is fraction) bit 20 to 11 a22 10bit signed real (lower8bit is fraction) bit 9 to 0 a23 10bit signed real (lower8bit is fraction)
fujistu limited prel iminary an d confidential MB86295S 230 specification manual rev1.1 rgbcmcr (rgb color convert matrix cr coefficient ) register address caputurebaseaddress + c8 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a3 1 re a3 2 re a3 3 r/w rw r rw r rw initial value 0001110000 b 0 1110100010 b 0 1111 101110 b this register sets the rgb color convert matrix coefficient . bit 31 to 22 a3 1 10bit signed real (lower8bit is fraction) bit 20 to 11 a32 10bit signed real (lower8bit is fraction) bit 9 to 0 a33 10bit signed real (lower8bit is fract ion) rgbcmb ( rgb color convert matrix b coefficient ) register address caputurebaseaddress + cc h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name r b 1 re s b 2 re s b 3 r/w r rw r rw r rw ini tial value 0 000010000 b 0 010000000 b 0 010000000 b this register sets the rgb color convert matrix coefficient . bit 30 to 22 b 1 9bit unsigned integer bit 19 to 11 b2 9bit unsigned integer bit 8 to 0 b3 9bit unsigned integer
fujistu limited prel iminary and confiden tial MB86295S 231 specification manual rev1.1 10.2 . 6 d raw ing c ontrol r egisters ctr (control register) register address drawbaseaddress + 400 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fo pe ce fcnt nf ff fe ss ds ps r/w rw rw rw r r r r r r r initial value 0 0 0 011101 0 0 1 00 00 00 this register indicates draw ing flags and status information . bits 24 to 22 are not cleared until 0 is set. bit 1 and 0 ps (pixel engine status) indicate status of pixel engine unit 00 idle 01 busy 10 reserved 11 reserved bit 5 and 4 ds (dda status) indicate status of dda 00 idle 01 busy 10 busy 11 reserved bit 9 and 8 ss (setup status) indicate status of setup unit 00 idle 01 busy 10 reserved 11 reserv ed bit 12 fe (fifo empty) indicates whether data contained or not in display list fifo 0 valid data 1 no valid data bit 13 ff (fifo full) indicates whether display list fifo is full or not 0 not full 1 full bit 14 nf (fifo near fu ll) indicates how empty the display list fifo is
fujistu limited prel iminary an d confidential MB86295S 232 specification manual rev1.1 0 empty entries equal to or more than half 1 empty entries less than half bit 20 to 15 fcnt (fifo counter) indicate s count of empty entries of display list fifo (0 to 100000 h ) bit 22 ce (disp lay list command error) indicates command error occurrence 0 normal 1 command error detected bit 23 pe (display list packet code error) indicates packet code error occurrence 0 normal 1 packet code error detected bit 24 fo (fifo overflo w) indicates fifo overflow occurrence 0 normal 1 fifo overflow detected
fujistu limited prel iminary and confiden tial MB86295S 233 specification manual rev1.1 ifsr (input fifo status register) register address drawbaseaddress + 404 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bi t field name nf ff fe r/w r r r initial value 0 0 1 this is a mirror register for bits 14 to 12 of the ctr register. ifcnt (input fifo counter) register address drawbaseaddress + 408 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fcnt r/w r initial value 011101 this is a mirror register for bits 19 to 15 of the ctr register. sst (setup engine status) register address drawbaseaddress + 40c h bit number 31 30 29 28 27 26 25 24 2 3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ss r/w r initial value 00 this is a miller register for bits 9 to 8 of the ctr register. dst (dda status) register address drawbaseaddress + 410 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ds r/w rw initial value 00 this is a mirror register for bits 5 to 4 of the ctr register. pst (pixel engine status) register address drawbaseaddress + 414 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ps r/w r initial value 00 this is a mirror register for bits 1 to 0 of the ctr register. est (error status) register address drawbaseaddress + 418 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fo pe ce r/w rw rw rw initial value 0 0 0 this is a mirror register for bits 24 to 22 of the ctr register.
fujistu limited prel iminary an d confidential MB86295S 234 specification manual rev1.1 10.2 . 7 draw ing mode r egisters when wr i te to the registers, use the setregister command. the registers cannot be accessed from the cpu. mdr0 (mode register for miscellaneous) register address drawbaseaddress + 420 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name zp cf cy cx bsv bsh r/w rw rw rw rw rw rw initial value 0 00 0 0 00 00 bit 1 to 0 bsh (bitmap scale horizontal) set s horizontal zoom ratio of bitmap draw 00 x1 01 x2 10 x1/2 01 reserved bit 3 to 2 bsv (bitmap scale vertical) set s vertical zoom ratio of bitmap draw 00 x1 01 x2 10 x1/2 01 reserved bit 8 cx (clip x enable) sets x coordinate s clipping mode 0 disable d 1 enable d bit 9 cy (clip y enable) sets y coordinate s clipping mode 0 disable d 1 enable d bit 16 and 15 cf (color format) sets drawing color format 0 0 indirect color mode (8 bits/pixel) 0 1 direct color mode (16 bits/pixel) 10 direct color mode (24 bits/pixel) bit 20 zp ( z precision) sets the precision of the z value used for erasing hidden planes. 16 bits/pixel 8 bits/pixel
fujistu limited prel iminary and confiden tial MB86295S 235 specification manual rev1.1 mdr1 /mdr1s/mdr1b (mode register for line /for shadow/for border/for topleft ) register address drawbaseaddress + 424 h bit number 31 30 29 28 2 7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name lw bp bl log bm zw zcl zc as r/w rw rw rw rw rw rw rw rw rw initial value 00000 0 0 0011 0 0 0000 0 0 this register sets the mode of line and pixel draw ing . this register is used for the body primitive, for the shade primitive, for the edge primitive, and for the top - left non - applicable primitive. the value after a drawing that involves the shade primitive, the edge primitive, or the top - left non - applicab le primitive is the value set for mdr1. bit 1 as (alpha shading mode) sets the shading mode for alpha. 0 alpha flat shading 1 alpha gouraud shading bit 2 zc (z compare mode) sets z comparison mode 0 disable d 1 enable d bit 5 to 3 zcl (z compare logic) select s type of z comparison 000 never 001 always 010 less 011 lequal 100 equal 101 gequal 110 greater 111 notequal bit 6 zw (z write mode ) sets z write mode 0 writes z values. 1 not write z values. bit 8 to 7 bm (blend mode) set s blend mode 00 normal (source copy) 01 alpha blending 10 drawing with logic operation
fujistu limited prel iminary an d confidential MB86295S 236 specification manual rev1.1 11 reserved bit 12 to 9 log (logical operation) set s type of logic operation 0000 clear 0001 and 0010 and reverse 0011 copy 0100 and inverted 0101 nop 0110 xor 0111 or 1000 nor 1001 equiv 1010 invert 1011 or reverse 1100 copy inverted 1101 or inverted 1110 nand 1111 set bit 19 bl (broken line) selects line type 0 solid line 1 broken line bi t 20 bp (broken line period) selects broken line cycle 0: 32 bits 1: 24 bits bit 28 to 24 lw (line width) set s line width for drawing line 00000 1 pixel 00001 2 pixels : : 11111 32 pixels
fujistu limited prel iminary and confiden tial MB86295S 237 specification manual rev1.1 mdr 2/mdr2s/mdr2tl (mode register for pol ygon/for shadow/for topleft ) register address drawbaseaddress + 428 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name tt log bm zw zcl zc as sm r/w rw rw rw rw rw rw rw rw initial value 00 0011 0 0 0000 0 0 0 this register sets the polygon draw ing mode. this register is used for the body primitive, for the shade primitive, and for the top - left non - applicable primitive. the value after a drawing that involves the shade primitive or the top - left non - applicable primitive is the value set for mdr2. (must set sm=as=tt=0 for mdr2s) bit 0 sm (shading mode) sets shading mode 0 flat shading 1 gouraud shading bit 1 as (alpha shading mode) sets alpha shading mode . this mode is enabl ed for only alpha. 0 alpha flat shading 1 alpha gouraud shading bit 2 zc (z compare mode) sets z comparison mode 0 disable d 1 enable d bit 5 to 3 zcl (z compare logic) select s type of z comparison 000 never 001 always 010 less 01 1 lequal 100 equal 101 gequal 110 greater 111 notequal bit 6 zw (z write mask) sets z write mode 0 writes z values 1 not write z values
fujistu limited prel iminary an d confidential MB86295S 238 specification manual rev1.1 bit 8 to 7 bm (blend mode) set s blend mode 00 normal (source copy) 01 alpha blending 10 drawing with logic operation 11 reserved bit 12 to 9 log (logical operation) set s type of logic operation 0000 clear 0001 and 0010 and reverse 0011 copy 0100 and inverted 0101 nop 0110 xor 0111 or 1000 nor 1001 equiv 1010 inv ert 1011 or reverse 1100 copy inverted 1101 or inverted 1110 nand 1111 set bit 29 to 28 tt (texture - tile select) select s texture or tile pattern 00 neither used 01 enable d tiling 10 enable d texture 11 reserved
fujistu limited prel iminary and confiden tial MB86295S 239 specification manual rev1.1 mdr3 (mode register for texture) register address d rawbaseaddress + 42c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ba tab tbl tws twt tf tc tbu r/w rw rw rw rw rw rw rw rw initial value 0 00 00 00 00 0 0 0 this register sets the texture mapping mode. bit 0 tbu (texture buffer) selects whether to use the internal buffer or graphics memory as texture memory . internal buffer is always used for tiling . 0 external (frame) graphics memory 1 internal buffer bit 3 tc (texture coordinates correct) sets texture coordinates correction mode 0 disable d 1 enable d bit 5 tf (texture filtering) sets type of texture interpolation ( filtering) 0 point sampling 1 bi - linear fil tering bit 9 and 8 twt (texture wrap t) set s type of texture coordinate s t direction wrapping 00 repeat 01 cramp 10 border 11 reserved bit 11 and 10 tws (texture wrap s) set s type of texture coordinate s s direction wrapping 00 repeat 01 cramp 10 border 11 reserved bit 17 and 16 tbl (texture blend mode) set s texture blending mode 00 de - curl 01 modulate 10 stencil
fujistu limited prel iminary an d confidential MB86295S 240 specification manual rev1.1 11 reserved bit 21 and 20 tab (texture alpha blend mode) sets texture blending mode the stencil mod e and the stencil alpha mode are enabled only when the mdr2 register blend mode (bm) is set to the alpha blending mode. if it is not set to the alpha blending mode, the stencil mode and stencil alpha mode perform the same function as the normal mode. 00 normal 01 stencil 10 stencil alpha 11 reserved bit 24 ba (bilinear accelerate mode) improve s the performance of bi - linear filtering, although a texture area of four times the default texture area is used. 0 default texture area used 1 tex ture area four times default texture area used
fujistu limited prel iminary and confiden tial MB86295S 241 specification manual rev1.1 mdr4 (mode register for blt) register address drawbaseaddress + 430 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name log bm te r/w rw rw rw initial value 0011 00 0 this register controls the blt mode. bit 1 te (transparent enable) sets transparent mode 0: not perform transparent processing 1: not draw pixels that corresponds to set transparent color in blt ( transparancy cop y) note: set the blend mode (bm) to normal. bit 8 to 7 bm (blend mode) set s blend mode 00 normal (source copy) 01 reserved 10 drawing with logic operation 11 reserved bit 12 to 9 log (logical operation) set s logic operation 0000 clea r 0001 and 0010 and reverse 0011 copy 0100 and inverted 0101 nop 0110 xor 0111 or 1000 nor 1001 equiv 1010 invert 1011 or reverse 1100 copy inverted 1101 or inverted 1110 nand 1111 set
fujistu limited prel iminary an d confidential MB86295S 242 specification manual rev1.1 fbr (frame buffer base) register addre ss drawbaseaddress + 440 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fbase r/w rw r0 initial value don?t care 0 this register stores the base address of the drawing frame. xres ( x resolution) register address drawbaseaddress + 444 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name xres r/w rw initial value don?t care this register sets the drawing frame horizon tal resolution. zbr (z buffer base) register address drawbaseaddress + 448 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name zbase r/w rw r0 initial value don?t care 0 this register se ts the z buffer base address. tbr (texture memory base) register address drawbaseaddress + 44c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name tbase r/w rw r0 initial value don?t care 0 this register sets the texture memory base address. pfbr (2d polygon flag - buffer base) register address drawbaseaddress + 450 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name pfbase r /w rw r0 initial value don?t care 0 this register sets the polygon flag buffer base address.
fujistu limited prel iminary and confiden tial MB86295S 243 specification manual rev1.1 cxmin (clip x minimum) register address drawbaseaddress + 454 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name clipxmin r/w rw initial value don?t care this register sets the clip frame minimum x position. cxmax (clip x maximum) register address drawbaseaddress + 458 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name clipxmax r/w rw initial value don?t care this register sets the clip frame maximum x position. cymin (clip y minimum) register address drawbaseaddress + 45c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name clipymin r/w rw initial value don?t care this register sets the clip frame minimum y position. cymax (clip y maximum) register address drawbaseaddress + 460 h bit number 31 30 29 28 2 7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name clipymax r/w rw initial value don?t care this register sets the clip frame maximum y position.
fujistu limited prel iminary an d confidential MB86295S 244 specification manual rev1.1 txs (texture size) register address drawbaseaddress + 464 h bit n umber 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name txsn txsm r/w rw rw initial value 100000000000 100000000000 this register specifies the texture size (m, n). bit 12 to 0 txsm (texture siz e m) set s horizontal texture size. any power of 2 between 4 and 4096 can be used. values that are not a power of 2 cannot be used. 0_0000_0000_0100 m=4 0_0010_0000_0000 m=512 0_0000_0000_1000 m=8 0_0100_0000_0000 m=1024 0_0000_0001_0000 m=16 0_10 00_0000_0000 m=2048 0_0000_0010_0000 m=32 1_0000_0000_0000 m=4096 0_0000_0100_0000 m=64 0_0000_1000_0000 m=128 0_0001_0000_0000 m=256 other than the above setting disabled bit 28 to 16 txsn (texture size n) set s vertical texture size. an y power of 2 between 4 and 4096 can be used. values that are not a power of 2 cannot be used. 0_0000_0000_0100 n =4 0_0010_0000_0000 n =512 0_0000_0000_1000 n =8 0_0100_0000_0000 n =1024 0_0000_0001_0000 n =16 0_1000_0000_0000 n =2048 0_0000_0010_0000 n =32 1_0000_0000_0000 n =4096 0_0000_0100_0000 n =64 0_0000_1000_0000 n =128 0_0001_0000_0000 n =256 other than the above setting disabled
fujistu limited prel iminary and confiden tial MB86295S 245 specification manual rev1.1 tis (tile size) register address drawbaseaddress + 468 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 1 8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name tisn tism r/w rw rw initial value 1000000 1000000 this register specifies the tile size (m, n). bit 6 to 0 tism (title size m) set s horizontal tile size. any power of 2 between 4 and 64 can be used. values that are not a power of 2 cannot be used. 0.000100 m=4 0001000 m=8 0010000 m=16 0100000 m=32 1000000 m=64 other than the above setting disabled bit 22 to 16 tisn (title size n) set s vertical tile size. any power of 2 between 4 and 64 can be used. values that are not a power of 2 cannot be used. 0000100 n=4 0001000 n=8 0010000 n=16 0100000 n=32 1000000 n=64 other than the above setting disabled toa (texture buffer offset address) register address dra wbaseaddress + 46c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name xbo r/w rw initial value don?t care this register sets the texture buffer offset address. using this offset value, texture patterns can be referred to the texture buffer memory. specify the word - aligned byte address (16 bits). (bit 0 is always ?0?.)
fujistu limited prel iminary an d confidential MB86295S 246 specification manual rev1.1 sho (shadow offset) register address drawbaseaddress + 470 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name shoffs r/w rw initial value don?t care this register sets the offset address of the shadow relative to the body primitive at drawing with shadow. at body drawing, this offset address is set to ? 0 ? ; at shadow drawing, the offset address calculated from each offset value of the x coordinates and of the y coordinates is set. this register is hardware controlled. abr (alpha map base) register address drawbaseaddress + 474 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name abase r/w rw r0 initial value don?t care 0 this register sets the base address of the alpha map.
fujistu limited prel iminary and confiden tial MB86295S 247 specification manual rev1.1 fc (foreground color) register address drawbaseaddress + 480 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fgc r/w rw initial value 0 this register sets the drawing foreground color. this color is for the object color for flat shading and fore ground color for bitmap draw ing and broken line draw ing. all bits set to ?1? are drawn in the color set at this register. 8 bit color mode: bit 7 to 0 fgc8 (foreground 8 bit color) sets the indirect color for the foreground (color index code). bit 31 to 8 these bits are not used. 16 bit color mode: bit 15 to 0 fgc16 (foreground 16 bit color) this field sets the 16 - bit direct color for the foreground. note that the handling of bit 15 is different from that in orchid. up to orchid, bit 15 is ? 0 ? for other than bit map and rectangular drawing, but starting with coral, the setting value is reflected in memory as is. this bit is also reflected in bit 15 of the 16 - bit color at gouraud shading. bit 31 to 16 these bits are not used. 24 bit color mode: b it 23 to 0 fgc24 (foreground 24 bit color) this field sets the 24 - bit direct color for the foreground. bit 31 to 24 these bits are not used. 32 - bit units are used for memory, but these bits are reflected in bit 31 to 24 (msb side).
fujistu limited prel iminary an d confidential MB86295S 248 specification manual rev1.1 bc (background col or) register address drawbaseaddress + 484 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name bgc8/16/24 r/w rw initial value 0 this register sets the drawing frame background color. this color is used for the background color of bitmap draw ing and broken line draw ing . at bitmap drawing, all bits set to ? 0 ? are drawn in the color set at this register. bt bit of this register allows the background color of be transparent (no drawing). 8 bi t color mode: bit 7 to 0 bgc8 (background 8 bit color) sets the indirect color for the background (color index code) bit 14 to 8 not used bit 15 bt (background transparency) sets the transparent mode for the background color 0 background drawn usin g color set for bgc field 1 background not drawn (transparent) bit 31 to 16 not used 16 bit color mode: bit 14 to 0 bgc16 (background 16 bit color) sets 16 - bit direct color (rgb) for the background bit 15 bt (background transparency) sets the tra nsparent mode for the background color 0 background drawn using color set for bgc field 1 background not drawn (transparent) bit 31 to 16 not used 24 bit color mode: bit 23 to 0 bgc24 (background 24 bit color) sets 24 - bit direct color for the back ground bit 30 to 24 not used 32 - bit units are used for memory, but these bits are reflected in bit 31 to 24 (msb side) bit 31 bt (background transparency) sets the transparent mode for the background color 0 background drawn using color set for bgc f ield 1 background not drawn (transparent)
fujistu limited prel iminary and confiden tial MB86295S 249 specification manual rev1.1 alf (alpha factor) register address drawbaseaddress + 488 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r/w rw initial value 0 this register sets the alpha blending coefficient . blp (broken line pattern) register address drawbaseaddress + 48c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name blp r/w rw initial value 0 this register sets the broken - line pattern. the bit 1 set in the broken - line pattern is drawn in the foreground color and bit 0 is drawn in the background color. the line pattern for 1 pixel line is laid out in the direction of msb to lsb and when it r eaches lsb, it goes back to msb . the blpo register manage s the bit numbers of the broken - line pattern. 32 or 24 bits can be selected as the repetition of the broken - line pattern by the bp bit of the mdr1 register. when 24 bits are selected, bits 23 to 0 of the blp register are used. tbc (texture border color) register address drawbaseaddress + 494 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name bc16/24 r/w rw initial value 0 this regis ter sets the border color for texture mapping. 16 bit color mode: bit 15 to 0 bc16 (border color) sets the 16 - bit direct color for the texture border color 24 bit color mode: bit 23 to 0 bc24 (border color) sets the 24 - bit direct color for the textu re border color bit 31 to 24 not used 32 - bit units are used for memory but these bits are reflected in bit 31 to 24 (msb side) blpo (broken line pattern offset) register address drawbaseaddress + 3e0 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name bcr r/w rw initial value 11111 this register stores the bit number of the broken - line pattern set to blp registers, for broken line drawing. this value is decremented at each pixel draw ing . broken line can be drawn starting from any starting position of the specified broken - line pattern by setting any value at this register. when no write is performed, the position of broken - line pattern is sustained.
fujistu limited prel iminary an d confidential MB86295S 250 specification manual rev1.1 10.2 . 8 triangle draw ing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or using the setregister command. (xy coordinate s register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ys 0000 h s s s s int 0 xs 0004 h s s s s int frac dxdy 0008 h s s s s int frac xus 000c h s s s s int frac dxudy 0010 h s s s s int frac xls 0014 h s s s s int frac dxldy 0018 h s s s s int frac usn 001b h 0 0 0 0 int 0 lsn 0020 h 0 0 0 0 int 0 addres s offset value from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets (x, y) coordinates for triangle drawing ys y coordinate s start position of long edge xs x coordinate s start position of long edge corresponding to ys dxdy x dda value of long edge direction xus x coordinate s start position of upper edge dxudy x dda value of upper edge direction xls x coordinate s start position of lower e dge dxldy x dda value of lower edge direction usn count of spans of upper triangle. if this value is ?0?, the upper triangle is not drawn. lsn count of spans of lower triangle. if this value is ?0?, the lower triangle is not drawn.
fujistu limited prel iminary and confiden tial MB86295S 251 specification manual rev1.1 (color setting r egister) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rs 0040 h 0 0 0 0 0 0 0 0 int frac drdx 0044 h s s s s s s s s int frac drdy 0048 h s s s s s s s s int frac gs 004c h 0 0 0 0 0 0 0 0 int frac dgdx 0050 h s s s s s s s s int frac dgdy 0054 h s s s s s s s s int frac bs 0058 h 0 0 0 0 0 0 0 0 int frac dbdx 005c h s s s s s s s s int frac dbdy 0060 h s s s s s s s s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets color parameters for triangle drawing. these parameters are enabled in the gouraud shading mode. rs r value at (xs, ys, zs) of long edge corre sponding to ys drdx r dda value of horizontal direction drdy r dda value of long edge gs g value at (xs, ys, zs) of long edge corresponding to ys dgdx g dda value of horizontal direction dgdy g dda value of long edge bs b value at (xs, ys, zs) of lon g edge corresponding to ys dbdx b dda value of horizontal direction dbdy b dda value of long edge (z coordinate s register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 zs 0080h 0 int frac dzdx 0084h s int frac dzdy 008ch s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets z coordinate s for 3d triangle drawing zs z coordinate start position of long edge dzdx z dda value of horizontal direction dzdy z dda value of long edge
fujistu limited prel iminary an d confidential MB86295S 252 specification manual rev1.1 (texture coordinate s - setting register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss 00c0 h s s s int frac dsdx 00c4 h s s s int frac dsdy 00c8 h s s s int frac ts 00cc h s s s int frac dtdx 00d0 h s s s int frac dtdy 00d4 h s s s int frac qs 00d8 h 0 0 0 0 0 0 0 int frac dqdx 00dc h s s s s s s s int frac dqdy 00e0 h s s s s s s s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets texture coordinate s parameters for triangle drawin g ss s texture coordinate s (xs, ys, zs) of long edge corresponding to ys dsdx s dda value of horizontal direction dsdy s dda value of long edge direction ts t texture coordinate s (xs, ys, zs) of long edge corresponding to ys dtdx t dda value of horizo ntal direction dtdy t dda value of long edge direction qs q (perspective correction value) of texture at (xs, ys, zs) of long edge corresponding to ys dqdx q dda value of horizontal direction dqdy q dda value of long edge direction
fujistu limited prel iminary and confiden tial MB86295S 253 specification manual rev1.1 10. 2. 9 line draw ing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or by using the setregister command. (coordinate s setting register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lpn 0140 h 0 0 0 0 int 0 lxs 0144 h s s s s int frac lxde 0148 h s s s s s s s s s s s s s s s int frac lys 014c h s s s s int frac lyde 0150 h s s s s s s s s s s s s s s s int frac lzs 0154 h s int frac lzde 0158 h s int frac add ress offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate s parameters for line drawing lpn pixel count of principal axis d irection lxs x coordinate s start position of draw line (in principal axis x ) integer value of x coordinate s rounded off (in principal axis y) x coordinate s in form of fixed point data lxde inclination data for x coordinate s (in principal axis x) incremen t or decrement according to drawing direction (in principal axis y) fraction part of dx/dy lys y coordinate s start position of draw line (in principal axis x) y coordinate s in form of fixed point data (in principal axis y) integer value of y coordinate s r ounded off lyde inclination data for y coordinate s (in principal axis x) fraction part of d y/ d x (in principal axis y) increment or decrement according to drawing direction lzs z coordinate s start position of line draw ing line lzde z inclination
fujistu limited prel iminary an d confidential MB86295S 254 specification manual rev1.1 10.2 . 10 pixel drawing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or using the setregister command. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pxdc 0180 h 0 0 0 0 int 0 pydc 0184 h 0 0 0 0 int 0 pzdc 0188 h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate s parameter for drawing pixel . the foreground color is used. pxdc set s x coordinate s position pydc set s y coordinate s position pzdc set s z coordinate s position 10.2 .1 1 rectangle draw ing registers each register is used by the dra wing commands. the registers cannot be accessed from the cpu or using the setregister command . register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxs 0200 h 0 0 0 0 int 0 rys 0204 h 0 0 0 0 int 0 rsize x 0208 h 0 0 0 0 int 0 rsizey 020c h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate s paramete rs for rectangle drawing. the foreground color is used. rxs set s the x coordinate s of top left vertex rys set s the y coordinate s of top left vertex rsizex set s horizontal size rsizey set s vertical size
fujistu limited prel iminary and confiden tial MB86295S 255 specification manual rev1.1
fujistu limited prel iminary an d confidential MB86295S 256 specification manual rev1.1 10. 2.1 2 blt registers set s the parameters of each register as described below : set the tcolor register with the setregister command. note that the tcolor register cannot be set at access from the cpu and by drawing commands. each register except the tcolor register is set by executing a drawing comma nd. note that access from the cpu and the setregister command cannot be used. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 saddr 0240 h 0 0 0 0 0 0 0 address sstride 0244 h 0 0 0 0 int 0 srxs 0248 h 0 0 0 0 int 0 srys 024c h 0 0 0 0 int 0 daddr 0250 h 0 0 0 0 0 0 0 address dstride 0254 h 0 0 0 0 int 0 drxs 0258 h 0 0 0 0 int 0 drys 025c h 0 0 0 0 int 0 brsizex 0260 h 0 0 0 0 int 0 brsizey 0264 h 0 0 0 0 int 0 tcolor 0280 h 0 color address offset f rom drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets parameters for blt operations saddr sets start address of source rectangle area in byte address sstride sets stride of source srxs sets x coordinate s start position of source rectangle area srys sets y coordinate s start position of source rectangle area daddr sets start address of destination rectangle area in byte address dstride sets stride of destination drxs sets x coordinate s start position of destination rectangle area drys sets y coordinate s start position of destination rectangle area brsizex sets horizontal size of rectangle brsizey sets vertical size of rectangle tcolor se ts transparent color for indirect color, set a palette code in the lower 8 bits.
fujistu limited prel iminary and confiden tial MB86295S 257 specification manual rev1.1 10.2 .1 3 high - speed 2d line draw ing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu. register address 31 30 29 28 2 7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lx0dc 0540 h 0 0 0 0 int 0 ly0dc 0544 h 0 0 0 0 int 0 lx1dc 0548 h 0 0 0 0 int 0 ly1dc 054c h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not us ed or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate s of line end points for high - speed 2dline drawing lx0dc sets x coordinate s of vertex v0 ly0dc sets y coordinate s of vertex v0 lx1dc sets x coordinate s of vertex v1 ly1dc sets y coordinate s of vertex v1
fujistu limited prel iminary an d confidential MB86295S 258 specification manual rev1.1 10.2 .1 4 high - speed 2d triangle draw ing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or using the setregister command. re gister address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x0dc 0580h 0 0 0 0 int 0 y0dc 0584h 0 0 0 0 int 0 x1dc 0588h 0 0 0 0 int 0 y1dc 058ch 0 0 0 0 int 0 x2dc 0590h 0 0 0 0 int 0 y2dc 0594h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate s of three vertices for high - speed 2dtriangle drawing x0dc sets x coordinate s of vertex v0 y0dc sets y coordinate s of vertex v0 x1dc sets x coordinate s of vertex v1 y1dc sets y coordinate s of vertex v1 x2dc sets x coordinate s of vertex v2 y2dc sets y coordinate s of vertex v2
fujistu limited prel iminary and confiden tial MB86295S 259 specification manual rev1.1 10.2 .1 5 geometry control regis ter gctr (geometry control register) register address geometrybaseaddress + 00 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d fo rsv fcnt nf ff fe rsv gs rsv ss rsv ps r/w rx rx rx rx rx rx rx rx r rx r rx r initial value x 0 x 100000 0 0 1 x 00 x 00 x 00 the flags and status information of the geometry section are reflected in this register. note that the flags and status information of the drawing section are reflected in ctr . bit 1 and 0 ps ( pixel engine status ) indicate s status of pixel engine unit 00 idle 01 processing 10 reserved 11 reserved bit 5 and 4 ss ( geometry setup engine status ) indicate s status of geometry setup engine unit 00 idle 01 processi ng 10 processing 11 reserved bit 9 and 8 gs ( geometry engine status ) indicate s status of geometry engine unit 00 idle 01 processing 10 reserved 11 reserved bit 12 fe ( fifo empty ) indicates whether the data is contained in display l ist fifo (dfifod) 0 data in dfifod 1 no data in dfifod bit 13 ff ( fifo full) indicates whether display list fifo ( dfifod ) is full or not 0 dfifod not full 1 dfifod full
fujistu limited prel iminary an d confidential MB86295S 260 specification manual rev1.1 bit 14 nf ( fifo near full) indicates free space in display list fif o ( dfifod ) 0 more than half of dfifod free 1 less than half of dfifod free bit 20 to 15 fcnt ( fifo counter) indicate s count of free stages (0 to 100000 h ) of display list fifo ( dfifod ) bit 24 fo ( fifo overflow ) indicates whether fifo overflo w occurred 0 normal 1 fifo overflow
fujistu limited prel iminary and confiden tial MB86295S 261 specification manual rev1.1 10.2 .1 6 geometry mode registers the setregister command is used to write values to geometry mode registers. the geometry mode registers cannot be accessed from the cpu. gmdr0 (geometry mode register for vertex) register address geometrybaseaddress + 40 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name cf df st z c f r/w rw rw rw rw rw rw initial value 0 00 0 0 0 0 this register sets the ty pes of parameters input as vertex data and the type of projective transformation. bit 7 cf (color format) specifies color data format 0 independent rgb format / packed rgb format 1 reserved bit 6 and 5 df (data format) specif ies vertex coordinat e s data format 00 specifies floating - point format (only independent rgb format can be used as color data format.) 01 specifies fixed - point format (only packed rgb format can be used as color data format.) 10 reserved 11 specifies packed integer for mat (only packed rgb format can be used as color data format.) cf df input data format 0 00 floating - point format + independent rgb format 01 fixed - point format + packed rgb format 10 reserved 11 packed integer format + packed rgb format 1 00 res erved 01 reserved 10 reserved 11 reserved
fujistu limited prel iminary an d confidential MB86295S 262 specification manual rev1.1 bit 3 st (texture s and t data enable) sets whether to use texture st coordinate s 0 not use texture st coordinate s 1 uses texture st coordinate s bit 2 z (z data enable) sets whether to use z c oordinate s 0 not use z coordinate s 1 uses z coordinate s bit 1 c (color data enable) sets whether to use vertex color 0 not use vertex color 1 uses vertex color bit 0 f (frustum mode) sets projective transformation mode 0 orthogonal pr ojection transformation mode 1 perspective projection transformation mode
fujistu limited prel iminary and confiden tial MB86295S 263 specification manual rev1.1 gmdr1 (geometry mode register for line) register address geometrybaseaddress + 44 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name bo ep aa r/w w w w initial value 0 0 0 this register sets the geometry mode at line drawing. bit 4 bo (broken line offset) sets broken line reference position 0 broken line reference position not cleared 1 broken lin e reference position cleared bit 2 ep (end point mode) sets end point drawing mode note that the end point is not drawn in line strip. 0 end point not drawn 1 end point drawn bit 0 aa (anti - alias mode) sets anti - alias mode 0 anti - alias no t performed 1 anti - alias performed
fujistu limited prel iminary an d confidential MB86295S 264 specification manual rev1.1 gmdr1e (geometry mode register for line extension) register address (setgmoderegister) bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name po lv tc bc uw bm tm bp sp bo ep aa r/w w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 0 this register sets the geometry processing extended mode at line drawing. the coral extended function can be used only when the c, z, and st fiel ds of gmdr0 are ? 0 ? . bit 31 po ( primitive order control) sets the draw order for body/edge/shadow 0 body - > edge - > shadow (faster) 1 shadow - > edge - > body (quality for anti - alias) bit 30 lv (line version control) sets the coral line algorit hm version 0 version 1.0 (for backward compatibility) 1 version 2.0 (recommended) bit 20 tc (thick line correct) sets the interpolation mode for the bold line joint 0 interpolation of bold line joint not performed 1 interpolation of bold line joint performed bit 16 bc (broken line correct) sets the interpolation mode for the dashed - line pattern 0 interpolation not performed 1 interpolation performed using dashed - line pattern reference address fixed mode bit 14 uw (uniform line wi dth) sets the line width equalization mode 0 equalization of line width not performed 1 equalization of line width performed bit 13 bm (broken line mode) sets the dashed - line pattern mode 0 dashed - line pattern pasted vertical to principal axi s of line (compatible with cremson). 1 dashed - line pattern pasted vertical to theoretical line bit 12 tm (thick line mode) sets the bold line mode 0 bold line drawn vertical to principal axis of line (compatible with cremson) o peration is not as s ured when tm = 0 is used together with tc = 1, sp = 1, or bp = 1.
fujistu limited prel iminary and confiden tial MB86295S 265 specification manual rev1.1 1 bold line drawn vertical to theoretical line operation is not assured w hen tm = 1 is used together with bm = 0. bit 9 bp (border primitive) sets the drawing mode for the border pri mitive 0 border primitive not drawn 1 border primitive drawn bit 8 sp (shadow primitive) sets the drawing mode for the shadow primitive 0 shadow primitive not drawn 1 shadow primitive drawn bit 4 bo (broken line offset) sets the reference position of the dashed - line pattern 0 reference position of dashed - line pattern cleared 1 reference position of dashed - line pattern not cleared bit 2 ep (end point mode) sets the drawing mode for the end point note that the end point is always n ot drawn in line strip 0 end point not drawn 1 end point drawn bit 0 aa (anti - alias mode) sets anti - alias mode 0 anti - alias not performed 1 anti - alias performed gmdr2 (geometry mode register for triangle) register address geometrybaseaddre ss + 48 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fd cf r/w w w initial value 0 0 this register sets the geometry processing mode when a triangle is drawn. drawing performed using commands in range from g_begin/g_begincont to g_end bit 2 fd (face definition) sets the face definition 0 face defined as state with vertexes arranged clockwise 1 face defined as state with vertexes arranged counterclockwise
fujistu limited prel iminary an d confidential MB86295S 266 specification manual rev1.1 bit 0 cf (cull face) sets the drawing mode of the back 0 b ack drawn 1 back not drawn (value disabled for polygons)
fujistu limited prel iminary and confiden tial MB86295S 267 specification manual rev1.1 gmdr2e (geometry mode register for triangle extension) register address (setgmoderegister) bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name tl sp fd cf r/w w w w w initial value 0 0 0 0 this register sets the geometry processing extended mode at triangle drawing. bit 10 tl (top - left rule mode) sets the drawing algorith m 0 top - left rule applied (compatible with cremson) 1 top - left rule not applied bit 8 sp (shadow primitive) sets the drawing mode for the shadow primitive 0 shadow primitive not drawn 1 shadow primitive drawn bit 2 fd (face definition) sets the face definition 0 face defined as state with vertexes arranged clockwise 1 face defined as state with vertexes arranged counterclockwise bit 0 cf (cull face) sets the drawing mode of the back 0 b ack drawn 1 back not drawn (value disa bled for polygons)
fujistu limited prel iminary an d confidential MB86295S 268 specification manual rev1.1 10. 2.1 7 display list fifo registers dfifog (geometry displaylist fifo with geometry) register address geometry baseaddress + 400 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name dfifog r/w w initial value don?t care fifo registers for display list transfer
fujistu limited prel iminary and confiden tial MB86295S 269 specification manual rev1.1 11 . timing diagram 11 .1 host interface 11 .1.1 pci interface standard pci v2.1.
fujistu limited prel iminary an d confidential MB86295S 270 specification manual rev1.1 11. 1.2 eeprom timing teds tedh tedd tedd teclkh teclkl teclkp pclk ecs ,edo edi eclk ~ ~
fujistu limited prel iminary and confiden tial MB86295S 271 specification manual rev1.1 11 .1.3 serial interfa ce timing tsds tsdh tssd clk strobe do tsdd di
fujistu limited prel iminary an d confidential MB86295S 272 specification manual rev1.1 11.2 i 2 c interface i 2 c bus timing fig.11.1 i2c bus timing interruption timing fig.11.2 interruption ti ming sda(i) scl(i) t s2scli t wbfi t h2scli t s2sdai t h2sdai t cscli t whscli t wlscli t s2scli t h2scli stop start restart sda(o) scl(o) t s2s clo t h2sclo t h2sdao t csclo t whsclo t wlsclo t s2sclo t h2sco stop start restart d7 d6 d5 d4 d3 d2 d1 d0 ack d7 d6 d5 d4 d3 d2 d1 d0 ack sda(i) scl(i) data or noise under acknowledg e input sda(i) scl(i) t phintr xint interruption timing except bus error t phintr xint interruption timi ng of bus error
fujistu limited prel iminary and confiden tial MB86295S 273 specification manual rev1.1 11.3 graphics memory interface the coral access timing and graphics memory access timing are explained here. 11.3.1 timing of read access to same row address fig. 11.3 timing of read access to same r ow a ddress the above ti ming diagram shows that read access is made four times from coral to the same row address of sdram. the actv command is issued and then the read command is issued after trcd elapses. then data that is output after the elapse of cl after the read command is issued is captured into coral. mclko cl trcd ma mwe mcas mras md row col data data data data col col col row: row address col: column address data: read data trc d: ras to cas delay time cl: cas latency dqm *timing when cl2 operating
fujistu limited prel iminary an d confidential MB86295S 274 specification manual rev1.1 11.3.2 timing of read access to different row addresses fig. 11.4 timing of r ead a ccess to d ifferent r ow a ddresses the above timing diagram shows that read access is made from coral to different row a ddresses of sdram. the first and next address to be read fall across a n sdram page boundary, so the pre - charge command is issued at the timing satisfying tras, and then after the elapse of trp, the actv command is reissued, and then the read command is is sued. row: row address col: column address data: read data tras: ras active time trcd: ras to cas delay time cl: cas latency trp: ras precharge time mclko tras cl trcd ma mwe mc as mras md row col data trp row col trcd cl data dqm *timing when cl2 operating
fujistu limited prel iminary and confiden tial MB86295S 275 specification manual rev1.1 11.3.3 timing of write access to same row address fig. 11.5 timing of write access to same r ow a ddress the above timing diagram shows that write access is made form times form coral to the same row address of sdram. the actv command is issued, and then after the elapse of trcd, the write command is issued to write to sdram. mclko trcd ma mwe mcas mras md row col data data data data col col col row: row address col: column address data: read data trcd: ras to cas delay time dqm
fujistu limited prel iminary an d confidential MB86295S 276 specification manual rev1.1 11.3.4 timing of write access to different row addresses fig. 11.6 timing of write a ccess to d ifferent r ow a ddresses the abov e timing diagram shows that write access is made from coral to different row addresses of sdram. the first and next address to be write fall across a n sdram page boundary, so the pre - charge command is issued at the timing satisfying tras, and then after t he elapse of trp, the actv command is reissued, and then the write command is issued. row: row address col: column address data: read data tras: ras active time trcd: ras to cas delay time trp: ras precharge time mclko tras trcd ma mwe mcas mras md row col data trp row col trcd data dqm
fujistu limited prel iminary and confiden tial MB86295S 277 specification manual rev1.1 11.3.5 timing of read/write access to same row address fig. 11.7 timing of r ead/ w rite a ccess to s ame r ow a ddress the above timing diagram shows th at write access is made immediately after read access is made from coral to the same row address of sdram. read data is output from sdram, lowd elapses, and then the write command is issued. row: row address col: column address data: read data tras: ras active time trcd: ras to cas delay time cl: cas latency trp: ras precharge time lowd: last output to write command delay mclko cl trcd ma mwe mcas mras md row col data dat a dqm timing when cl2 operating lowd col
fujistu limited prel iminary an d confidential MB86295S 278 specification manual rev1.1 11.3.6 delay between actv commands fig.11.8 de lay between actv commands the actv command is issued from coral to the row address of sdram after the elapse of trrd after issuance of the previous actv command. 11.3.7 delay between refresh command and next actv command fig. 11.9 delay between refresh command and next actv command the actv command is issued after the elapse of trc after issuance of the refresh command. row: row address trrd: ras to ras bank active delay time mclko ma mwe mcas mras row row trrd row: row address trc: ras cycle time mclko ma mwe mcas mras row trc
fujistu limited prel iminary and confiden tial MB86295S 279 specification manual rev1.1 11 . 4 display timing 11 . 4 .1 non - interlace mode fig. 11.10 non - interlace timing in the above dia gram, vtr, hdp, etc., are the setting values of their associated registers. the vsync/frame interrupt is asserted when display of the last raster ends. when updating display parameters, synchronize with the frame interrupt so no display disturbance occur s. calculation for the next frame is started immediately after the vertical synchronization pulse is asserted, so the parameters must be updated by the time that calculation is started. vdp+1 rasters vsync hsync vsp+1 rasters vtr+1 rasters vsw+1 rasters hdp+1 clocks hsp+1 clocks htp+1 clocks hsw+1 clocks hsync r i / gi / bi assert frame interrupt assert vsync interrupt latency ?? 14 clocks dispe ri/gi/bi dispe dclko 0 1 2 n - 1 n - 2 n=hdp+1 ri/gi/bi
fujistu limited prel iminary an d confidential MB86295S 280 specification manual rev1.1 11 . 4 .2 interlace video mode fig. 11.11 interlac e video timing in the above diagram, vtr, hdp, etc., are the setting values of their associated registers. the interlace mode also operates at the same timing as the interlace video mode. the only difference between the two modes is the output image data . vdp+1 rasters vsync hsync vsp+1 rasters vtr+1 rasters (odd field) vsw+1 rasters vtr+1 rasters (even field) vsw+1 rasters vsync hsync vdp+1 rasters vsp+1 rasters assert vsync interrupt asser t vsync interrupt assert frame interrupt ri/gi/bi ri/gi/bi
fujistu limited prel iminary and confiden tial MB86295S 281 specification manual rev1.1 11.4.3 composite synchronous signal when the eeq bit of the dcm register is ? 0 ? , the csync signal output waveform is as shown below. fig 11.12 composite synchronous signal without equalizing pulse when the eeq bit of the dcm register is ? 1 ? , the equalizing pulse is inserted into the csync signal, producing the waveform shown below. fig 11.13 composite synchronous signal with equalizing pulse the equalizing pulse is inserted when the vertical blanking time period starts. it is also inserted three times after the vertical synchronization time period has elapsed. csync vsync csync vsync odd field even field odd field even field csync vsync csync vsync odd field even field odd field even field
fujistu limited prel iminary an d confidential MB86295S 282 specification manual rev1.1 1 2 . electrical characteristics 12.1 introduction the values in this chapter are valid for the final specification of mb86295. 12.2 maximum rating maximum ratin g parameter symbol maximum rating unit power supply voltage v ddl * 1 v ddh - 0.5 < v ddl < 2.5 - 0.5 < v ddh < 4.0 v input voltage v i - 0.5 < v i < v ddh +0.5 (<4.0) v output current i o 13 ma power pin current ipow 6 8 ma ambient for storage temperature tst - 55 < tst < +125 c *1 includes pll power supply
fujistu limited prel iminary and confiden tial MB86295S 283 specification manual rev1.1 12 . 3 recommended operating conditions 1 2 . 3 .1 recommended operating conditions recommended operating conditions rating parameter symbol min. typ. max. unit supply voltage v ddl *1 v ddh 1.65 3.0 1.8 3.3 1.95 3.6 v input voltage (high level) v ih 2.0 v ddh + 0.3 v input voltage (low level) v il - 0.3 0.8 v ambient temperature for operation ta - 40 85 c *1 includes pll power supply 1 2 . 3 .2 note at power - on there is no restriction on the sequence of power - on/power - off between v ddl and v ddh . however, do not apply only v ddh for more than a few seconds. do not input hsync, vsync, and eo signals when the power supply voltage is not applied. (see the input voltage item in maximum rating .) th ere reset sequenc es is as follows: s is changed from ? low ? to ? high ? levels and then xrst is changed from ? low ? to ? high ? level: immediately after powe r - on, input the ? low ? level to the s pin for 500 ns or more . after the s pin is set to ? high ? level, input the ? low ? level to the xrst pins for 300 m s or more . s xrst more than 500ns 300 m s
fujistu limited prel iminary an d confidential MB86295S 284 specification manual rev1.1 1 2 . 4 dc characteristics measuring c ondition: v ddl = 1.8 1.5 v, v ddh = 3.3 0.3 v, v ss = 0.0 v, ta = 0 - 70 c rating parameter symbol min. typ. max. unit output voltage *1 (?high? level) v oh v ddh - 0.2 v ddh v output voltage *2 (?low? level) v ol 0.0 0.2 v output current (?high? level) i oh 1 *3 i oh 2 *4 i oh 3 *5 - 2.0 - 4.0 - 8.0 ma output current (?low? level) i ol 1 * 3 i ol 2 * 4 i ol 3 * 5 2.0 4.0 8.0 ma input leakage current il 5 a pin capacitance c 1 6 pf *1 i oh = - 100 a *2 i ol = 100 a *3 output characteristics of md0 to 63 and mdqm0 to 7 signals *4 output characteristics of signals other than signals indicated by *3 and *5 * 5 output characteristic of xint and mclk0 signals
fujistu limited prel iminary and confiden tial MB86295S 285 specification manual rev1.1 1 2 . 5 ac characteristic s 1 2 . 5 .1 host interface pci interface values parameter signal abbrev. min typ max units pci clock period pclk t pclkp 30 ns pci clock low time pclk t pclkl 11 ns pci clock high time pclk t pclkh 11 ns pci input setup (bussed signals) ad[31:0 ], c/be[3:0], par, frame, irdy, trdy, stop, idsel, devsel, perr t ps 7 ns pci input setup (point - to - point signals) gnt t psp 10 ns pci input hold ad[31:0], c/be[3:0], par, frame, irdy, trdy, stop, idsel, devsel, perr, gnt t ph 0 ns pci output delay a d[31:0], c/be[3:0], par, frame, irdy, trdy, stop, idsel, devsel, perr, serr, req t pd 2 11 ns pci eeprom interface values parameter signal abbrev. min typ max units eeprom data setup edi t eds 5 ns eeprom data hold edi t edh 5 ns
fujistu limited prel iminary an d confidential MB86295S 286 specification manual rev1.1 eeprom data d elay edo, eck, ecs t edd 3 20 ns eeprom clock period eck t eclkp 1000 ns eeprom clock low time eck t eclkl 500 ns eeprom clock high time eck t eclkh 500 ns serial interface values parameter signal abbrev. min typ max units serial strobe dela y sb t ssd - - ns serial data data edo t sdd - - ns serial data setup edi t sds - ns serial data hold edi t sdh - ns
fujistu limited prel iminary and confiden tial MB86295S 287 specification manual rev1.1 12.5.2 i 2 c interface i 2 c bus timing symbol min max unit standard 250 ns t s2sdai sda(i) setup time high - speed 100 ns standard 0 ns t h2sdai scl(i) hold time high - speed 0 ns standard 10.0 us t cscli scl(i) cycle time high - speed 2.5 us standard 4.0 us t whscli scl(i) h period high - speed 0.6 us standard 4.7 us t wlscli scl(i) l period high - speed 1.3 us standard 2*m+2 (*2) pclk *1 t csclo scl(o) cycle time high - speed int(1.5*m)+2 (*2) pclk *1 standard m+2 (*2) pclk *1 t whsclo scl(o) h period high - speed int(0.5*m)+2 (*2) pclk *1 standard m (*2) pclk *1 t wlsclo scl(o) l period high - speed m (*2) pclk *1 standard 4.0 us t w2scli scl(i) setup time high - speed 0.6 us standard 4.7 us t h2scli scl(i) hold time high - speed 1.3 us standard 4.7 us t wbfi bus free time hirh - speed 1.3 us standard m+2 (*2) pclk *1 t s2sclo scl(o) set up time high - spee d int(0.5*m)+2 (*2) pclk *1 standard m - 2 (*2) pclk *1 t h2sclo scl(o) hold time high - speed int(0.5*m) - 2 (*2) pclk *1 t h2sdao sda(o) hold time 5 pclk *1 *1 pclk is an internal clock of i2c module. (16.6mhz) *2 refer to the clock control register (ccr) for the value of m. timing of interrupt symbol min max unit t phintr xint delay (bus error) 4 pclk t phintr xint delay (except bus error) 4 pclk
fujistu limited prel iminary an d confidential MB86295S 288 specification manual rev1.1 1 2 . 5 . 3 video interface clock rating parameter symbol condition min. typ. max. unit clk frequen cy f clk 14.3 18 mhz clk h - width t hclk 25 ns clk l - width t lclk 25 ns dclki frequency f dclki 67 mhz dclki h - width t hdclki 5 ns dclki l - width t ldclki 5 ns dclko frequency f dclko 67 mhz input signals ratin g parameter symbol condition min. typ. max. unit t whsync0 *1 3 clock hsync input pulse width t whsync1 *2 3 clock hsync input setup time t shsync *2 10 ns hsync input hold time t hhsync *2 10 ns vsync input pulse width t whsync1 1 hsync 1 cycle *1 applied only i n pll synchronization mode (cks = 0), reference clock output from internal pll ( cycle = 1/14*fclk) *2 applied only i n dclki synchronization mode (cks = 1), reference clock = dclki output signals rating parameter symbol condition min. typ. max. unit r gb output delay time t rgb 2 11 ns dispe output delay time t deo 2 10 ns hsync output delay time t dhsync 2 10 ns vsync output delay time t dvsync 2 10 ns csync output delay time t dcsync 2 10 ns gv output delay time t dgv 2 10 ns
fujistu limited prel iminary and confiden tial MB86295S 289 specification manual rev1.1 1 2 . 5 . 4 gra phics memory interface an assumed external capacitance an assumed external capacitance parameter min typ max unit board pattern 5.0 15.0 pf sdram (clk) 2.5 4.0 pf sdram (d) 4.0 6.5 pf sdram (a, dqm) 2.5 5.0 pf clock rating parameter symbol conditi on min. typ. max. unit mclk o frequency f m clko *1 mhz m clk o h - width t hmclko 1 .0 ns m clk o l - width t lmclko 1 .0 ns mclki frequency f m clki *1 mhz mclki h - width t hmclki 1.0 ns mclki l - width t lmclki 1.0 ns *1 for the bus - async hronous mode, the frequency is 1/3 of the oscillation frequency of the internal pll. for the bus - synchronous mode, the frequency is the same as the frequency of bclki. input signals rating parameter symbol condition min. typ. max. unit md input da ta setup time t mdids *2 2.0 ns md input data hold time t mdidh *2 0.7 ns *2 it means against mclki.
fujistu limited prel iminary an d confidential MB86295S 290 specification manual rev1.1 there are some cases regarding ac specifications of output signals. the following tables shows typical twelve cases of external sdrfam capacitance. (1) external sdram capacitance case 1 external sdram capacitance sdram x1 total capacitance unit mclko 9.8pf (dram clk 2.5pf, board pattern 5pf) pf ma,mras,mcas,mwe 7.5pf (dram a.dqm 2.5pf, board pattern 5pf) pf md,dqm 9.0pf (dram d 4pf, board pattern 5 pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 4.2 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.0 ns mdqm a ccess time t mdqmd 1.1 5.4 ns md o utput access time t md od 1.1 5.4 ns (2) external sdram capacitance case 2 external sdram capacitance sdram x1 total capacitance unit mclko 24.8pf (dram clk 4.0pf, board pattern 15pf) pf ma,mras,mcas,mwe 20.0pf (dram a.dqm 5pf, board pattern 15pf) pf md,dqm 21.5pf (dram d 6.5pf, board pattern 15pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.5 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.2 ns mdqm a ccess time t mdqmd 1.2 5.5 ns m d o utput access time t mdod 1.2 5.5 ns
fujistu limited prel iminary and confiden tial MB86295S 291 specification manual rev1.1 (3) external sdram capacitance case 3 external sdram capacitance sdram x2 total capacitance unit mclko 12.3pf (dram clk 2.5pf x2, board pattern 5pf) pf ma,mras,mcas,mwe 10.0pf (dram a.dqm 2.5pf x2, board pattern 5pf) pf md,dqm 9.0pf (dram d 4pf, board pattern 5pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 4.1 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.0 ns mdqm a ccess time t mdqmd 1.1 5.2 ns md o utput access time t mdod 1.1 5.2 ns (4) external sdram capacitance case 4 external sdram capacitance sdram x2 total capacitance unit mclko 28.8pf (dram clk 4.0pf x2, board pattern 15pf) pf ma,mras,mcas,mwe 25.0pf (dram a. dqm 5pf x2, board pattern 15pf) pf md,dqm 21.5pf (dram d 6.5pf, board pattern 15pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.4 ns ma, mras, mcas, mwe a ccess time t m ad 1.1 5.4 ns mdqm a ccess time t mdqmd 1.1 5.5 ns md o utput access time t mdod 1.1 5.5 ns
fujistu limited prel iminary an d confidential MB86295S 292 specification manual rev1.1 (5) external sdram capacitance case 5 external sdram capacitance sdram x4 total capacitance unit mclko 17.3pf (dram clk 2.5pf x4, board pattern 5pf) pf m a,mras,mcas,mwe 15.0pf (dram a.dqm 2.5pf x4, board pattern 5pf) pf md,dqm 9.0pf (dram d 4pf, board pattern 5pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.9 ns ma, m ras, mcas, mwe a ccess time t m ad 1.0 5.2 ns mdqm a ccess time t mdqmd 1.0 5.0 ns md o utput access time t mdod 1.0 5.0 ns (6) external sdram capacitance case 6 external sdram capacitance sdram x4 total capacitance unit mclko 36.8pf (dram clk 4.0pf x4 , board pattern 15pf) pf ma,mras,mcas,mwe 35.0pf (dram a.dqm 5pf x4, board pattern 15pf) pf md,dqm 21.5pf (dram d 6.5pf, board pattern 15pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time agains t mclko t d id 0 3.4 ns ma, mras, mcas, mwe a ccess time t m ad 1.2 5.7 ns mdqm a ccess time t mdqmd 1.0 5.3 ns md o utput access time t mdod 1.0 5.3 ns (7) external sdram capacitance case 7 external sdram capacitance sdram x1 total capacitance unit
fujistu limited prel iminary and confiden tial MB86295S 293 specification manual rev1.1 m clko 10.0pf (dram clk 2.5pf, board pattern 5pf) pf ma,mras,mcas,mwe 7.5pf (dram a.dqm 2.5pf, board pattern 5pf) pf md,dqm 9.0pf (dram d 4pf, board pattern 5pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signa l delay time against mclko t d id 0 4.2 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.0 ns mdqm a ccess time t mdqmd 1.1 5.4 ns md o utput access time t mdod 1.1 5.4 ns (8) external sdram capacitance case 8 external sdram capacitance sdram x1 total capacitance unit mclko 25.0pf (dram clk 4.0pf, board pattern 15pf) pf ma,mras,mcas,mwe 20.0pf (dram a.dqm 5pf, board pattern 15pf) pf md,dqm 21.5pf (dram d 6.5pf, board pattern 15pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.5 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.2 ns mdqm a ccess time t mdqmd 1.2 5.5 ns md o utput access time t mdod 1.2 5.5 ns
fujistu limited prel iminary an d confidential MB86295S 294 specification manual rev1.1 (9) external sdram capacitance case 9 external sdram ca pacitance sdram x2 total capacitance unit mclko 12.5pf (dram clk 2.5pf x2, board pattern 5pf) pf ma,mras,mcas,mwe 10.0pf (dram a.dqm 2.5pf x2, board pattern 5pf) pf md,dqm 9.0pf (dram d 4pf, board pattern 5pf) pf output signals rating *1 parameter symbol condit ion min. typ. max. unit mclki signal delay time against mclko t d id 0 4.1 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.0 ns mdqm a ccess time t mdqmd 1.1 5.2 ns md o utput access time t mdod 1.1 5.2 ns (10) external sdram capacitan ce case 10 external sdram capacitance sdram x2 total capacitance unit mclko 29pf (dram clk 4.0pf x2, board pattern 15pf) pf ma,mras,mcas,mwe 25.0pf (dram a.dqm 5pf x2, board pattern 15pf) pf md,dqm 21.5pf (dram d 6.5pf, board pattern 15pf) pf output s ignals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.4 ns ma, mras, mcas, mwe a ccess time t m ad 1.1 5.4 ns mdqm a ccess time t mdqmd 1.1 5.5 ns md o utput access time t mdod 1.1 5.5 ns
fujistu limited prel iminary and confiden tial MB86295S 295 specification manual rev1.1 (11) external sdram capacitance case 11 external sdram capacitance sdram x4 total capacitance unit mclko 17.5pf (dram clk 2.5pf x4, board pattern 5pf) pf ma,mras,mcas,mwe 15.0pf (dram a.dqm 2.5pf x4, board pattern 5pf) pf md,dqm 9.0pf (dram d 4pf, bo ard pattern 5pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.9 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.2 ns mdqm a ccess time t mdqmd 1.0 5.0 ns md o utput ac cess time t mdod 1.0 5.0 ns (12) external sdram capacitance case 12 external sdram capacitance sdram x4 total capacitance unit mclko 37.0pf (dram clk 4.0pf x4, board pattern 15pf) pf ma,mras,mcas,mwe 35.0pf (dram a.dqm 5pf x4, board pattern 15pf) pf md,dqm 21.5pf (dram d 6.5pf, board pattern 15pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.4 ns ma, mras, mcas, mwe a ccess time t m ad 1.2 5.7 ns mdqm a ccess time t mdqmd 1.0 5.3 ns md o utput access time t mdod 1.0 5.3 ns
fujistu limited prel iminary an d confidential MB86295S 296 specification manual rev1.1 12 . 5 . 5 pll specifications parameter rating description input frequency (typ.) 14.31818 mhz output frequency 400.9090 mhz 28 duty ratio 101. 6 to 93. 0 % h/l pulse width ratio of pll out put jitter 60 to - 60 ps frequency tolerant of two consecutive clock cycles clksel1 clksel1 input frequency assured operation range (*1) l l 13.5 mhz 13.365 to 13.5 mhz l h 14.32 mhz 14.177 to 14.32 mhz h l 17.73 hz 17.553 to 17.73 mhz *1 assured o peration input frequency range: standard value ? 1%
fujistu limited prel iminary and confiden tial MB86295S 297 specification manual rev1.1 12.6 ac characteristics measuring conditions 80 % 20 % 80 % 20 % ?i v ih +v il ?j / 2 v dd / 2 v dd / 2 t r t f tphl tplh v dd / 2 tpzl tplz v dd / 2 0.5 v 0.5 v tphz tpzh input output output enabled output disabled tr, tf 5 ns v ih =2.0 v, v il = 0.8v ( 3.3 - v cmos interface input )
fujistu limited prel iminary an d confidential MB86295S 298 specification manual rev1.1 1 2 . 7 timing diagram 1 2 . 7 .1 host interface clock xint output delay times pclk 1/f pclk t lpclk t hpclk pclk t intd xint (output)
fujistu limited prel iminary and confiden tial MB86295S 299 specification manual rev1.1 12 . 7 .2 video interface clock hsync signal setup/hold output signal delay dclko t rgb , t deo , t dhsync, t dvsync , t dcsync, t dgv dr7 - 2, dg7 - 2 db7 - 2 md63 - 58* hsync (output) vsync (output) csync, de gv *valid if xrgben = 0 clk 1/f clk t lclk t hclk v ih v il dclki t hdclki t ldclki 1 / f dclki t shsyn t hhsyn hsync (input)
fujistu limited prel iminary an d confidential MB86295S 300 specification manual rev1.1 1 2 . 7 . 3 graphics memory interface clock input signal setup/hold time mclki signal delay mclko, mclki 1/f mclko, 1/f mclki t hmclko, t hmclki t lmclko, t lmclki mclki t mdids md t mdidh input data mclko t oid mclki
fujistu limited prel iminary and confiden tial MB86295S 301 specification manual rev1.1 output signal delay mclko t mad, t mdod, t mdqmd ma, mras, mcas, mwe, md, mdqm
the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of the information or package dimensions in this document. fujitsu semiconductor data sheet ball grid array package 256 pin plastic 256-pin plastic bga lead pitch 50 mil pin matrix 20 sealing method plastic mold 256-pin plastic bga (bga-256p-m02) (bga-256p-m02) c 1995 fujitsu limited bga256004sc-2-1 24.00?.10(.94?004) 27.00?.20(1.06?008)sq index 0.60?.10 (.024?004) 2.30?.20 (.091?008) 24.13?.20(.95?008) 0.75?.15(.03?006) 1 pin 1.27?.20 (.05?008) 0.15(.006) dimensions in mm (inches). bga-256p-m02 9711 note: the actual shape of corners may differ from the dimension.

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