the gd14516a high definition tv deserialiser is designed for point-to-point serial transmission systems for hdtv signals according to smpte292. the device provides a fully integrated solution for: u clock recovery and data re-timing at 1485 mbit/s u descrambler and nrzi decoder u frame detector for sav/eav u 1:20 demux. the clock and data recovery circuit consists of: u a bang-bang phase detector (pd) with data re-timing u phase-frequency comparator (pfc), u a lock detect circuit (lcd) with lock alarm output, u a tristatable charge pump u a wide tuning range vco. the vco centre frequency is determined by the refck multiplied by 20. the loop filter time constant is determined by an external rc filter. when in lock, the digital lock detect cir- cuit uses the incoming data to control the pll. when not in lock, i.e. the vco fre- quency is more than 500 ppm away from the refck frequency, the ldc switches to the local clock (refck) until the vco frequency once more enters the 500 ppm range. then it switches back to the pd, comparing the vco clock to the incoming data stream. the ldc con- tinuously monitors the vco frequency against the refck input, clearing lock if the vco leaves the lock range. a frame alignment circuit detects the eav/sav framing pattern and aligns data at the 20 bit output port. the frame align- ment can be disabled to allow other coding schemes. the high-speed data input is differential and compatible with pecl levels. it is connected via loop-through transmission lines to minimize stub related reflections. for repeater applications a re-timed 75 s cable driver output is provided, which also can be used to drive an optical module. the gd14516a is packaged in a 68 pin leaded multi layer ceramic (mlc) pack- age with cavity down for easy cooling. advance information features l nominal data-rate 1485 mbit/s nrzi. l two operating ranges: ? 1.2 -1.5 gbit/s ? 300 - 375 mbit/s l timing and alignment jitter in accor- dance with smpte292. l high-speed data input and output use loop-through bondings to reduce reflections. l complete clock/20 (data recovery) and lock acquisition on one ic. l digitally controlled capture and lock. ? full capture range with true phase/frequency detect between vco-clk and refck. ? bang-bang phase detector be- tween vco-clk and data. ? lock in range 500 ppm or 2000 ppm referred to refck. ? lock alarm output. l end of active video (eav) / start of active video (sav) detection and alignment of the parallel 20 bit output l re-timed differential 75 w cable driver output with external termination resistors. l supply operation : 5 v and 3.3 v. l power dissipation: 2500 mw typ. l power down modes for repeater applications. l 68 pin multi layer ceramic (mlc) leaded package with transmission lines. applications l hdtv studio equipment. hdtv deserialiser gd14516a data sheet rev. 03 sop son par dout0 dout19 sip sin den tcken vctl tck nen tckn sen sel1 cph0/1 vcca vccd vcco vcc_cdr vcc_dmx cip vee v3v3 v3v3a refckn refck /20 clock divide lock detect 4:2 mux phase ctrl pfc vco charge pump frame align. div. /4 bang bang phase detector demux nrzi & scrambler do di u u v u dd r d sel0 outchp ffin fp lock ckout
function details the clock and data recovery (cdr) part of the gd14516a consists of: u an input amplifier, u a voltage controlled oscillator (vco), u a phase detector u a loop filter u a charge pump u a phase-frequency comparator the charge pump performs the transfor- mation between the digital error signal of the phase detector and the voltage con- trolling the oscillator. the true phase-frequency comparator is used when acquiring lock and a lock detection circuit determines whether or not the pll is locked onto incoming data. a divide by 4 option (den input) follow- ing the on-chip oscillator provides two tuning ranges for the vco 1200 ? 1500 mhz (den = ?0?) 300 ? 375 mhz (den = ?1?) when the cdr has acquired lock, the frame detect/alignment circuit - if enabled - searches for an eav/sav framing pattern and aligns the parallel data outputs accordingly. all logic blocks in the design are differen- tially coupled, i.e. both clocks and signals are differential. this in conjunction with the de-coupled power planes in the pack- age, provide a low jitter content in the parallel output data. the phase detector the phase detector (pd) used in the cdr is designed to give minimum static phase error of the pll. it is of the true digital type (bang-bang), producing a bi- nary output. it samples data prior to, in the vicinity of and after any potential bit transition. when a transition has oc- curred the value of the sample in the vi- cinity of the transition tells whether the vco clock leads or lags the incoming data and the phase detector produces a binary output accordingly. hence the pll is controlled by the bit transition point. the output of the pd is binary with three values indicating whether the vco must go up or down in frequency, if a bit transition has occurred, or stay, if not (consecutive ?1"s or ?0"s). this informa- tion is fed into the charge pump, which transfers it into three output levels, sink- ing or sourcing current or tristating the output. the output of the charge pump is integrated and filtered outside the chip by two resistors and a capacitor. the initial values has been determined to 51 s and 100 nf in parallel with 2 m f, with a resis- tor of 1 k s connected in series with the charge pump output. these values can be altered to achieve the optimal charac- teristics for the application. the phase-frequency comparator the phase-frequency comparator (pfc) ensures predictable lock up condi- tions for the gd14516. it is used during acquisition, and serves as means to pull the vco into the range of the data rate where the pd is capable of acquiring lock. the comparator is of the set-reset type, comparing the edges of the vco frequency divided by 20 and the local ref- erence clock (refck). the output of the pfc tells whether the vco must be ad- justed up or down, proportional to the phase error between the clocks. this in- formation is fed into the charge pump, which provides sinking or sourcing cur- rent for the loop filter capacitor. figure 1. lock detect scheme. the refck input is configured as a dif- ferential input, but will also operate as single ended ttl input due to the inter- nal 1.4 v dc-bias on the inverted input. use external decoupling to set a clean threshold. the lock detect circuit the lock detect circuit (ldc) is the guarantee of a fast and reliable lock up. it monitors the difference between the di- vided vco clock and the reference clock (refck), when the pll is locked onto the incoming data by the pd. if the differ- ence between the divided vco clock and the clock reference is greater than 500 ppm, the ldc considers the pll to be out of lock, and switches to the pfc to pull the vco frequency into the data rate range. the alarm lock output is set low. when the ldc has monitored the vco frequency to be within the data rate range over a period corresponding to 500 ppm, it switches back to the pd and starts acquiring lock onto data. this way the recovered output clock is always kept within the 500 ppm, regardless of the serial data line is active or not. frame detector & alignment when the ffin signal is high, the frame detector & alignment (fda) starts look- ing for eav/sav in the incoming data stream and aligns data whenever sav/eav is found regardless of the cur- rent alignment. the 20 bit data outputs will be completely aligned by the fda upon reception of the first eav or sav sequence and the fp output activated. a parity output is provided for test pur- poses. this output is a synchronous xor of the parallel output data. power down gd14516a has been designed to allow 2 power down modes as listed below. please note that in all modes the appro- priate supply voltages should always be applied to the v 3v3 ,v cc and v ee pins: cdr (v cc_cdr = +5v, v cc_dmx = 0v): re-timed repeater without demux, but serial input and output, cdr, vco and lock detect are active. bypass (v cc_cdr = 0v, v cc_dmx = 0v): repeater with only serial input and out- put active. normal (v cc_cdr = +5v, v cc_dmx = +5v): standard mode of operation with all cir- cuits active. v cc_cdr &v cc_dmx require approximately 1 ma and can be switched by cmos logic. data sheet rev. 03 gd14516a page 2
applications figure 2. standard input configuration. figure 3. pecl input configuration. figure 4. loop filter note: de-coupling should be made from vcc to vee plane. use 33 nf chip capacitors close to package pins. figure 5. differential pecl driver figure 6. dual 75r cable driver data sheet rev. 03 gd14516a page 3 sip sip to cable sin 75 100n 100n 200n 37 10k 10k sin 3v vee vee sip sip in in sin 50 50 10k 10k sin 3v vee 3v vcc vctl 1k 51 100n || 2 2 m ouchp sop son cip vcc vcc vcc vee vee 4k 0.5ma 50 50 50 100 2k sop son cip vcc vcc vcc vee vee 1k 100n 100n 1.0ma 75 75 2k
pin list mnemonic: pin no.: pin type: description: sip sin 29, 30 27, 28 analog in serial data input (differential). compatible with pecl levels. loop-back termination: each input is connected to two pins, one for input and the other for the termination resistor. see figures on page 3. sop son 24, 25 22, 23 open collector re-timed differential serial data output. high speed open collec- tor outputs to be used with 75 w cable or 50 w termination for op- tical transmitter. see figures on page 3. cip 32 analog in dc-current control input for sop, son: 1ma current into cip generates 25ma bias for the differential output stage. maximum setting is 1.2ma => 30ma output stage bias. if cip is pulled low, the output stage will turn off. dout0, dout1 dout2, dout3 dout4, dout5 dout6, dout7 dout8, dout9 dout10, dout11 dout12, dout13 dout14, dout15 dout16, dout17 dout18, dout19 58, 59 61, 62 63, 64 66, 67 2, 3 5, 6 7, 8 10, 11 12, 13 15, 16 ttl out re-timed parallel data output from demux. after frame synchro- nisation, bit 0 holds the first bit received (lsb). ckout 57 ttl out regenerated output clock, vco frequency divided by 20. refck, refckn 44, 45 ttl in reference clock input with frequency equal to data rate divided by 20, 74.25 mhz @ 1.485 gbit/s. internal 1.4 v dc-bias on refckn should be externally de-coupled or driven. sel0 46 ttl in lock detect range select: ?0? 2000 ppm ?1? 500 ppm sel1 33 pll override ?0? pfc always used ?1? lock detect circuit selects pfc or pd cph0, cph1 20, 19 ttl in phase relation select between ckout and the loading of the parallel data. data ready after ckout rising edge: cph1 cph0 11 t del =0 e 00 t del =90 e 10 t del = 180 e 01 t del = 270 e ffin 49 ttl in enable alignment of the parallel outputs on each eav/sav. par 53 ttl out parity (synchronuos xor) of parallel output data. fp 50 ttl out eav/sav frame detect output. one pulse at 74.25 mhz indicates that a valid frame sequence has been detected. lock 40 ttl out cdr lock alarm output. when low, the divided vco frequency deviates more than 500/ 2000 ppm from refck. vctl 37 analog in vco control voltage input. ouchp 39 analog out charge pump output providing sink or source current for the integrating capacitor in the external loop filter. tcken 36 ttl in bypass vco input for dc-functional and parametric testing only . tie to vee when not used. ?0? enable vco, disable tck,tckn clock input. ?1? test mode: disable vco, enable tck,tckn clock input. tck, tckn 41, 42 analog in test clock input, see tcken. tie to vee when not used. sen 56 ttl in scrambler ?0? enable scrambler ?1? disable scrambler data sheet rev. 03 gd14516a page 4
mnemonic: pin no.: pin type: description: nen 54 ttl in nrzi encoder ?0? enable nrzi ?1? bypass nrzi den 47 ttl in control of vco divide by 4 ?0? disable divide by 4 ?1? enable divide by 4 vcc_dmx 17 pwr ctl power down demux. vcc_cdr must be ?1? ?0? disable demux and parallel clock output ?1? enable demux vcc_cdr 34 pwr ctl power down re-timer ?0? power down (async. repeater) ?1? enable re-timer v3v3 68 pwr +3.3 v power for data path. v3v3a 51 pwr +3.3 v power for pfc and cdr. vee 4, 9, 14, 21, 26, 31, 38, 43, 48, 55, 60, 65 pwr 0 v power. vcca 35 pwr +5 v power for vco. vccd 18 pwr +5 v power for cable driver vcco 1, 52 pwr +5 v power for ttl i/o. data sheet rev. 03 gd14516a page 5
package pinout figure 7. package 68 pin mlc, top view data sheet rev. 03 gd14516a page 6 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 vcc_dmx dout19 dout18 vee dout17 dout16 dout15 dout14 vee dout13 dout12 dout11 dout10 vee dout9 dout8 vcco v3v3 dout7 dout6 vee dout5 dout4 dout3 dout2 vee dout1 dout0 ckout sen vee nen par vcco v3v3a fp ffin vee den sel0 refckn refck vee tckn tck lock ouchp vee vctl tcken vcca vcc_cdr sel1 cip vee sip sip sin sin vee sop sop son son vee cph0 cph1 vccd
maximum ratings these are the limits beyond which the component may be damaged. symbol: characteristic: conditions: min.: typ.: max.: unit.: v 3v3 ,v cc positive supply v ee -0.5 7 v v i max,cip input voltage for cip v ee -0.5 v cc +0.5 v i i max,cip input current for cip -1.0 3.0 ma v o max output voltage v ee -0.5 v cc +0.5 v i o max output current 40 ma v i max input voltage v ee -0.5 v cc +0.5 v i i max input current -1.0 1.0 ma t o operating temperature junction -40 +125 o c t s storage temperature -65 +175 o c note: temperature range specify only reliability regarding damage. performance is only tested and quaranteed for the t case as given below. dc characteristics t case =0 cto70 c, q j-c =7 c/w. appropriate heat sinking is required. all voltages in the table are referred to v ee .v cc_cdr =5v,v cc_dmx =5v symbol: characteristic: conditions: min.: typ.: max.: unit: v cc v cca v cco 5 v supply voltage 4.75 5.00 5.25 v i cc total current from v cc ,v cca ,v cco 270 ma v 3v3 3.3 v core supply voltage 3.1 3.3 3.5 v i 3v3 current from v 3v3 350 ma pd power dissipation 2500 mw v c sip/sin sip/sin data common mode voltage v cc -2.0 v cc -0.5 v v i sip/sin sip/sin data minimum input voltage sip/sin data maximum input voltage note 1 200 400 1000 mv p-p mv p-p v iih ttl ttl input hi voltage 2.0 4.0 v v iil ttl ttl input lo voltage 0.8 v i ih ttl ttl input hi current v ih max 500 m a i il ttl ttl input lo current v il min -500 m a v oh ttl ttl output hi voltage note 2 2.4 v v ol ttl ttl output lo voltage note 2 0.5 v i oh sop/son open collector output hi sink current note 3 -20 -25 -30 ma i ol sop/son open collector output lo sink current note 3 -0.5 ma v vctl vco control voltage i vctl <30 m a 0.5 v cc -1.5 v i oh cph ouchp source current (dc steady) note 4 500 1000 m a i ol cph ouchp sink current (dc steady) note 4 -500 -1000 m a note 1: data eye diagram in accordance with smpte292, terminated via loop-through to 75 w . note 2: r load = 500 w to 1.4 v. note 3: r load =50 w to v cc . current into cip=1 ma. output logic level ?1" corresponds to lo current. note 4: output terminated to 2.5 v during test. data sheet rev. 03 gd14516a page 7
ac characteristics figure 8. data output delay from ckout for cph0/1 = 1,1 t case =0 cto70 c, v cc = 5.0 v, v 3v3 = 3.3 v symbol: characteristic: conditions: min.: typ.: max.: unit: j tol jitter tolerance 10h z package outline ordering information to order, please specify as shown below: product name: package type: case temperature range: option: GD14516A-68BA 68 pin ceramic (mlc) 0..70 o c gd14516a,(club device) data sheet rev. 03 - date: 26 february 1999 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark telephone : +45 4492 6100 telefax : +45 4492 5900 e-mail : sales@giga.dk web site : http://www.giga.dk please check our internet web site for latest version of this data sheet. distributor: copyright ? 1999 giga a/s all rights reserved
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