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ps008701-0201 product specification z86e72/73 otp microcontroller zilog worldwide headquarters ? 910 e. hamilton avenue campbell, ca 95008 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com
ps008701-0201 - this publication is subject to replacement by a later edition. to determine whether a later edition exists, or to request copies of publications, contact: zilog worldwide headquarters 910 e. hamilton avenue campbell, ca 95008 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com zilog is a registered trademark of zilog inc. in the united states and in other countries. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. document disclaimer ? 2001 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
z86e72/73 otp microcontroller ps008701-0201 iii table of contents features ....................................................... 1 generaldescription............................................... 2 pindescription .................................................. 5 absolutemaximumratings........................................ 13 standardtestconditions ......................................... 14 capacitance.................................................... 14 dccharacteristics .............................................. 15 accharacteristics............................................... 18 pinfunctions................................................... 25 /ds(output,activelow) ....................................... 25 /as(output,activelow) ....................................... 25 xtal1crystal1(time-basedinput) ............................. 25 xtal2crystal2(time-basedoutput) ............................ 25 r//wread/write(output,writelow) ............................. 25 r//rl(input) ................................................ 25 port0(p07?p00)............................................. 25 port1(p17?p10)............................................. 28 port2(p27?p20)............................................. 30 port3(p37?p31)............................................. 31 comparatorinputs............................................ 32 comparatoroutputs .......................................... 33 /reset(input,activelow)..................................... 35 functionaldescription............................................ 36 reset ...................................................... 36 programmemory............................................. 36 ram ...................................................... 37 extendeddataram .......................................... 37 externalmemory ............................................. 38 expandedregisterfile ........................................ 39 registerfile................................................. 42 stack ...................................................... 43 counter/timerregisterdescription .............................. 43 counter/timerfunctionalblocks ................................ 53 interrupts ................................................... 62 clock ...................................................... 64
z86e72/73 otp microcontroller ps008701-0201 iv power-onreset(por)........................................ 65 halt ...................................................... 66 stop...................................................... 66 portconfigurationregister(pcon) .............................. 66 stop-moderecoveryregister(smr) ............................. 67 stop-moderecoveryregister2(smr2) .......................... 71 watch-dogtimermoderegister(wdtmr)........................ 72 low-voltageprotection ........................................ 74 software-selectableoptions .................................... 75 epromprogramming............................................ 77 expandedregisterfilecontrolregisters(0d) ........................ 83 expandedregisterfilecontrolregisters(0f)......................... 86 z8standardcontrolregisterdiagrams .............................. 90 packageinformation ............................................. 94 orderinginformation ............................................. 97 customerfeedbackform......................................... 98 z86e72/73otpmicrocontroller ................................. 98 customerinformation ......................................... 98 productinformation ........................................... 98 returninformation............................................ 98 problemdescriptionorsuggestion ............................... 98
z86e72/73 otp microcontroller ps008701-0201 v list of figures figure1. z86e7xcounter/timerblockdiagram ....................... 3 figure2. z86e7xfunctionalblockdiagram .......................... 4 figure3. 40-pindippinassignments(standardmode) ................. 5 figure4. 40-pindippinassignments(eprommode) .................. 6 figure 5. 44-pin plcc pin assignments (standard mode) . . . . . . . . . . . . . . . 7 figure6. 44-pinplccpinassignments(eprommode) ................ 7 figure7. 44-pinqfppinassignments(standardmode)................. 8 figure8. 44-pinqfppinassignments(eprommode) ................. 9 figure9. testloaddiagram ..................................... 14 figure10. externali/oormemoryread/writetiming................... 18 figure11. additionaltiming ....................................... 21 figure12. inputhandshaketiming ................................. 23 figure13. outputhandshaketiming ................................ 23 figure14. port0configuration..................................... 27 figure15. port1configuration..................................... 29 figure16. port2configuration..................................... 30 figure17. port3configuration..................................... 31 figure18. port3configuration..................................... 33 figure19. port3configuration..................................... 34 figure20. programmemorymap ................................... 37 figure21. externalmemorymap ................................... 39 figure22. expandedregisterfilearchitecture ........................ 41 figure23. registerpointer ........................................ 42 figure24. registerpointer ........................................ 43 figure25. glitchfiltercircuitry .................................... 53 figure26. eight-bitcounter/timercircuits............................ 54 figure27. transmitmodeflowchart ................................ 55 figure28. t8_outinsingle-passmode ............................. 56 figure29. t8_outinmodulo-nmode .............................. 56 figure 30. demodulation mode count capture flowchart . . . . . . . . . . . . . . . . 57 figure31. demodulationmodeflowchart............................. 58 figure32. sixteen-bitcounter/timercircuits ......................... 59 figure33. t16_outinsingle-passmode ............................ 60 figure34. t16_outinmodulo-nmode ............................. 60
z86e72/73 otp microcontroller ps008701-0201 vi figure35. ping-pongmode ....................................... 61 figure36. outputcircuit.......................................... 62 figure37. interruptblockdiagram .................................. 63 figure38. oscillatorconfiguration .................................. 65 figure39. portconfigurationregister(pcon)?writeonly .............. 66 figure40. stop-moderecoveryregister ............................ 68 figure41. sclkcircuit........................................... 69 figure 42. stop-mode recovery register 2?(0f) dh: d2?d4, d6 writeonly............................................. 71 figure43. watch-dogtimermoderegister?writeonly ................ 72 figure44. resetsandwdt ....................................... 74 figure 45. typical z86e7x low voltage versus temperature at 8 mhz . . . . . 76 figure46. epromread.......................................... 79 figure47. epromprogramandverify .............................. 80 figure 48. programming eprom, ram protect, and 16k size selection . . . . 81 figure49. programmingflowchart.................................. 82 figure 50. tc8 control register?(0d) 0h: read/write except wherenoted .......................................... 83 figure 51. t8 and t16 common control functions?(0d) 1h: read/write . . . 84 figure 52. t16 control register?(0d) 2h: read/write except wherenoted .......................................... 85 figure 53. stop-mode recovery register?(f) 0bh: d6?d0=write only, d7=readonly ......................................... 86 figure 54. stop-mode recovery register 2?(0f) dh: d2?d4, d6 writeonly ............................................ 87 figure55. optionbitregister...................................... 88 figure 56. watch-dog timer mode register?(f) 0fh: write only . . . . . . . . . 88 figure 57. port configuration register (pcon)?(0f) 0h: write only . . . . . . . 89 figure58. port2moderegister?f6h:writeonly ..................... 89 figure59. port3moderegister?f7h:writeonly ..................... 90 figure60. port0and1moderegister?f8h:writeonly ................ 91 figure 61. interrupt priority registers?(0) f9h: write only . . . . . . . . . . . . . . 91 figure 62. interrupt request register?(0) fah: read/write . . . . . . . . . . . . . 92 figure 63. interrupt mask register?(0) fbh: read/write . . . . . . . . . . . . . . . . 92 figure64. flagregister?(0)fch:read/write ........................ 93 figure65. registerpointer?(0)fdh:read/write...................... 93 figure66. stackpointerhigh?(0)feh:read/write.................... 93
z86e72/73 otp microcontroller ps008701-0201 vii figure67. stackpointerlow?(0)ffh:read/write .................... 93 figure68. 40-pindippackagediagram ............................. 94 figure69. 44-pinqfppackagediagram ............................ 95 figure70. 44-pinplccpackagediagram ........................... 96 figure71. orderingcodesexample ................................ 97
z86e72/73 otp microcontroller ps008701-0201 viii list of tables table1. z86e72/73features ..................................... 1 table2. powerconnections ...................................... 3 table3. pinidentification(standardmode) .......................... 9 table 4. z86e72/73 40-pin dip identification?eprom mode . . . . . . . . . . . 11 table 5. z86e72/73 44-pin qfp/plcc pin identification?eprom mode . . 12 table6. absolutemaximumratings ............................... 13 table7. capacitance........................................... 14 table8. dccharacteristics...................................... 15 table9. externali/oormemoryreadandwritetiming ............... 19 table10. additionaltiming ....................................... 21 table11. handshaketiming...................................... 23 table12. pinassignments ....................................... 32 table13. expandedregistergroupd .............................. 43 table14. hi8(d)0bhregister ..................................... 44 table15. lo8(d)0ahregister .................................... 44 table16. hi16(d)09hregister .................................... 45 table17. lo16(d)08hregister ................................... 45 table18. tc16h(d)07hregister .................................. 45 table19. tc16l(d)06hregister .................................. 45 table20. tc8h(d)05hregister ................................... 46 table21. tc8l(d)04hregister ................................... 46 table22. ctr0(d)00hregister ................................... 46 table23. ctr1(d)01hregister ................................... 48 table24. ctr2(d)02hregister ................................... 51 table25. smr2(f)0dhregister ................................... 52 table26. interrupttypes,sources,andvectors ...................... 63 table27. irqregister .......................................... 64 table28. stop-moderecoverysource ............................. 69 table29. wdttimeselect ...................................... 73 table30. software-selectableoptions .............................. 75 table31. programmingandtestmodes ............................ 77 table32. timingofprogrammingwaveform ......................... 78 table33. orderingcodes ........................................ 97
z86e72/73 otp microcontroller ps008701-0201 1 features table 1 shows some of the features of the z86e72/73 microcontrollers. ? low power consumption?60 mw (typical) two standby modes (typical) ? stop?2 a ? halt?0.8 ma special architecture to automate both generation and reception of complex pulses or signals: ? one programmable 8-bit counter/timer with two capture registers ? one programmable 16-bit counter/timer with one capture register ? programmable input glitch filter for pulse reception five priority interrupts ? three external ? two assigned to counter/timers two independent comparators with programmable interrupt polarity on-chip oscillator that accepts a crystal, ceramic resonator, lc, rc (mask option), or external clock drive software-selectable 200 50% k ? resistive transistor pull-ups on port 0 and port 2 ? port 2 pull-ups are bit selectable ? pull-ups automatically disabled as outputs software mouse/trackball interface on p00 through p03 table 1. z86e72/73 features part rom (kb) ram* (bytes) i/o voltage range z86e73 32 236 31 3.0 v to 5.5 v z86e72 16 748 31 3.0 v to 5.5 v note: *general-purpose
z86e72/73 otp microcontroller ps008701-0201 2 general description the z86e7x family are otp-based members of the z8 ? mcu single-chip family with 236 or 748 bytes of general-purpose ram. the only differentiating factor between the e72/73 versions is the availability of ram and rom. this eprom microcontroller family of otp controllers also offers the use of external memory, which enables this z8 microcontroller to be used where code flexibility is required. zilog's cmos microcontrollers offer fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and easy hardware/software system expansion along with cost-effective and low power consumption. the z86e7x architecture is based on zilog's 8-bit microcontroller core with an expanded register file to allow access to register-mapped peripherals, i/o cir- cuits, and powerful counter/timer circuitry. the z8 offers a flexible i/o scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery- operated hand-held applications. z8 applications demand powerful i/o capabilities. the z86e7x family fulfills this with three package options in which the e72/73 versions provide 31 pins of dedi- cated input and output. these lines are grouped into four ports. each port consists of eight lines (port 3 has seven lines of i/o and one pref comparator input) and is configurable under software control to provide timing, status signals, parallel i/o with or without handshake, and an address/data bus for interfacing external mem- ory. there are five basic address spaces available to support a wide range of configu- rations: program memory, register file, expanded register file, extended data ram, and external memory. the register file is composed of 256 bytes of ram. it includes 4 i/o port registers, 16 control and status registers, and the rest are gen- eral-purpose registers. the extended data ram adds 512 (e72) of usable gen- eral-purpose registers. the expanded register file consists of two additional register groups (f and d). to unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the z86e7x family offers a new intelligent counter/timer architecture with 8-bit and 16- bit counter/timers (figure 1). also included are a large number of user-selectable modes and two on-board comparators to process analog signals with separate reference voltages (figure 19 on page 34). all signals with a preceding front slash, ?/?, are active low. for example, b//w (word is active low); /b/w (byte is active low, only). note:
z86e72/73 otp microcontroller ps008701-0201 3 figure 1. z86e7x counter/timer block diagram power connections follow the conventions listed in table 2. figure 2 shows the functional block diagram. table 2. power connections connection circuit device power v cc v dd ground gnd v ss hi 16 lo 16 8 8 16-bit t16 16 timer 16 1248 sclk clock divider 8 8 tc16h tc16l and/or logic timer 8/16 input glitch filter edge detect circuit 8-bit t8 8 8 tc8h tc8l timer 8 8 8 hi8 lo8
z86e72/73 otp microcontroller ps008701-0201 4 figure 2. z86e7x functional block diagram port 0 p00 p07 p20 p21 p22 p23 p24 p25 p26 p27 p31 p32 p33 port 3 port 2 register file 256 x 8-bit rom 16k x 8 z8 core register bus internal address bus internal data bus extended register file extended register bus counter/timer 8 8-bit counter/timer 16 16-bit machine timing & instruction control power xtal2 vdd vss p34 p35 p36 512 x 8-bit e72 only i/o bit programmable extended data ram two analog comparators interrupt control xtal1
z86e72/73 otp microcontroller ps008701-0201 5 pin description figure 3 shows the pin assignments for the standard mode of the 40-pin dual in- line package (dip). figure 4 on page 6 shows the pin assignments for the elec- tronically programmable read-only memory (eprom) mode of the 40-pin dip. figure 3. 40-pin dip pin assignments (standard mode) r//w p25 p26 p27 p04 p05 p06 p14 p15 p07 vdd p16 p17 xtal2 xtal1 p31 p32 p33 p34 /as /ds p24 p23 p22 p21 p20 p03 p13 p12 vss p02 p11 p10 p01 p00 pref1 p36 p37 p35 /reset 40 z86e72/73 dip 1 20 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
z86e72/73 otp microcontroller ps008701-0201 6 figure 4. 40-pin dip pin assignments (eprom mode) figure 5 on page 7 shows the pin assignments for the standard mode of the 44- pin plastic leaded chip carrier (plcc). figure 6 on page 7 shows the pin assign- ments for the eprom mode of the 44-pin plcc. nc a13 a14 /pgm a4 a5 a6 d4 d5 a7 vdd d6 d7 nc nc /oe epm vpp nc nc nc a12 a11 a10 a9 a8 a3 d3 d2 vss a2 d1 d0 a1 a0 /ce nc nc nc nc 40 z86e72/73 dip 1 20 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
z86e72/73 otp microcontroller ps008701-0201 7 figure 5. 44-pin plcc pin assignments (standard mode) figure 6. 44-pin plcc pin assignments (eprom mode) z86e72/73 plcc 7 8 9 10 11 12 13 14 15 16 17 p21 p22 p23 p24 /ds r//rl r//w p25 p26 p27 p04 pref1 p36 p37 p35 /reset vss /as p34 p33 p32 p31 1 28 18 40 6 39 38 37 36 35 34 33 32 31 30 29 20 22 24 26 4 42 p05 p06 p14 p15 p07 vdd vdd p16 p17 xtal2 xtal1 p20 p03 p13 p12 vss vss p02 p11 p10 p01 p00 z86e72/73 plcc 7 8 9 10 11 12 13 14 15 16 17 a9 a10 a11 a12 nc nc nc a13 a14 /pgm a4 /ce nc nc nc nc vss nc nc vpp epm /oe 1 28 18 40 6 39 38 37 36 35 34 33 32 31 30 29 20 22 24 26 4 42 a8 a3 d3 d2 vss vss a2 d1 d0 a1 a0 a5 a6 d4 d5 a7 vdd vdd d6 d7 xtal2 xtal1
z86e72/73 otp microcontroller ps008701-0201 8 figure 7 shows the pin assignments for the standard mode of the 44-pin quad flat pack (qfp). figure 8 on page 9 shows the pin assignments for theeprommodeofthe44-pinqfp. figure 7. 44-pin qfp pin assignments (standard mode) 34 35 36 37 38 39 40 41 42 43 44 p21 p22 p23 p24 /ds r//rl r//w p25 p26 p27 p04 pref1 p36 p37 p35 /reset vss /as p34 p33 p32 p31 1 23 33 z86e72/73 qfp 11 22 21 20 19 18 17 16 15 14 13 12 25 27 29 31 9 7 5 3 p20 p03 p13 p12 vss vss p02 p11 p10 p01 p00 p05 p06 p14 p15 p07 vdd vdd p16 p17 xtal2 xtal1
z86e72/73 otp microcontroller ps008701-0201 9 figure 8. 44-pin qfp pin assignments (eprom mode) table 3 identifies the pins in packages in standard mode. table 4 on page 11 iden- tifies the pins in the 40-pin dip in eprom mode. table 5 on page 12 identifies the pins in the 44-pin qfp and plcc. table 3. pin identification (standard mode) 40-pin dip # 44-pin plcc # 44-pin qfp # symbol direction description 26 40 23 p00 input/output port 0 is nibble programmable. 27 41 24 p01 input/output port 0 can be configured as a15 ? a8 external program 30 44 27 p02 input/output 34 5 32 p03 input/output rom address bus. 5 17 44 p04 input/output port 0 can be configured as a 6 18 1 p05 input/output mouse/trackball input. 7 19 2 p06 input/output 10 22 5 p07 input/output 28 42 25 p10 input/output port 1 is byte programmable. 34 35 36 37 38 39 40 41 42 43 44 a9 a10 a11 a12 n/c n/c n/c a13 a14 /pgm a4 /ce n/c n/c n/c n/c vss n/c n/c vpp epm /oe 1 23 33 z86e72/73 qfp 11 22 21 20 19 18 17 16 15 14 13 12 3 579 31 29 27 25 a8 a3 d3 d2 vss vss a2 d1 d0 a1 a0 a5 a6 d4 d5 a7 vdd vdd d6 d7 xtal2 xtal1
z86e72/73 otp microcontroller ps008701-0201 10 29 43 26 p11 input/output port 1 can be configured as multiplexed a7 ? a0/d7 ? d0 external program rom address/data bus 32 3 30 p12 input/output 33 4 31 p13 input/output 8 20 3 p14 input/output . 9 21 4 p15 input/output 12 25 8 p16 input/output 13 26 9 p17 input/output 35 6 33 p20 input/output port 2 pins are individually configurable as input or output 36 7 34 p21 input/output 37 8 35 p22 input/output 38 9 36 p23 input/output 39 10 37 p24 input/output 2 14 41 p25 input/output 3 15 42 p26 input/output 4 16 43 p27 input/output 16 29 12 p31 input irq2/modulator input 17 30 13 p32 input irq0 18 31 14 p33 input irq1 19 32 15 p34 output t8 output 22 36 19 p35 output t16 output 24 38 21 p36 output t8/t16 output 23 37 20 p37 output 20 33 16 /as output address strobe 40 11 38 /ds output data strobe 1 13 40 r//w output read/write 21 35 18 /reset i nput reset 15 28 11 xtal1 input crystal, oscillator clock table 3. pin identification (standard mode) (continued) 40-pin dip # 44-pin plcc # 44-pin qfp # symbol direction description
z86e72/73 otp microcontroller ps008701-0201 11 14 27 10 xtal2 output crystal, oscillator clock 11 23, 24 6, 7 v dd power supply 31 1, 2, 34 17, 28, 29 v ss ground 25 39 22 pref1 input comparator 1 reference nc 12 39 r//rl input rom//romless table 4. z86e72/73 40-pin dip identification ? eprom mode 40-pin # symbol function direction 1 n/c not connected 2 ? 3a13 ? 14 address 13, 14 input 4 /pgm program mode input 5 ? 7a4 ? a6 address 4, 5, 6 input 8 ? 9d4 ? d5 data 4, 5 input/output 10 a7 address 7 input 11 v dd power supply 12 ? 13 d6 ? d7 data 6, 7 input/output 14 ? 15 n/c not connected 16 /oe output enable input 17 epm eprom prog. mode input 18 v pp prog. voltage input 19 ? 24 n/c not connected 25 /ce chip enable input 26 ? 27 a0 ? a1 address 0, 1 input 28 ? 29 d0 ? d1 data 0, 1 input/output 30 a2 address 2 input 31 v ss ground 32 ? 33 d2 ? d3 data 2, 3 input/output table 3. pin identification (standard mode) (continued) 40-pin dip # 44-pin plcc # 44-pin qfp # symbol direction description
z86e72/73 otp microcontroller ps008701-0201 12 34 a3 address 3 input 35 ? 39 a8 ? a12 address 8, 9, 10, 11, 12 input 40 n/c not connected table 5. z86e72/73 44-pin qfp/plcc pin identification ? eprom mode 44-pin qfp 44-pin plcc symbol function direction 1 ? 218 ? 19 a5 ? a6 address 5, 6 input 3 ? 420 ? 21 d4 ? d5 data 4, 5 input/output 5 22 a7 address 7 input 6 ? 723 ? 24 v dd power supply 8 ? 925 ? 26 d6 ? d7 data 6, 7 input/output 10 27 xtal2 crystal oscillator clock 11 28 xtal1 crystal oscillator clock 12 29 /oe output enable input 13 30 epm eprom prog. mode input 14 31 v pp prog. voltage input 15 ? 16 32 ? 33 n/c not connected 17 34 v ss ground 18 ? 21 35 ? 38 n/c not connected 22 39 /ce chip select input 23 ? 24 40 ? 41 a0 ? a1 address 0, 1 input 25 ? 26 42 ? 43 d0 ? d1 data 0, 1 input/output 27 44 a2 address 2 input 28 ? 29 1 ? 2v ss ground 30 ? 31 3 ? 4d2 ? d3 data 2, 3 input/output 32 5 a3 address 3 input 33 ? 37 6 ? 10 a8 ? a12 address 8, 9, 10, 11, 12 input 38 ? 40 11 ? 13 n/c not connected table 4. z86e72/73 40-pin dip identification ? eprom mode (continued) 40-pin # symbol function direction
z86e72/73 otp microcontroller ps008701-0201 13 absolute maximum ratings table 6 lists the absolute maximum ratings for the z86e72/73 microcontrollers. stresses greater than those listed under absolute maximum ratings might cause permanent damage to the device. this rating is a stress rating only. operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating condi- tions for an extended period might affect device reliability. 41 ? 42 14 ? 15 a13 ? a14 address 13, 14 input 43 16 /pgm prog. mode input 44 17 a4 address 4 input table 6. absolute maximum ratings symbol description min max units v max supply voltage (*) ? 0.3 +7.0 v t stg storage temperature ? 65 +150 c t a oper. ambient temperature ? c notes: * voltage on all pins with respect to gnd. ? see ? ordering information ? on page 97. table 5. z86e72/73 44-pin qfp/plcc pin identification ? eprom mode 44-pin qfp 44-pin plcc symbol function direction
z86e72/73 otp microcontroller ps008701-0201 14 standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (see figure 9). figure 9. test load diagram capacitance table 7 lists the capacitances for the z86e72/73 microcontrollers. table 7. capacitance parameter max input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf note: t a =25 c, v cc = gnd = 0 v, f = 1.0 mhz, unmeasured pins returned to gnd. from output under test i
z86e72/73 otp microcontroller ps008701-0201 15 dc characteristics table 8 lists the direct current (dc) characteristics. table 8. dc characteristics t a =0 cto+70 ctypical sym. parameter v cc min max @ 25 c units conditions max input voltage 3.0 v 5.5 v 7 7 v v i in 250 a i in 250 a v ch clock input high voltage 3.0 v 5.5 v 0.9 v cc 0.9 v cc v cc +0.3 v cc +0.3 v v driven by external clock generator v cl clock input low voltage 3.0 v 5.5 v v ss ? 0.3 v ss ? 0.3 0.2 v cc 0.2 v cc v v driven by external clock generator v ih input high voltage 3.0 v 5.5 v 0.7 v cc 0.7 v cc v cc +0.3 v cc +0.3 0.5 v cc 0.5 v cc v v v il input low voltage 3.0 v 5.5 v v ss ? 0.3 v ss ? 0.3 0.2 v cc 0.2 v cc 0.5 v cc 0.5 v cc v v v oh1 output high voltage 3.0 v 5.5 v v cc ? 0.4 v cc ? 0.4 2.9 5.4 v v i oh = ? 0.5 ma i oh = ? 0.5 ma v oh2 output high voltage (p00, p01, p36, p37) 3.0 v 5.5 v v cc 0.7 v cc 0.7 v v i oh = ? 7ma i oh = ? 7ma v ol1 output low voltage 3.0 v 5.5v 0.4 0.4 0.1 0.2 v v i ol =1.0ma i ol =4.0ma v ol2* output low voltage 3.0 v 5.5 v 0.8 0.8 0.5 0.3 v v i ol =5.0ma i ol =7.0ma v ol2 output low voltage (p00, p01, p36, p37) 3.0 v 5.5 v 0.8 0.8 0.3 0.2 v v i ol =10ma i ol =10ma v rh reset input high voltage 3.0 v 5.5 v 0.8 v cc 0.8 v cc v cc v cc 1.5 2.5 v v v rl reset input low voltage 3.0 v 5.5 v v ss ? 0.3 v ss ? 0.3 0.2 v cc 0.2 v cc 0.9 1.8 v offset comparator input offset voltage 3.0 v 5.5 v 25 25 10 10 mv mv i il input leakage 3.0 v 5.5 v ? 1 ? 1 1 1 <1 <1 a a v in =0v,v cc v in =0v,v cc i ol output leakage 3.0 v 5.5 v ? 1 ? 1 1 1 <1 <1 a a v in =0v,v cc v in =0v,v cc
z86e72/73 otp microcontroller ps008701-0201 16 i ir reset input current 3.0 v 5.5 v ? 230 ? 400 ? 50 ? 80 a a i cc supply current (wdt off) 3.0 v 5.5 v 10 15 4 10 ma ma @8.0mhz @8.0mhz i cc1 standby current (wdt off) 3.0 v 5.5 v 3 5 1 4 ma ma halt mode v in =0v, v cc at 8.0 mhz, notes 1, 2 halt mode v in =0v,v cc @8.0mhz, notes 1, 2 3.0 v 5.5 v 2 4 0.8 2.5 ma ma clock divide-by-16 @8.0mhz notes 1, 2 clock divide-by-16 @8.0mhz notes 1, 2 i cc2 standby current 3.0 v 5.5 v 8 10 2 3 a a stop mode v in =0v,v cc wdt is not running notes 3, 5 stop mode v in =0v,v cc wdt is not running notes 3, 5 3.0 v 5.5 v 500 800 310 600 a a stop mode notes 3, 5 v in =0v,v cc wdt is running v icr input common mode voltage range 3.0 v 5.5 v 0 0 v cc ? 1.0 v v cc ? 1.0 v v v note 8 t por power-on reset 3.0 v 5.5 v 12 5 75 20 18 7 ms ms table 8. dc characteristics (continued) t a =0 cto+70 ctypical sym. parameter v cc min max @ 25 c units conditions
z86e72/73 otp microcontroller ps008701-0201 17 v ram static ram data retention voltage vram 0.5 v worst case 0.8 v guaranteed by design only note 6 notes: icc1 crystal/resonator external clock drive typ 3.0 ma 0.3 ma max 5 5 unit ma ma frequency 8.0 mhz 8.0 mhz 1. all outputs unloaded, inputs at rail 2. cl1 = cl2 = 100 pf 3. same as note [4] except inputs at v cc 4. the v lv increases as the temperature decreases. 5. oscillator stopped 6. oscillator stops when v cc falls below v lv limit. 7. 32 khz clock driver input 8. for analog comparator, inputs when analog comparators are enabled * all outputs excluding p00, p01, p36, and p37 table 8. dc characteristics (continued) t a =0 cto+70 ctypical sym. parameter v cc min max @ 25 c units conditions
z86e72/73 otp microcontroller ps008701-0201 18 ac characteristics figure 10 shows the external input/output (i/o) or memory read and write timing. table 9 describes the i/o or memory read and write timing. figure 10. external i/o or memory read/write timing r//w 9 12 18 3 16 13 4 5 8 11 6 17 10 15 7 14 2 1 port 0, /dm port 1 /as /ds (read) port 1 /ds (write) a7 - a0 d7 - d0 in d7 - d0 out a7 - a0 19 20
z86e72/73 otp microcontroller ps008701-0201 19 table 9. external i/o or memory read and write timing t a =0 cto+70 c 16 mhz no. symbol parameter v cc min. max. units notes 1 tda(as) address valid to /as rising delay 3.0 v 5.5 v 55 55 ns ns 2 2 tdas(a) /as rising to address float delay 3.0 v 5.5 v 70 70 ns ns 2 3 tdas(dr) /as rising to read data required valid 3.0 v 5.5 v 400 400 ns ns 1, 2 1, 2 4 twas /as low width 3.0 v 5.5 v 80 80 ns ns 2 2 5td addressfloatto /ds falling 3.0 v 5.5 v 0 0 ns ns 6 twdsr /ds (read) low width 3.0 v 5.5 v 300 300 ns ns 1, 2 7 twdsw /ds (write) low width 3.0 v 5.5 v 165 165 ns ns 1, 2 8 tddsr(dr) /ds falling to read data required valid 3.0 v 5.5 v 260 260 ns ns 1, 2 9 thdr(ds) read data to /ds rising hold time 3.0 v 5.5 v 0 0 ns ns 10 tdds(a) /ds rising to address active delay 3.0 v 5.5 v 85 95 ns ns 2 11 tdds(as) /ds rising to /as falling delay 3.0 v 5.5 v 60 70 ns ns 2 12 tdr/w(as) r//w valid to /as rising delay 3.0 v 5.5 v 70 70 ns ns 2 13 tdds(r/w) /ds rising to r//w not valid 3.0 v 5.5 v 70 70 ns ns 2 14 tddw(dsw) write data valid to /ds falling (write) delay 3.0 v 5.5 v 80 80 ns ns 2 15 tdds(dw) /ds rising to write data not valid delay 3.0 v 5.5 v 70 80 ns ns 2 16 tda(dr) address valid to read data required valid 3.0 v 5.5 v 475 475 ns ns 1, 2
z86e72/73 otp microcontroller ps008701-0201 20 figure 11 shows additional timing. table 10 describes the additional timing. 17 tdas(ds) /as rising to /ds falling delay 3.0 v 5.5 v 100 100 ns ns 2 2 18 tddm(as) /dm valid to /as falling delay 3.0 v 5.5 v 55 55 ns ns 2 19 tdds(dm) /ds rise to /dm valid delay 3.0 v 5.5 v 70 70 ns ns 20 thds(a) /ds rise to address valid hold time 3.0 v 5.5 v 70 70 ns ns notes: 1. when using extended memory timing, add 2 tpc. 2. timing numbers given are for minimum tpc. standard test load all timing references use 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. table 9. external i/o or memory read and write timing (continued) t a =0 cto+70 c 16 mhz no. symbol parameter v cc min. max. units notes
z86e72/73 otp microcontroller ps008701-0201 21 figure 11. additional timing table 10. additional timing t a =0 cto+70 c no symbol parameter v cc min max units notes 1 tpc input clock period 3.0 v 5.5 v 121 121 dc dc ns ns 1 1 2 trc,tfc clock input rise and fall times 3.0 v 5.5 v 25 25 ns ns 1 1 3 twc input clock width 3.0 v 5.5 v 37 37 ns ns 1 4 twtinl timer input low width 3.0 v 5.5 v 100 70 ns ns 1 5 twtinh timer input high width 3.0 v 5.5 v 3tpc 3tpc 1 clock t in irq n clock setup stop mode recovery source 2 2 3 3 1 7 7 4 5 6 9 8 11 10
z86e72/73 otp microcontroller ps008701-0201 22 figure 12 shows the input handshake timing, and figure 13 shows the output handshake timing. table 11 describes the handshake timing. 6 tpti timer input period 3.0 v 5.5 v 8tpc 8tpc 1 7 trtin,tfti timer input rise and fall timers 3.0 v 5.5 v 100 70 ns ns 1 1 8a twil interrupt request low time 3.0 v 5.5 v 100 70 ns ns 1, 2 1, 2 8b twil int. request low time 4.5 v 5.5 v 3tpc 5tpc 1, 3 1, 3 9 twih interrupt request input high time 4.5 v 5.5 v 5tpc 5tpc 1, 2 1, 2 10 twsm stop-mode recovery width spec 3.0 v 5.5 v 3.0 v 5.5 v 12 12 5tpc 5tpc ns ns 7 7 6 6 11 tost oscillator start-up time 3.0 v 5.5 v 5tpc 5tpc 4 12 twdt watch-dog timer delay time (5 ms) 3.0 v 5.5 v 12 5 75 20 ms ms (10ms) 3.0v 5.5 v 25 10 150 40 ms ms (20ms) 3.0v 5.5 v 50 20 300 80 ms ms (80ms) 3.0v 5.5 v 225 80 1200 320 ms ms notes: 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33 ? p31). 3. interrupt request through port 3 (p30). 4. smr ? d5 = 0 5. reg. wdtmr 6. reg. smr ? d5 = 0 7. reg. smr ? d5 = 1 table 10. additional timing (continued) t a =0 cto+70 c no symbol parameter v cc min max units notes
z86e72/73 otp microcontroller ps008701-0201 23 figure 12. input handshake timing figure 13. output handshake timing table 11. handshake timing t a =0 cto+70 c 16 mhz data no symbol parameter v cc min max direction 1 tsdi(dav) data in setup time 4.0 v 5.5 v 0in in 2 thdi(dav) data in hold time 4.0 v 5.5 v 0 0 in in 3 twdav data available width 4.0 v 5.5 v 155 110 in in data in 1 2 3 4 5 6 da v (input) rdy (output) next data in valid delayed rdy delayed dav data in valid data out dav (output) rdy (input) next data out valid delayed rdy delayed dav data out valid 7 8 9 10 11
z86e72/73 otp microcontroller ps008701-0201 24 4 tddavi(rdy) dav falling to rdy falling delay 4.0 v 5.5 v 160 115 in in 5 tddavid(rdy) dav rising to rdy falling delay 4.0 v 5.5 v 120 80 in in 6 tdrdyo(dav) rdy rising to dav falling delay 4.0 v 5.5 v 0 0 in in 7 tddo(dav) data out to dav falling delay 4.0 v 5.5 v 63 63 out out 8 tddav0(rdy) dav falling to rdy falling delay 4.0 v 5.5 v 0 0 out out 9 tdrdy0(dav) rdy falling to dav rising delay 4.0 v 5.5 v 160 115 out out 10 twrdy rdy width 4.0 v 5.5 v 110 80 out out 11 tdrdy0d(dav) rdy rising to dav falling delay 4.0 v 5.5 v 110 80 out table 11. handshake timing (continued) t a =0 cto+70 c 16 mhz data no symbol parameter v cc min max direction
z86e72/73 otp microcontroller ps008701-0201 25 pin functions /ds (output, active low) data strobe is activated once for each external memory transfer. for a read operation, data must be available before the trailing edge of /ds. for write operations, the falling edge of /ds indicates that output data is valid. /as (output, active low) address strobe is pulsed once at the beginning of each machine cycle. address output is through port 0/port 1 for all external programs. memory address trans- fers are valid at the trailing edge of /as. under program control, /as is placed in the high-impedance state along with ports 0 and 1, data strobe, and read/write. xtal1 crystal 1 (time-based input) this pin connects a parallel-resonant crystal, ceramic resonator, lc, or rc net- work or an external single-phase clock to the on-chip oscillator input. xtal2 crystal 2 (time-based output) this pin connects a parallel-resonant, crystal, ceramic resonant, lc, or rc net- work to the on-chip oscillator output. r//w read/write (output, write low) the r//w signal is low when the ccp is writing to the external program or data memory. r//rl (input) this pin, when connected to gnd, disables the internal rom and forces the device to function as a romless z8. when left unconnected or pulled high to v cc , the part functions normally as a z8 rom version. port 0 (p07 ? p00) port 0 is an 8-bit, bidirectional, cmos-compatible port. these eight i/o lines are configured under software control as a nibble i/o port or as an address port for interfacing external memory. the output drivers are push-pull. port 0 is placed under handshake control. in this configuration, port 3, lines p32 and p35 are used as the handshake control /dav0 and rdy0. handshake signal direction is note:
z86e72/73 otp microcontroller ps008701-0201 26 dictated by the i/o direction to port 0 of the upper nibble p07 ? p04. the lower nib- ble must have the same direction as the upper nibble. for external memory references, port 0 can provide address bits a11 ? a8 (lower nibble)ora15 ? a8 (lower and upper nibble) depending on the required address space. if the address range requires 12 bits or less, the upper nibble of port 0 can be programmed independently as i/o while the lower nibble is used for address- ing. if one or both nibbles are needed for i/o operation, they must be configured bywritingtotheport0moderegister.afterahardwarereset,port0isconfigured as an input port. port 0 is set in the high-impedance mode if selected as an address output state along with port 1 and the control signals /as, /ds, and r//w. a software option is available to program 0.4 v dd cmos trip inputs on p00 ? p03. this allows direct interface to mouse/trackball ir sensors. an optional 200 50% k ? resistive transistor pull-up is available as a software option of all port 0 bits with nibble select. these pull-ups are disabled when configured (bit by bit) as an output. see figure 14.
z86e72/73 otp microcontroller ps008701-0201 27 figure 14. port 0 configuration port 0 (i/o or a15 ? a8) z86e7x mcu oen program option v cc 200 k ? + 50% pad out in in 0.4 vdd trip point buffer * note: on p00 and p07 only 4 4 resistive transistor pull-ups optional handshake controls /dav0 and rdy0 (p32 and p35) ** poim, di, do mask selectable
z86e72/73 otp microcontroller ps008701-0201 28 port 1 (p17 ? p10) port 1 is a multiplexed address (a7 ? a0) and data (d7 ? d0), cmos-compatible port. port 1 is dedicated to the zilog zbus ? -compatible memory interface. the operations of port 1 are supported by the address strobe (/as) and data strobe (/ds) lines and by the read/write (r//w) and data memory (/dm) control lines. data memory read/write operations are done through this port. if more than 256 external locations are required, port 0 outputs the additional lines. port 1 can be placed in the high-impedance state along with port 0, /as, /ds, and r//w, allowing the z86e7x to share common resources in multiprocessor and dma applications. port 1 can also be configured for standard port output mode. seefigure15.
z86e72/73 otp microcontroller ps008701-0201 29 figure 15. port 1 configuration port 1 (i/o or ad7 - ad0) optional handshake controls /dav1 and rdy1 (p33 and p34) z86e7x mcu 8 oen out in pa d auto latch r 500 k
z86e72/73 otp microcontroller ps008701-0201 30 port 2 (p27 ? p20) port 2 is an 8-bit, bidirectional, cmos-compatible i/o port (see figure 16). these eight i/o lines can be independently configured under software control as inputs or outputs. port 2 is always available for i/o operation. a software option is avail- able to connect eight 200 k ? (50%) pull-up resistors on this port. bits pro- grammed as outputs are globally programmed as either push-pull or open-drain. port 2 can be placed under handshake control. in this configuration, port 3 lines, p31 and p36 are used as the handshake controls lines /dav2 and rdy2. the handshake signal assignment for port 3, lines p31 and p36 is dictated by the direction (input or output) assigned to bit 7, port 2. figure 16. port 2 configuration port 2 (i/o) z86e7x mcu open-drain oen program option v cc pad out in 200 k ? + 50% resistive transistor pull-ups optional handshake controls /dav2 and rdy2 (p31 and p36) (e72 only)
z86e72/73 otp microcontroller ps008701-0201 31 the ccp wakes up with the 8 bits of port 2 configured as inputs with open-drain outputs. port2alsohasan8-bitinputorandanandgatethatcanbeusedtowakeup the part. p20 can be programmed to access the edge-selection circuitry. port 3 (p37 ? p31) port 3 is a 7-bit, cmos-compatible port (see figure 17). port 3 consists of three fixed inputs (p33 ? p31) and four fixed outputs (p37 ? p34) and can be configured under software control for input/output, interrupt, port handshake, data memory functions, and output from the counter/timers. p31, p32, and p33 are standard cmos inputs; outputs are push-pull. figure 17. port 3 configuration two on-board comparators process analog signals on p31 and p32 with refer- ence to the voltage on pref1 and p33. the analog function is enabled by program- ming the port 3 mode register (bit 1). p31 and p32 are programmable as rising, falling, or both edge-triggered interrupts (irq register bits 6 and 7). pref1 and p33 p34 out p37 out p32 + - p33 (pref2) 0 = p34, p37 standard output 1 = p34, p37 comparator output pcon d0 p31 + - pref1 p37 pad p34 pad * t8 p34 out 0 normal control 1 8-bit timer output active ctr0 d0 counter/timer reset condition. * comp2 comp1
z86e72/73 otp microcontroller ps008701-0201 32 are the comparator reference voltage inputs. access to the counter timer edge- detection circuit is through p31 or p20 (see ? ctr1(d)01h register ? on page 48). port 3 provides the following control functions: handshake for ports 0, 1, and 2 (/dav and rdy); three external interrupt request signals (irq2 ? irq0); data memory select (/dm). see table 12. port 3 also provides output for each of the counter/timers and the and/or logic. control is performed by programming bits d5 ? d4 of ctri, bit 0 of ctr0, and bit 0 of ctr2. comparator inputs in analog mode, port 3 (p31 and p32) has a comparator front end. the compara- tor reference is supplied to p33 and pref1. in this mode, the p33 internal data latch and its corresponding irq1 are diverted to the smr sources (excluding p31, p32, and p33) as shown in figure 18. in digital mode, p33 is used as d3 of the port 3 input register which then generates irq1 as shown in figure 23. comparators are disabled/powered down by entering stop mode. for p31 ? p33tobeusedasastop-moderecovery source, these inputs must be placed into digital mode. table 12. pin assignments pin i/o c/t comp. int. p0 hs p1 hs p2 hs ext pref1 in rf1 p31 in in an1 irq2 d/r p32 in an2 irq0 d/r p33 in rf2 irq1 d/r p34 out t8 a01 r/d d/m p35 out t16 r/d p36 out t8/16 r/d p37 out a02 p20 i/o in notes: hs = handshake signals d=/dav r = rdy note:
z86e72/73 otp microcontroller ps008701-0201 33 figure 18. port 3 configuration comparator outputs theseoutputscanbeprogrammedtobeoutputonp34andp37throughthe pcon register (figure 19). port 3 z86e7x mcu r247 = p3m p31 p32 p33 p34 p35 p36 p37 + ? + ? 1 = analog 0=digital p31 (an1) comp1 dig. an. pref1 d1 p32 (an2) comp1 p33 (ref2) from stop-mode recovery source irq2, p31 data latch irq0, p32 data latch irq1, p33 data latch pref1 (i/o or handshake)
z86e72/73 otp microcontroller ps008701-0201 34 figure 19. port 3 configuration vdd pad p34 mux ctr0, d0 out 34 t8_out vdd pad p35 mux out 35 t16_out ctr2, d0 vdd pad p36 mux out 36 t8/16_out ctr1, d6
z86e72/73 otp microcontroller ps008701-0201 35 /reset (input, active low) reset initializes the mcu. reset is accomplished either through power-on, watch-dog timer, stop-mode recovery, low-voltage detection, or external reset. during power-on reset and watch-dog timer reset, the internally generated reset drives the reset pin low for the por time. any devices driving the reset line need to be open-drain to avoid damage from a possible conflict during reset con- ditions. pull-up is provided internally. there is no condition internal to the z86e7x that does not allow an external reset to occur. after the por time, /reset is a schmitt-triggered input. to avoid asynchronous and noisy reset problems, the z86e7x is equipped with a reset filter of four exter- nal clocks (4tpc). if the external reset signal is less than 4tpc in duration, no reset occurs. on the fifth clock after the reset is detected, an internal rst signal is latched and held for an internal register count of 18 external clocks or for the dura- tion of the external reset, whichever is longer. during the reset cycle, /ds is held active low while /as cycles at a rate of tpc/2. program execution begins at location 000ch, 5 ? 10 tpc cycles after the rst is released. for power-on reset, the typical reset output time is 5 ms. the z86e7x devices do not have internal pull resistors on port 3 inputs. note:
z86e72/73 otp microcontroller ps008701-0201 36 functional description the z86e72/73 microcontrollers incorporate special functions to enhance the z8's functionality in consumer and battery-operated applications. reset the device is reset in one of the following conditions: power-on reset watch-dog timer stop-mode recovery source low voltage detection external reset program memory the z86e72/73 microcontrollers address up to 16k/32 kb of internal program memory, with the remainder being external memory (figure 20). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain five 16-bit vectors that correspond to the five available interrupts. addresses of 16k/32k consist of on-chip otp. at addresses 16k or 32k and greater, the z86e72/73 microcontrollers execute external program memory fetches (see ? external memory ? on page 38).
z86e72/73 otp microcontroller ps008701-0201 37 figure 20. program memory map ram thez86e72hasa768-byteram;256bytesmakeuptheregisterfile.the remaining 512 bytes make up the extended data ram. the z86e73 has just the 256 bytes of the register file. extended data ram the extended data ram of the z86e72 occupies the address range fe00h ? ffffh (512 bytes). this range of addresses fd00h ? ffffh cannot be used to directly read from or write to external memory. accessing the extended data ram is accomplished by using lde or ldei instructions. port 1 and port 0 are free to be set as i/o or addr/data modes; expect high-impedance when accessing extended data ram. in addition, if the external memory uses the same address range of the extended data ram, it can be used as the external stack only. exercise caution when using extended data ram (not z8 ram) on the z86e72 otp microcontroller. extended ram spaces ff0c ? ff0f, ff10, fe0c ? fe0f, and fe10 are reserved. do not use these extended ram locations. location of first byte of instruction executed after reset 16384 12 11 10 9 8 7 6 5 4 3 2 1 0 external rom on-chip rom reset start address reserved reserved irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 interrupt vector (lower byte) interrupt vector (upper byte) 65535
z86e72/73 otp microcontroller ps008701-0201 38 the extended data ram cannot be used as stack or instruction/code memory. accessing the extended data ram has the following condition: p01m register bits d4 ? d3 cannot be set to 11. external memory the z86e72/73 microcontrollers address up to 32 kb (minus fd00h ? ffffh) of external memory beginning at address 8000h (32k+1). external data memory is included with, or separated from, the external program memory space. /dm, an optional i/o function that is programmed to appear on p34, is used to distinguish between data and program memory space. the state of the /dm signal is con- trolled by the type of instruction being executed. an ldc op code references program (/dm inactive) memory, and an lde instruction references data (/dm active low) memory. see figure 21. note:
z86e72/73 otp microcontroller ps008701-0201 39 figure 21. external memory map expanded register file the register file has been expanded to allow for additional system control regis- ters and for mapping of additional peripheral devices into the register address area. the z8 register address space r0 through r15 has been implemented as 16 banks of 16 registers per bank. these register groups are known as the expanded register file (erf). bits 7 ? 4 of register rp select the working register group. bits 3 ? 0ofregisterrp select the expanded register file bank. the expanded register bank is also referred to as the expanded register group (see figure 22). 65535 0 external data memory not addressable 32,768 note:
z86e72/73 otp microcontroller ps008701-0201 40 the upper nibble of the register pointer (figure 23 on page 42) selects which working register group of 16 bytes in the register file, out of the possible 256, is accessed. the lower nibble selects the expanded register file bank and, in the case of the z86e7x family, banks 0, f, and d are implemented. a 0h in the lower nibble allows the normal register file (bank 0) to be addressed, but any other value from 1h to fh exchanges the lower 16 registers to an expanded register bank. for example, z86e73 (see figure 22): r253 rp = 00h r0 = port0 r1 = port1 r2 = port2 r3 = port3 but if: r253 rp = 0dh r0 = ctrl0 r1 = ctrl1 r2 = ctrl2 r3 = reserved the counter/timers are mapped into erf group d. access is easily done using the following example: ld rp,#0dh ; select erf d for access and register ; bank 0 as the working register group. ld r0,#xx ; access ctrl0 ld 1,#xx ; access ctrl1 ld rp,#7dh ; select expanded register group (erf) ; group d for access and register ; bank 7 as the working register bank. ld r1,2 ; ctrl2 register 71h
z86e72/73 otp microcontroller ps008701-0201 41 figure 22. expanded register file architecture uuuuuuuu register pointer 76543210 reset condition d7 d6 d5 d4 d3 d2 d1 d0 register** expanded reg. bank/group (d) register** reset condition reset condition expanded reg. bank/group (f) register** working register group pointer z8 register file (bank 0)** expanded register bank group pointer reserved reserved expanded reg. group (0) register** reset condition u = unknown * not reset with a stop-mode recovery ** all addresses are in hexadecimal. ? not reset with a stop-mode recovery, except bit 0. ff f0 7f 0f 00 * * * * ff fe fd fc fb fa f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 (f) 0f (f) 0e (f) 0d (f) 0c (f) 0b (f) 0a (f) 09 (f) 08 (f) 07 (f) 06 (f) 05 (f) 04 (f) 03 (f) 02 (f) 01 (f) 00 (d) 0c (d) 0b (d) 0a (d) 09 (d) 08 (d) 07 (d) 06 (d) 05 (d) 04 (d) 03 (d) 02 (d) 01 (d) 00 reserved hi8 lo8 hi16 lo16 tc16h tc16l tc8h tc8l reserved ctr2 ctr1 ctr0 u u u u u u u u 0 0 0 u u u u u u u u u 0 0 u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u 0 wdtmr reserved smr2 reserved smr reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pcon u u 0 u 0 0 u u 1 0 0 0 1 0 0 1 0 0 0 u u 1 u 0 spl sph rp flags imr irq ipr p01m p3m p2m reserved reserved reserved reserved reserved reserved u u 0 u 0 0 u 0 0 1 u u u u 0 0 u u 0 u u 0 u 1 0 1 u u u u 0 u u u 0 u u 0 u 0 0 1 u u u u 0 u u u 0 u u 0 u 0 0 1 u u u u 0 0 u u 0 u u 0 u 1 0 1 u u u u 0 0 u u 0 u u 0 u 1 0 1 u u u u 0 0 u u 0 u u 0 u 0 0 1 u u u u 0 0 u u 0 u u 0 u 1 0 1 u u u u 0 0 ? * * (0) 03 (0) 02 (0) 01 p3 p2 p1 0 u 0 u 0 u 0 u u u u u u u u u z8 standard control registers 00000000 (0) 00 p0 uuuuuuuu uuuuuuu0
z86e72/73 otp microcontroller ps008701-0201 42 figure 23. register pointer register file the register file (bank 0) consists of 4 i/o port registers, 236 general-purpose reg- isters, and 16 control and status registers (r0 ? r3, r4 ? r239, and r240 ? r255, respectively), plus two expanded registers groups (banks d and f). instructions can access registers directly or indirectly through an 8-bit address field. this allows a short, 4-bit register address using the register pointer (figure 24). in the 4-bit mode, the register file is divided into 16 working register groups, each occu- pying 16 continuous locations. the register pointer addresses the starting location of the active working register group. working register group e0 ? ef of bank 0 are only accessed through working registers and indirect addressing modes. r253 rp d7 d6 d5 d4 d3 d2 d1 d0 expanded register file pointer working register pointer default setting after reset = 0000 0000 note:
z86e72/73 otp microcontroller ps008701-0201 43 figure 24. register pointer stack the z86e7x external data memory or the internal register file is used for the stack. an 8-bit stack pointer (r255) is used for the internal stack that resides in the general-purpose registers (r4 ? r239). sph is used as a general-purpose reg- ister only when using internal stacks. when sph is used as a general-purpose register and port 0 is in address mode, the contents of sph are loaded into port 0 whenever the internal stack is accessed. counter/timer register description table 13 describes the expanded register group d. table 13. expanded register group d (d) 0ch reserved (d) 0bh hi8 (d) 0ah lo8 ff f0 2f 20 1f 10 0f 00 00 r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 the upper nibble of the register file address provided by the register pointer specifies the active working-register group r253 specified working register group the lower nibble of the register file address provided by the instruction points to the specified register register group 1 register group 0 i/o ports r15 to r0 r15 to r4 r3 to r0 r15 to r0 note:
z86e72/73 otp microcontroller ps008701-0201 44 hi8(d)0bh register this register (table 14) holds the captured data from the output of the 8-bit counter/timer0. this register is typically used to hold the number of counts when the input signal is 1. l08(d)0ah register this register (table 15) holds the captured data from the output of the 8-bit counter/timer0. this register is typically used to hold the number of counts when the input signal is 0. (d) 09h hi16 (d) 08h lo16 (d) 07h tc16h (d) 06h tc16l (d) 05h tc8h (d) 04h tc8l (d) 03h reserved (d) 02h ctr2 (d) 01h ctr1 (d) 00h ctr0 table 14. hi8(d)0bh register field bit position value description t8_capture_hi 76543210 r/w captured data no effect table 15. lo8(d)0ah register field bit position value description t8_capture_l0 76543210 r/w captured data no effect table 13. expanded register group d (continued)
z86e72/73 otp microcontroller ps008701-0201 45 hi16(d)09h register this register (table 16) holds the captured data from the output of the 16-bit counter/timer16. this register holds the ms-byte of the data. l016(d)08h register this register (table 17) holds the captured data from the output of the 16-bit counter/timer16. this register holds the ls-byte of the data. tc16h(d)07h register table 18 describes the counter/timer2 ms-byte hold register. . tc16l(d)06h register table 19 describes the counter/timer2 ls-byte hold register. table 16. hi16(d)09h register field bit position value description t16_capture_hi 76543210 r/w captured data no effect table 17. lo16(d)08h register field bit position value description t16_capture_lo 76543210 r/w captured data no effect table 18. tc16h(d)07h register field bit position value description t16_data_hi 76543210 r/w data table 19. tc16l(d)06h register field bit position value description t16_data_lo 76543210 r/w data
z86e72/73 otp microcontroller ps008701-0201 46 tc8h(d)05h register table 20 describes the counter/timer8 high hold register. tc8l(d)04h register table 21 describes the counter/timer8 low hold register. ctr0(d)00h register table 22 describes the counter/timer8 control register. table 20. tc8h(d)05h register field bit position value description t8_level_hi 76543210 r/w data table 21. tc8l(d)04h register field bit position value description t8_level_lo 76543210 r/w data table 22. ctr0(d)00h register field bit position value description t8_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo -6------ r/w 0 1 modulo-n single pass time_out --5------ r w 0 1 0 1 no counter time-out counter time-out occurred no effect resetflagto0 t8 _clock ---43--- r/w 0 0 01 10 11 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0 1 disable data capture int. enable data capture int.
z86e72/73 otp microcontroller ps008701-0201 47 t8 enable this field enables t8 when set (written) to 1. single/modulo-n when set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. when set to 1 (single pass), the counter stops when the terminal count is reached. time-out this bit is set when t8 times out (terminal count reached). to reset this bit, a 1 must be written to this location. this is the only way to reset this status condition; therefore, you must reset this bit before using/enabling the counter/ timers. care must be taken when using the or or and commands to manipulate ctr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode). these instructions use a read-modify-write sequence in which the current status from the ctr0 and ctr1 registers is ored or anded with the designated value and then written back into the registers. for example, when the status of bit 5 is 1, a reset condition occurs. t8 clock this bit defines the frequency of the input signal to t8. capture_int_mask set this bit to allow interrupt when data is captured into either lo8 or hi8 upon a positive or negative edge detection in demodulation mode. counter_int_mask counter_int_mask ------1- r/w 0 1 disable time-out int. enable time-out int. p34_out -------0 r/w 0* 1 p34 as port output t8 output on p34 note: *indicates the value upon power-on reset table 22. ctr0(d)00h register (continued) field bit position value description notes:
z86e72/73 otp microcontroller ps008701-0201 48 set this bit to allow interrupt when t8 has a time out. p34_out this bit defines whether p34 is used as a normal output pin or the t8 output. ctr1(d)01h register this register (table 23) controls the functions in common with the t8 and t16. table 23. ctr1(d)01h register field bit position value description mode 7------- r/w 0* 1 transmit mode demodulation mode p36_out/demodulator_input -6------ r/w 0* 1 0 1 transmit mode port output t8/16 output demodulation mode p31 p20 t8/t16_logic/edge _detect --54---- r/w 00 01 10 11 00 01 10 11 transmit mode and or nor nand demodulation mode falling edge rising edge both edges reserved transmit_submode/glitch_filter ----32-- r/w 00 01 10 11 00 01 10 11 transmit mode normal operation ping-pong mode t16_out = 0 t16_out = 1 demodulation mode no filter 4 sclk cycle 8 sclk cycle 16 sclk cycle
z86e72/73 otp microcontroller ps008701-0201 49 mode if it is 0, the counter/timers are in the transmit mode; otherwise, they are in the demodulation mode. p36_out/demodulator_input in transmit mode, this bit defines whether p36 is used as a normal output pin or the combined output of t8 and t16. in demodulation mode, this bit defines whether the input signal to the counter/tim- ers is from p20 or p31. t8/t16_logic/edge _detect in transmit mode, this field defines how the outputs of t8 and t16 are combined (and, or, nor, nand). in demodulation mode, this field defines which edge needs to be detected by the edge detector. transmit_submode/glitch filter in transmit mode, this field defines whether t8 and t16 are in the ? ping-pong ? mode or in independent normal operation mode. setting this field to ? normal initial_t8_out/rising_edge ------1- r/w r w 0 1 0 1 0 1 transmit mode t8_out is 0 initially t8_out is 1 initially demodulation mode no rising edge rising edge detected no effect resetflagto0 initial_t16_out/falling _edge -------0 r/w r w 0 1 0 1 0 1 transmit mode t16_out is 0 initially t16_out is 1 initially demodulation mode no falling edge falling edge detected no effect resetflagto0 note: * indicates the value upon power-on reset. table 23. ctr1(d)01h register (continued) field bit position value description
z86e72/73 otp microcontroller ps008701-0201 50 operation mode ? terminates the ? ping-pong mode ? operation. when set to 10, t16 is immediately forced to a 0. when set to 11, t16 is immediately forced to a 1. in demodulation mode, this field defines the width of the glitch that must be filtered out. initial_t8_out/rising_edge in transmit mode, if 0, the output of t8 is set to 0 when it starts to count. if 1, the output of t8 is set to 1 when it starts to count. when this bit is set to 1 or 0, t8_out is set to the opposite state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d1. in demodulation mode, this bit is set to 1 when a rising edge is detected in the input signal. to reset it, a 1 must be written to this location. initial_t16 out/falling _edge intransmitmode,ifitis0,theoutputoft16issetto0whenitstartstocount.ifit is 1, the output of t16 is set to 1 when it starts to count. this bit is effective only in normal or ping-pong mode (ctr1, d3, d2). when this bit is set, t16_out is set to the opposite state of this bit. this ensures that when the clock is enabled a tran- sition occurs to the initial state set by ctr1, d0. in demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. to reset it, a 1 must be written to this location. modifying ctr1 (d1 or d0) while the counters are enabled causes unpredictable output from t8/t16 out. note:
z86e72/73 otp microcontroller ps008701-0201 51 ctr2(d)02h register table 24 describes the counter/timer16 control register. t16_enable this field enables t16 when set to 1. single/modulo-n in transmit mode, when set to 0, the counter reloads the initial value when termi- nal count is reached. when set to 1, the counter stops when the terminal count is reached. table 24. ctr2(d)02h register field bit position value description t16_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter submode/modulo-n -6------ r/w 0 1 0 1 transmit mode modulo-n single pass demodulation mode t16 recognizes edge t16 does not recognize edge time_out --5----- r w 0 1 0 1 no counter time-out counter time-out occurred no effect resetflagto0 t16 _clock ---43--- r/w 00 01 10 11 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0 1 disable time-out int. enable time-out int. p35_out -------0 r/w 0* 1 p35 as port output t16outputonp35 note: * indicates the value upon power-on reset.
z86e72/73 otp microcontroller ps008701-0201 52 in demodulation mode, when set to 0, t16 captures and reloads on detection of all the edges. when set to 1, t16 captures and detects on the first edge, but ignores the subsequent edges. for details, see ? t16 demodulation mode ? on page 60. time_out this bit is set when t16 times out (terminal count reached). to reset it, a 1 must be written to this location. t16_clock this bit defines the frequency of the input signal to counter/timer16. capture_int_mask set this bit to allow interrupt when data is captured into lo16 and hi16. counter_int_mask set this bit to allow interrupt when t16 times out. p35_out this bit defines whether p35 is used as a normal output pin or t16 output. smr2(f)0dh register table 25 describes stop-mode recovery register 2. table 25. smr2(f)0dh register field bit position value description reserved 7------- 0 reserved (must be 0) recovery level -6------ w0* 1 low high reserved --5----- 0 reserved (must be 0) source ---432-- w 000* 001 010 011 100 101 110 111 a. por only b. nand of p23 ? p20 c. nand or p27 ? p20 d. nor of p33 ? p31 e. nand of p33 ? p31 f. n o r o f p 3 3 ? p31, p00, p07 g. nand of p33 ? p31, p00, p07 h. nand of p33 ? p31, p22 ? p20 reserved ------10 00 reserved (must be 0) note: * indicates the value upon power-on reset.
z86e72/73 otp microcontroller ps008701-0201 53 counter/timer functional blocks the following are the counter/timer functional blocks: input circuit eight-bit counter/timer circuits (page 54) sixteen-bit counter/timer circuits (page 59) output circuit (page 62) input circuit the edge detector monitors the input signal on p31 or p20. based on ctr1 d5 ? d4,apulseisgeneratedattheposedgeornegedgelinewhenanedgeis detected. glitches in the input signal that have a width less than specified (ctr1 d3, d2) are filtered out (see figure 25). figure 25. glitch filter circuitry ctr1 d5, d4 p31 p20 mux ctr1 d6 glitch filter edge detector pos edge neg edge ctr1 d3, d2
z86e72/73 otp microcontroller ps008701-0201 54 eight-bit counter/timer circuits figure 26 shows the 8-bit counter/timer circuits. figure 26. eight-bit counter/timer circuits t8 transmit mode when t8 is enabled, the output of t8 depends on ctr1, d1. if it is 0, t8_out is 1. if it is 1, t8_out is 0. when t8 is enabled, the output t8_out switches to the initial value (ctr1 d1). if the initial value (ctr1 d1) is 0, tc8l is loaded; otherwise, tc8h is loaded into the counter (see figure 27). in single-pass mode (ctr0 d6), t8 counts down to 0 and stops, t8_out toggles, the time-out status bit (ctr0 d5) is set, and a time- out interrupt can be generated if it is enabled (ctr0 d1). see figure 28. in mod- ulo-n mode, upon reaching terminal count, t8_out is toggled, but no interrupt is generated. then t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 counts down to 0, toggles t8_out, sets the time-out status bit (ctr0 d5), and generates an interrupt if enabled (ctr0 d1). see figure 29. this completes one cycle. t8 then loads from tc8h or tc8l according to the t8_out level, and repeats the cycle. z8 data bus pos edge neg edge ctr0 d2 irq4 ctr0 d1 t8_out tc8l tc8h clock select sclk ctr0 d4, d3 clock 8-bit counter t8 hi8 lo8 z 8 data bus
z86e72/73 otp microcontroller ps008701-0201 55 figure 27. transmit mode flowchart t8 (8-bit) transmit mode no t8_enable bit set ctr0, d7 ye s reset t8_enable bit load tc8l reset t8_out load tc8h set t8_out enable t8 no t8_timeout ye s single pass single pass? modulo-n t8_out value 1 0 load tc8h set t8_out enable t8 no t8_timeout yes set time-out status bit (ctr0, d5) and generate timeout_int if enabled set time-out status bit (ctr0, d5) and generate timeout_int if enabled t8_out val ue load tc8l reset t8_out disable t8 low high
z86e72/73 otp microcontroller ps008701-0201 56 figure 28. t8_out in single-pass mode figure 29. t8_out in modulo-n mode you can modify the values in tc8h or tc8l at any time. the new values take effect when they are loaded. do not write these registers at the time the values are to be loaded into the counter/timer, to ensure known operation. an initial count of 1 is not allowed (a nonfunction occurs). an initial count of 0 causes tc8 to count from 0 to ffh to feh. ? h ? is used for hexadecimal values. transition from 0 to ffh is not a time-out condition. do not use the same instructions for stopping the counter/ timers and setting the status bits. two successive commands are necessary. first, stop the counter/timers, and, second, reset the status bits. this is required because it takes one counter/timer clock interval for the initiated event to actually occur. t8 demodulation mode youneedtoprogramtc8landtc8htoffh.aftert8isenabled,whenthefirst edge (rising, falling, or both depending on ctr1 d5, d4) is detected, it starts to tc8h counts ? counter enable ? command, t8_out switches to its initial value (ctr1 d1) t8_out toggles, t ime-out interrupt ? counter enable ? command, t8_out switches to its initial value (ctr1 d1) t8_out toggles t8_out tc8l tc8h tc8l tc8h tc8l t ime-out interrupt t ime-out interrupt note: note:
z86e72/73 otp microcontroller ps008701-0201 57 count down. when a subsequent edge (rising, falling, or both depending on ctr1 d5, d4) is detected during counting, the current value of t8 is one's comple- mented and put into one of the capture registers. if it is a positive edge, data is put into lo8; if negative edge, hi8. one of the edge-detect status bits (ctr1 d1, d0) is set, and an interrupt can be generated if enabled (ctr0 d2). meanwhile, t8 is loaded with ffh and starts counting again. when t8 reaches 0, the time-out sta- tus bit (ctr0 d5) is set, an interrupt can be generated if enabled (ctr0 d1), and t8 continues counting from ffh (see figure 30 and figure 31). figure 30. demodulation mode count capture flowchart no ye s pos neg t8 lo8 t8 hi8 ffh t8 what kind of edge edge present t8_enable (set by user) t8 (8-bit) count capture no ye s
z86e72/73 otp microcontroller ps008701-0201 58 figure 31. demodulation mode flowchart t8 (8-bit) demodulation t8 enable ctr0, d7 no yes ffh tc8 first edge present no yes enable tc8 disable t8 t8_enable bit set edge present no yes t8 time-out no yes set edge present status bit and trigger data capture int. if enabled continue counting set edge present status bit and trigger time out int. if enabled mode no yes
z86e72/73 otp microcontroller ps008701-0201 59 sixteen-bit counter/timer circuits figure 32 shows the 16-bit counter/timer circuits. figure 32. sixteen-bit counter/timer circuits t16 transmit mode in normal or ping-pong mode, the output of t16, when not enabled, is dependent onctr1,d0.ifitisa0,t16_outisa1;ifitisa1,t16_outis0.youcanforce the output of t16 to either a 0 or 1 whether it is enabled or not by programming ctr1d3,d2toa10or11. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1 d0). when t16 counts down to 0, t16_out is toggled (in normal or ping-pong mode), an interrupt is generated if enabled (ctr2 d1), and astatusbit(ctr2d5)isset. global interrupts override this function as described in ? interrupts ? on page 62. if t16 is in single-pass mode, it is stopped at this point (see figure 33). if it is in modulo-n mode, it is loaded with tc16h * 256 + tc16l, and the counting contin- ues (see figure 34). z8 data bus pos edge neg edge ctr2 d2 irq3 ctr2 d1 t16_out tc16l tc16h clock select sclk ctr2 d4, d3 clock 16-bit counter t16 hi16 lo16 z 8 data bus note:
z86e72/73 otp microcontroller ps008701-0201 60 figure 33. t16_out in single-pass mode figure 34. t16_out in modulo-n mode you can modify the values in tc16h and tc16l at any time. the new values take effect when they are loaded. to ensure known operation, do not load these regis- tersatthetimethevaluesaretobeloadedintothecounter/timer.aninitialcount of 1 is not allowed. an initial count of 0 causes t16 to count from 0 to ffffh to fffeh. transition from 0 to ffffh is not a time-out condition. t16 demodulation mode you need to program tc16l and tc16h to ffh. after t16 is enabled, when the first edge (rising, falling or both depending on ctr1, d5, d4) is detected, t16 captures hi16 and lo16, reloads, and begins counting. if d6 of ctr2 is 0 when a subsequent edge (rising, falling, or both depending on ctr1 d5, d4) is detected during counting, the current count in t16 is one's complemented and put into hi16 and lo16. when data is captured, one of the edge-detect status bits (ctr1 d1, d0) is set, and an interrupt is generated if enabled (ctr2 d2). t16 is loaded with ffffh and starts again. tc16h*256+tc16l counts ? counter enable ? command, t16_out switches to its initial value (ctr1 d0) t16_out toggles, t ime-out interrupt tc16h*256+tc16l ? counter enable ? command, t16_out switches to its initial value (ctr1 d0) t16_out toggles, time-out interrupt tc16h*256+tc16l tc16h*256+tc16l t16_out toggles, t ime-out interrupt t 16_out
z86e72/73 otp microcontroller ps008701-0201 61 if d6 of ctr2 is 1 t16 ignores the subsequent edges in the input signal and continues counting down. a time out of t8 causes t16 to capture its current value and generate an interrupt if enabled (ctr2, d2). in this case, t16 does not reload and continues counting.ifd6bitofctr2istoggled(bywritinga0andthena1toit),t16cap- tures and reloads on the next edge (rising, falling, or both, depending on ctr1 d5, d4) but continues to ignore subsequent edges. when t16 reaches 0, it continues counting from ffffh. meanwhile, a status bit (ctr2 d5) is set, and an interrupt time-out can be generated if enabled (ctr2 d1). ping-pong mode this operation mode is only valid in transmit mode. t8 and t16 need to be pro- grammed in single-pass mode (ctr0 d6, ctr2 d6), and ping-pong mode needs to be programmed in ctr1 d3, d2. you can begin the operation by enabling either t8 or t16 (ctr0 d7 or ctr2 d7). for example, if t8 is enabled, t8_out is set to this initial value (ctr1 d1). according to t8_out's level, tc8h or tc8l is loaded into t8. after the terminal count is reached, t8 is disabled and t16 is enabled. t16_out switches to its initial value (ctr1 d0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the termi- nal count, it stops, t8 is enabled again, and the whole cycle repeats. interrupts can be allowed when t8 or t16 reaches terminal control (ctr0 d1, ctr2 d1). to stop the ping-pong operation, write 00 to bits d3 and d2 of ctr1. see figure 35. enabling ping-pong operation while the counter/timers are running might cause intermittent counter/timer function. disable the counter/timers and then reset the status flags before instituting this operation. figure 35. ping-pong mode note: enable tc8 time-out enable tc16 time-out ping-pong ctr1 d3,d2
z86e72/73 otp microcontroller ps008701-0201 62 starting ping-pong mode first, make sure both counter/timers are not running. then set t8 into single- pass mode (ctr0 d6), set t16 into single-pass mode (ctr2 d6), and set ping- pong mode (ctr1 d2, d3). these instructions do not have to be in any particular order. finally, start ping-pong mode by enabling either t8 (ctr0 d7) or t16 (ctr2 d7). during ping-pong mode the enable bits of t8 and t16 (ctr0 d7, ctr2 d7) are alternately set and cleared by hardware. the time-out bits (ctr0 d5, ctr2 d5) are set every time the counter/timers reach the terminal count. output circuit figure 36 shows the output circuit. figure 36. output circuit interrupts the z86e7x has five different interrupts. the interrupts are maskable and priori- tized, as shown in figure 37. the five sources are divided as follows: three sources are claimed by port 3 lines p33 ? p31 and the remaining two by the counter/timers (see table 26). the interrupt mask register globally or individually enables or disables the five interrupt requests. and/or/nor/nand logic t8_out ctr1 d5,d4 p34_internal ctr0 d0 p36_internal ctr1 d6 p35_internal ctr2 d0 p35_ext p36_ext p34_ext mux mux mux t16_out mux ctr1, d2 ctr1 d3
z86e72/73 otp microcontroller ps008701-0201 63 figure 37. interrupt block diagram table 26. interrupt types, sources, and vectors name source vector location comments irq0 /dav0, irq0 0, 1 external (p32), rising falling edge triggered irq1 irq1 2, 3 external (p33), falling edge triggered irq2 /dav2, irq2, t in 4,5 external (p31), rising falling edge triggered irq3 t16 6, 7 internal irq4 t8 8, 9 internal interrupt edge select irq register (d6, d7) irq 1, 3, 4 irq imr ipr priority logic 5 vector select irq0 irq2 global interrupt enable interrupt r equest
z86e72/73 otp microcontroller ps008701-0201 64 when more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder controlled by the interrupt priority register. an interrupt machine cycle is activated when an interrupt request is granted. this disables all subsequent interrupts, saves the program counter and status flags, and then branches to the program memory vector location reserved for that interrupt. all z86e7x interrupts are vectored through locations in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt ser- vice routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 can be rising, falling, or both edge triggered and are programmable by the user. the software can poll to identify the state of the pin. programming bits for the interrupt edge select are located in the irq register (r250), bits d7 and d6. the configuration is indicated in table 27. clock the z86e7x on-chip oscillator has a high-gain, parallel-resonant amplifier for con- nection to a crystal, lc, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal must be at cut, 1 mhz to 8 mhz maximum, with a series resistance (rs) less than or equal to 100 ohms. the z86e7x on-chip oscillator can be driven with a cost-effective rc network or other suitable external clock source. table 27. irq register irq interrupt edge d7 d6 irq2 (p31) irq0 (p32) 0 0 1 1 0 1 0 1 f f f r/f f r f r/f notes: f = falling edge r = rising edge in analog mode, the stop-mode recovery sources selected by the smr register are connected to the irq1 input. any of the stop-mode recovery sources for smr (except p31, p32, and p33) can be used to generate irq1 (falling edge triggered).
z86e72/73 otp microcontroller ps008701-0201 65 the crystal must be connected across xtal1 and xtal2 using the recommended capacitors (capacitance greater than or equal to 22 pf) from each pin to ground. the rc oscillator configuration is an external resistor connected from xtal1 to xtal2, with a frequency-setting capacitor from xtal1 to ground (see figure 38). figure 38. oscillator configuration power-on reset (por) a timer circuit clocked by a dedicated on-board rc oscillator is used for the power-on reset (por) timer function. the por time allows vcc and the oscilla- tor circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of three conditions: power fail to power ok status. stop-mode recovery (if d5 of smr = 1). wdt time-out. the por time is a nominal 5 ms. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop-mode recovery (typical for external clock, rc, and lc oscillators). c1 c2 xtal1 xtal2 l r rf rd c1 c1 c1 c2 c2 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal c1, c2 = 47pf typ* f=8mhz lc c1, c2 = 22 pf l=130 h* f=3mhz* rc @ 3v vcc (typ) c1 = 33 pf* r=1k* 32 khz xtal c1 = 20 pf, c = 33 pf rd = 56 ? 470k rf = 10m external clock * preliminary value including pin parasitics
z86e72/73 otp microcontroller ps008701-0201 66 halt halt turns off the internal cpu clock, but not the xtal oscillation. the counter/ timers and external interrupts irq0, irq1, irq2, irq3, and irq4 remain active. the devices are recovered by interrupts, either externally or internally generated. an interrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. stop this instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 a (typical) or less. stop mode is terminated only by a reset, such as wdt time-out, por, smr, or external reset. this causes the processor to restart the application program at address 000ch. to enter stop (or halt) mode, you need to first flush the instruction pipeline to avoid sus- pending execution in mid-instruction. to do this, you must execute a nop (op code = ffh) immediately before the appropriate sleep instruction. for example: ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode port configuration register (pcon) the pcon register (figure 39) configures the comparator output on port 3. it is located in the expanded register file at bank f, location 00. figure 39. port configuration register (pcon) ? write only d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 reserved (must be 1) port 0 0=open-drain 1 = push-pull* reserved (must be 1) *default setting after reset pcon (0f) 0h 0 p34, p37, standard output* 1 p34, p37, comparator output
z86e72/73 otp microcontroller ps008701-0201 67 comparator output port 3 (d0) bit 0 controls the comparator used in port 3. a 1 in this location brings the compar- atoroutputstop34andp37,anda0releasestheporttoitsstandardi/oconfigu- ration. port 0 output mode (d2) bit 2 controls the output mode of port 0. a 1 in this location sets the output to push-pull,anda0setstheoutputtoopen-drain. stop-mode recovery register (smr) this register selects the clock divide value and determines the mode of stop- mode recovery (figure 40). all bits are write only except bit 7, which is read only. bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a high level is required from the recovery source. bit 5 controls the reset delay after recovery. bits d2, d3, and d4 of the smr register specify the source of the stop-mode recovery signal. bit d0 determines if sclk/tclk are divided by 16 or not. the smr is located in bank f of the expanded register group at address 0bh.
z86e72/73 otp microcontroller ps008701-0201 68 figure 40. stop-mode recovery register p00 p32 vcc p31 p32 p33 p27 p20 p23 p20 p27 smr d4 0 d3 0 d2 0 smr d4 0 d3 1 d2 0 smr d4 0 d3 1 d2 1 smr d4 1 d3 0 d2 0 smr d4 1 d3 0 d2 1 smr d4 1 d3 1 d2 0 smr d4 1 d3 1 d2 1 smr2 d4 0 d3 0 d2 0 smr2 d4 0 d3 1 d2 0 smr2 d4 0 d3 1 d2 1 smr2 d4 1 d3 0 d2 0 smr2 d4 1 d3 0 d2 1 smr2 d4 1 d3 1 d2 0 smr2 d4 1 d3 1 d2 1 smr2 d4 0 d3 0 d2 1 vcc p20 p32 p23 p20 p27 p31 p33 p31 p33 p32 p31 p33 p00 p07 p32 p31 p33 p07 p20 p32 p31 p33 p21 p22 smr2 d6 smr d6 to reset and wdt circuitry (active low) s1 s2 s3 s4 t o irq1
z86e72/73 otp microcontroller ps008701-0201 69 sclk/tclk divide-by-16 select (d0) d0 of the smr controls a divide-by-16 prescaler of sclk/tclk (figure 41). the purpose of this control is to selectively reduce device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources interrupt logic). after stop-mode recovery, this bit is set to a 0. figure 41. sclk circuit stop-mode recovery source (d2, d3, and d4) these three bits of the smr specify the wake-up source of the stop recovery (figure 40 on page 68 and table 28). any port 2 bit defined as an output drives the corresponding input to the default state to allow the remaining inputs to control the and/or function. refer to ? stop-mode recovery register 2(smr2) ? on page 71 for other recovery sources. table 28. stop-mode recovery source smr:432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 0 0 1 reserved 0 1 0 p31 transition 0 1 1 p32 transition 1 0 0 p33 transition 1 0 1 p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 osc divide by 2 divide by 16 sclk tclk smr, d0 note:
z86e72/73 otp microcontroller ps008701-0201 70 stop-mode recovery delay select (d5) this bit, if low, disables the 5 ms /reset delay after stop-mode recovery. the default configuration of this bit is one. if the ? fast ? wake up is selected, the stop- mode recovery source needs to be kept active for at least 5tpc. stop-mode recovery edge select (d6) a 1 in this bit position indicates that a high level on any one of the recovery sources wakes the z86e7x from stop mode. a 0 indicates low level recovery. thedefaultis0onpor. cold or warm start (d7) this bit is set by the device upon entering stop mode. it is a read-only flag bit. a 1ind7(warm)indicatesthatthedeviceawakesfromasmrsourceorawdt while in stop mode. a 0 in this bit (cold) indicates that the device is reset by a por or wdt while not in stop mode.
z86e72/73 otp microcontroller ps008701-0201 71 stop-mode recovery register 2 (smr2) this register (see figure 42) determines the mode of stop mode recovery for smr2. figure 42. stop-mode recovery register 2 ? (0f) dh: d2 ? d4, d6 write only if smr2 is used in conjunction with smr, either of the specified events causes a stop-mode recovery. port pins configured as outputs are ignored as a smr or smr2 recovery source. for example, if the nand of p23 ? p20 is selected as the recovery source and p20 is configured as an output, the remaining smr pins (p23 ? p21) form the nand equation. d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 = por only * 001 = nand p20, p21, p22, p23 010 = nand p20, p21, p22, p33, p24, p25, p26, p27 011 = nor p31, p32, p33 100 = nand p31, p32, p33 101 = nor p31, p32, p33, p00, p07 110 = nand p31, p32, p33, p00, p07 111 = nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level 0=low* 1=high * default setting after reset reserved (must be 0) smr2 (0f) dh note: if used in conjunction with smr, either of the two specified events causes a stop-mode recovery. note:
z86e72/73 otp microcontroller ps008701-0201 72 watch-dog timer mode register (wdtmr) the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its termi- nal count. the wdt must initially be enabled by executing the wdt instruction and refreshed on subsequent executions of the wdt instruction. the wdt circuit is driven by an on-board rc oscillator or external oscillator from the xtal1 pin. thewdtinstructionaffectsthezero(z),sign(s),andoverflow(v)flags. theporclocksourceisselectedwithbit4ofthewdtregister.bit0and1con- trol a tap circuit that determines the time-out period. bit 2 determines whether the wdt is active during halt, and bit 3 determines wdt activity during stop. bits 5 through 7 are reserved. see figure 43. figure 43. watch-dog timer mode register ? write only this register is accessible only during the first 60 processor cycles (sclk) from the execution of the first instruction after power-on-reset, watch-dog reset, or a stop-mode recovery (figure 40 on page 68). after this point, the register cannot be modified by any means, intentional or otherwise. the wdtmr cannot be read and is located in bank f of the expanded register group at address location 0fh. it is organized as shown in figure 43. d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc external clock * default setting after reset 00 5 ms min 256 tpc 01* 10 ms min 512 tpc 10 20 ms min 1024 tpc 11 80 ms min 4096 tpc wdt during halt 0=off 1=on* wdt during stop 0=off 1=on* reserved (must be 0) wdtmr (0f) fh xtal/int rc select for wdt 0 = on-board rc* 1 = xtal
z86e72/73 otp microcontroller ps008701-0201 73 wdt time select (d0, d1) this bit selects the wdt time period. it is configured as shown in table 29. wdtmr during halt (d2) this bit determines whether or not the wdt is active during halt mode. a 1 indi- catesactiveduringhalt.thedefaultis1. wdtmr during stop (d3) this bit determines whether or not the wdt is active during stop mode. since thextalclockisstoppedduringstopmode,theon-boardrchastobe selected as the clock source to the wdt/por counter. a 1 indicates active during stop. the default is 1. clock source for wdt (d4) this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc oscillator is bypassed, and the por and wdt clock source is driven from the external pin, xtal1. the default configuration of this bit is 0, which selects the rc oscillator. see figure 44. table 29. wdt time select d1 d0 time-out of internal rc osc time-out of xtal clock 0 0 5 ms min 256 tpc 0 1 10 ms min 512 tpc 1 0 20 ms min 1024 tpc 1 1 80 ms min 4096 tpc notes: tpc = xtal clock cycle the default on reset is 10 ms.
z86e72/73 otp microcontroller ps008701-0201 74 figure 44. resets and wdt low-voltage protection an on-board voltage comparator checks that v cc is at the required level to ensure correct operation of the device. reset is globally driven if v cc is below v lv (low voltage). the minimum operating voltage varies with the temperature and operating frequency, while v lv varies with temperature only. clk 18 clock reset generator reset * /clr 2 wdt tap select internal rc osc. clk *clr1 por wdt1 234 low operating voltage det. internal reset active high ck source select (wdtmr) xtal vdd vbo/vlv 2v ref. from stop mode recovery source wdt stop delay select (smr) 12 ns glitch filter + - 5 clock filter wdt/por counter chain m u x /reset * /clr1 and /clr2 enable the wdt/por and 18 clock reset timers upon a low to high input translation. vcc
z86e72/73 otp microcontroller ps008701-0201 75 software-selectable options there are four software-selectable options to choose from based on the rom- based parts mask options. register (f0) eh otp byte is where these options are controlled. these options are listed in table 30. the rc oscillator xtal1/2 option is invoked during otp programming as a user-selectable item. thelowvoltagetripvoltage(v lv ) is less than 3.0 v under the following condi- tions. maximum (v lv ) conditions t a =0 c, +70 c internal clock frequency equal to or less than 8.0 mhz the internal clock frequency is one-half the external clock frequency. the device functions normally above 3.0 v under all conditions. the minimum functionality point below 3 v is to be defined. the v lv is a function of temperature and process parameters. see figure 45. table 30. software-selectable options bit name reg(0f)eh port 0 pull-ups (lower nibble) on/off port 0 pull-ups (upper nibble) on/off port 2 pull-ups on/off mouse/normal m/n note: note:
z86e72/73 otp microcontroller ps008701-0201 76 figure 45. typical z86e7x low voltage versus temperature at 8 mhz vlv temperature 15 25 35 45 55 0 tbd
z86e72/73 otp microcontroller ps008701-0201 77 eprom programming table 31 describes the programming and test modes. table 31. programming and test modes device pins user/test mode device pin # user modes p33 v pp p32 epm pref1 /ce p31 /oe p20 /pgm addr v cc port 1 cnfg data test addr a0 ? a3 note eprom read v cc v h v il v il v ih addr 3.0 v out xx program v pp v cc v il v ih v il addr 6.0 v in xx program verify v pp v cc v il v il v ih addr 6.0 v out xx rc option v pp v cc v h v ih v il xx 6.0 v xx xx margin read v va v h v il v h v ih addr 6.0 v out 00 1 shadow row rd v cc v h v il v il v ih col 3.0 v out 01 1 shadow row prg v pp v h v il v ih v il col 6.0 v in 01 1 shadow row ver v pp v h v il v il v ih col 6.0 v out 01 1 shadow col rd v cc v h v il v il v ih row 3.0 v out 02 1 shadow col prg v pp v h v il v ih v il row 6.0 v in 03 1 shadow col ver v pp v h v il v il v ih row 6.0 v out 02 1 page prg 2 byte v pp v h v il v ih v il tbd 6.0 v in 04 1 page prg 4 byte v pp v h v il v ih v il tbd 6.0 v in 05 1 page prg 8 byte v pp v h v il v ih v il tbd 6.0 v in 06 1 page prg 16 byte v pp v h v il v ih v il tbd 6.0 v in 07 1 notes: 1. all test modes are entered by first setting up the corresponding test address and then latching the address by bringing the /oe to v h and then to v il , except for the margin read which requires /oe to be kept at v h . v va =variablefrom v cc to v pp v pp = 12.5 v 0.5 v v h =12.5v0.5v v ih =3v v il =0v xx = irrelevant i pp during programming = 40 ma maximum i cc during programming, verify, or read = 40 ma maximum.
z86e72/73 otp microcontroller ps008701-0201 78 table 32 lists the timing of the programming waveform. figure 46 shows the eprom read timing diagram. figure 47 on page 80 shows the eprom program and verify timing diagram. figure 48 on page 81 shows the programming eprom, ram protect, and 16k size selection timing diagram. table 32. timing of programming waveform parameters name min max units 1 address setup time 2 s 2 data setup time 2 s 3v pp setup time 2 s 4v cc setup time 2 s 5 chip enable setup time 2 s 6 program pulse width 0.95 s 7 data hold time 2 s 8/oesetuptime 2 s 9 data access time 200 ns 10 data output float time 100 ns 11 overprogram pulse width 2.85 ms 12 epm setup time 2 s 13 /pgm setup time 2 s 14 address to /oe setup time 2 s 15 option program pulse width 78 ms
z86e72/73 otp microcontroller ps008701-0201 79 figure 46. eprom read
z86e72/73 otp microcontroller ps008701-0201 80 figure 47. eprom program and verify address v ih v il address stable data v ih v il data stable data out valid 1 2 10 9 3 v v h v ih epm v il 4 5 7 /ce v il 6 8 11 /pgm v ih v il v ih v h v 4.5 v 6 v /oe v ih v il program cycle verify cycle 15 pp cc
z86e72/73 otp microcontroller ps008701-0201 81 figure 48. programming eprom, ram protect, and 16k size selection figure 49 shows the programming flowchart.
z86e72/73 otp microcontroller ps008701-0201 82 figure 49. programming flowchart
z86e72/73 otp microcontroller ps008701-0201 83 expanded register file control registers (0d) figure 50 through figure 52 show the expanded register file control registers (0d). figure 50. tc8 control register ? (0d) 0h: read/write except where noted d7 d6 d5 d4 d3 d2 d1 d0 0 = p34 as port output * * default setting after reset 1=timer8output 0 = disable t8 time-out interrupt 1 = enable t8 time-out interrupt 1 = enable t8 data capture interrupt 0 = disable t8 data capture interrupt 00 = sclk on t8 01=sclk/2ont8 10=sclk/4ont8 11=sclk/8ont8 r = 0 no t8 counter time-out r = 1 t8 counter time-out occurred w=0noeffect w = 1 reset flag to 0 1 = single pass 0 = modulo-n r = 0 t8 disabled * r = 1 t8 enabled w=0stopt8 w = 1 enable t8 ctr0 (0d) 0h
z86e72/73 otp microcontroller ps008701-0201 84 figure 51. t8 and t16 common control functions ? (0d) 1h: read/write d7 d6 d5 d4 d3 d2 d1 d0 transmit mode r/w 0 t16_out is 0 initially 1 t16_out is 1 initially demodulation mode r 0 = no falling edge detection r 1 = falling edge detection w0=noeffect w 1 = reset flag to 0 transmit mode r/w 0 = t8_out is 0 initially r/w 1 = t8_out is 1 initially demodulation mode r0=norisingedgedetection r 1 = rising edge detection w0=noeffect w 1 = reset flag to 0 transmit mode 0 0 = normal operation 0 1 = ping-pong mode 10t16_out=0 11t16_out=1 demodulation mode 00=nofilter 01=4sclkcyclefilter 10=8sclkcyclefilter 1 1 = reserved transmit mode/t8/t16 logic 00=and 01=or 10=nor 11=nand demodulation mode 0 0 = falling edge detection 0 1 = rising edge detection 1 0 = both edge detection 1 1 = reserved transmit mode 0=p36asportoutput* 1=p36ast8/t16_out demodulation mode 0 = p31 as demodulator input 1 = p20 as demodulator input transmit/demodulation modes 0 = transmit mode * 1 = demodulation mode * default setting after reset ctr1 (0d) 1h note: care must be taken in differentiating note: changing from one mode to transmit mode from demodulation mode. depending on which of these two modes is operating, the ctr1 bit has different functions. another cannot be done without disabling the counter/timers.
z86e72/73 otp microcontroller ps008701-0201 85 figure 52. t16 control register ? (0d) 2h: read/write except where noted d7 d6 d5 d4 d3 d2 d1 d0 0 = p35 is port output * * default setting after reset 1=p35istc16output 0 = disable t16 time-out interrupt 1 = enable t16 time-out interrupt 1 = enable t16 data capture interrupt 0 = disable t16 data capture interrupt 00 = sclk on t16 01 = sclk/2 on t16 10 = sclk/4 on t16 11=sclk/8ont16 r = 0 no t16 time-out r = 1 t16 time-out occurs w=0noeffect w = 1 reset flag to 0 r = 0 t16 disabled * r = 1 t16 enabled w=0stopt16 w = 1 enable t16 ctr2 (0d) 02h transmit mode 0 = modulo-n for t16 1 = single pass for t16 demodulator mode 0 = t16 recognizes edge 1 = t16 does not recognize edge
z86e72/73 otp microcontroller ps008701-0201 86 expanded register file control registers (0f) figure 53 through figure 58 show the expanded register file control registers (0f). figure 53. stop-mode recovery register ? (f) 0bh: d6 ? d0=write only, d7=read only d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0=off** reserved (must be 0) stop-mode recovery source smr (0f) 0b 1=on 000 = por only * 001 = reserved 010 = p31 011 = p32 100 = p33 101 = p27 110 = p2 n or 0 ? 3 111 = p2 nor 0 ? 7 stop delay 0=off 1=on* stop recovery level 0 = low * 1=high stop flag 0=por* 1 = stop recovery ** * default setting after reset ** default setting after reset and stop-mode recovery
z86e72/73 otp microcontroller ps008701-0201 87 figure 54. stop-mode recovery register 2 ? (0f) dh: d2 ? d4, d6 write only d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 = por only * 001 = nand p20, p21, p22, p23 010 = nand p20, p21, p22, p33, p24, p25, p26, p27 011 = nor p31, p32, p33 100 = nand p31, p32, p33 101 = nor p31, p32, p33, p00, p07 110 = nand p31, p32, p33, p00, p07 111 = nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level 0=low* 1=high * default setting after reset reserved (must be 0) smr2 (0f) dh note: if used in conjunction with smr, either of the two specified events causes a stop-mode recovery.
z86e72/73 otp microcontroller ps008701-0201 88 figure 55. option bit register figure 56. watch-dog timer mode register ? (f)0fh:writeonly d7 d6 d5 d4 d3 d2 d1 d0 port 0 (0 ? 3) pull-up 1 pull-up active 0 pull-up inactive port 0 (7 ? 4) pull-up 1 pull-up active port 2 pull-up option 1 pull-up active 0 pull-up inactive reserved (must be 0) reserved (must be 0) opt (0f) ef mask option for mouse trackball interface p00 ? p03 1 for mouse trackball interface 0normal 2 pull-up inactive d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc external clock * default setting after reset 00 5 ms min 256 tpc 01* 10 ms min 512 tpc 10 20 ms min 1024 tpc 11 80 ms min 4096 tpc wdt during halt 0=off 1=on* wdt during stop 0=off 1=on* reserved (must be 0) wdtmr (0f) fh xtal/int rc select for wdt 0 = on-board rc* 1 = xtal
z86e72/73 otp microcontroller ps008701-0201 89 figure 57. port configuration register (pcon) ? (0f) 0h: write only figure 58. port 2 mode register ? f6h: write only d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 reserved (must be 1) port 0 0 = open-drain 1 = push-pull* reserved (must be 1) *default setting after reset pcon (0f) 0h 0 p34, p37, standard output* 1 p34, p37, comparator output d7 d6 d5 d4 d3 d2 d1 d0 r246 p2m p27 ? p20 i/o definition 0 = defines bit as output 1 = defines bit as input * *default setting after reset
z86e72/73 otp microcontroller ps008701-0201 90 z8 standard control register diagrams figure 59 through figure 67 show the z8 standard control register diagrams. figure 59. port 3 mode register ? f7h: write only d7 d6 d5 d4 d3 d2 d1 d0 0 port 2 open-drain* * default setting after reset 1 port 2 push-pull 0 = p31, p32 digital mode 1 = p31, p32 analog mode 1 p32 = /dav0/rdy0 0 p32 = input 00 p33 =input p34 = output* 01 p33 = input 10 p34 = /dm 0 p31 = input (tin) p36 = output (tout) 1 p31 = /dav1/rdy2 p36 = rdy2//dav2 p37 = output 0 p30 = input 0parityoff 1parityon r247 p3m p34 = output* p35 = rdy0//dav0 p33 = /dav1/rdy1 p34 = rdy1//dav1 1p30=serialin p37 = serial out 11
z86e72/73 otp microcontroller ps008701-0201 91 figure 60. port 0 and 1 mode register ? f8h: write only figure 61. interrupt priority registers ? (0) f9h: write only d7 d6 d5 d4 d3 d2 d1 d0 p00 ? p03 mode 00 output 1x a15 ? a12 01 input* 1x a11 ? a8 stack selection 0 external 1 internal* p17 ? p10 mode 00 byte output 01 reserved 10 ad7 ? ad0 11 high-impedance ad7ad0, /as, /ds, /r//w, a11 ? a8, external memory timing 0normal* 1 extended p07 ? p04 mode 00 output 01 input* a15 ? a12, if selected d7 d6 d5 d4 d3 d2 d1 d0 r249 ipr interrupt group priority 000 = reserved reserved (must be 0) 001 = c>a>b 101 = a>b>c 011 = a>c>b 100 = b>c>a 101 = c>b>a 110 = b>a>c 111 = reserved irq1, irq, priority (group c) 0=irq1>irq4 1=irq4>irq1 irq0, irq2, priority (group b) 0=irq2>irq0 1=irq0>irq2 irq3, irq5, priority (group a) 0=irq5>irq3 1=irq3>irq5
z86e72/73 otp microcontroller ps008701-0201 92 figure 62. interrupt request register ? (0) fah: read/write figure 63. interrupt mask register ? (0)fbh:read/write d7 d6 d5 d4 d3 d2 d1 d0 r250 irq irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = t16 irq4 = t8 inner edge p31 p32 =00 p31 p32 =01 p31 p32 =10 p31 p32 =11 reserved (must be 0) default setting after reset = 0000 0000 d7 d6 d5 d4 d3 d2 d1 d0 1 enables irq4 ? irq0 reserved (must be 0) r251 imr reserved (must be 0) 0 master interrupt disable* 1 master interrupt enable * default setting after reset (d0 = irq0)
z86e72/73 otp microcontroller ps008701-0201 93 figure 64. flag register ? (0) fch: read/write figure 65. register pointer ? (0) fdh: read/write figure 66. stack pointer high ? (0)feh:read/write figure 67. stack pointer low ? (0)ffh:read/write d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow tag sign flag zero flag r252 flags d7 d6 d5 d4 d3 d2 d1 d0 expanded register (bank) pointer working register pointer r253 rp default setting after reset = 0000 d7 d6 d5 d4 d3 d2 d1 d0 stack pointer upper byte (sp15 ? sp8) r254 sph d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp7 ? sp0) r255 spl
z86e72/73 otp microcontroller ps008701-0201 94 package information the z86e72/73 is available in 40-pin dip (figure 68), 44-pin qfp (figure 69 on page 95), and 44-pin plcc (figure 70 on page 96) packages. figure 68. 40-pin dip package diagram
z86e72/73 otp microcontroller ps008701-0201 95 figure 69. 44-pin qfp package diagram
z86e72/73 otp microcontroller ps008701-0201 96 figure 70. 44-pin plcc package diagram
z86e72/73 otp microcontroller ps008701-0201 97 ordering information table 33 shows the ordering codes for the 16-mhz z86e72/73. figure 71 shows an example of what the ordering codes represent. figure 71. ordering codes example for fast results, contact your local zilog sales office for assistance in ordering the part wanted. package p=plasticdip f = plastic quad flat pack v = plastic chip carrier temperature s=0 cto+70 c speed 16 = 16 mhz environmental c = plastic standard table 33. ordering codes 40-pin dip 44-pin plcc 44-pin qfp z86e7216psc z86e7216vsc Z86E7216FSC z86e7316psc z86e7316vsc z86e7316fsc example: z 86e73 16 p s c isaz86e73,16mhz,dip,0 cto+70 c, plastic standard environmental flow temperature package speed product number zilog prefix
z86e72/73 otp microcontroller ps008701-0201 98 customer feedback form z86e72/73 otp microcontroller if you experience any problems while operating this product, or if you note any inaccura- cies while reading this product specification, please copy and complete this form, then mail or fax it to zilog (see return information , below). we also welcome your sugges- tions! customer information product information return information zilog system test/customer support 910 e. hamilton avenue, suite 110, ms 4 ? 3 campbell, ca 95008 fax: (408) 558-8536 email: tools@zilog.com problem description or suggestion provide a complete description of the problem or your suggestion. if you are reporting a specific problem, include all steps leading up to the occurrence of the problem. attach additional pages as necessary. _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ name country company phone address fax city/state/zip email serial # or board fab #/rev # software version document number host computer description/type

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