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1 ps8550 07/31/01 product description pericom semiconductor?s pi74avc+ series of logic circuits are produced using the company?s advanced submicron cmos technology, achieving industry leading speed. the pi74avc+16652 is a 16-bit bus transceiver and register designed for low 1.65v to 3.6v v cc operation. it consists of d-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. the device can be used as two 8-bit transceivers or one 16-bit transceiver. complementary output enable (oeab and oeba) inputs are provided to control the transceiver functions. select control (sab and sba) inputs are provided to select whether real-time or stored data is transferred. a low input level selects real-time data, and a high input level selects stored data. circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. data on the a or b bus, or both, can be stored in the internal d flip- flops by low-to-high transitions at the appropriate clock (clkab or clkba) inputs regardless of the levels on the select control or output enable inputs. when sab and sba are in the real-time transfer mode, it also is possible to store data without using the internal d-type flip-lops by simultaneously enabling oeab and oeba. in this configuration, each output reinforces its input. thus, when all other data sources to the two sets of bus lines are in the high-impedance state, each set of bus lines remains at its last level configuration. to ensure the high-impedance state during power up or power down, oeba should be tied to v cc through a pull-up resistor and oeab should be tied to gnd through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking current sourcing capability of the driver. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs logic block diagram product features ? pi74avc + 16652 is designed for low-voltage operation, v cc = 1.65v to 3.6v ? true 24ma balanced drive @ 3.3v ? i off supports partial power-down operation ? 3.6v i/o tolerant inputs and outputs ? all outputs contain a patented ddc (dynamic drivecontrol) circuit that reduces noise without degrading propagation delay. ? industrial operation: ?40c to +85c ? available packages: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 173 mil wide plastic tvsop (k) 1oeba c1 1d to seven other channels 1oeab 1clkba 56 1 55 1sba 1clkab 1sab 54 2 3 5 1a1 c1 1d 52 1b1 one of eight channels 2oeba c1 1d to seven other channels 2oeab 2clkba 29 28 30 2sba 2clkab 2sab 31 27 26 15 2a1 c1 1d 42 2b1 one of eight channels
2 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 pin configuration 1 oeab 1 1 clkab 2 1 sab 3 gnd 4 1 a 1 5 1 a 2 6 v cc 7 1 a 3 8 1 a 4 9 1 a 5 10 gnd 11 1 a 6 12 1 a 7 13 1 a 8 14 2 a 1 15 2 a 2 16 2 a 3 17 gnd 18 2 a 4 19 2 a 5 20 2 a 6 21 v cc 22 2 a 7 23 2 a 8 24 1 oeba 56 1 clkba 55 1 sba 54 gnd 53 1 b 1 52 1 b 2 51 v cc 50 1 b 3 49 1 b 4 48 1 b 5 47 gnd 46 1 b 6 45 1 b 7 44 1 b 8 43 2 b 1 42 2 b 2 41 2 b 3 40 gnd 39 2 b 4 38 2 b 5 37 2 b 6 36 v cc 35 2 b 7 34 2 b 8 33 gnd 25 2 sab 26 2 clkab 27 2 oeab 28 gnd 32 2 sba 31 2 clkba 30 2 oeba 29 product pin description e m a n n i pn o i t p i r c s e d b a e o) h g i h e v i t c a ( s t u p n i e l b a n e t u p t u o a b e o) w o l e v i t c a ( s t u p n i e l b a n e t u p t u o , b a k l c x a b k l c x s t u p n i e s l u p k c o l c a b s x , b a s xs t u p n i l o r t n o c t c e l e s x a x , s t u p n i a r e t s i g e r a t a d s t u p t u o b r e t s i g e r a t a d x b x , s t u p n i b r e t s i g e r a t a d s t u p t u o a r e t s i g e r a t a d d n gd n u o r g v c c r e w o p 56-pin a, k truth table (1) s t u p n i* o / i a t a d n o i t c n u f r o n o i t a r e p o b a e oa b e ob a k l ca b k l cb a sa b s8 a - 1 a8 b - 1 b lh l r o hl r o hxx t u p n it u p n in o i t a l o s i lh - -xx t u p n it u p n ia t a d b d n a a e r o t s xh - l r o hxx t u p n i* * d e i f i c e p s n ub d l o h , a e r o t s hh - - * * xx t u p n it u p t u os r e t s i g e r h t o b n i a e r o t s lx l r o h-xx * * d e i f i c e p s n ut u p n ib e r o t s , a d l o h ll - -x* * xt u p t u ot u p n is r e t s i g e r h t o b n i b e r o t s llxxxl t u p t u ot u p n is u b a o t a t a d b e m i t - l a e r llx l r o hxh t u p t u ot u p n is u b a o t a t a d b d e r o t s hhxxlx t u p n it u p t u os u b b o t a t a d a e m i t - l a e r hh l r o hxhx t u p n it u p t u os u b b o t a t a d a d e r o t s hl l r o hl r o hhh t u p t u ot u p t u o d n a s u b b o t a t a d a d e r o t s s u b a o t a t a d b d e r o t s * the data output functions may be enabled or disabled by a variety of level combinations at the oeab or oeba inputs. data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to -high transition on the clock inputs. ** select control = l; clocks can occur simultaneously. select control = h; to load both registers, clocks must be staggered. notes: 1. h = high voltage level, x = don?t care, l = low voltage level, - = low-to-high transition
3 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 real-time transfer bus b to a real-time transfer bus a to b oeab oeba xclkab xclkba xsab xsba ll x x x l oeab oeba xclkab xclkba xsab xsba h h x x l x oeab oeba xclkab xclkba xsab xsba xh - - - - - xxx lx x - - - - - xx lh - - - - - - - - - - xx oeab oeba xclkab xclkba xsab xsba h l h or l h or l h h storage from a,b, or a and b transfer stored data to a and/or b note: 1. cannot transfer data to a bus and b bus simultaneously. bus a bus b bus a bus b bus a bus b bus a bus b
4 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 recommended operating conditions (1) note: 1. all unused inputs must be held at v cc or gnd to ensure proper device operation. . n i m. x a ms t i n u v c c e g a t l o v y l p p u sg n i t a r e p o5 6 . 16 . 3v y l n o n o i t n e t e r a t a d2 . 1 v h i e g a t l o v t u p n i l e v e l - h g i hv c c v 2 . 1 =v c c v c c v 5 9 . 1 o t v 5 6 . 1 =x 5 6 . 0v c c v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 3 =2 v l i e g a t l o v t u p n i l e v e l - w o lv c c v 2 . 1 =d n g v c c v 5 9 . 1 o t v 5 6 . 1 =x 5 3 . 0v c c v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 3 =8 . 0 v i e g a t l o v t u p n i 06 . 3 v o e g a t l o v t u p t u oe t a t s e v i t c a0v c c e t a t s - 306 . 3 i h o t n e r r u c t u p t u o l e v e l - h g i hv c c v 5 9 . 1 o t v 5 6 . 1 =6 ?a m v c c v 7 . 2 o t v 3 . 2 =2 1 ? v c c v 6 . 3 o t v 3 =4 2 ? i l o t n e r r u c t u p t u o l e v e l - w o lv c c v 5 9 . 1 o t v 5 6 . 1 =6 v c c v 7 . 2 o t v 3 . 2 =2 1 v c c v 6 . 3 o t v 3 =4 2 d t d e t a r l l a f r o e s i r n o i t i s n a r t t u p n i v v c c v 6 . 3 o t v 5 6 . 1 =5v / s n t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o0 4 ?5 8c note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) supply voltage range, v cc .................................................. ?0.5v to +4.6v input voltage range, v i .......................................................... ?0.5v to +4.6v voltage range applied to any output in the high-impedance or power-off state, v o (1) .............. ?0.5v to +4.6v voltage range applied to any output in the high or low state, v o (1,2) .......................................... ?0.5v to v cc +0.5v input clamp current, i ik (v i <0) ............................................ ?50ma output clamp current, i ok (v o <0) ...................................... ?50ma continuous output current, i o ............................................................ 50ma continuous current through each v cc or gnd ................. 100ma package thermal impedance, q ja (3) : package a .................. 64c/w package k ................... 48c/w storage temperature range, t stg ..................................... ?65c to 150c notes: 1. input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. output positive-voltage rating may be exceeded up to 4.6v maximum if theoutput current rating is observed. 3. package thermal impedance is calculated in accordance with jesd 51.
5 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a ps n o i t i d n o c t s e t 1 ( ) v c c . n i m. x a ms t i n u v h o i h o 0 0 1 ? =a v 6 . 3 o t v 5 6 . 1v c c v 2 . 0 ? v i h o 6 ? =m v a h i v 7 0 . 1 =v 5 6 . 12 . 1 i h o 2 1 ? =m v a h i v 7 . 1 =v 3 . 25 7 . 1 i h o 4 2 ? =m v a h i v 2 =v 30 . 2 v l o i l o 0 0 1 =a v 6 . 3 o t v 5 6 . 12 . 0 i l o 6 =m v a h i v 7 5 . 0 =v 5 6 . 15 4 . 0 i l o 2 1 =m v a h i v 7 . 0 =v 3 . 25 5 . 0 i l o 4 2 =m v a h i v 8 . 0 =v 38 . 0 i i s t u p n i l o r t n o cv i v = c c d n g r ov 6 . 35 . 2 a i f f o v i v r o o v 6 . 3 =00 1 i z o v i v = c c d n g r ov 6 . 30 1 i c c v o v = c c i d n g r o o 0 =v 6 . 30 4 c i s t u p n i l o r t n o c v i v = c c d n g r o v 5 . 24 f p v 3 . 34 s t u p n i a t a d v 5 . 26 v 3 . 36 c o s t u p t u ov o v = c c d n g r o v 5 . 28 v 3 . 38 note: 1. typical values are measured at t a = 25c. dc electrical characteristics (over operating range, t a = ?40c +85c)
6 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 timing requirements ( over recommended operating free-air temperature range, unless otherwise noted, see figures 1 thru 4) switching characteristics ( over recommended operating free-air temperature range, unless otherwise noted, see figures 1 thru 4) v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u n i mx a mn i mx a mn i mx a mn i mx a mn i mx a m f k c o l c y c n e u q e r f k c o l c0 5 10 5 20 5 3z h m t w , n o i t a r u d e s l u p r o b a k l c w o l r o h g i h a b k l c 3 . 30 . 14 . 1 s n t u s , e m i t p u t e s b a k l c e r o f e b a , - r o a b k l c e r o f e b b - 0 . 10 . 10 . 19 . 08 . 0 t h , e m i t d l o h b a k l c r e t f a a , - r o a b k l c r e t f a b - 3 . 10 . 19 . 09 . 08 . 0 s r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u l a c i p y t. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m f x a m 0 5 10 5 20 5 3z h m t d p b r o aa r o b0 . 59 . 12 . 45 . 16 . 32 . 12 . 39 . 06 . 2 s n r o b a k l c a b k l c b r o a5 . 50 . 20 . 49 . 18 . 33 . 15 . 30 . 12 . 3 r o b a s a b s a r o b8 . 44 . 21 . 40 . 20 . 47 . 18 . 34 . 11 . 3 t n e e o r o e ob r o a 5 . 48 . 16 . 35 . 15 . 34 . 10 . 30 . 15 . 2 t s i d 5 . 50 . 20 . 48 . 10 . 44 . 17 . 31 . 12 . 3 operating characteristics, t a = 25c s r e t e m a r a p t s e t s n o i t i d n o c v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u l a c i p y tl a c i p y tl a c i p y t c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p d e l b a n e s t u p t u o c l , f p 0 = z h m 0 1 = f 0 35 30 4 f p d e l b a s i d s t u p t u o2 15 10 2
7 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 1.2v and 1.5v 0.1v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 1. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times
8 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 parameter measurement information v cc = 1.8v 0.15v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 2. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 1 k w 1 k w 0.15v 0.15v 30
9 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 2.5v 0.2v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 3. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.15v C0.15v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 30
10 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 parameter measurement information v cc = 3.3v 0.3v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 4. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 0.3v 0.3v 30
11 ps8550 07/31/01 pi74avc+16652 2.5v 16-bit bus transceiver and register with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 56-pin tssop (a) package 56-pin tvsop (k) package .002 .006 seating plane .007 .011 .004 .008 1 56 .236 .244 0.50 0.17 0.27 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 max. 1.20 6.0 6.2 .547 .555 13.9 14.1 .319 8.1 .0197 bsc bsc .047 .031 .041 seating plane .016 bsc 1 56 .169 .177 11.20 11.40 4.30 4.50 1.20 0.40 0.13 0.23 0.80 1.05 x.xx x.xx denotes dimensions in millimeters .002 .006 0.05 0.15 .0035 .008 0.09 0.20 .018 .030 0.45 0.75 6.4 .252 bsc .005 .009 .441 .449 max. a t a d g n i r e d r on o i t p i r c s e d a 2 5 6 6 1 + c v a 4 7 i p p o s s t c i t s a l p e d i w l i m 0 4 2 , n i p - 6 5 k 2 5 6 6 1 + c v a 4 7 i p p o s v t c i t s a l p e d i w l i m 3 7 1 , n i p - 6 5 ordering information

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