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general description the gd16591a and gd16592a is a front-end transmitter/receiver chip set de - signed for multiple line interfaces: stm-4 / oc-12 stm-1 / oc-3 pdh e4 this chip set is designed to interconnect the high speed line interface to standard cmos asics providing low speed data interface. the gd16591a and gd16592a devices are designed for use in both electrical and optical line interface modules. the devices support line speeds of: 140/155 mbit/s nrz mode for e4/ oc-3/stm-1 for an optical line inter- face. 280/311 mbit/s for e4/oc-3/stm-1 in cmi mode for electrical line interface, where en-/decoding is made at the system site. 622 mbit/s nrz mode line speed for oc-12/stm-4 operation. the on-chip vco and pll blocks for clock generation eliminate the need for an external high-speed clock signal. the gd16592a comprises a limiting in - put amplifier (lia), clock & data recov - ery, and a configurable demux circuit. the lia offers a differential input sensi - tivity of 10 mv peak to peak for the high- speed serial input. a lock detect output monitors the pll locked onto the re - ceived serial data. the low-speed interface i/os are lvttl-level, and the high-speed i/os are differential lvpecl levels (the lia input is usable as lvpecl input). system (local) loop-back and line (re- mote) loop-back functions offer simpli- fied manufacturing and field testing. low power consumption is achieved by the 3.3 v single power supply and by omitting all circuitry, which can easily be implemented in the low speed system asic, thus reducing the overall power consumption. the devices are housed in 48 pin edquad tqfp plastic packages. an intel company data sheet rev.: 14 features general low jitter on-chip vco and pll. jitter performance exceeds the rec - ommendations of itu-t and bellcore. the chip set offers seven line and system speed mode: 622 mbit/s 78 mbit/s, 8 bit 311 mbit/s 78 mbit/s, 4 bit 155 mbit/s 78 mbit/s, 2 bit 155 mbit/s 19 mbit/s, 8 bit 280 mbit/s 70 mbit/s, 4 bit 140 mbit/s 70 mbit/s, 2 bit 140 mbit/s 17 mbit/s, 8 bit four phase selectable clock to data timing at parallel interface. selectable reference clock input fre- quencies: 17.408/19.44mhz, 34.816/ 38.88mhz, and 69.632/77.76mhz. loop back for system & line test modes. 48 pin edquad tqfp packages. single supply: 3.1 ... 3.6 v. gd16591a (transmitter) 8:1 / 4:1 / 2:1 mux. differential transmitted clock output. lvpecl data outputs. optional forward/counter clocking scheme. power dissipation, typ.: 350 mw gd16592a (receiver) 1:8 / 1:4 / 1:2 demux. stm-4/stm-1/e4 3.3 v multifunction transmitter and receiver gd16591a/gd16592a gd16591a mux/ retiming pll cmos system asic gd16592a demux/ cdr with pll data 70/78 mbit/s 17/19 mbit/s system / line loop back 2/4/8bit 2/4/8bit data 70/78 mbit/s 17/19 mbit/s clock clock line interface 140/155 mbit/s (optical) 280/311 mbit/s (electrical) 622 mbit/s (stm-4 opt.) line interface 140/155 mbit/s (optical) 280/311 mbit/s (electrical) 622 mbit/s (stm-4 opt.)
functional details general the transmitter and receiver functional blocks are split up into two devices in or - der to reduce cross talk and pin count per device. the telecommunication system (line speed group) is choosen by the select pin (selpdh ): for sdh/sonet (622/311/155 mbit/s) set selpdh high. for pdh (280/140 mbit/s) set selpdh low. the devices can operate in different line and system speed modes; selected by dsel1, dsel2 and selpdh , see table 1. the bit order on the low speed parallel interface is defined with bit 0 as the first bit transferred (id0 for the transmitter and od0 for the receiver). the bit rate per connection can be kept at 78(70) mbit/s regardless of the line speed. in addition a separate low speed 1:8 mode support the transmission of 155(140) mbit/s serial to 19(17) mbit/s, 8 bit parallel. all data pins are used. both devices have a selectable clock di- vider for the system reference clock, which allows the circuits to be driven from either 19 (17), 38(35), or 78(70) mhz reference, independantly of the line and system speed. the refer- ence clock frequency is selected by rsel1, rsel2, and selpdh , see table 2. connecting the differential line loop sig - nals and clocks (llxxx) between gd16591a and gd16592a allows clock recovered loop-back of the received line signal, when llb on both devices is low. connecting the differential system loop signals (slsxx) between gd16591a and gd16592a allows system loop-back, when slb on both devices is low. both circuits comprise fully integrated pll functions for re-timing data at the transmit site, and for clock and data re - covery at the receive site. a passive loop filter (consisting of a re - sistor and a capacitor) is used for both devices. the external loop filter connect - ing ouchp to vctl is shown in figure 1 (for the transmitter gd16591a) and fig - ure 2 (for the receiver gd16592a). the loop filter values are optimized at the evaluation board gd90591/592. the optimal values depends on the ac - tual application. the suggested values in figures 1 and 2 are optimized for best jitter transfer at the evaluation board. the loop filter values should be opti - mized for the actual application. figure 1. loop filter for the transmitter, gd16591a. figure 2. loop filter for the receiver, gd16592a. data sheet rev.: 14 gd16591a/gd16592a page 2 of 16 selpdh dsel1 dsel2 line speed system speed used bits 0 0 0 0 0 0 1 1 0 1 0 1 140 mbit/s 140 mbit/s 280 mbit/s --- 70 mbit/s 17 mbit/s 70 mbit/s --- 0&1 0...7 0...3 --- 1 1 1 1 0 0 1 1 0 1 0 1 155 mbit/s 155 mbit/s 311 mbit/s 622 mbit/s 78 mbit/s 19 mbit/s 78 mbit/s 78 mbit/s 0&1 0...7 0...3 0...7 table 1. line and system speed mode selection. selpdh rsel1 rsel2 ref. clock 0 0 0 0 1 1 0/1 0 1 69.632 mhz 34.816 mhz 17.408 mhz 1 1 1 0 1 1 0/1 0 1 77.76 mhz 38.88 mhz 19.44 mhz table 2. reference clock frequency selection. vcc vctl vcca 1.5k 1f ouchp vcc vctl vcca 15 1f ouchp
the transmitter - gd16591a the schematic block diagram of gd16591a is shown in figure 3 . by the select signal (csel) two different reference clock inputs can be selected (ckr0/ckr1). this allows for line timing in normal operation with a selection of a separate reference when the received line input data is flawed. thus, allowing forwarding alarm status in the event of a loss of received data. forward clocking co-directional timing for input data is pro - vided. the phase can with the select pins psel1-2 be set to 0 /90 / 180 / 270 dif - ference between data input sampling and reference clock (ckr0/ckr1). when forward clocking, the frequency of the reference clock must be identical to the input data bit rate. i.e. for 78(70) mbit/s use 78(70) mhz ref - erence clock, and for 19(17) mbit/s use 19(17) mhz reference clock. refer to ac characteristics on page 12 . counter clocking in addition, contra directional timing is provided. the phase between input and ckout is adjustable with (0 /90 /180 / 270 ). refer to ac characteristics on page 12 . ckout is kept synchronous to the refer- ence clock by the phase frequency comparator (pfc). outputs the outputs from the multiplexer is fed to differential lvpecl output stages. see figures 4 and 5 for output temination. the serial data output (sop/son) are accompanied by a serial clock output (cop/con). see timing data on page 12. slsop/slson is enabled when slb is low. when slb is high (e.g. by internal pull-up resistor) slso p=0and slson = 1; thus avoiding noise injection at normal operation. figure 3. the gd16591a multifunction transmitter. figure 4. lvpecl output termination, ac-coupled. figure 5. lvpecl output termination, dc-coupled. data sheet rev.: 14 gd16591a/gd16592a page 3 of 16 phase adjust 0 /90 180 /270 oo oo clock gen. mux vco divide by 1/2/4 pfc vu u ld rd d id0 dsel1 psel1 dsel2 psel2 llcip llsip llcin llsin llb slb id7 selpdh vctl seltck rsel1 ckr0 ckr1 csel rsel2 sop slsop cop son slson con ckout vcc vcca gnd gnda ouchp 180 50 180 100nf 100nf 0v ( gnd ) 2v ( vcc -1.3v ) 50 lvpecl output input lvpecl 50 1.3v ( vcc -2v ) 50 lvpecl output input lvpecl
the receiver - gd16592a the schematic block diagram of gd16592a is shown in figure 6 . lock detect circuit the lock detect circuit continuously moni - tors the frequency difference between the reference clock and the divided vco clock. if the reference clock and the di - vided vco frequency differs by more than 500 ppm (or 2000 ppm, selectable), it switches the pfc into the pll in order to pull the vco back inside the lock-in range. this mode is called the acquisi - tion mode . the pfc is used to ensure predictable lock up conditions for the gd16592a by locking the vco to an external reference clock source. it is only used during acqui - sition and pulls the vco into the lock range where the bang-bang phase de - tector is capable of acquiring lock to in - coming data. the pfc is made with digital set/reset cells giving it a true phase and frequency characteristic. once the vco is inside the lock-range the lock-detection circuit switches the bang-bang phase detector into the pll in order to lock to the data signal. this mode is called cdr mode . figure 6. the gd16592a multifunction receiver. bang-bang phase detector the bang-bang phase detector is used in cdr mode as a true digital type de - tector, producing a binary output. it sam - ples the incoming data twice each bit period: once in the transition of the (pre - vious) bit period and once in the middle of the bit period. when a transition oc - curs between 2 consecutive bits - the value of the sample in the transition be - tween the bits will show whether the vco clock leads or lags the data. hence the pll is controlled by the bit transition point, thereby ensuring that data is sam - pled in the middle of the eye, once the system is in cdr mode. the external loop filter components control the chara - cteristics of the pll. the binary output of either the pfc or the bang-bang phase detector (depend - ing of the mode of the lock-detection cir - cuit) is fed to a charge pump capable of sinking or sourcing current or tristating. the output of the charge pump is filtered through the loop filter and controls the tuning-voltage of the vco. as a result of the continuous monitoring lock-detect circuit the vco frequency never deviates more than 500 ppm (2000 ppm) from the reference clock be- fore the pll is considered to be ? out of lock ? . hence the acquisition time is pre- dictable and short and the output clock ckout is always kept within the 500 ppm (2000 ppm) limits, ensuring safe clocking of down stream circuitry. the lock signal the status of the lock-detection circuit is given by the lock signal. in cdr mode lock is steady high. in acquisition mode lock is alternating indicating the con - tinuous shifts between the bang-bang detector (high) and the pfc (low). the lock output may be used to gener - ate a pseudo loss of signal (los). the time for lock to assert is predictable and short, equal to the time to go into lock, but the time for lock to de-assert must be considered. when the line is down (i.e. no information received) the optical receiver circuit may produce ran - dom noise. it is possible that this random noise will keep the gd16592a within the 500 ppm (2000 ppm) range of the line frequency, hence lock will remain as - serted for a non-deterministic time. this may be prevented by injecting a small current at the loop filter node, which ac - tively pulls the pll out of the lock range when the output of the phase detector acts randomly. the negligible penalty paid is a static phase error on the sampling time in the decision gate. however, due to the na- ture of the phase detector the error will be small (few degrees), forcing the loop to be at one edge of the error-function shaped transfer characteristic of the de- tector. inputs the input amplifier (pin sip / sin) is de - signed as a limiting amplifier with a sen - sitivity of 10 mv (differential). standard lvpecl levels may be applied as well. the inputs may be either ac or dc cou - pled. if the inputs are ac coupled the amplifier features an internal offset can - celling dc feedback. notice that the off - set cancellation will only work when the input is differential and ac-coupled as shown in the figures 7 and 8 on page 5 . the serial input slsip/slsin is selected when slb is low. outputs the ckout provides the necessary con - trol for clocking the received data into the system asic. the phase can be ad - justed with psel1-2 (0 /90 /180 /270 ). data sheet rev.: 14 gd16591a/gd16592a page 4 of 16 demux bang bang phase detector vco divide by 1/2/4 pfc dsel1 psel1 rsel1 rsel1 slb dsel2 psel2 llb llsop llcop llson llcon selpdh sin slsin sip slsip vctl seltck ckrf ouchp vcca vcc gnda gnd lock lsel2 lsel1 ckout od7 od0 divide by 4 lock detect clock gen. phase adjust. 0 /90 180 /270 oo oo
figure 7. ac coupled input (using internal offset compensation). figure 8. dc coupled input (ignoring internal offset compensation). v tt depends on the termination requirements of the previous stage, and the resulting ampli- tude on the input. practical considerations the pcb must be designed with shortest possible conductors for the signals to the line interfaces. these connections should be designed as transmission lines. de-coupling capacitors should be applied to each power supply pin. care should be taken to reduce ground bounce. the line loop signal and clock must be terminated close to the transmitter device (gd16591a). the system loop signal must be termi - nated close to the receiver device (gd16592a). data sheet rev.: 14 gd16591a/gd16592a page 5 of 16 50 50 100nf 8 k 8k 100nf 100nf 100nf sip sin lia + - vtt 50 50 8 k 8k sip sin lia + -
pin list, gd16591a - transmitter mnemonic: pin no.: pin type : description: ckr0, ckr1 csel 38, 40 39 lvttl in reference clock inputs selectable by csel. usable for forward clocking (co-directional timing), see ac-characteristics on page 12 . the ckrx input must be noise free, since noise injected here passes onto the line. the fre - quency is determined by rsel1-2. maximum frequency is 78 mhz. csel=0 => ckr0; csel=1 =>ckr1 id0..id7 31, 29, 28, 22, 21, 19, 18, 17 lvttl in data input port to mux. see dsel1-2 for bit use. id0 is the first bit transmit - ted. see psel1-2 for timing. dsel1, dsel2 27, 26 lvttl in dsel1 dsel2 line speed system speed used bit 0 0 155 mbit/s 78 mbit/s 0 & 1 0 1 155 mbit/s 19 mbit/s 0 .. 7 1 0 311 mbit/s 78 mbit/s 0 .. 3 1 1 622 mbit/s 78 mbit/s 0 .. 7 selpdh 1 lvttl in pdh(e4) mode select: 0 line speeds 140 or 280 mbit/s 1 line speeds 155, 311, or 622 mbit/s selpdh is used as test clock input when seltck is low. rsel1, rsel2 35, 34 lvttl in reference clock frequency select: rsel1 rsel2 ckref (mhz) 0 0/1 77.76 1 0 38.88 1 1 19.44 psel1, psel2 42, 41 lvttl in idx input phase versus ckout/ckrx select: (note 2) psel2 psel1 00 t del =0 01 t del =90 10 t del = 180 11 t del = 270 seltck 47 lvttl in connect to vcc. used for test purpose (selects selpdh as test clock when low). llb 25 lvttl in line loop-back, enabled when low. slb 3 lvttl in system loop-back, enabled when low. llsip, llsin 16, 15 lvpecl in line loop-back serial differential data. connect to llsop/llson of gd16592a . llcip, llcin 14, 13 lvpecl in line loop-back serial differential clock. connect to llcop/llcon of gd16592a. ckout 32 lvttl out 77.76 mhz /19.44 mhz output clock. usable for counter clocking (contra- directional timing) . slsop, slson 10, 9 lvpecl out system loop-back serial differential data. connect and terminate close to slsip/slsin of gd16592a. sop, son 5, 4 lvpecl out differential data output from mux. sop is true output, son is inverted. cop, con 8, 7 lvpecl out differential clock output from mux. vctl 45 analog in vco control voltage input. connect to ouchp and terminate with 1 k in series with 1 f to vcca. ouchp 43 analog out charge pump output. vcc 2, 11, 20, 23, 30, 37 pwr +3.3 v power for core and i/o. vcca 44 pwr +3.3 v power for vco. gnd 6, 12, 24, 33, 36, 48 gnd 0 v power for core and i/o. gnda 46 gnd 0 v power for vco. heat sink connected to gnd. note 1: only standard line speeds for sdh/sonet applications are indicated. for pdh (e4) usage, corresponding values apply, i.e. substitute 19 mhz clock with 17 mhz, 78 mhz with 70 mhz, 155 mbit/s with 140 mbit/s, 311 mbit/s with 280 mbit/s. note 2: when forward clocking, the frequency of the reference clock must be identical to the input data bit rate. data sheet rev.: 14 gd16591a/gd16592a page 6 of 16
pin list, gd16592a - receiver mnemonic: pin no.: pin type: description: ckrf 32 lvttl in reference clock input (19 / 39 / 78 mhz), determined by rsel1, rsel2. dsel1, dsel2 39, 38 lvttl in dsel1 dsel2 line speed system speed used bit 0 0 155 mbit/s 78 mbit/s 0 & 1 0 1 155 mbit/s 19 mbit/s 0 .. 7 1 0 311 mbit/s 78 mbit/s 0 .. 3 1 1 622 mbit/s 78 mbit/s 0 .. 7 selpdh 1 lvttl in active low, pdh(e4) mode select: 0 line speeds 140 or 280 mbit/s 1 line speeds 155, 311, or 622 mbit/s selpdh is used as test clock input when seltck is low. rsel1, rsel2 3, 34 lvttl in rsel1 rsel2 reference clock frequency select: 0 0/1 ckrf = 78 mhz 1 0 ckrf = 38 mhz 1 1 ckrf = 19 mhz lsel1, lsel2 10, 9 lvttl in lsel1 lsel2 lock select inputs for clock and data recovery set-up. 0 0 manual, phase freq. comp. (pfc) 0 1 manual, phase detect (bb) 1 0 auto lock, 2000 ppm 1 1 auto lock, 500 ppm ( default, when not connected ) seltck 47 lvttl in connect to vcc. test purpose (selects selpdh as test clock when low). llb 41 lvttl in line loop-back, enabled when low. slb 40 lvttl in system loop-back, enabled when low. psel1, psel2 25, 35 lvttl in psel2 psel1 odx output phase versus ckout select: 00 t del =0 01 t del =90 10 t del = 180 11 t del = 270 sip, sin 4, 5 analog in differential serial data input. slsip, slsin 7, 8 lvpecl in system loop-back serial differential data. connect to slsop/n of gd16591a. ckout 29 lvttl out regenerated output clock (77.76 / 19.44 mhz). used for odx timing. od0...od7 28, 27, 26, 22, 21, 19, 18, 17 lvttl out re-timed data output from demux. see dsel1-2 for bit use. od0 is the first bit received. see psel1-2 for timing. llsop, llson 13, 14 lvpecl out line loop-back serial differential data. connect and terminate close to llsip/llsin of gd16591a. llcop, llcon 15, 16 lvpecl out line loop-back serial differential clock. connect and terminate close to llcip/llcin of gd16591a. lock 42 lvttl out high level indicates pll locked to incoming data signal. low level indicates pll out of lock. vctl 45 analog in vco control voltage input. connect to ouchp and terminate with 22 in series with 1 f to vcca. ouchp 43 analog out charge pump output for pll. vcc 2, 11, 20, 23, 30, 37 pwr +3.3 v power for core and i/o. vcca 44 pwr +3.3 v power for vco. gnd 6, 12, 24, 33, 36, 48 gnd 0 v power for core and i/o. gnda 46 gnd 0 v power for vco. nc 31 nc not connected. heat sink connected to gnd. note: only standard line speeds for sdh/sonet applications are indicated. for pdh (e4) usage, corresponding values apply, i.e. substitute 19 mhz clock with 17 mhz, 78 mhz with 70 mhz, 155 mbit/s with 140 mbit/s, 311 mbit/s with 280 mbit/s. data sheet rev.: 14 gd16591a/gd16592a page 7 of 16
package pinouts figure 9. gd16591a, package 48 pin tqfp - top view. figure 10. gd16592a, package 48 pin tqfp - top view. data sheet rev.: 14 gd16591a/gd16592a page 8 of 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 24 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd seltck gnda vctl vcca ouchp psel1 psel2 ckr1 csel ckr0 vcc gnd rsel1 rsel2 gnd ckout id0 vcc id1 id2 dsel1 dsel2 llb vcc gnd id3 id4 vcc id5 id6 id7 llsip llsin llcip llcin gnd vcc slsop slson cop con gnd sop son slb vcc selpdh 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 24 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd seltck gnda vctl vcca ouchp lock llb slb dsel1 dsel2 vcc gnd psel2 rsel2 gnd ckrf nc vcc ckout od0 od1 od2 psel1 vcc gnd od3 od4 vcc od5 od6 od7 llcon llcop llson llsop gnd vcc lsel1 lsel2 slsin slsip gnd sin sip rsel1 vcc selpdh
maximum ratings these are the limits beyond which the component may be damaged. all voltages in the table are referred to gnd. all currents in the table are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit.: v cc, v cca supply voltage 0 6 v v 0 max output voltage -0.5 v cc +0.5 v i 0 max, lvpecl output current 30 ma i 0 max, vctl output current 0.5 ma i oo, lvttl lvttl output source current 24 ma i oi, lvttl lvttl output sink current -24 ma v i max input voltage -0.5 v cc +0.5 v i i max input current -1.0 1.0 ma t 0 operating temperature junction -55 125 c t s storage temperature -65 150 c v esd electro static discharge voltage note 1 500 v note1: according to mil std. 883, method 3015, human body model. thermal characteristics the worst case thermal resistance from junction to ambient is ja =75 c/w in still air, using a low conductivity board (2 layers) according to jedec standard jesd51.3. when using a low conductivity board with no air flow it is recommended that the heat sink is soldered to the board, and that the board is a multilayer. data sheet rev.: 14 gd16591a/gd16592a page 9 of 16
dc characteristics t ambient = -25 o cto85 o c. all voltages in the table are referred to gnd . all input signal and power currents in the table are defined positive into the pin. all output signal currents are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit: v cc ,v cca positive supply voltage 3.1 3.3 3.6 v i cc,gd16591a positive supply current (gd16591a) note 1 105 130 ma i cc,gd16592a positive supply current (gd16592a) note 1 135 160 ma v sin,sip data input voltage swing, differential note 5 10 1400 mv p-p v icm, lvpecl lvpecl input common mode voltage v cc -1.5 v cc -1.1 v v idiff, lvpecl lvpecl input differential voltage 0.25 0.5 1.4 v i i, lvpecl lvpecl input current -100 100 a v oh, lvpecl lvpecl output hi voltage note 2 v cc -1.2 v cc -0.6 v v ol, lvpecl lvpecl output lo voltage note 2 v cc -2.0 v cc -1.6 v v odiff, lvpecl lvpecl output differential voltage note 2 0.6 1.1 v v ih, lvttl lvttl input hi voltage note 3, 4 2.0 v cc v v il, lvttl lvttl input lo voltage note 3, 4 0.0 0.8 v i ih, lvttl lvttl input hi current note 3, 4 100 a i il, lvttl lvttl input lo current note 3, 4 -500 a v oh, lvttl lvttl output hi voltage i oh = 3 ma, note 4, 6 v cc -1.1 v v ol, lvttl lvttl output lo voltage i ol = -1 ma, note 4 0 0.5 v note 1: power: 0.8 x p typ ac characteristics - general t ambient = -25 cto+85 c. symbol: characteristic: conditions: min.: typ.: max.: unit: ftr sdh sdh tuning range relative to center frequency note 1 98 102 % ftr pdh pdh tuning range relative to center frequency note 1 97 101 % t r-lvpecl lvpecl output rise time note 2 270 500 ps t f-lvpecl lvpecl output fall time note 2 200 500 ps t r-lvttl lvttl output rise time note 3 0.8 1 ns t f-lvttl lvttl output fall time note 3 0.8 1 ns dc ckout duty cycle, ckout @ 78 mhz note 4 40 50 60 % note 1: the frequency tuning range may be larger. the minimum/maximum values define the worst case range of the vco at temperature and power extremes. note 2: 20-80%,50 to v cc -2.0 v. note 3: 20 - 80 %, 10 pf. the 20 - 80 % rise and fall times are 2 ns (maximum) with 20 pf load. note 4: measured at v th = 1.4 v, 10 pf. data sheet rev.: 14 gd16591a/gd16592a page 11 of 16
ac characteristics - gd16591a t ambient = -25 cto+85 c. forward clocking counter clocking data sheet rev.: 14 gd16591a/gd16592a page 12 of 16 ckrx (78 mhz) ckrx (39 mhz) ckrx (19 mhz) ckout (19 mhz) t rc t rc19 ckout (78 mhz) ckout (78 mhz) idx(0 ) o t sa t sb t sc t hc t sd t ha t hb t hd idx(90 ) o idx(180 ) o idx(270 ) o cop sop/son slsop/n t co t slco intrinsic vco jitter generation gd16591a frequency range: period [s] jitter: [uip-p] pdh e4 200 hz - 3.5 mhz 10 0.05 stm-1 / oc-3 (cmi) 500 hz - 1.3 mhz 60 0.05 stm-1 / oc-3 (optical) 100 hz - 1.3 mhz 60 0.1 stm-4 / oc-12 1000 h z - 5 mhz 60 0.05 maximum allowed rms jitter on reference clocks inputs line rate ref. clk. frq. 622 mbit/s 311 mbit/s 155 mbit/s 78 mhz 13 ps 26 ps 52 ps 39mhz 9ps 18ps 36ps 19mhz 5ps 10ps 20ps 3 db - pll bw (note 1) 12 500 khz 12 250 khz 12 125 khz note 1: measure the rms jitter on the reference clock within the 3 db pll bandwidth used for the actual line rate. note 2: adding the maximum allowed jitter on the reference clock inputs the resulting output jitter will meet the standard recommendations (itu-t g.751, g.813, g.952, and de/tm-3017-4). t se t sf t sg t hg t sh t he t hf t hh ckout (19/78 mhz) idx(0 ) o idx(90 ) o idx(180 ) o idx(270 ) o
ac characteristics - gd16591a - continued t ambient = -25 cto+85 c. symbol: characteristic: conditions: min.: typ.: max.: unit: t co cop (falling edge) to sop/son valid 100 200 400 ps t slco cop (falling edge) to slsop/n valid 100 200 400 ps t sll llsip/n set-up time before llcip falling edge 500 ps t hll llsip/n hold time after llcip falling edge 50 ps t sa idx set-up time before ckrx rising edge note 5 3.5 ns t sb idx set-up time after ckrx rising edge note 1, 5 t/4 - 3.5 ns t sc idx set-up time after ckrx rising edge note 1, 5 t/2 - 3.5 ns t sd idx set-up time after ckrx rising edge note 1, 5 3 t/4 - 3.5 ns t ha idx hold time after ckrx rising edge note 5 2.5 ns t hb idx hold time after ckrx rising edge note 1, 5 t/4 + 2.5 ns t hc idx hold time after ckrx rising edge note 1, 5 t/2 + 2.5 ns t hd idx hold time after ckrx rising edge note 1, 5 3 t/4+2.5 ns t rc delay from ckrx rising edge to ckout falling edge 78 mhz, 5 pf load 2.5 3.5 4.5 ns t rc19 delay from ckrx rising edge to ckout falling edge 19 mhz, 5 pf load note 6 12 13 14 ns pw hi, ckrx high pulse width, ckrx inputs note 2 3 ns t se idx set-up time before ckout falling edge note 3 t rc + 3.5 ns t sf idx set-up time after ckout falling edge note 1, 3 t/4- t rc -3.5 ns t sg idx set-up time after ckout falling edge note 1, 3 t/2- t rc -3.5 ns t sh idx set-up time after ckout falling edge note 1, 3 3 t/4- t rc -3.5 ns t he idx hold time before ckout falling edge note 3 t rc -2.5 ns t hd idx hold time after ckout falling edge note 1, 3 t/4- t rc +2.5 ns t hf idx hold time after ckout falling edge note 1, 3 t/2- t rc +2.5 ns t hg idx hold time after ckout falling edge note 1, 3 3 t/4- t rc +2.5 ns jt jitter transfer note 4 0.0 0.1 db note 1: t equals the period time for ckout, which is the bit period for the parallel data; i.e. 12.9 ns for 78 mbit/s or 51.4 ns for 19 mbit/s. note 2: measured at v th = 1.4 v. it is the rising edge, which is used for the timing and frequency comparison. the 20% - 80% rise time should be less than 1 ns to minimise jitter at the reference clock inputs. note 3: set-up and hold times with respect to the delay t rc . note 4: pll 3 db bandwidth 12 khz to n 125 khz for stm-n. peaking and bandwidth depends on actual loop filter values. note 5: valid for 78 mhz forward clocking. for 19 mhz forward clocking the setup and hold windows are delayed 9.6 ns. note 6: t rc19 is actually t rc + 9.6 ns. data sheet rev.: 14 gd16591a/gd16592a page 13 of 16
ac characteristics - gd16592a t ambient = -25 cto+85 c. symbol: characteristic: conditions: min.: typ.: max.: unit: t llco llcop to llsop/n valid 100 200 400 ps t a ckout to odx valid note 3 0 1 ns t b ckout to odx valid note 1, 3 t/4 t/4+1 ns t c ckout to odx valid note 1, 3 t/2 t/2+1 ns t d ckout to odx valid note 1, 3 3 t/4 3 t/4+1 ns t acquisition acquisition time transition density = 0.5 25 s cid consecutive indentical digits # bits without transition 250 d ckrf ckrf frequency deviation from nominal line frequency 200 ppm jt jitter transfer note 2 0.0 0.1 db note 1: t equals the period time for ckout, which is the bit period for the parallel data; i.e. 12.9 ns for 78 mbit/s or 51.4 ns for 19 mbit/s. note 2: pll 3 db bandwidth 12 khz to 500 khz; n 125 khz for stm-n. peaking and bandwidth depends on actual loop filter values. note 3: 10 pf load at ckout and odx outputs. data sheet rev.: 14 gd16591a/gd16592a page 14 of 16 a1 [ui] a2 f2 f3 f4 [hz] f1 jitter tolerance gd16592a f1 [hz] f2 [hz] f3 [hz] f4 [hz] a1 [ui p-p ] a2 [ui p-p ] pdh e4 200 500 10k 3.5m 2 0.15 stm-1 / oc-3 (cmi) 500 3.25k 65k 1.3m 2 0.15 stm-1 / oc-03 (optical) 500 6.5k 65k 1.3m 2 0.2 stm-4 / oc-12 300 25k 250k 2.5m 2 0.2 note: the stated jitter tolerance of gd16592a exceeds the stan- dard recommendations (itu-t g.823, g.825, and de/tm-03067). ck o ut (19/78 mhz) (0 ) o t a t b t c t d (90 ) o (180 ) o (270 ) o odx odx odx odx llcop llsop/n t llco
package outline figure 11. package 48 pin edquad tqfp (7x7x1.4 mm). external references gd90591/592 : data sheet for the evaluation board for the gd16591a/gd16592a chip set. itu-t g.751 (11/88) : digital multiplex equipments operating at the third order bit rate of 34368 kbit/s. itu-t g.813 (8/96) : timing characteristics of sdh equipment slave clocks. itu-t g.823 (3/93) : the control of jitter and wander within digital networks based on the 2048 kbit/s hierarchy. itu-t g.825 (3/93) : the control of jitter and wander within digital networks based on sdh. itu-t g. 958 (11/94) : digital line system based on the sdh for use on optical fibre channels. de/tm-3017-4 (draft) : transmission and multiplexing; generic requirements for synchronisation networks. de/tm-03067 (draft) : transmission and multiplexing; the control of jitter and wander in transport networks. mil std. 883 (3/89) : method 3015, human body model. jedec jesd51 (12/95) : methology for the thermal measurement of component packages (single semiconductor device) jedec jesd51.3 (8/96) : low effective thermal conductivity test boards for leaded surface mount packages. data sheet rev.: 14 gd16591a/gd16592a page 15 of 16
device marking figure 12. device marking - gd16591a. top view. figure 13. device marking - gd16592a. top view. gd16591a/gd16592a, data sheet rev.: 14 - date: 16 may 2001 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.giga.dk please check our internet web site for latest version of this data sheet. distributor: copyright ? 2001 giga aps an intel company all rights reserved an intel company ordering information to order, please specify as shown below: product name: type: package type: ambient temperature range: GD16591A-48BA transmitter edquad tqfp , 48 pin -25...85 c gd16592a-48ba receiver edquad tqfp , 48 pin -25...85 c gd16591a - - pin 1 - mark gd16592a - - pin 1 - mark

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