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october 2006 rev 4 1/64 1 m50flw080a m50flw080b 8-mbit (13 x 64-kbyte blocks + 3 16 4 kbyte sectors) 3-v supply, firmware hub / low-pin-count flash memory feature summary flash memory ? compatible with either the lpc interface or the fwh interface (intel spec rev1.1) used in pc bios applications ? 5-signal communication interface supporting read and write operations ? 5 additional general-purpose inputs for platform design flexibility ? synchronized with 33 mhz pci clock 16 blocks of 64 kbytes ? 13 blocks of 64 kbytes each ? 3 blocks, subdivided into 16 uniform sectors of 4 kbytes each two blocks at the top and one at the bottom (m50flw080a) one block at the top and two at the bottom (m50flw080b) enhanced security ? hardware write protect pins for block protection ? register-based read and write protection ? individual lock register for each 4 kbyte sector supply voltage ?v cc = 3.0 to 3.6 v for program, erase and read operations ?v pp = 12 v for fast program and erase two interfaces ? auto detection of firmware hub (fwh) or low pin count (lpc) memory cycles for embedded operation with pc chipsets ? address/address multiplexed (a/a mux) interface for programming equipment compatibility. programming time: 10 s typical program/erase controller ? embedded program and erase algorithms ? status register bits program/erase suspend ? read other blocks/sectors during program suspend ? program other blocks/sectors during erase suspend electronic signature ? manufacturer code: 20h ? device code (m50flw080a): 80h ? device code (m50flw080b): 81h packages ? ecopack? (rohs compliant) tsop32 (nb) 8 14 mm plcc32 (k) tsop40 (n) 10 20 mm www.st.com
contents m50flw080a, m50flw080b 2/64 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 firmware hub/low-pin-count (fwh/lpc) signal descriptions . . . . . . . . . 13 2.1.1 input/output communications (fwh0/lad0-fwh3/lad3) . . . . . . . . . . 13 2.1.2 input communication frame (fwh4/lframe ) . . . . . . . . . . . . . . . . . . . 13 2.1.3 identification inputs (id0-id3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.4 general-purpose inputs (gpi0-gpi4) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.5 interface configuration (ic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.6 interface reset (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.7 cpu reset (init ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.8 clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.9 top block lock (tbl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.10 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.11 reserved for future use (rfu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 address/address multiplexed (a/a mux) si gnal descriptions . . . . . . . . . . 15 2.2.1 address inputs (a0-a10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.2 data inputs/outputs (dq0-dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.4 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.5 row/column address select (rc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 supply signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.1 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 v pp optional supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.3 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 firmware hub/low-pin-count (fwh/lpc) bus operations . . . . . . . . . . . . 17 3.1.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.3 bus abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.6 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
m50flw080a, m50flw080b contents 3/64 3.2 address/address multiplexed (a/a mux) bus operations . . . . . . . . . . . . . 19 3.2.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.3 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 read memory array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 quadruple byte program command (a/a mu x interface) . . . . . . . . . . . . . 27 4.6 double/quadruple byte program command (fwh mode) . . . . . . . . . . . . 27 4.7 chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.8 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.9 sector erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.11 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.12 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 program/erase controller status (bit sr7) . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 erase suspend status (bit sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 erase status (bit sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 program status (bit sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 v pp status (bit sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6 program suspend status (bit sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 block/sector protection status (bit sr1) . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.8 reserved (bit sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 firmware hub/low-pin-c ount (fwh/lpc) interface configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 lock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.1 write lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.2 read lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
contents m50flw080a, m50flw080b 4/64 6.1.3 lock down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 firmware hub/low-pin-count (fwh/lpc) general-purpose input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 manufacturer code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 program and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 appendix a block and sector address ta ble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 appendix b flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
m50flw080a, m50flw080b list of tables 5/64 list of tables table 1. signal names (fwh/lpc interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. signal names (a/a mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. addresses (m50flw080a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. addresses (m50flw080b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. memory identification input configuration (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. fwh bus read field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. fwh bus write field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. lpc bus read field definitions (1-byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 table 9. lpc bus write field definitions (1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. a/a mux bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. configuration register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. lock register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. general-purpose input register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. program and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 21. fwh/lpc interface ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. a/a mux interface ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 23. impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 24. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 25. fwh/lpc interface clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 26. fwh/lpc interface ac signal timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 27. reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 28. a/a mux interface read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 29. a/a mux interface write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 30. plcc32 ? 32 pin rectangular plastic leaded chip carrier, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 31. tsop32 ? 32 lead plastic thin small outline, 8x14 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 32. tsop40 ? 40 lead plastic thin small outline, 10 x 20mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 33. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 34. m50flw080a block, sector and lock register addresses . . . . . . . . . . . . . . . . . . . . . . . . 52 table 35. m50flw080b block, sector and lock register addresses . . . . . . . . . . . . . . . . . . . . . . . . 54 table 36. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
list of figures m50flw080a, m50flw080b 6/64 list of figures figure 1. logic diagram (fwh/lpc interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. logic diagram (a/a mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. plcc connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. tsop32 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. tsop40 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. fwh bus read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. fwh bus write waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. lpc bus read waveforms (1-byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. lpc bus write waveforms (1 byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. fwh/lpc interface ac measurement i/o waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 11. a/a mux interface ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 13. fwh/lpc interface clock waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 figure 14. fwh/lpc interface ac signal timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 15. reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16. a/a mux interface read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17. a/a mux interface write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 18. plcc32 ? 32 pin rectangular plastic leaded chip carrier, package outline . . . . . . . . . . 48 figure 19. tsop32 ? 32 lead plastic thin small outline, 8x14 mm, package outline . . . . . . . . . . . . 49 figure 20. tsop40 ? 40 lead plastic thin small outline, 10 x 20mm, package outline . . . . . . . . . . . 50 figure 21. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 figure 22. double/quadruple byte program flowchart and pseudo code (fwh mode only). . . . . . . . 57 figure 23. quadruple byte program flowchart and pseudo code (a/a mux interface only). . . . . . . . . 58 figure 24. program suspend and resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . 59 figure 25. chip erase flowchart and pseudo code (a/a mux interface only). . . . . . . . . . . . . . . . . . . . 60 figure 26. sector/block erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 27. erase suspend and resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 62
m50flw080a, m50flw080b summary description 7/64 1 summary description the m50flw080 is a 8 mbit (1m x8) non-volatile memory that can be read, erased and reprogrammed. these operations can be performed using a single low voltage (3.0 to 3.6v) supply. for fast programming and fast erasing on production lines, an optional 12v power supply can be used to reduce the erasing and programming time. the memory is divided into 16 uniform blocks of 64 kbytes each, three of which are divided into 16 uniform sectors of 4 kbytes each (see appendix a for details). all blocks and sectors can be erased independently. so, it is possible to preserve valid data while old data is erased. blocks can be protected individually to prevent accidental program or erase commands from modifying their contents. program and erase commands are written to the command interface of the memory. an on- chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set to cont rol the memory is cons istent with the jedec standards. two different bus interfaces are supported by the memory: the primary interface, the fwh/lpc interface, uses intel?s proprietary firmware hub (fwh) and low pin count (lpc) protocol. this has been designed to remove the need for the isa bus in current pc chipsets. the m50flw080 acts as the pc bios on the low pin count bus for these pc chipsets. the secondary interface, the address/address multiplexed (or a/a mux) interface, is designed to be compatible with current flash programmers, for production line programming prior to fitting the device in a pc motherboard. in order to meet environmental requirements, st offers the m50flw080a and m50flw080b in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack specifications are available at: www.st.com . the memory is supplied with all the bits erased (set to ?1?).
summary description m50flw080a, m50flw080b 8/64 figure 1. logic diagram (fwh/lpc interface) table 1. signal names (fwh/lpc interface) fwh0/lad0-fwh3/lad3 input /output communications fwh4/lframe input communication frame id0-id3 identification inputs (id0 and id1 are reserved for future use (rfu) in lpc mode) gpi0-gpi4 general purpose inputs ic interface configuration rp interface reset init cpu reset clk clock tbl top block lock wp write protect rfu reserved for future use. leave disconnected v cc supply voltage v pp optional supply voltage for fast program and erase operations v ss ground nc not connected internally ai09229b 4 fwh4/lframe fwh0/lad0 fwh3/lad3 v cc m50flw080a m50flw080b clk v ss 4 ic rp tbl 5 init wp id0-id3 gpi0- gpi4 v pp
m50flw080a, m50flw080b summary description 9/64 figure 2. logic diagram (a/a mux interface) table 2. signal names (a/a mux interface) ic interface configuration a0-a10 address inputs dq0-dq7 data inputs/outputs g output enable w write enable rc row/column address select rp interface reset v cc supply voltage v pp optional supply voltage for fast program and erase operations v ss ground nc not connected internally ai09230b 11 rc dq0-dq7 v cc m50flw080a m50flw080b ic v ss 8 g w rp a0-a10 v pp
summary description m50flw080a, m50flw080b 10/64 figure 3. plcc connections 1. pins 27 and 28 are not internally connected. figure 4. tsop32 connections ai09231c gpi4 nc fwh4/lframe rfu 17 id1/rfu id0/rfu fwh0/lad0 fwh1/lad1 fwh2/lad2 fwh3/lad3 rfu gpi1 tbl id3 id2 gpi0 wp 9 clk v ss 1 rp v cc nc gpi2 rfu 32 v pp v cc m50flw080a m50flw080b gpi3 ic (v il ) rfu init nc 25 v ss a1 a0 dq0 a7 a4 a3 a2 a6 a5 a10 rc rp a8 v pp v cc a9 nc w v ss v cc nc dq7 ic (v ih ) g nc dq5 dq1 dq2 dq3 dq4 dq6 v ss a/a mux a/a mux a/a mux a/a mux ai09701b a1 a0 dq0 a7 a4 a3 a2 a6 a5 a9 a8 w dq7 g nc dq5 dq1 dq2 dq3 dq4 dq6 a/a mux a/a mux id1/rfu fwh1/lad1 fwh2/lad2 gpi3 tbl id2 gpi0 wp nc nc rfu gpi4 nc fwh4/lframe rfu fwh3/lad3 v ss rfu rfu clk rp v pp v cc m50flw080a m50flw080b 8 1 9 16 17 24 25 32 id3 v ss init ic nc gpi2 fwh0/lad0 gpi1 id0/rfu nc nc ic (v ih ) nc nc rc rp v pp v cc a10 v ss
m50flw080a, m50flw080b summary description 11/64 figure 5. tsop40 connections table 3. addresses (m50flw080a) block size (kbyte) address range sector size (kbyte) 64 f0000h-fffffh 16 x 4 kbytes 64 e0000h-effffh 16 x 4 kbytes 64 d0000h-dffffh 13 x 64 kbytes 64 c0000h-cffffh 64 b0000h-bffffh 64 a0000h-affffh 64 90000h-9ffffh 64 80000h-8ffffh 64 70000h-7ffffh 64 60000h-6ffffh 64 50000h-5ffffh 64 40000h-4ffffh 64 30000h-3ffffh 64 20000h-2ffffh 64 10000h-1ffffh 64 00000h-0ffffh 16 x 4 kbytes ai09232c a1 a0 dq0 a7 a4 a3 a2 a6 a5 a9 a8 w v ss v cc dq7 g nc dq5 dq1 dq2 dq3 dq4 dq6 a/a mux a/a mux id1/rfu fwh1/lad1 fwh2/lad2 gpi3 tbl id2 gpi0 wp nc v cc nc ic (v il ) rfu gpi4 nc v ss fwh4/lframe rfu fwh3/lad3 v ss v cc rfu rfu nc clk rp nc v pp v cc nc m50flw080a m50flw080b 10 1 11 20 21 30 31 40 id3 nc init nc nc gpi2 fwh0/lad0 gpi1 id0/rfu v ss nc nc nc ic (v ih ) nc nc nc nc rc rp v pp v cc nc a10 v ss v ss v cc
summary description m50flw080a, m50flw080b 12/64 table 4. addresses (m50flw080b) (1) 1. also see appendix a , table 34 and table 35 for a full listing of the block addresses. block size (kbyte) address range sector size (kbyte) 64 f0000h-fffffh 16 x 4 kbytes 64 e0000h-effffh 13 x 64 kbytes 64 d0000h-dffffh 64 c0000h-cffffh 64 b0000h-bffffh 64 a0000h-affffh 64 90000h-9ffffh 64 80000h-8ffffh 64 70000h-7ffffh 64 60000h- 6ffffh 64 50000h- 5ffffh 64 40000h- 4ffffh 64 30000h-3ffffh 64 20000h-2ffffh 64 10000h-1ffffh 16 x 4 kbytes 64 00000h-0ffffh 16 x 4 kbytes
m50flw080a, m50flw080b signal descriptions 13/64 2 signal descriptions there are two distinct bus interfaces available on this device. the active interface is selected before power-up, or during reset, using the interface configuration pin, ic. the signals for each interface are discussed in the firmware hub/low-pin-count (fwh/lpc) signal descriptions section and the address/address multiplexed (a/a mux) signal descriptions section, respectively, while the supply signals are discussed in the supply signal descriptions section. 2.1 firmware hub/low-pin-count (fwh/lpc) signal descriptions please see figure 1 and ta b l e 1 . 2.1.1 input/output communicat ions (fwh0/lad0-fwh3/lad3) all input and output communications with the memory take place on these pins. addresses and data for bus read and bus write operations are encoded on these pins. 2.1.2 input communication frame (fwh4/lframe ) the input communication frame (fwh4/lframe ) signal indicates the start of a bus operation. when input communication frame is low, v il , on the rising edge of the clock, a new bus operation is initiated. if input communication frame is low, v il , during a bus operation then the operation is aborted. when input communication frame is high, v ih , the current bus operation is either proceeding or the bus is idle. 2.1.3 identificatio n inputs (id0-id3) up to 16 memories can be addressed on a bus, in the firmware hub (fwh) mode. the identification inputs allow each device to be given a unique 4-bit address. a ?0? is signified on a pin by driving it low, v il , or leaving it floating (since there is an internal pull-down resistor, with a value of r il ). a ?1? is signified on a pin by driving it high, v ih (and there will be a leakage current of i li2 through the pin). by convention, the boot memory must have address ?0000?, and all additional memories are given addresses, allocated sequentially, from ?0001?. in the low pin count (lpc) mode, the identification inputs (id2-id3) can address up to 4 memories on a bus. in the lpc mode, the id0 and id1 signals are reserved for future use (rfu). the value on address a20-a21 is compared to the hardware strapping on the id2- id3 lines to select the memory that is being addressed. for an address bit to be ?1?, the corresponding id pin can be left floating or driven low, v il (again, with the internal pull- down resistor, with a value of r il ). for an address bit to be ?0?, the corresponding id pin must be driven high, v ih (and there will be a leakage current of i li2 through the pin, as specified in ta bl e 2 4 ). for details, see ta b l e 5 .
signal descriptions m50flw080a, m50flw080b 14/64 2.1.4 general-purpose inputs (gpi0-gpi4) the general purpose inputs can be used as di gital inputs for the cpu to read, with their contents being available in the general purpose inputs register. the pins must have stable data throughout the entire cycle that reads the general purpose input register. these pins should be driven low, v il, or high, v ih , and must not be left floating. 2.1.5 interface configuration (ic) the interface configuration input selects whether the fwh/lpc interface or the address/address multiplexed (a/a mux) interface is used. the state of the interface configuration, ic, should not be changed during operation of the memory device, except for selecting the desired interface in the period before power-up or during a reset. to select the fwh/lpc interface, the interface configuration pin should be left to float or driven low, v il . to select the address/address multiplexed (a/a mux) interface, the pin should be driven high, v ih . an internal pull-down resistor is included with a value of r il ; there will be a leakage current of i li2 through each pin when pulled to v ih . 2.1.6 interface reset (rp ) the interface reset (rp ) input is used to reset the device. when interface reset (rp ) is driven low, v il , the memory is in reset mode (the outputs go to high impedance, and the current consumption is minimized). when rp is driven high, v ih , the device is in normal operation. after exiting reset mode, the memory enters read mode. 2.1.7 cpu reset (init ) the cpu reset, init , signal is used to reset the device when the cpu is reset. it behaves identically to interface reset, rp , and the internal reset line is the logical or (electrical and) of rp and init . 2.1.8 clock (clk) the clock, clk, input is used to clock the signals in and out of the input/output communication pins, fwh0/lad0-fwh3/lad3. the clock conforms to the pci specification. 2.1.9 top block lock (tbl ) the top block lock input is used to prevent the top block (block 15) from being changed. when top block lock, tbl , is driven low, v il , program and erase operations in the top block have no effect, regardless of the state of the lock register. when top block lock, tbl , is driven high, v ih , the protection of the block is determined by the lock registers. the state of top block lock, tbl , does not affect the protection of the main blocks (blocks 0 to 14). for details, see appendix a . top block lock, tbl , must be set prior to a program or erase operation being initiated, and must not be changed until the operation has completed, otherwise unpredictable results may occur. similarly, unpredicta ble behavior is possible if wp is changed during program or erase suspend, and care should be taken to avoid this.
m50flw080a, m50flw080b signal descriptions 15/64 2.1.10 write protect (wp ) the write protect input is used to prevent the main blocks (blocks 0 to 14) from being changed. when write protect, wp , is driven low, v il , program and erase operations in the main blocks have no effect, regardless of the state of the lock register. when write protect, wp , is driven high, v ih , the protection of the block or sector is determined by the lock registers. the state of write protect, wp , does not affect the protection of the top block (block 15). for details, see appendix a . write protect, wp , must be set prior to a program or erase operation is initiated, and must not be changed until the operation has completed otherwise unpredictable results may occur. similarly, unpredictable behavior is possible if wp is changed during program or erase suspend, and care should be taken to avoid this. 2.1.11 reserved for future use (rfu) reserved for future use (rfu). these pins do not presently have assigned functions. they must be left disconnected, except for id0 and id1 (when in lpc mode) which can be left connected. the electrical characteristics for these signals are as described in the ? identification inputs (id0-id3) ? section. 2.2 address/address multiplexed (a/a mux) signal descriptions please see figure 2 and ta b l e 2 . 2.2.1 address inputs (a0-a10) the address inputs are used to set the row address bits (a0-a10) and the column address bits (a11-a19). they are latched during any bus operation by the row/column address select input, rc . 2.2.2 data inputs/outputs (dq0-dq7) the data inputs/outputs hold the data that is to be written to or read from the memory. they output the data stored at the selected address during a bus read operation. during bus write operations they carry the commands that are sent to the command interface of the internal state machine. the data inputs/outputs, dq0-dq7, are latched during a bus write operation. 2.2.3 output enable (g ) the output enable signal, g , controls the output buffers during a bus read operation. 2.2.4 write enable (w ) the write enable signal, w , controls the bus write operation of the command interface. 2.2.5 row/column address select (rc ) the row/column address select input selects whether the address inputs are to be latched into the row address bits (a0-a10) or the column address bits (a11-a19). the row address bits are latched on the falling edge of rc whereas the column address bits are latched on its rising edge.
signal descriptions m50flw080a, m50flw080b 16/64 2.3 supply signal descriptions the supply signals are the same for both interfaces. 2.3.1 v cc supply voltage the v cc supply voltage supplies the power for all operations (read, program, erase, etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this is to prevent bus write operations from accidentally damaging the data during power up, power down and power surges. if the program/erase controller is programming or erasing during this time, the operation aborts, and the memory contents that were being altered will be invalid. after v cc becomes valid, the command interface is reset to read mode. a 0.1f capacitor should be connected between the v cc supply voltage pins and the v ss ground pin to decouple the current surges from the power supply. both v cc supply voltage pins must be connected to the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations. 2.3.2 v pp optional supply voltage the v pp optional supply voltage pin is used to select the fast program (see the quadruple byte program command description in a/a mux interface and the double/quadruple byte program command description in fwh mode) and fast erase options of the memory. when v pp = v cc , program and erase operations take place as normal. when v pp = v pph , fast program and erase operations are used. any other voltage input to v pp will result in undefined behavior, and should not be used. v pp should not be set to v pph for more than 80 hours during the life of the memory. 2.3.3 v ss ground v ss is the reference for all the voltage measurements. table 5. memory identification input configuration (lpc mode) memory number id3 id2 a21 a20 1 (boot memory) v il or float v il or float 1 1 2v il or float v ih 10 3v ih v il or float 0 1 4v ih v ih 00
m50flw080a, m50flw080b bus operations 17/64 3 bus operations the two interfaces, a/a mux and fwh/lpc, support similar operations, but with different bus signals and timings. the firmware hub/lo w pin count (fwh/lpc) interface offers full functionality, while the address/address multiplexed (a/a mux) interface is orientated for erase and program operations. see the sections below, the firmware hub/low-pin-count (fwh/lpc) bus operations and address/address multiplexed (a/a mux) bus operations , for details of the bus operations on each interface. 3.1 firmware hub/low-pin-co unt (fwh/lpc) bus operations the m50flw080 automatically identifies the type of fwh/lpc protocol from the first received nibble (start nibble) and decodes the data that it receives afterwards, according to the chosen fwh or lpc mode. the firmware hub/low pin count (fwh/lpc) interface consists of four data signals (fwh0/lad0-fwh3/lad3), one control line (fwh4/lframe ) and a clock (clk). protection against accidental or malicious data corruption is achieved using two additional signals (tbl and wp ). and two reset signals (rp and init ) are available to put the memory into a known state. the data, control and clock signals are designed to be compatible with pci electrical specifications. the interface operates with clock speeds of up to 33mhz. the following operations can be performed using the appropriate bus cycles: bus read, bus write, standby, reset and block protection. 3.1.1 bus read bus read operations are used to read from the memory cells, specific registers in the command interface or firmware hub/low pin count registers. a valid bus read operation starts on the rising edge of the clock signal when the input communication frame, fwh4/lframe , is low, v il , and the correct start cycle is present on fwh0/lad0- fwh3/lad3. on subsequent clock cycle s the host will send to the memory: id select, address and other control bits on fwh0-fwh3 in fwh mode. type+dir address and other control bits on lad0-lad3 in lpc mode. the device responds by outputting sync data until the wait states have elapsed, followed by data0-data3 and data4-data7. see ta b l e 6 and ta b l e 8 , and figure 6 and figure 8 , for a description of the field definitions for each clock cycle of the transfer. see ta bl e 2 6 , and figure 14 , for details on the timings of the signals.
bus operations m50flw080a, m50flw080b 18/64 3.1.2 bus write bus write operations are used to write to the command interface or firmware hub/low pin count registers. a valid bus write operation starts on the rising edge of the clock signal when input communication frame, fwh4/lframe , is low, v il , and the correct start cycle is present on fwh0/lad0-fwh3 /lad3. on subsequent clock cycles the host will send to the memory: id select, address, other control bits, data0-data3 and data4-data7 on fwh0-fwh3 in fwh mode. cycle type + dir, address, other control bits, data0-data3 and data4-data7 on lad0- lad3. the device responds by outputting sync data until the wait states have elapsed. see ta b l e 7 and ta b l e 9 , and figure 7 and figure 9 , for a description of the field definitions for each clock cycle of the transfer. see ta bl e 2 6 , and figure 14 , for details on the timings of the signals. 3.1.3 bus abort the bus abort operation can be used to abort the current bus operation immediately. a bus abort occurs when fwh4/lframe is driven low, v il , during the bus operation. the device puts the input/output communication pins, fwh0/lad0-fwh3/lad3, to high impedance. note that, during a bus write operation, the command interface starts executing the command as soon as the data is fully received. a bus abort during the final tar cycles is not guaranteed to abort the command. the bus, however, will be released immediately. 3.1.4 standby when fwh4/lframe is high, v ih , the device is put into standby mode, where fwh0/lad0-fwh3/lad3 are put into a high-impedance state and the supply current is reduced to the standby level, i cc1 . 3.1.5 reset during the reset mode, all internal circuits are switched off, the device is deselected, and the outputs are put to high-impedance. the device is in the reset mode when interface reset, rp , or cpu reset, init , is driven low, v il . rp or init must be held low, v il , for t plph . the memory reverts to the read mode upon return from the reset mode, and the lock registers return to their default states regardless of their states before reset. if rp or init goes low, v il , during a program or erase operation, the operation is aborted and the affected memory cells no longer contain valid data. the device can take up to t plrh to abort a program or erase operation. 3.1.6 block protection block protection can be forced using the signals top block lock, tbl , and write protect, wp , regardless of the state of the lock registers.
m50flw080a, m50flw080b bus operations 19/64 3.2 address/address multiplexe d (a/a mux) bus operations the address/address multiplexed (a/a mux) interface has a more traditional-style interface. the signals consist of a multiplexed address si gnals (a0-a10), data signals, (dq0-dq7) and three control signals (rc , g , w ). an additional signal, rp , can be used to reset the memory. the address/address multiplexed (a/a mux) interface is included for use by flash programming equipment for faster factory programming. only a subset of the features available to the firmware hub (fwh)/low pin count (lpc) interface are available; these include all the commands but exclude the security features and other registers. the following operations can be performed using the appropriate bus cycles: bus read, bus write, output disable and reset. when the address/address multiplexed (a/a mux) interface is selected, all the blocks are unprotected. it is not possible to protect any blocks through this interface. 3.2.1 bus read bus read operations are used to read the c ontents of the memory array, the electronic signature or the status register. a valid bus read operation begins by latching the row address and column address signals into the memory using the address inputs, a0-a10, and the row/column address select rc . write enable (w ) and interface reset (rp ) must be high, v ih , and output enable, g , low, v il . the data inputs/outputs will output the value, according to the timing constraints specified in figure 16 , and ta b l e 2 8 . 3.2.2 bus write bus write operations are used to write to the command interface. a valid bus write operation begins by latching the row address and column address signals into the memory using the address inputs, a0-a10, and the row/column address select rc . the data should be set up on the data inputs/outputs; output enable, g , and interface reset, rp , must be high, v ih ; and write enable, w , must be low, v il . the data inputs/outputs are latched on the rising edge of write enable, w . see figure 17 , and ta bl e 2 9 , for details of the timing requirements. 3.2.3 output disable the data outputs are high-impedance when the output enable, g , is at v ih . 3.2.4 reset during the reset mode, all internal circuits are switched off, the device is deselected, and the outputs are put at high-impedance. the device is in the reset mode when rp is low, v il . rp must be held low, v il for t plph . if rp goes low, v il , during a program or erase operation, the operation is aborted, and the affected memory cells no longer contain valid data. the memory can take up to t plrh to abort a program or erase operation.
bus operations m50flw080a, m50flw080b 20/64 figure 6. fwh bus read waveforms table 6. fwh bus read field definitions clock cycle number clock cycle count field fwh0- fwh3 memory i/o description 1 1 start 1101b i on the rising edge of clk with fwh4 low, the contents of fwh0- fwh3 indicate the start of a fwh read cycle. 2 1 idsel xxxx i indicates which fwh flash memory is selected. the value on fwh0-fwh3 is compared to the idsel strapping on the fwh flash memory pins to select which fwh flash memory is being addressed. 3-9 7 addr xxxx i a 28-bit address is transferred, with the most significant nibble first. for the multi-byte read oper ation, the least significant bits (msize of them) are treated as don't care, and the read operation is started with each of these bits reset to 0. address lines a20-21 and a23-27 are treated as don?t care during a normal memory array access, with a22=1, but are taken into account for a register access, with a22=0. (see ta b l e 1 5 ) 10 1 msize xxxx i this one clock cycle is driven by the host to determine the number of bytes that will be transferred. m50flw080 supports: single byte transfer (0000b), 2-byte transfer (0001b), 4-byte transfer (0010b), 16-byte transfer (0100b) and 128-byte transfer (0111b). 11 1 tar 1111b i the host drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. 12 1 tar 1111b (float) o the fwh flash memory takes control of fwh0-fwh3 during this cycle. 13-14 2 wsync 0101b o the fwh flash memory drives fwh0-fwh3 to 0101b (short wait-sync) for two clock cycles, indi cating that the data is not yet available. two wait-states are always included. 15 1 rsync 0000b o the fwh flash memory drives fwh0-fwh3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 m=2n data xxxx o data transfer is two clk cycles, st arting with the least significant nibble. if multi-byte read operation is enabled, repeat cycle-16 and cycle-17 n times, where n = 2 msize . previous +1 1 tar 1111b o the fwh flash memory drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. previous +1 1tar 1111b (float) n/a the fwh flash memory floats its outputs, the host takes control of fwh0-fwh3. ai08433b clk fwh4 fwh0-fwh3 number of clock cycles start idsel addr msize tar sync data tar 117123m2
m50flw080a, m50flw080b bus operations 21/64 figure 7. fwh bus write waveforms table 7. fwh bus writ e field definitions clock cycle number clock cycle count field fwh0- fwh3 memory i/o description 1 1 start 1110b i on the rising edge of clk with fwh4 low, the contents of fwh0-fwh3 indicate the start of a fwh write cycle. 2 1 idsel xxxx i indicates which fwh flash memory is selected. the value on fwh0-fwh3 is compared to the idsel strapping on the fwh flash memory pins to select which fwh flash memory is being addressed. 3-9 7 addr xxxx i a 28-bit address is transferred, with the most significant nibble first. address lines a20-21 and a23-27 are treated as don?t care during a normal memory array access, with a22=1, but are taken into account for a register access, with a22=0. (see ta b l e 1 5 ) 10 1 msize xxxx i 0000(single byte transfer) 0001 (double byte transfer) 0010b (quadruple byte transfer). 11-18 m=2/4/8 data xxxx i data transfer is two cycles, starting with the least significant nibble. (the first pair of nibbles is that at the address with a1- a0 set to 00, the second pair with a1-a0 set to 01, the third pair with a1-a0 set to 10, and the fourth pair with a1-a0 set to 11. in double byte program the first pair of nibbles is that at the address with a0 set to 0, the second pair with a0 set to 1) previous +1 1 tar 1111b i the host drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. previous +1 1 tar 1111b (float) o the fwh flash memory takes control of fwh0-fwh3 during this cycle. previous +1 1 sync 0000b o the fwh flash memory drives fwh0-fwh3 to 0000b, indicating it has received data or a command. previous +1 1 tar 1111b o the fwh flash memory drives fwh0-fwh3 to 1111b, indicating a turnaround cycle. previous +1 1 tar 1111b (float) n/a the fwh flash memory floats its outputs and the host takes control of fwh0-fwh3. ai08434b clk fwh4 fwh0-fwh3 number of clock cycles start idsel addr msize data tar sync tar 1171m212
bus operations m50flw080a, m50flw080b 22/64 figure 8. lpc bus read waveforms (1-byte) table 8. lpc bus read field definitions (1-byte) clock cycle number clock cycle count field lad0- lad3 memory i/o description 1 1 start 0000b i on the rising edge of clk with lframe low, the contents of lad0-lad3 must be 0000b to indicate the start of a lpc cycle. 21 cyctype + dir 0100b i indicates the type of cycle and selects 1-byte reading. bits 3:2 must be 01b. bit 1 indicates the direction of transfer: 0b for read. bit 0 is don?t care. 3-10 8 addr xxxx i a 32-bit address is transferred, with the most significant nibble first. a23-a31 must be set to 1. a22=1 for memory access, and a22=0 for register access. ta b l e 5 shows the appropriate values for a21-a20. 11 1 tar 1111b i the host drives lad0-lad3 to 1111b to indicate a turnaround cycle. 12 1 tar 1111b (float) o the lpc flash memory takes control of lad0-lad3 during this cycle. 13-14 2 wsync 0101b o the lpc flash memory drives lad0-lad3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. two wait-states are always included. 15 1 rsync 0000b o the lpc flash memory drives lad0-lad3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 2 data xxxx o data transfer is two clk cycles, starting with the least significant nibble. 18 1 tar 1111b o the lpc flash memory drives lad0-lad3 to 1111b to indicate a turnaround cycle. 19 1 tar 1111b (float) n/a the lpc flash memory floats its outputs, the host takes control of lad0-lad3. ai04429 clk lframe lad0-lad3 number of clock cycles start cyctype + dir addr tar sync data tar 1182322
m50flw080a, m50flw080b bus operations 23/64 figure 9. lpc bus write waveforms (1 byte) table 9. lpc bus write field definitions (1 byte) clock cycle number clock cycle count field lad0- lad3 memory i/o description 1 1 start 0000b i on the rising edge of clk with lframe low, the contents of lad0-lad3 must be 0000b to indicate the start of a lpc cycle. 21 cyctype + dir 011xb i indicates the type of cycl e. bits 3:2 must be 01b. bit 1 indicates the direction of transfer: 1b for write. bit 0 is don?t care (x). 3-10 8 addr xxxx i a 32-bit address is transferred, with the most significant nibble first. a23-a31 must be set to 1. a22=1 for memory access, and a22=0 for register access. ta bl e 5 shows the appropriate values for a21-a20. 11-12 2 data xxxx i data transfer is two cycles, starting with the least significant nibble. 13 1 tar 1111b i the host drives lad0-lad3 to 1111b to indicate a turnaround cycle. 14 1 tar 1111b (float) o the lpc flash memory takes control of lad0- lad3 during this cycle. 15 1 sync 0000b o the lpc flash memory drives lad0-lad3 to 0000b, indicating it has received data or a command. 16 1 tar 1111b o the lpc flash memory drives lad0-lad3 to 1111b, indicating a turnaround cycle. 17 1 tar 1111b (float) n/a the lpc flash memory floats its outputs and the host takes control of lad0-lad3. ai04430 clk lframe lad0-lad3 number of clock cycles start cyctype + dir addr data tar sync tar 1182212
bus operations m50flw080a, m50flw080b 24/64 table 10. a/a mux bus operations operation g w rp v pp dq7-dq0 bus read v il v ih v ih don't care data output bus write v ih v il v ih v cc or v pph data input output disable v ih v ih v ih don't care hi-z reset v il or v ih v il or v ih v il don't care hi-z
m50flw080a, m50flw080b command interface 25/64 4 command interface all bus write operations to the device are interpreted by the command interface. commands consist of one or more sequential bus write operations. an internal program/erase controller handles all timings, and verifies the correct execution of the program and erase commands. the program/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface reverts to the read mode when power is first applied, or when exiting from reset. command sequences must be followed exactly. any invalid combination of commands will be ignored. see ta bl e 1 1 for the available command codes. the following commands are the basic commands used to read from, write to, and configure the device. the following text descriptions should be read in conjunction with ta bl e 1 3 . 4.1 read memory array command the read memory array command returns the device to its read mode, where it behaves like a rom or eprom. one bus write cycle is required to issue the read memory array command and return the device to read mode. once the command is issued, the device remains in read mode until another command is issued. from read mode, bus read operations access the memory array. if the program/erase controller is executing a program or erase operation, the device will not accept any read memory array commands until the operation has completed. for a multibyte read, in the fwh mode, the address, that was transmitted with the command, will be automatically a ligned, according to the msize granularity. for example, if msize=7, regardless of any values that are prov ided for a6-a0, the firs t output will be from the location for which a6-a0 are all ?0?s. table 11. command codes hexa-decimal command 10h alternative program setup, double/quadruple byte program setup, chip erase confirm 20h block erase setup 32h sector erase setup 40h program, double/quadruple byte program setup 50h clear status register 70h read status register 80h chip erase setup 90h read electronic signature b0h program/erase suspend d0h program/erase resume, block erase confirm, sector erase confirm ffh read memory array
command interface m50flw080a, m50flw080b 26/64 4.2 read status register command the read status register command is used to read the status register. one bus write cycle is required to issue the read status register command. once the command is issued, subsequent bus read operations read the status register until another command is issued. see the section on the status register for details on the definitions of the status register bits. 4.3 read electronic signature command the read electronic signature command is used to read the manufacturer code and the device code. one bus write cycle is required to issue the read electronic signature command. once the command is issued, the manufacturer code and device code can be read using conventional bus read operations, and the addresses shown in ta bl e 1 2 . the device remains in this mode until another command is issued. that is, subsequent bus read operations continue to read the manufacturer code, or the device code, and not the memory array. 4.4 program command the program command can be used to program a value to one address in the memory array at a time. the program command works by changing appropriate bits from ?1? to ?0?. (it cannot change a bit from ?0? back to ?1?. atte mpting to do so will not modify th e value of the bit. only the erase command can set bits back to ?1?. and does so for all of the bits in the block.) two bus write operations are required to issue the program command. the second bus write cycle latches the address and data, and starts the program/erase controller. once the command is issued, subsequent bus read operations read the value in the status register. (see the section on the status register for details on the definitions of the status register bits.) if the address falls in a protected block, the program o peration will abort, th e data in the memory array will not be chan ged, and the status regist er will indicate the error. during the program operation, the memory will only accept the read status register command and the program/erase suspend command. all other commands are ignored. see figure 21 , for a suggested flowchart on using the program command. typical program times are given in ta bl e 1 8 . table 12. electronic signature codes code address (1) 1. a22 should be ?1?, and the id lines and upper address bits should be set according to the rules illustrated in table 5 , table 6 and table 8 . data manufacturer code ...00000h 20h device code m50flw080a m50flw080b ...00001h 80h 81h
m50flw080a, m50flw080b command interface 27/64 4.5 quadruple byte program command (a/a mux interface) the quadruple byte program command is used to program four adjacent bytes in the memory array at a time. the four bytes must differ only for addresses a0 and a1. programming should not be attempted when v pp is not at v pph . five bus write operations are required to issue the command. the second, third and fourth bus write cycles latch the respective addresses and data of the first, second and third bytes in the program/erase controller. the fifth bus write cycle latches the address and data of the fourth byte and starts the program/erase controller. once the command is issued, subsequent bus read operations read the value in the status register. (see the section on the status register for details on the definitions of the status register bits.) during the quadruple byte program operation, the memory will only accept the read status register and program/erase suspend commands. all other commands are ignored. note that the quadruple byte program command cannot change a bit set to ?0? back to ?1? and attempting to do so will not modify its valu e. one of the erase commands must be used to set all of the bits in the block to ?1?. see figure 23 , for a suggested flowchart on using the quadruple byte program command. typical quadruple byte program times are given in ta b l e 1 8 . 4.6 double/quadruple byte program command (fwh mode) the double/quadruple byte program command can be used to program two/four adjacent bytes to the memory array at a time. the two bytes must differ only for address a0; the four bytes must differ only for addresses a0 and a1. two bus write operations are required to issue the command. the second bus write cycle latches the start address and two/four data bytes and starts the program/erase controller. once the command is issued, subsequent bus read operations read the contents of the status register. (see the section on the status register for details on the definitions of the status register bits.) during the double/quadruple by te program operation the memo ry will only accept the read status register and program/erase suspend commands. all other commands are ignored. note that the double/quadruple byte program command cannot change a bit set to ?0? back to ?1? and attempting to do so will not modify its value. one of the erase commands must be used to set all of the bits in the block to ?1?. see figure 22 , for a suggested flowchart on using the double/quadruple byte program command. typical double/quadruple byte program times are given in ta b l e 1 8 .
command interface m50flw080a, m50flw080b 28/64 4.7 chip erase command the chip erase command erases the entire memory array, setting all of the bits to ?1?. all previous data in the memory array are lost. this command, though, is only available under the a/a mux interface. two bus write operations are required to issue the command, and to start the program/erase controller. once the command is issued, subsequent bus read operations read the contents of the status register. (see the section on the status register for details on the definitions of the status register bits.) erasing should not be attempted when v pp is not at v pph , otherwise the result is uncertain. during the chip erase operatio n, the memory will only accept the read status register command. all other commands are ignored. see figure 25 , for a suggested flowchart on using the chip erase command. typical chip erase times are given in ta b l e 1 8 . 4.8 block erase command the block erase command is used to erase a block, setting all of the bits to ?1?. all previous data in the block are lost. two bus write operations are required to issue the command. the second bus write cycle latches the block address and starts the program/erase controller. once the command is issued, subsequent bus read operations read the contents of the status register. (see the section on the status register for details on the definitions of the status register bits.) if the block, or if at least one sector of the block (for the blocks that are split into sectors), is protected (fwh/lpc only) then the block eras e operation will abort, the data in the block will not be changed, and the status register will indicate the error. during the block erase operation the memory w ill only accept the read status register and program/erase suspend commands. all other commands are ignored. see figure 26 , for a suggested flowchart on using the block erase command. typical block erase times are given in ta b l e 1 8 . 4.9 sector erase command the sector erase command is used to erase a uniform 4-kbyte sector, setting all of the bits to ?1?. all previous data in the sector are lost. two bus write operations are required to issue the command. the second bus write cycle latches the sector address and starts the program/erase controller. once the command is issued, subsequent bus read operations read the contents of the status register. (see the section on the status register for details on the definitions of the status register bits.) if the sector is protected (fwh/lpc only), th e sector erase operatio n will abort, the data in the sector will not be changed, and the status register will indicate the error. during the sector erase operat ion the memory will only acce pt the read status register and program/erase suspend commands. all other commands are ignored. see figure 26 , for a suggested flowchart on using the sector erase command. typical sector erase times are given in ta bl e 1 8 .
m50flw080a, m50flw080b command interface 29/64 4.10 clear status register command the clear status register command is used to reset status register bits sr1, sr3, sr4 and sr5 to ?0?. one bus write is required to issue the command. once the command is issued, the device returns to its previous mode, subsequent bus read operations continue to output the data from the same area, as before. once set, these status register bits remain set. they do not automatically return to ?0?, for example, when a new program or erase command is issued. if an error has occurred, it is essential that any error bits in the status register are cleared, by issuing the clear status register command, before attempting a new program or erase command. 4.11 program/erase suspend command the program/erase suspend command is used to pause the program/erase controller during a program or sector/block erase operation. one bus write cycle is required to issue the command. once the command has been issued, it is necessary to poll the program/erase controller status bit until the program/erase controller has paused. no other commands are accepted until the program/erase controller has paused. after the program/erase controller has paused, the device continues to output the contents of the status register until another command is issued. during the polling period, between issuing the program/erase suspend command and the program/erase controller pausing, it is possible for the operation to complete. once the program/erase controller status bit indicates that the program/erase controller is no longer active, the program suspend status bit or the erase suspend status bit can be used to determine if the operation has completed or is suspended. during program/erase suspend, the read memory array, read status register, read electronic signature and pr ogram/erase resume commands will be accepted by the command interface. additionally, if the suspended operation was sector erase or block erase then the program command will also be acce pted. however, it should be noted that only the sectors/blocks not being erased may be read or programmed correctly. see figure 24 , and figure 27 , for suggested flowcharts on using the program/erase suspend command. typical times and delay durations are given in ta bl e 1 8 . 4.12 program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend has paused it. one bus write cycle is required to issue the command. once the command is issued, subsequent bus read operations read the contents of the status register.
command interface m50flw080a, m50flw080b 30/64 table 13. commands command cycle bus operations (1) 1st 2nd 3rd 4th 5th addr data addr data addr data addr data addr data read memory array (2),(3),(4) 1+ x ffh read addr read data (read addr2) (read data2) (read addr3) (read data3) (read addr4) (read data4) read status register (5),(3) 1+ x 70h x status reg (x) (status reg) (x) (status reg) (x) (status reg) read electronic signature (3) 1+ x 90h or 98h sig addr signat ure (sig addr) (signat ure) (sig addr) (signatu re) (sig addr) (signat ure) program / multiple byte program (fwh) (6),(7),(4) 2x 40h or 10h prog addr prog data quadruple byte program (a/a mux) (6),(8) 5x30ha1 prog data1 a2 prog data2 a3 prog data3 a4 prog data4 chip erase (6) 2 x 80h x 10h block erase (6) 2x20hbad0h sector erase (6) 2x32hsad0h clear status register (9) 1x50h program/erase suspend (10) 1xb0h program/erase resume (11) 1xd0h invalid reserved (12) 1x00h 1x01h 1x60h 1x2fh 1xc0h 1. for all commands: the first cy cle is a write. for the first three comm ands (read memory, read status register, read electronic signature), the second and next cycles are read. for the remaining commands, the second and next cycles are write. ba = any address in the block, sa = any address in the sect or. x = don?t care, except t hat a22=1 (for fwh or lpc mode), and a21 and a20 are set according to the rules shown in table 5 (for lpc mode) 2. after a read memory array command, read the me mory as normal until another command is issued. 3. ?1+? indicates that there is one write cycl e, followed by any number of read cycles. 4. configuration registers are accessed directly without usi ng any specific command code. a single bus write or bus read operation is all that is needed. 5. after a read status register command, read the stat us register as normal unt il another command is issued. 6. after the erase and program commands read the status r egister until the command completes and another command is issued. 7. multiple byte program pa= start address, a0 (double by te program) a0 and a1 (quadruple byte program) are don`t care. pd is two or four bytes depending on msize code. 8. addresses a1, a2, a3 and a4 must be consecutive addresses, differing only in address bits a0 and a1. 9. after the clear status register command bits sr1, sr3, sr4 and sr5 in the status register are reset to ?0?. 10. while an operation is being program/erase suspended, the read memory array, read status register, program (during erase suspend) and program/erase resume commands can be issued. 11. the program/erase resume command causes the program /erase suspended operation to resume. read the status register until the program/erase controller completes and the memory returns to read mode. 12. do not use invalid or reserved commands.
m50flw080a, m50flw080b status register 31/64 5 status register the status register provides information on the current or previous program or erase operation. the bits in the status register convey specific information about the progress of the operation. to read the status register, the read status register command can be issued. the status register is automatically read after program, erase and program/erase resume commands are issued. the status register can be read from any address. the text descriptions, below, should be read in conjunction with ta b l e 1 4 , where the meanings of the status register bits are summarized. 5.1 program/erase controller status (bit sr7) this bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is ?0?, the program/erase controller is active; when the bit is ?1?, the program/er ase controller is inactive. the program/erase controller status is ?0? immediately after a program/erase suspend command is issued, until the program/erase controller pauses. after the program/erase controller pauses, the bit is ?1?. the end of a program and er ase operation can be found by polling the program/erase controller status bit can be polled. the other bits in the status register should not be tested until the program/erase controller has completed the operation (and the program/erase controller status bit is ?1?). after the program/erase controller has completed its operation, the erase status, program status, v pp status and block/sector protection status bits should be tested for errors. 5.2 erase suspend status (bit sr6) this bit indicates that an erase operation has been suspended, and that it is waiting to be resumed. the erase suspend status should only be considered valid when the program/erase controller status bit is ?1? (program/erase controller inactive). after a program/erase suspend command is issued, th e memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is ?0?, the program/erase controller is active or has completed its operation. when the bit is ?1?, a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is i ssued, the erase suspend status bit returns to ?0?.
status register m50flw080a, m50flw080b 32/64 5.3 erase status (bit sr5) this bit indicates if a problem has occurred during the erasing of a sector or block. the erase status bit should be read once the program/erase controller status bit is ?1? (program/erase controller inactive). when the erase status bit is ?0?, the memory has successfully verified that the sector/block has been erased correctly. when the erase status bit is ?1?, the program/erase controller has applied the maximum number of pulses to the sector/block and still failed to verify that the sector/block has been erased correctly. once the erase status bit is set to ?1?, it can only be reset to ?0? by a clear status register command, or by a hardware reset. if it is set to ?1?, it should be reset before a new program or erase command is issued, otherwise the new command will a ppear to have failed, too. 5.4 program status (bit sr4) this bit indicates if a problem has occurred during the programming of a byte. the program status bit should be read once the program/erase controller status bit is ?1? (program/erase controller inactive). when the program status bit is ?0?, the memory has successfully verified that the byte has been programmed correctly. when the program status bit is ?1?, the program/erase controller has applied th e maximum number of pulses to t he byte and still failed to verify that the byte has been programmed correctly. once the program status bit is set to ?1?, it can only be reset to ?0? by a clear status register command, or by a hardware reset. if it is set to ?1?, it should be reset before a new program or erase command is issued, otherwise the new command will a ppear to have failed, too. 5.5 v pp status (bit sr3) this bit indicates whether an invalid voltage was detected on the v pp pin at the beginning of a program or erase operation. the v pp pin is only sampled at the beginning of the operation. indeterminate results can occur if v pp becomes invalid during a program or erase operation. once the v pp status bit set to ?1?, it can only be reset to ?0? by a clear status register command, or by a hardware reset. if it is set to ?1?, it should be reset before a new program or erase command is issued, otherwise the new command will a ppear to have failed, too.
m50flw080a, m50flw080b status register 33/64 5.6 program suspend status (bit sr2) this bit indicates that a program operation has been suspended, and that it is waiting to be resumed. the program suspend status should only be considered valid when the program/erase controller status bit is ?1? (program/erase controller inactive). after a program/erase suspend command is issued, th e memory may still complete the operation instead of entering the suspend mode. when the program suspend status bit is ?0?, the program/erase controller is active, or has completed its operation. when the bit is ?1?, a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is issued, the program suspend status bit returns to ?0?. 5.7 block/sector protection status (bit sr1) the block/sector protection status bit can be used to identify if the program or erase operation has tried to modify the contents of a protected block or sector. when the block/sector protection status bit is reset to ?0?, no program or erase operations have been attempted on protected blocks or sectors since the last clear status register command or hardware reset. when the block/sector protection status bit is ?1?, a program or erase operation has been attempted on a protected block or sector. once it is set to ?1?, the block/sector protection status bit can only be reset to ?0? by a clear status register command or by a hardware reset. if it is set to ?1?, it should be reset before a new program or erase command is issued, otherwise the ne w command will appear to have failed, too. using the a/a mux interface, the block/sect or protection status bit is always ?0?. 5.8 reserved (bit sr0) bit 0 of the status register is reserved. its value should be masked.
status register m50flw080a, m50flw080b 34/64 table 14. status register bits operation sr7 sr6 sr5 sr4 sr3 sr2 sr1 program active ?0? x (1) 1. for program operations during eras e suspend, the sr6 bit is ?1?, otherwise the sr6 bit is ?0?. ?0? ?0? ?0? ?0? ?0? program suspended ?1 x (1) ?0? ?0? ?0? ?1? ?0? program completed successfully ?1? x (1) ?0? ?0? ?0? ?0? ?0? program failure due to v pp error ?1? x (1) ?0? ?1? ?1? ?0? ?0? program failure due to block/sector protection (fwh/lpc interface only) ?1? x (1) ?0? ?1? ?0? ?0? ?1? program failure due to cell failure ?1? x (1) ?0? ?1? ?0? ?0? ?0? erase active ?0? ?0? ?0? ?0? ?0? ?0? ?0? erase suspended ?1? ?1? ?0? ?0? ?0? ?0? ?0? erase completed successfu lly ?1? ?0? ?0? ?0? ?0? ?0? ?0? erase failure due to v pp error ?1? ?0? ?1? ?0? ?1? ?0? ?0? erase failure due to block/sector protection (fwh/lpc interface only) ?1? ?0? ?1? ?0? ?0? ?0? ?1? erase failure due to failed cell(s) in block or sector ?1? ?0? ?1? ?0? ?0? ?0? ?0?
m50flw080a, m50flw080b firmware hub/low-pin- count (fwh/lpc) interface configuration 35/64 6 firmware hub/low-pin-count (fwh/lpc) interface configuration registers when the firmware hub interface/low pin count is selected, several additional registers can be accessed. these registers control the protection status of the blocks/sectors, read the general purpose input pins and identify the memory using the manufacturer code. see ta bl e 1 5 for the memory map of the configuration registers. the configuration registers are accessed directly without using any specific command code. a single bus write or bus read operation, with the appropriate address (including a22=0), is all that is needed. 6.1 lock registers the lock registers control the protection status of the blocks/sectors. each block/sector has its own lock register. three bits within each lock register control the protection of each block/sector: the write lock bit, the read lock bit and the lock down bit. the lock registers can be read and written. care should be taken, though, when writing. once the lock down bit is set, ?1?, further modifications to the lock register cannot be made until it is cleared again by a reset or power-up. see ta bl e 1 6 for details on the bit definitions of the lock registers. 6.1.1 write lock the write lock bit determines whether the cont ents of the block/sector can be modified (using the program or erase command). when the write lock bit is set, ?1?, the block/sector is write protected ? any operations that attempt to change the data in the block/sector will fail, and the stat us register will report the erro r. when the write lock bit is reset, ?0?, the block/sector is not write protected by the lock register, and may be modified, unless it is write protected by some other means. if the top block lock signal, tbl , is low, v il , then the top block (block 15) is write protected, and cannot be modified. similarly, if the write protect signal, wp , is low, v il , then the main blocks (blocks 0 to 14) are write protected, and cannot be modified. for details, see appendix a and ta b l e 1 6 . after power-up, or reset, the write lock bit is always set to ?1? (write-protected). 6.1.2 read lock the read lock bit determines whether the contents of the block/sector can be read (in read mode). when the read lock bit is set, ?1?, the block/sector is read protected ? any operation that atte mpts to read the contents of the bl ock/sector will read 00h instead. when the read lock bit is reset, ?0?, read operations are allowed in the block/sector, and return the value of the data that had been programmed in the block/sector. after power-up, or reset, the read lock bit is always reset to ?0? (not read-protected).
firmware hub/low-pin-count (fwh/lpc) inte rface configuration registers m50flw080a, 36/64 6.1.3 lock down the lock down bit provides a mechanism for protecting software data from simple hacking and malicious attack. when the lock down bit is set, ?1?, further modification to the write lock, read lock and lock down bits cannot be performed. a reset, or power-up, is required before changes to these bits can be made. when the lock down bit is reset, ?0?, the write lock, read lock and lock down bits can be changed. 1. in lpc mode, a most significant nibble, f, must be added to the memory address. for all registers, a22=0, and the remaining address bits should be set accordin g to the rules shown in the addr field of table 6 to table 9 . table 15. configuration register map mnemonic register name memory address default value access lock registers (for details, see appendix a ) gpi_reg firmware hub/low pin count (fwh/lpc) general purpose input register fbc0100h n/a r manu_reg manufacturer code register fbc0000h 20h r table 16. lock register bit definitions bit bit name value function (1) 1. applies to the registers that are defined in table 34 and table 35 . 7-3 reserved 2 read-lock ?1? bus read operations in this block or sector always return 00h. ?0? bus read operations in this block or sector return the memory array contents. (default value). 1 lock-down ?1? changes to the read-lock bit and the write-lock bit cannot be performed. once a ?1? is written to the lock-down bit it cannot be cleared to ?0?; the bit is always reset to ?0? following a reset (using rp or init ) or after power-up. ?0? read-lock and write-lock can be changed by writing new values to them. (default value). 0write-lock ?1? program and erase operations in this block or sector will set an error in the status register. the memory contents will not be changed. (default value). ?0? program and erase operations in this block or sector are executed and will modify the block or sector contents.
m50flw080a, m50flw080b firmware hub/low-pin- count (fwh/lpc) interface configuration 37/64 6.2 firmware hub/low-pin-coun t (fwh/lpc) general-purpose input register the fwh/lpc general purpose input register holds the state of the general purpose input pins, gpi0-gpi4. when this register is read, the state of these pins is returned. this register is read-only. writing to it has no effect. the signals on the fwh/lpc interface general purpose input pins should remain constant throughout the whole bus read cycle. 6.3 manufacturer code register reading the manufacturer code register returns the value 20h, which is the manufacturer code for stmicroelectronics. this register is read-only. writing to it has no effect. table 17. general-purpose input register definition bit bit name value function (1) 1. applies to the general pur pose inputs regist er (gpi-reg). 7-5 reserved 4gpi4 ?1? input pin gpi4 is at v ih ?0? input pin gpi4 is at v il 3gpi3 ?1? input pin gpi3 is at v ih ?0? input pin gpi3 is at v il 2gpi2 ?1? input pin gpi2 is at v ih ?0? input pin gpi2 is at v il 1gpi1 ?1? input pin gpi1 is at v ih ?0? input pin gpi1 is at v il 0gpi0 ?1? input pin gpi0 is at v ih ?0? input pin gpi0 is at v il
program and erase times m50flw080a, m50flw080b 38/64 7 program and erase times the program and erase times are shown in ta bl e 1 8 . table 18. program and erase times parameter interface test condition min typ (1) 1. t a = 25c, v cc = 3.3v max unit byte program 10 200 s double byte program fwh v pp = 12v 5% 10 (2) 2. time to program two bytes. 200 s quadruple byte program a/a multiplexed fwh v pp = 12v 5% 10 (3) 3. time to program four bytes. 200 s block program v pp = 12v 5% 0.1 (4) 4. time obtained executing the quadruple byte program command. 5 s v pp = v cc 0.4 5 sector erase (4 kbytes) (5) 5. sampled only, not 100% tested. v pp = 12v 5% 0.4 4 s v pp = v cc 0.5 5 block erase (64 kbytes) v pp = 12v 5% 0.75 8 s v pp = v cc 110 chip erase a/a multiplexed v pp = 12v 5% 10 s program/erase suspend to program pause (5) 5 s program/erase suspend to block erase/sector erase pause (5) 30 s
m50flw080a, m50flw080b maximum rating 39/64 8 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 19. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c v io input or output range (1) 1. minimum voltage may undershoot to ?2v for less than 20ns during transiti ons. maximum voltage may overshoot to v cc + 2v for less than 20ns during transitions. ?0.50 v cc + 0.6 v v cc supply voltage ?0.50 4 v v pp program voltage ?0.6 13 v v esd electrostatic discharge voltage (human body model) (2) 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) ?2000 2000 v
dc and ac parameters m50flw080a, m50flw080b 40/64 9 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in ta bl e 2 0 , ta bl e 2 1 and ta b l e 2 2 . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 10. fwh/lpc interface ac measurement i/o waveforms table 20. operating conditions symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v t a ambient operating temperature ?20 85 c table 21. fwh/lpc interface ac measurement conditions parameter value unit load capacitance (c l )10pf input rise and fall times 1.4 ns input pulse voltages 0.2 v cc and 0.6 v cc v input and output timing ref. voltages 0.4 v cc v table 22. a/a mux interface ac measurement conditions parameter value unit load capacitance (c l )30pf input rise and fall times 10 ns input pulse voltages 0 to 3 v input and output timing ref. voltages 1.5 v ai03404 0.6 v cc 0.2 v cc 0.4 v cc i o > i lo i o < i lo i o < i lo input and output ac testing waveform output ac tri-state testing waveform
m50flw080a, m50flw080b dc and ac parameters 41/64 figure 11. a/a mux interface ac measurement i/o waveform figure 12. ac measurement load circuit table 23. impedance (1) 1. t a = 25c, f = 1mhz. symbol parameter test condition min max unit c in (2) 2. sampled only, not 100% tested. input capacitance v in = 0v 13 pf c clk (2) clock capacitance v in = 0v 3 12 pf l pin (3) 3. see pci specification. recommended pin inductance 20 nh ai01417 3v 0v 1.5v ai08430 v dd c l c l includes jig capacitance 16.7k ? device under test 0.1f v dd 0.1f v pp 16.7k ?
dc and ac parameters m50flw080a, m50flw080b 42/64 table 24. dc characteristics symbol parameter interface te st condition min max unit v ih input high voltage fwh 0.5 v cc v cc + 0.5 v a/a mux 0.7 v cc v cc + 0.3 v v il input low voltage fwh/lpc ?0.5 0.3 v cc v a/a mux -0.5 0.8 v v ih (init )init input high voltage fwh/lpc 1.1 v cc + 0.5 v v il (init )init input low voltage fwh/lpc ?0.5 0.2 v cc v i li (1) input leakage current 0v v in v cc 10 a i li2 ic, idx input leakage current ic, id0, id1, id2, id3 (2) = v cc 200 a r il ic, idx input pull low resistor 20 100 k ? v oh output high voltage fwh/lpc i oh = ?500 a 0.9 v cc v a/a mux i oh = ?100 av cc ? 0.4 v v ol output low voltage fwh/lpc i ol = 1.5ma 0.1 v cc v a/a mux i ol = 1.8ma 0.45 v i lo output leakage current 0v v out v cc 10 a v pp1 v pp voltage 3 3.6 v v pph v pp voltage (fast erase) 11.4 12.6 v v lko (3) v cc lockout voltage 1.8 2.3 v i cc1 supply current (standby) fwh/lpc fwh4/lframe = 0.9v cc , v pp = v cc all other inputs 0.9v cc to 0.1v cc v cc = 3.6v, f(clk) = 33mhz 100 a i cc2 supply current (standby) fwh/lpc fwh4/lframe = 0.1 v cc , v pp = v cc all other inputs 0.9 v cc to 0.1 v cc v cc = 3.6 v, f(clk) = 33 mhz 10 ma i cc3 supply current (any internal operation active) fwh/lpc v cc = v cc max, v pp = v cc f(clk) = 33 mhz, i out = 0ma 60 ma i cc4 supply current (read) a/a mux g = v ih , f = 6mhz 20 ma i cc5 (3) supply current (program/erase) a/a mux program/erase controller active 20 ma i pp v pp supply current (read/standby) v pp > v cc 400 a i pp1 (3) v pp supply current (program/erase active) v pp = v cc 40 ma v pp = 12v 5% 15 ma 1. input leakage currents include high-z output leakage for all bidirectional buffers with tri-state outputs. 2. id0 and id1 are rfu in lpc mode. 3. sampled only, not 100% tested.
m50flw080a, m50flw080b dc and ac parameters 43/64 figure 13. fwh/lpc interface clock waveform 1. devices on the pci bus must work with any clock frequency between dc and 33mhz. below 16mhz devices may be guaranteed by des ign rather than tested. refer to pci specification. table 25. fwh/lpc interface clock characteristics symbol parameter test condition value unit t cyc clk cycle time (1) min 30 ns t high clk high time min 11 ns t low clk low time min 11 ns clk slew rate peak to peak min 1 v/ns max 4 v/ns ai03403 thigh tlow 0.6 v cc tcyc 0.5 v cc 0.4 v cc 0.3 v cc 0.2 v cc 0.4 v cc , p-to-p (minimum)
dc and ac parameters m50flw080a, m50flw080b 44/64 figure 14. fwh/lpc interface ac signal timing waveforms clk fwh0-fwh3/ lad0-lad3 valid tchqv tchqz tchqx tchdx tdvch valid output data float output data valid input data ai09700 tchfh tflch fwh4 start cycle table 26. fwh/lpc interface ac signal timing characteristics symbol pci symbol pa rameter value unit t chqv t val clk to data out min 2 ns max 11 ns t chqx (1) t on clk to active (float to active delay) min 2 ns t chqz t off clk to inactive (active to float delay) max 28 ns t avch t dvch t su input set-up time (2) min 7 ns t chax t chdx t h input hold time (2) min 0 ns t flch input set-up time on fwh4 min 10 ns t chfh input hold time on fwh4 min 5 ns 1. the timing measurements for active/fl oat transitions are defined when the curr ent through the pin equals the leakage current specification. 2. applies to all inputs except clk and fwh4.
m50flw080a, m50flw080b dc and ac parameters 45/64 figure 15. reset ac waveforms table 27. reset ac characteristics symbol parameter test condition value unit t plph rp or init reset pulse width min 100 ns rp or init slew rate (1) 1. see chapter 4 of the pci specification. rising edge only min 50 mv/ns t phfl rp or init high to fwh4/lframe low fwh/lpc interface only min 30 s t phwl t phgl rp high to write enable or output enable low a/a mux interface only min 50 s rp, int ai09705 w, g, fwh4/lframe tplph tphwl, tphgl, tphfl
dc and ac parameters m50flw080a, m50flw080b 46/64 figure 16. a/a mux interface read ac waveforms ai03406 tavav tclax tchax tglqx tglqv tghqx valid a0-a10 g dq0-dq7 rc tchqv tghqz column addr valid w rp tphav row addr valid next addr valid tavcl tavch table 28. a/a mux interface read ac characteristics symbol parameter test condition value unit t avav read cycle time min 250 ns t avcl row address valid to rc low min 50 ns t clax rc low to row address transition min 50 ns t avch column address valid to rc high min 50 ns t chax rc high to column address transition min 50 ns t chqv (1) rc high to output valid max 150 ns t glqv (1) output enable low to output valid max 50 ns t phav rp high to row address valid min 1 s t glqx output enable low to output transition min 0 ns t ghqz output enable high to output hi-z max 50 ns t ghqx output hold from output enable high min 0 ns 1. g may be delayed up to t chqv ? t glqv after the rising edge of rc without impact on t chqv .
m50flw080a, m50flw080b dc and ac parameters 47/64 figure 17. a/a mux interface write ac waveforms ai04185 tclax tchax twhdx tdvwh valid srd a0-a10 g dq0-dq7 rc tchwh c1 w r1 tavcl tavch r2 c2 twlwh twhwl v pp tvphwh twhgl tqvvpl d in1 d in2 write erase or program setup write erase confirm or valid address and data automated erase or program delay read status register data ready to write another command table 29. a/a mux interface write ac characteristics symbol parameter test condition value unit t wlwh write enable low to write enable high min 100 ns t dvwh data valid to write enable high min 50 ns t whdx write enable high to data transition min 5 ns t avcl row address valid to rc low min 50 ns t clax rc low to row address transition min 50 ns t avch column address valid to rc high min 50 ns t chax rc high to column address transition min 50 ns t whwl write enable high to write enable low min 100 ns t chwh rc high to write enable high min 50 ns t vphwh (1) v pp high to write enable high min 100 ns t whgl write enable high to output enable low min 30 ns t whrl write enable high to rb low min 0 ns t qvvpl (1) (2) output valid, rb high to v pp low min 0 ns 1. sampled only, not 100% tested. 2. applicable if v pp is seen as a logic input (v pp < 3.6v).
package mechanical m50flw080a, m50flw080b 48/64 10 package mechanical figure 18. plcc32 ? 32 pin rectangular plastic leaded chip carrier, package outline 1. drawing is not to scale. table 30. plcc32 ? 32 pin rectangular plastic leaded chip carrier, package mechanical data symbol millimeters inches typ min max typ min max a 3.18 3.56 0.125 0.140 a1 1.53 2.41 0.060 0.095 a2 0.38 ? 0.015 ? b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 cp 0.10 0.004 d 12.32 12.57 0.485 0.495 d1 11.35 11.51 0.447 0.453 d2 4.78 5.66 0.188 0.223 d3 7.62 ? ? 0.300 ? ? e 14.86 15.11 0.585 0.595 e1 13.89 14.05 0.547 0.553 e2 6.05 6.93 0.238 0.273 e3 10.16 ? ? 0.400 ? ? e1.27 ? ? 0.050 ? ? f 0.00 0.13 0.000 0.005 r0.89 ? ? 0.035 ? ? n32 32 plcc-a d e3 e1 e 1 n d1 d3 cp b e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 e2 d2 d2
m50flw080a, m50flw080b package mechanical 49/64 figure 19. tsop32 ? 32 lead plastic thin small outline, 8x14 mm, package outline 1. drawing is not to scale. table 31. tsop32 ? 32 lead plastic thin small outline, 8x14 mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.950 1.050 0.0374 0.0413 0 5 0 5 b 0.170 0.270 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d 13.800 14.200 0.5433 0.5591 d1 12.300 12.500 0.4843 0.4921 e 0.500 ? ? 0.0197 ? ? e 7.900 8.100 0.3110 0.3189 l 0.500 0.700 0.0197 0.0276 n32 32 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1
package mechanical m50flw080a, m50flw080b 50/64 figure 20. tsop40 ? 40 lead plastic thin small outline, 10 x 20mm, package outline 1. drawing is not to scale. table 32. tsop40 ? 40 lead plastic thin small outline, 10 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d1 10.000 9.900 10.100 0.3937 0.3898 0.3976 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? l 0.500 0.700 0.0197 0.0276 l1 0.800 0.0315 3 0 5 3 0 5 tsop40-m b e die c e1 e 20 1 40 d1 cp 21 l a1 a a2 l1 0.25
m50flw080a, m50flw080b part numbering 51/64 11 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 33. ordering information scheme example: m50flw080 a k 5 t g device type m50 = flash memory for pc bios architecture fl = firmware hub/low pin count interface operating voltage w = v cc = 3.0 to 3.6v device function 080 = 8 mbit (x8), uniform blocks and sectors array matrix a = 2 x 16 x 4kbyte top sectors + 1 x 16 x 4kbyte bottom sectors b = 1 x 16 x 4kbyte top sectors + 2 x 16 x 4kbyte bottom sectors package k = plcc32 nb = tsop32: 8 x 14mm (1) 1. the tsop32 package is only available in devices of the a type array matrix. n = tsop40: 10 x 20mm (2) 2. devices delivered in this pack age are not recommended for new design. device grade 5 = temperature range ?20 to 85 c. device tested with standard test flow option blank = standard packing t = tape and reel packing plating technology p or g = ecopack? (rohs compliant)
block and sector address table m50flw080a, m50flw080b 52/64 appendix a block and sector address table table 34. m50flw080a block, sector and lock register addresses block size (kbyte) address range block no and type sector size (kbyte) sector no register address 64 ff000h-fffffh 15 (top) 4 47 fbff002 fe000h-fefffh 4 46 fbfe002 fd000h-fdfffh 4 45 fbfd002 fc000h-fcfffh 4 44 fbfc002 fb000h-fbfffh 4 43 fbfb002 fa000h-fafffh 4 42 fbfa002 f9000h-f9fffh 4 41 fbf9002 f8000h-f8fffh 4 40 fbf8002 f7000h-f7fffh 4 39 fbf7002 f6000h-f6fffh 4 38 fbf6002 f5000h-f5fffh 4 37 fbf5002 f4000h-f4fffh 4 36 fbf4002 f3000h-f3fffh 4 35 fbf3002 f2000h-f2fffh 4 34 fbf2002 f1000h-f1fffh 4 33 fbf1002 f0000h-f0fffh 4 32 fbf0002 64 ef000h-effffh 14 (main) 4 31 fbef002 ee000h-eefffh 4 30 fbee002 ed000h-edfffh 4 29 fbed002 ec000h-ecfffh 4 28 fbec002 eb000h-ebfffh 4 27 fbeb002 ea000h-eafffh 4 26 fbea002 e9000h-e9fffh 4 25 fbe9002 e8000h-e8fffh 4 24 fbe8002 e7000h-e7fffh 4 23 fbe7002 e6000h-e6fffh 4 22 fbe6002 e5000h-e5fffh 4 21 fbe5002 e4000h-e4fffh 4 20 fbe4002 e3000h-e3fffh 4 19 fbe3002 e2000h-e2fffh 4 18 fbe2002 e1000h-e1fffh 4 17 fbe1002 e0000h-e0fffh 4 16 fbe0002
m50flw080a, m50flw080b block and sector address table 53/64 1. in lpc mode, a most significant nibble, f, must be added to the memory address. for all registers, a22=0, and the remaining address bits should be set accordin g to the rules shown in the addr field of table 6 to table 9 . 64 d0000h-dffffh 13 (main) fbd0002 64 c0000h-cffffh 12 (main) fbc0002 64 b0000h-bffffh 11 (main) fbb0002 64 a0000h-affffh 10 (main) fba0002 64 90000h-9ffffh 9 (main) fb90002 64 80000h-8ffffh 8 (main) fb80002 64 70000h-7ffffh 7 (main) fb70002 64 60000h-6ffffh 6 (main) fb60002 64 50000h-5ffffh 5 (main) fb50002 64 40000h-4ffffh 4 (main) fb40002 64 30000h-3ffffh 3 (main) fb30002 64 20000h-2ffffh 2 (main) fb20002 64 10000h-1ffffh 1 (main) fb10002 64 0f000h-0ffffh 0 (main) 4 15 fb0f002 0e000h-0efffh 4 14 fb0e002 0d000h-0dfffh 4 13 fb0d002 0c000h-0cfffh 4 12 fb0c002 0b000h-0bfffh 4 11 fb0b002 0a000h-0afffh 4 10 fb0a002 09000h-09fffh 4 9 fb09002 08000h-08fffh 4 8 fb08002 07000h-07fffh 4 7 fb07002 06000h-06fffh 4 6 fb06002 05000h-05fffh 4 5 fb05002 04000h-04fffh 4 4 fb04002 03000h-03fffh 4 3 fb03002 02000h-02fffh 4 2 fb02002 01000h-01fffh 4 1 fb01002 00000h-00fffh 4 0 fb00002 table 34. m50flw080a block, sector and lock register addresses (continued) block size (kbyte) address range block no and type sector size (kbyte) sector no register address
block and sector address table m50flw080a, m50flw080b 54/64 table 35. m50flw080b block, sector and lock register addresses block size (kbyte) address range block no and type sector size (kbyte) sector no register address 64 ff000h-fffffh 15 (top) 447fbff002 fe000h-fefffh 4 46 fbfe002 fd000h-fdfffh 4 45 fbfd002 fc000h-fcfffh 4 44 fbfc002 fb000h-fbfffh 4 43 fbfb002 fa000h-fafffh 4 42 fbfa002 f9000h-f9fffh 4 41 fbf9002 f8000h-f8fffh 4 40 fbf8002 f7000h-f7fffh 4 39 fbf7002 f6000h-f6fffh 4 38 fbf6002 f5000h-f5fffh 4 37 fbf5002 f4000h-f4fffh 4 36 fbf4002 f3000h-f3fffh 4 35 fbf3002 f2000h-f2fffh 4 34 fbf2002 f1000h-f1fffh 4 33 fbf1002 f0000h-f0fffh 4 32 fbf0002 64 e0000h-effffh 14 (main) fbe0002 64 d0000h-dffffh 13 (main) fbd0002 64 c0000h-cffffh 12 (main) fbc0002 64 b0000h-bffffh 11 (main) fbb0002 64 a0000h-affffh 10 (main) fba0002 64 90000h-9ffffh 9 (main) fb90002 64 80000h-8ffffh 8 (main) fb80002 64 70000h-7ffffh 7 (main) fb70002 64 60000h-6ffffh 6 (main) fb60002 64 50000h-5ffffh 5 (main) fb50002 64 40000h-4ffffh 4 (main) fb40002 64 30000h-3ffffh 3 (main) fb30002 64 20000h-2ffffh 2 (main) fb20002
m50flw080a, m50flw080b block and sector address table 55/64 1. in lpc mode, a most significant nibble, f, must be added to the memory address. for all registers, a22=0, and the remaining address bits should be set accordin g to the rules shown in the addr field of table 6 to table 9 . 64 1f000h-1ffffh 1 (main) 4 31 fb1f002 1e000h-1efffh 4 30 fb1e002 1d000h-1dfffh 4 29 fb1d002 1c000h-1cfffh 4 28 fb1c002 1b000h-1bfffh 4 27 fb1b002 1a000h-1afffh 4 26 fb1a002 19000h-19fffh 4 25 fb19002 18000h-18fffh 4 24 fb18002 17000h-17fffh 4 23 fb17002 16000h-16fffh 4 22 fb16002 15000h-15fffh 4 21 fb15002 14000h-14fffh 4 20 fb14002 13000h-13fffh 4 19 fb13002 12000h-12fffh 4 18 fb12002 11000h-11fffh 4 17 fb11002 10000h-10fffh 4 16 fb10002 64 0f000h-0ffffh 0 (main) 4 15 fb0f002 0e000h-0efffh 4 14 fb0e002 0d000h-0dfffh 4 13 fb0d002 0c000h-0cfffh 4 12 fb0c002 0b000h-0bfffh 4 11 fb0b002 0a000h-0afffh 4 10 fb0a002 09000h-09fffh 4 9 fb09002 08000h-08fffh 4 8 fb08002 07000h-07fffh 4 7 fb07002 06000h-06fffh 4 6 fb06002 05000h-05fffh 4 5 fb05002 04000h-04fffh 4 4 fb04002 03000h-03fffh 4 3 fb03002 02000h-02fffh 4 2 fb02002 01000h-01fffh 4 1 fb01002 00000h-00fffh 4 0 fb00002 table 35. m50flw080b block, sector and lock register addresses (continued) block size (kbyte) address range block no and type sector size (kbyte) sector no register address
flowcharts and pseudo codes m50flw080a, m50flw080b 56/64 appendix b flowcharts and pseudo codes figure 21. program flowchart and pseudo code 1. a status check of sr1 (protected block/sector), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation by fo llowing the correct command sequence. 2. if an error is found, the status register must be cleared before further pr ogram/erase controller operations. write 40h or 10h ai09092 start write address and data read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program command: ? write 40h or 10h ? write address and data (memory enters read status state after the program command) do: ? read status register ? if sr7=0 and a program/erase suspend command has been executed ? sr7 is set to 1 ? enter suspend program loop if sr3 = 1, ? enter the "v pp invalid" error handler if sr4 = 1, ? enter the "program error" error handler yes end yes no sr1 = 0 program to protected block/sector error (1, 2) if sr1 = 1, ? enter the "program to protected block/sector" error handler suspend suspend loop no yes fwh/lpc interface only
m50flw080a, m50flw080b flowcharts and pseudo codes 57/64 figure 22. double/quadruple byte program flowchart and pseudo code (fwh mode only) 1. a status check of sr3 (v pp invalid) and sr4 (program error) can be made after each program operation by following the co rrect command sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. a0 and/or a1 are treated as don?t care (a0 for double byte program and a1-a0 for quadruple byte program). for double byte program: starting at the start address, the first dat a byte is programmed at the even address, and the second at the odd address. for quadruple byte program: starting at the start a ddress, the first data byte is programmed at the address that has a1-a0 at 00, the second at the address that has a1-a0 at 01, the third at the address that has a1-a0 at 10, and the fourth at the address that has a1-a0 at 11. ai09093 read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) double/quadruple byte program command: ? write 40h or 10h ? write start address and 2/4 data bytes (3) (memory enters read status state after the double/quadruple byte program command) do: ? read status register ? if sr7=0 and a program/erase suspend command has been executed ? sr7 is set to 1 ? enter suspend program loop if sr3 = 1, v pp invalid error: ? error handler if sr4 = 1, program error: ? error handler suspend suspend loop no yes write 40h or 10h start write start address and 2/4 data bytes (3) yes end yes no sr1 = 0 program to protected block/sector error (1, 2) if sr1 = 1, program to protected block/sector error: ? error handler
flowcharts and pseudo codes m50flw080a, m50flw080b 58/64 figure 23. quadruple byte program flowchart and pseudo code (a/a mux interface only) 1. a status check of sr3 (v pp invalid) and sr4 (program error) can be made after each program operation by following the co rrect command sequence. 2. if an error is found, the status register must be cleared before further pr ogram/erase controller operations. 3. address1, address 2, address 3 and address 4 mu st be consecutiv e addresses differi ng only for address bits a0 and a1. ai09099 write address 4 & data 4 (3) read status register yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) quadruple byte program command: ? write 30h ? write address 1 & data 1 (3) ? write address 2 & data 2 (3) ? write address 3 & data 3 (3) ? write address 4 & data 4 (3) (memory enters read status state after the quadruple byte program command) do: ? read status register ? if sr7=0 and a program/erase suspend command has been executed ? sr7 is set to 1 ? enter suspend program loop if sr3 = 1, v pp invalid error: ? error handler if sr4 = 1, program error: ? error handler end yes suspend suspend loop no yes write 30h start write address 1 & data 1 (3) write address 2 & data 2 (3) write address 3 & data 3 (3)
m50flw080a, m50flw080b flowcharts and pseudo codes 59/64 figure 24. program suspend and resume flowchart and pseudo code 1. if an error is found, the status register must be cleared before further program/erase operations. 2. any address within the bank can equally be used. write 70h ai08426b read status register yes no sr7 = 1 yes no sr2 = 1 program continues write a read command program/erase suspend command: ? write b0h ? write 70h do: ? read status register while sr7 = 0 if sr2 = 0 program completed write d0h program/erase resume command: ? write d0h to resume the program ? if the program operation completed then this is not necessary. the device returns to read as normal (as if the program/erase suspend was not issued). read data from another address start write b0h program complete write ffh read data
flowcharts and pseudo codes m50flw080a, m50flw080b 60/64 figure 25. chip erase flowchart and pseudo code (a/a mux interface only) 1. if an error is found, the status register must be cleared before further pr ogram/erase controller operations. write 80h ai08428b start write 10h read status register yes no sr7 = 1 yes no sr3 = 0 no sr4, sr5 = 0 v pp invalid error (1) command sequence error (1) chip erase command: ? write 80h ? write 10h (memory enters read status register after the chip erase command) do: ? read status register while sr7 = 0 if sr3 = 1, v pp invalid error: ? error handler if sr4, sr5 = 1, command sequence error: ? error handler yes no sr5 = 0 erase error (1) if sr5 = 1, erase error: ? error handler end yes
m50flw080a, m50flw080b flowcharts and pseudo codes 61/64 figure 26. sector/block erase flowchart and pseudo code 1. if the block erase command is used on a block that is split into 4kbyte se ctors, each of the 16 sectors of the block should be unlocked befor e performing the erase operation. 2. if an error is found, the status register must be cleared before further pr ogram/erase controller operations. write 20h/32h ai09094 start write block/sector address and d0h read status register yes no sr7 = 1 yes no sr3 = 0 no sr4, sr5 = 0 v pp invalid error (1) command sequence error (1) block/sector erase command: ? write 20h/32h ? write block/sector address and d0h (memory enters read status register after the block/sector erase command) do: ? read status register ? if sr7=0 and a program/erase suspend command has been executed ? sr7 is set to 1 ? enter suspend program loop if sr3 = 1, ? enter the "v pp invalid" error handler if sr4, sr5 = 1, ? enter the "command sequence"error handler yes no sr5 = 0 erase error (1) yes no suspend suspend loop if sr5 = 1, ? enter the "erase error" error handler end yes no sr1 = 0 erase to protected block/sector error (1) if sr1 = 1, ? enter the "erase to protected block/sector" error handler yes fwh/lpc interface only
flowcharts and pseudo codes m50flw080a, m50flw080b 62/64 figure 27. erase suspend and resume flowchart and pseudo code write 70h ai08429b read status register yes no sr7 = 1 yes no sr6 = 1 erase continues program/erase suspend command: ? write b0h ? write 70h do: ? read status register while sr7 = 0 if sr6 = 0, erase completed write d0h read data from another block/sector or program start write b0h erase complete write ffh read data program/erase resume command: ? write d0h to resume erase ? if the erase operation completed then this is not necessary. the device returns to read as normal (as if the program/erase suspend was not issued).
m50flw080a, m50flw080b revision history 63/64 12 revision history table 36. document revision history date version changes 02-feb-2004 0.1 first issue 21-apr-2004 0.2 tsop32 package added 24-may-2004 1.0 first public release 18-aug-2004 2.0 pins 2 and 5 of the tsop32 connections illustration corrected 21-jun-2005 3.0 datasheet status changed to full datasheet. 26-oct-2006 4 document converted to new st template. packages are ecopack? compliant. t lead removed from table 19: absolute maximum ratings . blank option removed below plating technology in table 33: ordering information scheme . tsop40 (n) package is not recommended for new design. tsop32 (nb) package only available in a type array matrix devices. tsop40 package specifications updated (see ta b l e 3 2 and figure 20 ).
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