general information the gd16523 multiplexes sixteen data inputs into a single data output, the bit rates of the inputs are selectable (see table below). the data inputs are forward clocked by the differential input (dclkp / dclkn). the gd16523 tolerates up to 1.7 ui pp (155 mhz) jitter on the input data and for - ward clock. a double pll system combined with an elastic buffer ensures low output jitter. each pll has a separate pcmos lock- detect output. the vcxo reference clock input is differ - ential and the frequency is selectable 78 mhz or 155 mhz. data inputs are differential lvpecl in - puts. 2.5 ghz clock and data outputs are differential cml with internal 50 w termi - nations. the gd16523 requires only one supply voltage of +3.3 v and consumes less than 1 w. the gd16523 is available in a 100 pin tqfp package (14 14 mm) with heat slug on bottom surface. preliminary features l 2.5 gbit/s 16:1 multiplexer. l forward clocked input data. l differential reference clock input. l 2.5 ghz clock output. l lvttl lock detect outputs. l single power supply: +3.3 v. l power consumption: less than 1 w. l available in a 100 pin tqfp package (14 14 mm) with exposed heat slug on bottom surface. 2.5 gbit/s 16:1 multiplexer gd16523 data sheet rev. 11 16 16 dip0 din0 dip15 din15 chap1 vcxip vcxin csel xsel chap2 vctl tck sltck doutp slbop dclkp vbb vbbs lsel ckop doutn slbon dclkn ckon nldc1 nlock1 brs1 brs0 ibr = input bit rate obr = output bit rate nldc2 nlock2 veea vee vcca vcc pfd2 wideband lpf narrow band lpf pfd1 16:1 mux clock generator /2 /2 elastic buffer vco 2.5 ghz vcxo wr ibr obr ibr 72-81mhz 143 - 163 mhz ibr/2 ibr/2 brs1 brs0 input bit rate (ibr) output bit rate (obr) 0 0 9.0 - 10.1 mbit/s 143 - 163 mbit/s 0 1 36 - 40 mbit/s 575 - 650 mbit/s 1 0 72 - 81 mbit/s 1150 - 1300 mbit/s 1 1 143 - 163 mbit/s 2300 - 2600 mbit/s
functional details the gd16523 multiplexes the sixteen data inputs (dip/n0-15) into a single data output (dout) with dip/n0 as the first bit to be output and dip/n15 as the last. the data inputs are differential lvpecl type and the output is differen - tial cml, driving 10 ma in a 50 w load connected to vcc. furthermore the input data is forward clocked by the dclk input. to reduce noise on the output to a mini - mum a double pll system has been im - plemented. the first pll in addition to a passive loop filter requires an external crystal vco (vcxo). the centre fre - quency of the vcxi input which is driven by the external vcxo can be selected to be in either range 143 - 163 mhz or 72 - 81 mhz by the xsel pin. the second pll requires only a passive external loop filter typically consisting of a resistor and a capacitor. the noise performance on the output of the chip depends on three noise generat - ing sources, the forward clock (dclk), the external vco (vcxo) and the inter - nal vco, see figure 1 . the output noise is a combination of theese three curves. first the noise follows the dclk curve until the loop-bandwidth of lpf1 then the noise follows the curve of vcxo until the loop-bandwidth of lpf2, and finally it fol- lows the noise of the internal vco, see figure 2 . figure 1. noise sources contributing to the output noise. normalized to same signal power and carrier frequency. figure 2. spectrum of output clock, with optimized lbw2. above the pll1 loop-filter frequency the noise performance is determined by the vcxo therefore the pll1 loop-filter fre - quency should be set as low as possible. at the same time the the jitter on the for - ward clock integrated at frequencies above the pll1 loop-filter frequency may not exceed 1.7 ui pp (155 mhz). the opti - mum pll1 loop bandwidth is therefore the frequency above which the integrated noise is just below 1.7 ui pp (155 mhz). the optimum loop bandwidth of pll2 is the frequency where the vco curve crosses the vcxo curve, see figure 1. a pcmos lock detect output pin is avail - able for each pll, indicating if the corre - sponding pll is in lock. to enable this functio na5-10nf capacitor should be connected to each of the nldc pins. this capacitor filters the nldet signal generated internally by xoring the two signals going to the pfd and putting this through a charge pump to the nldc pin. this filtering enables the nlock pin to go low when the corresponding pll is in lock and high when out of lock. a high level on the csel input bypasses the pll1 so that the write signal to the elastic buffer goes directly to the pfd2. it also bypasses the divider between the clock generator and the pfd2. note that changing the bit rate in this mode changes the loop-bandwidth of the ppl2. the auxillary output slbop/slbon is a second data output to accommodate near-end loop back. to save power in normal operation and reduce noise in the receiver the output can be turned off by setting lsel low. the two bit rate select signals brs1 and brs0 select the bit rate of the chip. brs1 brs0 dip/n0..15 doutp/n 1 1 155 mbit/s 2.5 gbit/s 1 0 77 mbit/s 1.25 gbit/s 0 1 38 mbit/s 622 mbit/s 0 0 9.7 mbit/s 155 mbit/s application details pll loop filters the loop filters can be made as shown in figure 3 . the values in figure 3 are the same as used in the production test sets. for optimal jitter performance the values of lpf1 should be adjusted according to the jitter on the input data and the values for lpf2 should be adjusted according to the jitter on the vcxo. figure 3. loop filters for noise and jitter reasons it is important that the capacitor (c2) is connected to vcca close to the vctl pin. biasing the data inputs all the data inputs are biased internally on the chip with the resistive network as shown in figure 4 . the data inputs can be used both differ - ential and single-ended without any ex - ternal pull-ups/downs and can also be ac-coupled. the vbb input may be shorted to the vbbs output and de-copled with at least one external capacitor on either pin 23 or 61. figure 4. data inputs data sheet rev. 11 gd16523 page 2 of 10 from dclk from vcxo from vco frequency signal power signal power frequency lbw1 lbw2 pfd1 pfd2 vco vcxo vcxip vcxin r1 r2 c1 c2 chap1 chap2 vctl vcc vcca dip0 dip15 din0 din15 5k w 5k w 5k w 5k w vbb
pin list mnemonic: pin numbers: pin type: description: dip0 din0 dip1 din1 dip2 din2 dip3 din3 dip4 din4 dip5 din5 dip6 din6 dip7 din7 dip8 din8 dip9 din9 dip10 din10 dip11 din11 dip12 din12 dip13 din13 dip14 din14 dip15 din15 26, 27 28, 29 30, 31 32, 33 34, 35 36, 37 39, 40 41, 42 43, 44 45, 46 47, 48 49, 50 53, 54 55, 56 57, 58 59, 60 lvpecl in differential data inputs multiplexed to the serial output starting with dip0, followed by dip1, dip2....dip15. pre-biased to vbb. dclkp, dclkn 63, 64 lvpecl in differential clock input. these pins are used to forward clock the data inputs. vcxip, vcxin 88, 89 lvpecl in differential vcxo clock input for pll1. vctl 96 anl in internal vco frequency control input. csel 71 lvttl in pll1 bypass select signal. low pll1 is active. high pll1 is by - passed. unconnected is same as low. lsel 72 lvttl in loop select. when lsel is low slbop/n output buffer is powered down, when lsel is high it is powered up. unconnected is same as low. xsel 73 lvttl in select input for reference clock frequency. low selects 77 mhz; high selects 155 mhz. unconnected is same as high. brs0, brs1 68, 69 lvttl in bit rate select. unconnected selects 1,1. brs1 brs0 dip0..dip15 doutp/n 1 1 155.52 mbit/s 2.488 gbit/s 1 0 77.76 mbit/s 1.244 gbit/s 0 1 38.88 mbit/s 622 mbit/s 0 0 9.72 mbit/s 155 mbit/s doutp, doutn 9, 10 cml out multiplexed data output. on-chip terminated, refer to figure 6 . slbop, slbon 3, 4 cml out near-end loop back output. on-chip terminated, refer to figure 6 . sltck 91 lvttl in clock source select input. low selects internal vco; high selects tck input as clock source. unconnected is same as low. tck 92 lvttl in test clock input. this pin is used as clock source instead of the internal vco when the sltck input pin is high. ckop, ckon 18, 19 cml out clock output in phase with the multiplexed data output. on-chip terminated, refer to figure 6 . chap1 84 anl out charge-pump 1 output. sinks current when vcxo is leading. sources current when vcxo is lagging, use positive transfer vcxo. chap2 93 anl out charge-pump 2 output. sources current when internal vco is leading. sinks current when internal vco is lagging. internal vco is negative transfer. vbb 23, 61 anl in reference voltage input for differential data inputs. vbbs 22 anl out reference voltage output for differential data inputs. nlock1 77 pcmos out pll1 lock detect output. high when pll1 is out of lock. low when pll1 is in lock. nlock2 78 pcmos out pll2 lock detect output. high when pll2 is out of lock. low when pll2 is in lock. nldc1 80 anl in/out a capacitor should be connected to this pin to set the time con - stant for the nlock1 output. data sheet rev. 11 gd16523 page 3 of 10
mnemonic: pin numbers: pin type: description: nldc2 82 anl in/out a capacitor should be connected to this pin to set the time con - stant for the nlock2 output. vee 12, 25, 38, 51, 62, 65, 67, 74, 75, 81, 87, 90 pwr 0 v power for core and pecl i/o. veea 95, 97, 98 pwr 0 v power for vco. veeo 13, 14 pwr 0 v power for high-speed outputs. vcc 1, 24, 52, 66, 70, 76, 79, 83, 85, 86 pwr +3.3 v power for core and pecl i/o. vcca 94, 99, 100 pwr +3.3 v power for vco. vcco 6, 7, 15, 16, 21 pwr +3.3 v power for high-speed outputs. nc 2, 5, 8, 11, 17, 20 heat sink package bottom internally connected to vee. package pinout figure 5. package pinout. top view. data sheet rev. 11 gd16523 page 4 of 10 63 62 61 60 59 75 58 74 57 73 56 55 54 53 52 51 72 71 70 69 68 67 66 65 64 45 50 44 49 43 48 42 47 41 46 40 39 38 37 36 35 34 33 32 31 28 30 27 29 26 17 16 15 14 13 12 10 9 8 25 7 24 6 23 5 22 4 21 3 20 2 19 1 18 97 100 96 99 95 98 94 93 92 91 90 89 88 87 86 85 80 84 79 83 78 82 77 81 76 vee vee xsel lsel csel vcc brs1 brs0 vee vcc vee dclkn dclkp vee vbb din15 dip15 din14 dip14 dip13 din13 din12 dip12 vcc vee dip9 din11 din8 dip11 dip8 din10 din7 dip10 dip7 din9 din6 dip6 vee din5 dip5 din4 dip4 din3 dip3 din2 dip1 dip2 din0 din1 dip0 nc slbop slbon nc vcco vcco nc doutp doutn nc vee veeo veeo vcco vcco nc ckop ckon nc vcco vbbs vbb vcc vee vcc veea vcca vctl vcca veea veea vcca chap2 tck sltck vee vcxin vcxip vee vcc vcc nldc1 chap1 vcc vcc nlock2 nldc2 nlock1 vee vcc
maximum ratings these are the limits beyond which the component may be damaged. all voltages in the table are referred to v ee . all currents in the table are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit: v cc power supply -0.5 6 v i o cml cml output current -15 15 ma v i applied voltage (all inputs) -0.5 v cc +0.5 v v o applied voltage (all outputs) -0.5 6.0 v v io esd,cml static discharge voltage note 1 500 v i i lvpecl lvpecl input current -1 1 ma i o pcmos pcmos output source current -250 250 m a i o pcmos pcmos output sink current -250 250 m a i o chap, nldc charge pump output current -250 250 m a t o operating temperature case -40 +110 c t s storage temperature -65 +150 c note 1: human body model (100 pf, 1500 w ) mil 883 std. data sheet rev. 11 gd16523 page 5 of 10
dc characteristics t case = -40 cto+85 c. appropriate heat sink may be required. device is dc tested in the temperature range 0 cto85 c. specifications from -40 cto0 c are guaranteed by design and evaluated during the engineering test. v cc = 2.97 v to 3.6 v. all voltages in the table are referred to v ee . all input signal and power currents in the table are defined positive into the pin. all output signal currents are defined positive out of the pin. symbol: characteristic: conditions: min.: typ.: max.: unit: v cc supply voltage +2.97 +3.3 +3.6 v i cc supply current 277 ma p diss power dissipation note 1 1000 mw v ih lvpecl lvpecl-input hi voltage v cc -1.17 v cc -0.87 v v il lvpecl lvpecl-input lo voltage v cc -2.01 v cc -1.47 v i ih lvpecl lvpecl-input current v ih max to v il min -200 +100 m a v i lvttl lvttl-input hi voltage 2.0 v cc v v il lvttl lvttl-input lo voltage 0.0 0.8 v i ih lvttl lvttl-input hi current 800 m a i il lvttl lvttl-input lo current -1000 m a i vctl vctl leakage current v ee ac characteristics t case = -40 cto+85 c. appropriate heat sink may be required. device is dc tested in the temperature range 0 cto85 c. specifications from ?40 cto0 c are guaranteed by design and evaluated during the engineering test. v cc = 2.97 v to 3.6 v. symbol: characteristic: conditions: min.: typ.: max.: unit: j gen jitter generation 12 khz to 20 mhz, note 1 5 khz to 20 mhz, note 1 5 0.08 mui rms ui pp j tol input data jitter tolerance see figure 8 , note 2 1.7 ui pp t lh cml cml output rise time design target, note 3 60 110 ps t hl cml cml output fall time design target, note 3 60 110 ps c duty vcxi vcxi input clock duty cycle 50 % c duty ckop/n output clock duty cycle 50 % t su input data set-up time before dclk 800 ps t ho input data hold time from dclk 800 ps f vcxi vcxi input frequency xsel is high xsel is low 144 72 155.52 77.76 162 81 mhz mhz f doutp,doutn output data bit rate note 4 2.3 2.488 2.6 gbit/s k vco vco gain constant vctl = 2.0 v 100 mhz/v t lock lock response time note 4 200 tbd m s t pd time from dclk to first bit is output note 4 38 ns t sosk serial output skew tbd-50 tbd+50 ps f vco min vco frequency vctl = v cc -0.25 v 2.3 ghz f vco max vco frequency vct l=0v 2.6 ghz note 1: 1 ui = 402 ps, vctl of vcxo is kept dc, pll2 is in lock and loop filter 2 is optimized. note 2: 1 ui = 6430 ps. the tolerance is reduced 0.2 ui pp per 10 m a sunk from the chap1 output. note 3: 20% - 80%, loaded with 50 w and 0.5 pf in parallel to vcc. see figure 6. note 4: with 10 nf on nldc. data sheet rev. 11 gd16523 page 7 of 10 t ho t su dclkp dip0..15 6400 ps ckop doutp t sosk
f0 [hz] f1 [hz] f2 [hz] f3 [hz] f4 [hz] a1 [ui p-p ] a2 [ui p-p ] a3 [ui p-p ] oc-3/sts-3 10 30 300 6.5k 65k 0.15 1.5 15 stm-1 0.125 19.3 500 6.5k 65k 0.15 1.5 15 figure 7. minimum required jitter tolerance on a sonet or sdh line. figure 8. minimum jitter tolerance of gd16523 (1 ui = 6400 ps). the total jitter on the inputs integrated from dc to a certain fre - quency may not exceed the shown curve. data sheet rev. 11 gd16523 page 8 of 10 jitter frequency [hz] slope = -20 db/decade slope = -20 db/decade jitter (log) [uipp] f 0 a 1 a 2 a 3 f 1 f 2 f 3 f 4 jitter frequency (log) [hz] slope = -20 db/decade input jitter (log) [uipp] 1.7 f lpf1
package outline figure 9. 100 pin tqfp. all dimensions are in mm. exposed heat slug is mounted on bottom of the package. data sheet rev. 11 gd16523 page 9 of 10
device marking tbd ordering information product name : package type: case temperature range: options: GD16523-100BA 100 pin edquad tqfp -40...+85 c gd16523,(club device) data sheet rev. 11 - date: 2 march 2000 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.giga.dk please check our internet web site for latest version of this data sheet. distributor: copyright ? 2000 giga a/s all rights reserved
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