 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| orca? or3lxxxb series device datasheet june 2010 all devices discontinued! product change notifications (pcns) have been issued to discontinue all devices in this data sheet. the original datasheet pages have not been modified and do not reflect those changes. please refer to the table below for refe rence pcn and current product status. product line ordering part number product status reference pcn or3l165b8ps208-db or3l165b7ps208-db or3l165b7ps208i-db or3l165b8ps240-db or3l165b7ps240-db or3l165b7ps240i-db pcn#06-07 or3l165b8ba352-db or3l165b7ba352-db or3l165b7ba352i-db OR3L165B8BC432-DB or3l165b7bc432-db or3l165b7bc432i-db or3l165b8bm680-db or3l165b7bm680-db or3lb165b or3l165b7bm680i-db discontinued pcn#09-10 or3l225b8bc432-db or3l225b7bc432-db or3l225b7bc432i-db or3l225b8bm680-db or3l225b7bm680-db or3l225b or3l225b7bm680i-db discontinued pcn#06-07 `` 5555 n.e. moore ct. z hillsboro, oregon 97124-6421 z phone (503) 268-8000 z fax (503) 268-8347 internet: http://www.latticesemi.com
data addendum march 2002 orca or3lxxxb series field-programmable gate arrays introduction this data addendum refers to the information found in the orca series 3c and 3t field-programmable gate arrays data sheet. features high-performance, cost-effective, 0.25 ? 5-level metal technology. 2.5 v internal supply voltage and 3.3 v i/o supply voltage for speed and compatibility. up to 340,000 usable gates in 0.25 ?. up to 612 user i/os in 0.25 ?. (or3lxxxb i/os are 5 v tolerant to allow interconnection to both 3.3 v and 5 v devices, selectable on a per-pin basis, when using 3.3 v i/o supply.) twin-quad programmable function unit (pfu) architecture with eight 16-bit look-up tables (luts) per pfu, organized in two nibbles for use in nibble- or byte-wide functions. allows for mixed arithmetic and logic functions in a single pfu. nine user registers per pfu, one following each lut, plus one extra. all have programmable clock enable and local set/reset, plus a global set/reset that can be disabled per pfu. flexible input structure (fins) of the pfus pro- vides a routability enhancement for luts with shared inputs and the logic ?xibility of luts with independent inputs. fast-carry logic and routing to adjacent pfus for nibble-wide, byte-wide, or longer arithmetic func- tions, with the option to register the pfu carry-out. softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu. supplemental logic and interconnect cell (slic) provides 3-statable buffers, up to 10-bit decoder, and pa l *-like and-or-invert (aoi) in each pro- grammable logic cell (plc). abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementa- tions and less routing delay. individually programmable drive capability: 12 ma sink/6 ma source or 6 ma sink/3 ma source. built-in boundary scan ( ieee ? 1149.1 jtag) and testability function to 3-state all i/o pins. enhanced system clock routing for low-skew, high- speed clocks originating on-chip or at any i/o. up to four expressclk inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. stopclk feature to glitchlessly stop/start the expressclks independently by user command. * pa l is a trademark of lattice semiconductor ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc. the usable gate counts range from a logic-only gate count to a gate count assuming 30% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates/pfu), including 12 gates per lut/ff pair (eight per pfu), and 12 gates per slic/ff pair (one per pfu). each of the four pios per pic is counted as 16 gates (three ffs, fast-capture latch, output logic, clk, and i/o buffers). pfus used as ram are counted at four gates per bit, with each pfu capable of implementing a 32 4 ram (or 512 gates) per pfu. table 1. orca or3lxxxb series fpgas device system gates luts registers max user ram user i/os array size process technology or3l165b 120k?44k 8192 10752 131k 516 32 32 0.25 ?/5 lm or3l225b 166k?40k 11552 14820 185k 612 38 38 0.25 ?/5 lm all devices discontinued table of contents contents page contents page data addendum march 2002 2 lattice semiconductor orca or3lxxxb series fpgas introduction................................................................ 1 features .................................................................... 1 system-level features.............................................. 4 support...................................................................... 5 description ................................................................ 5 fpga overview ...................................................... 5 plc logic ............................................................... 5 pic logic ................................................................ 8 system features ..................................................... 9 routing.................................................................... 9 con?uration........................................................... 9 configuration data format...................................... 9 series 3l i/os and 5 v tolerance......................... 10 designing with orca series 3t parts with series 3l in mind................................................ 10 powerup sequencing for series 3l devices......... 10 orca foundry development system .................. 11 additional information ........................................... 11 timing characteristics ............................................. 12 configuration timing............................................. 12 pfu timing ........................................................... 13 plc timing ........................................................... 19 slic timing .......................................................... 19 pio timing ............................................................ 20 special function blocks timing ............................ 23 clock timing ......................................................... 25 description ............................................................ 35 estimating power dissipation................................. 37 or3lxxxb............................................................ 37 pin information ....................................................... 38 absolute maximum ratings.................................... 76 recommended operating conditions .................... 76 electrical characteristics ........................................ 77 package thermal characteristics .......................... 78 ja ...................................................................... 78 jc ...................................................................... 78 jc ...................................................................... 78 jb ...................................................................... 78 fpga maximum junction temperature .............. 79 package coplanarity .............................................. 80 package parasitics................................................. 80 package outline diagrams..................................... 81 terms and definitions .......................................... 81 208-pin sqfp2.................................................... 82 240-pin sqfp2.................................................... 83 352-pin pbga ..................................................... 84 432-pin ebga ..................................................... 85 680-pin pbgam .................................................. 86 ordering information .............................................. 87 all devices discontinued lattice semiconductor 3 data addendum march 2002 orca or3lxxxb series fpgas table of contents (continued) figure page table page figure 1. simpli?d pfu diagram ............................... 6 figure 2. slic all modes diagram .............................. 7 figure 3. or3lxxx programmable input/output image from orca foundry.................................... 8 figure 4. synchronous memory write characteristics ............................................ 17 figure 5. synchronous memory read cycle............. 18 figure 6. expressclk to output delay ..................... 27 figure 7. fast clock to output delay......................... 28 figure 8. system clock to output delay ................... 29 figure 9. input to expressclk setup/hold time....... 31 figure 10. input to fast clock setup/hold time ........ 33 figure 11. input to system clock setup/hold time... 34 figure 12. package parasitics ................................... 80 table page table 1. orca or3lxxxb series fpgas ..................1 table 2. orca series 3l system performance ..........4 table 3. con?uration frame size .............................. 9 table 4. general con?uration mode timing characteristics ..................................................... 12 table 5. combinatorial pfu timing characteristics .. 13 table 6. sequential pfu timing characteristics ....... 14 table 7. ripple mode pfu timing characteristics .... 15 table 8. synchronous memory write characteristics............................................ 17 table 9. synchronous memory read characteristics............................................ 18 table 10. pfu output mux and direct routing timing characteristics.................. 19 table 11. supplemental logic and interconnect cell timing characteristics.............. 19 table 12. programmable i/o timing characteristics ......................................... 20 table 13. microprocessor interface (mpi) timing characteristics...................................................... 23 table 14. expressclk (eclk) and fast clock (fclk) timing characteristics ............................ 25 table 15. general-purpose clock timing characteristics (internally generated clock)....... 26 table 16. or3lxxx expressclk to output delay (pin-to-pin) .................................... 27 table 17. or3lxxx fast clock (fclk) to output delay (pin-to-pin) .................................... 28 table 18. or3lxxx general system clock (sclk) to output delay (pin-to-pin).................... 29 table 19. or3lxxx input to expressclk (eclk) fast-capture setup/hold time (pin-to-pin) ......... 30 table 20. or3lxxx input to fast clock setup/hold time (pin-to-pin)............................... 32 table 21. or3lxxx input to general system clock (sclk) setup/hold time (pin-to-pin) .................. 34 table 22. derating for commercial/industrial or3lxxx devices (i/o supply v dd ) .................... 36 table 23. derating for commercial/industrial or3lxxx devices (i/o supply v dd 2) .................. 36 table 24. 208-pin sqfp2 pinout .............................. 38 table 25. 240-pin sqfp2 pinout ............................. 41 table 26. 352-pin pbga pinout ................................ 44 table 27. 432-pin ebga pinout ............................... 49 table 28. 680-pin pbgam pinout ............................. 60 table 29. absolute maximum ratings....................... 76 table 30. recommended operating conditions ....... 76 table 31. electrical characteristics ........................... 77 table 32. plastic package thermal characteristics for the orca series............................................ 79 table 33. package coplanarity.................................. 80 table 34. package parasitics .................................... 80 table 35. voltage options ......................................... 87 table 36. temperature options ................................. 87 table 37. package options ....................................... 87 table 38. orca or3lxxxb series package matrix .................................................... 87 all devices discontinued 4 4 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas features (continued) programmable i/o (pio) has: ?fast-capture input latch and input ?p-?p (ff)/ latch for reduced input setup time and zero hold time. ?capability to (de)multiplex i/o signals. ?fast access to slic for decodes and pa l -like functions. ?output ff and two-signal function generator to reduce clk to output propagation delay. ?fast open-drain drive capability. new programmable i/o 3-state ff allows 3-state buffer control signals to be set up a clock cycle early for improved clock to output delays. system-level features system-level features reduce glue logic requirements and make a system on a chip possible. these features in the orca or3lxxxb include the following: full pci local bus compliance for all devices in 3.3 v and 5 v pci systems. pin-selectable i/o clamping diodes provide 3.3 v and 5 v compliance and 5 v tolerance. dual-use microprocessor interface (mpi) can be used for con?uration, readback, device control, and device status, as well as for a general-purpose inter- face to the fpga. glueless interface to i960 * and powerpc ? processors with user-con?urable address space provided. parallel readback of con?uration data capability with the built-in microprocessor interface. programmable clock manager (pcm) adjusts clock phase and duty cycle for input clock rates from 5 mhz to 120 mhz. the pcm may be combined with fpga logic to create complex functions, such as dig- ital phase-locked loops (dpll), frequency counters, and frequency synthesizers. two pcms are provided per device. true internal 3-state, bidirectional buses with simple control provided by the slic. 32 4 ram per pfu, con?urable as single- or dual- port. create large, fast ram/rom blocks (128 8 in only eight pfus) using the slic decoders as bank drivers. full utopia level iii i/o compliance (6.0 ns clk -> out, 2.0 ns setup with 0 ns hold). * i960 is a registered trademark of intel corporation. ? powerpc is a registered trademark of international business machines, inc. table 2 . orca series 3l system performance 1. implemented using 8 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. implemented using two 32 12 roms and one 12-bit adder, one 8-bit input, one ?ed operand, one 16-bit output. 3. implemented using 8 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 pfus contain only pipelining registers). 4. implemented using 32 4 ram mode with read data on 3-state buffer to bidirectional read/write bus. 5. implemented using 32 4 dual-port ram mode. 6. implemented in one partially occupied slic with decoded output set up to ce in same plc. 7. implemented in ?e partially occupied slics. parameter # pfus -7 -8 unit 16-bit loadable up/down counter 2 151 176 mhz 16-bit accumulator 2 151 176 mhz 8 8 parallel multiplier: multiplier mode, unpipelined 1 rom mode, unpipelined 2 multiplier mode, pipelined 3 11.5 8 15 38 93 129 46 116 152 mhz mhz mhz 32 16 ram (synchronous): single-port, 3-state bus 4 dual-port 5 4 4 173 231 209 277 mhz mhz 128 8 ram (synchronous): single-port, 3-state bus 4 dual-port 5 8 8 151 151 181 181 mhz mhz 8-bit address decode (internal): using softwired luts using slics 6 0.25 0 2.30 1.29 2.00 1.12 ns ns 32-bit address decode (internal): using softwired luts using slics 7 2 0 7.97 3.75 6.84 3.16 ns ns 36-bit parity check (internal) 2 7.97 6.84 ns all devices discontinued lattice semiconductor 5 data addendum march 2002 orca or3lxxxb series fpgas support orca foundry development system support. supported by industry-standard cae tools for design entry, synthesis, simulation, and timing analysis. description fpga overview the orca or3lxxxb fpgas are a new generation of sram-based fpgas built on the successful series 2 and series 3 fpga lines, with enhancements and innovations geared toward today s high-speed designs and tomorrow s systems on a single chip. designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the orca series 2 devices, the or3lxxxb series more than doubles the logic avail- able in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed. orca or3lxxxb devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges. the orca or3lxxxb series fpgas consist of three basic elements: plcs, programmable input/output cells (pics), and system-level features. an array of plcs is surrounded by pics. each plc contains a pfu, a slic, local routing resources, and con?uration ram. most of the fpga logic is performed in the pfu (see figure 1), but decoders, pa l -like functions, and 3-state buffering can be performed in the slic (see figure 2). the pics provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals (see figure 3). some of the system-level functions include the mpi and the pcm. plc logic each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one additional ff that may be used independently or with arithmetic func- tions. the pfu is organized in a twin-quad fashion: two sets of four luts and ffs that can be controlled indepen- dently. luts may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be con?ured as a synchronous 32 4 sin- gle- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected to plc routing resources and to the outputs of the pfu. it contains 3-state, bidirectional buffers and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pa l -like functions. the 3-state drivers in the slic and their direct connections to the pfu outputs make fast, true 3-state buses possible within the fpga, reducing required routing and allowing for real- world system performance. all devices discontinued 6 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas description (continued) note: all multiplexers without select inputs are con?uration selector multiplexers. figure 1. simpli?d pfu diagram 5-5743 sel cin d ce ck s/r ff8 regcout cout 1 aswe lsr k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 f5d k7_0 k7_1 k7_2 k5_3 k4_0 k4_1 k4_2 k4_3 f5c clk a b c d a b c d a b c d k4 k5 k6 k7 din7 din6 din5 din4 reg5 d0 d1 ce ck s/r dsel q5 f5 reg6 d0 d1 ce ck s/r dsel q6 f6 reg7 d0 d1 ce ck s/r dsel q7 f7 reg4 d0 d1 ce ck s/r dsel q4 f4 a b c d f5mode45 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 f5b k3_0 k3_1 k3_2 k1_3 k0_0 k0_1 k0_2 k0_3 f5a a b c d a b c d a b c d k0 k1 k2 k3 din3 din2 din1 din0 reg1 d0 d1 ce ck s/r dsel q1 f1 reg2 d0 d1 ce ck s/r dsel q2 f2 reg3 d0 d1 ce ck s/r dsel q3 f3 reg0 d0 d1 ce ck s/r dsel q0 f0 a b c d f5mode01 f5mode67 f5mode23 0 0 0 0 0 0 0 0 0 0 0 0 ce 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 all devices discontinued lattice semiconductor 7 data addendum march 2002 orca or3lxxxb series fpgas description (continued) 5-5744(f) figure 2. slic all modes diagram bri9 i9 bli9 bri8 i8 bli8 bri7 i7 bli7 bri6 i6 bli6 bri5 i5 bli5 bri4 i4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl09 br09 bl08 br08 bl07 br07 bl06 br06 bl05 br05 bl04 br04 bl03 br03 bl02 br02 bl01 br01 bl00 br00 dec dec 0/1 0/1 tri 0/1 0/1 high z when low all devices discontinued 8 8 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas description (continued) pic logic the or3lxxxb pic addresses the demand for ever- increasing system clock speeds. each pic contains four programmable inputs/outputs (pios) and routing resources. on the input side, each pio contains a fast- capture latch that is clocked by an expressclk. this latch is followed by a latch/ff that is clocked by a sys- tem clock from the internal general clock routing. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer. two input signals are available to the plc array from each pio, and the orca series 2 capability to use any input pin as a clock or other global input is maintained. on the output side of each pio, two outputs from the plc array can be routed to each output ?p-?p, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the i/o buffer associated with each pad is very similar to the series 2 buffer with a new, fast, open-drain option for ease of use on system buses. these features may also be combined with the new 3-state ff that allows the 3-state control signal to be registered. this allows for early control setup and faster clock-to-out times. 5-5805(f).a figure 3. or3lxxx programmable input/output image from orca foundry in2 in1 d0 d1 ck sp sd lsr inregmode latchff latch ff d ck normal inverted reset set level mode ttl cmos up down none pull-mode buffer ts fast slew sink reset set lsr sp ck d out1 out2 eclk sclk ce ce_over_lsr lsr_over_ce async lsr enable_gsr disable_gsr out1outreg out2outreg out1out2 nor xor xnor and nand or pio logic clkin 0 0 1 0 pad q q 1 pd to routing q 1 eclk sclk pmux from routing mode lsr ck d0 q all devices discontinued lattice semiconductor 9 data addendum march 2002 orca or3lxxxb series fpgas description (continued) system features the or3lxxxb series also provides system-level func- tionality by means of its dual-use mpi and its innovative pcm. these functional blocks allow for easy glueless system interfacing and the capability to adjust to vary- ing conditions in today s high-speed systems. the mpi provides a glueless interface between the fpga, powerpc, and i960 microprocessors. it can be used for con?uration and readback, as well as for monitoring fpga status. the mpi also provides a gen- eral-purpose microprocessor interface to the fpga user-de?ed logic following con?uration. two pcms are provided on each orca 3l device. each pcm can be used to manipulate the frequency, phase, and duty cycle of a clock signal. clocks may be input from the dedicated corner expressclk input (in the same corner as the pcm block) or from general routing. output clocks from the pcm can be sent to the system clock spines, and/or to the expressclk and fast clock spines on the edges of the device adjacent to the pcm. expressclk/fast clock and system clock out- put frequencies can differ by up to a factor of eight to allow slow i/o clocking with fast internal processing (or vice versa). each pcm is capable of manipulating clocks from 5 mhz to 120 mhz. frequencies can be adjusted from 1/8 to 64 the input clock frequency, duty cycles, and phase delays can be adjusted from 3.125% to 96.875%. routing the abundant routing resources of the orca 3lxxxb fpgas are organized to route signals individually or as buses with related control signals. clocks are routed on a low-skew, high-speed distribution network and may be sourced from plc logic, externally from any i/o pad, or from the very fast expressclk pins. expressclks may be glitchlessly and independently enabled and disabled with a programmable control sig- nal using the new stopclk feature. the improved pic routing resources are now similar to the patented intra- plc routing resources and provide great ?xibility in moving signals to and from the pios. this ?xibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to speci? pins. con?uration the fpga s functionality is determined by internal con- ?uration ram. the fpga s internal initialization/con- ?uration circuitry loads the con?uration data at powerup or under system control. the ram is loaded by using one of several con?uration modes. the con- ?uration data resides externally in an eeprom or any other storage media. serial eeproms provide a simple, low pin count method for con?uring fpgas. a new, easy method for con?uring the devices is through the microprocessor interface. con?uration data format the length and number of data frames and information on the prom size for the series or3lxxxb fpgas are given in table 3. table 3. configuration frame size devices 3l165b 3l225b number of frames 2136 2520 data bits/frame 502 592 con?uration data (number of frames number of data bits/frame) 1,072,272 1,552,320 maximum total number bits/frame (align bits, 01 frame start, 8-bit checksum, eight stop bits) 520 610 maximum con?uration data (number bits/frame number of frames) 1,110,720 1,537,200 maximum prom size (bits) (add con?uration header and postamble) 1,110,760 1,537,240 all devices discontinued 10 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas description (continued) series 3l i/os and 5 v tolerance series 3l devices use the same i/o structure as orca series 3t devices. orca series 3l devices use a 3.3 v supply (v dd ) to power the i/os and a 2.5 v sup- ply (v dd 2) to power the internal logic. because the i/o structure and voltage is common between 3t and 3l devices, the series 3l devices maintain 5 v tolerance and the same i/o characteristics as series 3t devices. the or3lxxxb uses a default mode that maintains a 5 v tolerant setting on all i/os. designing with orca series 3t parts with series 3l in mind due to many package compatibilities across device sizes and families, it is possible to design using a series 3t device today, and migrate to a series 3l device later. the pinouts are the same on both families with the exception of additional i/o voltage pins for the series 3l family. to design a board that is both series 3t compatible and series 3l compatible, using the following proce- dures will allow easy and fast component swapping from series 3t to series 3l. design to the series 3l pinouts, especially if planning to use the or3l225b pinout. the or3l225b has addi- tional power pins that are not on smaller series 3l parts. (note that if the designer is using a series 3l device smaller than the or3l225b, but may eventually migrate to a or3l225b, the or3l225b pinout should also be used). designing for series 3l in this manner does sacri?e some user i/o pins available in the series 3t (or smaller series 3l devices if using the or3l225b). these i/os will have power applied to them when a series 3t device is used on the board. however, this is acceptable and these i/os will default to 3-state outputs which eliminates any contention risk. design with two power planes: one for the internal sup- ply (2.5 v), and one for the i/o supply (3.3 v). for series 3t operation, connect both the internal supply and i/o voltage planes to 3.3 v. for series 3l opera- tion, change the core plane connection from 3.3 v to 2.5 v. powerup sequencing for series 3l devices orca series 3l devices use two power supplies: one to power the device i/os (v dd ) which is set to 3.3 v for 3.3 v operation and 5 v tolerance, and another supply for the internal logic (v dd 2) which is set to 2.5 v. it is understood that many users will derive the 2.5 v core logic supply from a 3.3 v power supply, so the following recommendations are made as to the powerup sequence of the supplies and allowable delays between power supplies reaching stable voltages. in general, both the 3.3 v and the 2.5 v supplies should ramp-up and become stable as close together in time as possible. there is no delay requirement if the v dd 2 (2.5 v) supply becomes stable prior to the v dd (3.3 v) supply. there is a delay requirement imposed if the v dd supply becomes stable prior to the v dd 2 supply. the requirement is that the v dd 2 (2.5 v) supply transi- tions from 0.8 v to 2.3 v within 15.7 ms when the v dd (3.3 v) supply is already stable at a minimum of 3.0 v. if the chosen power supplies cannot meet this delay requirement, it is always possible to delay con?uration of the fpga by asserting init or prgm until the v dd 2 supply has reached 2.3 v. this process eliminates any power supply sequencing issues. all devices discontinued lattice semiconductor 11 data addendum march 2002 orca or3lxxxb series fpgas description (continued) orca foundry development system the orca foundry development system is used to process a design from a netlist to a con?ured fpga. this system is used to map a design onto the orca architecture and then place and route it using orca foundry s timing-driven tools. the development system also includes interfaces to, and libraries for, other popu- lar cae tools for design entry, synthesis, simulation, and timing analysis. the orca foundry development system interfaces to front-end design entry tools and provides the tools to produce a con?ured fpga. in the design ?w, the user de?es the functionality of the fpga at two points in the design ?w: at design entry and at the bit stream generation stage. following design entry, the development system s map, place, and route tools translate the netlist into a routed fpga. a static timing analysis tool is provided to deter- mine device speed, and a back-annotated netlist can be created to allow simulation. timing and simulation output ?es from orca foundry are also compatible with many third-party analysis tools. its bit stream generator is then used to generate the con?uration data, which is loaded into the fpga s internal con?uration ram. when using the bit stream generator, the user selects options that affect the functionality of the fpga. com- bined with the front-end tools, orca foundry pro- duces con?uration data that implements the various logic and routing options discussed in this product brief. additional information contact your local lattice representative for additional information regarding the orca or3lxxxb fpga devices, or visit our website at: http://www.latticesemi.com . all devices discontinued 12 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics con?uration timing table 4. general con?uration mode timing characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. * not applicable to asynchronous peripheral mode. note: t po is triggered when v dd reaches between 2.7 v and 3.0 v for the or3lxxxb. symbol parameter min max unit all con?uration modes t smode m[3:0] setup time to init high 0.00 ns t hmode m[3:0] hold time from init high 600.00 ns t rw reset pulse width low to start recon?uration 50.00 ns t pgw prgm pulse width low to start recon?uration 50.00 ns master and asynchronous peripheral modes t po t cclk t cl power-on reset delay cclk period (m3 = 0) (m3 = 1) con?uration latency (autoincrement mode): or3l165b (m3 = 0) (m3 = 1) or3l225b (m3 = 0) (m3 = 1) 15.70 60.00 480.00 66.65 533.16 92.23 737.88 52.40 200.00 1600.00 222.15* 1777.22* 307.45* 2459.8* ms ns ns ms ms ms ms microprocessor (mpi) mode t po t cl power-on reset delay con?uration latency (autoincrement mode): or3l165b or3l225b 15.70 147,405 202,251 52.40 ms write cycles write cycles t pr partial recon?uration (explicit mode): or3l165b or3l225b 69 81 write cycles write cycles slave serial mode t po t cclk t cl power-on reset delay cclk period con?uration latency (autoincrement mode): or3l165b or3l225b 3.90 15.00 16.66 23.06 13.10 ms ns ms ms slave parallel mode t po t cclk t cl power-on reset delay cclk period: con?uration latency (normal mode): or3l165b or3l225b 3.90 15.00 2.08 2.88 13.10 ms ns t pr partial recon?uration (explicit mode): or3l165b or3l225b 1.0 1.2 ?/frame ?/frame all devices discontinued lattice semiconductor 13 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) in addition to supply voltage, process variation, and operating temperature, circuit and process improve- ments of the orca series fpgas over time will result in signi?ant improvement of the actual performance over those listed for a speed grade. even though lower speed grades may still be available, the distribution of yield to timing parameters may be several speed grades higher than that designated on a product brand. design practices need to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing. the routing delays are a function of fan-out and the capacitance associated with the con?urable interface points (cips) and metal interconnect in the path. the number of logic elements that can be driven (fan-out) by pfus is unlimited, although the delay to reach a valid logic level can exceed timing requirements. it is dif?ult to make accurate routing delay estimates prior to design compilation based on fan-out. this is because the cae software may delete redundant logic inserted by the designer to reduce fan-out, and/or it may also automatically reduce fan-out by net splitting. the waveform test points are given in the input/output buffer measurement conditions section of this data sheet. the timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and the values they re?ct are described below. propagation delay ?he time between the speci?d reference points. the delays provided are the worst case of the tphh and tpll delays for noninverting func- tions, tplh and tphl for inverting functions, and tphz and tplz for 3-state enable. setup time ?he interval immediately preceding the transition of a clock or latch enable signal, during which the data must be stable to ensure it is recognized as the intended value. hold time ?he interval immediately following the transition of a clock or latch enable signal, during which the data must be held stable to ensure it is recognized as the intended value. 3-state enable ?he time from when a 3-state control signal becomes active and the output pad reaches the high-impedance state. pfu timing table 5. combinatorial pfu timing characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. * four-input variables (k z [3:0]) path delays are valid for luts in both f4 (four-input lut) and f5 (?e-input lut) modes. symbol parameter -7 -8 unit min max min max f4_del f5_del swl2_del swl2f5_del swl3_del swl3f5_del co_del combinatorial delays (t j = +85 ?, v dd = min, v dd 2 = min) : four-input variables (kz[3:0] to f[z])* five-input variables (f5[a:d] to f[0, 2, 4, 6]) two-level lut delay (kz[3:0] to f w/feedbk)* two-level lut delay (f5[a:d] to f w/feedbk) three-level lut delay (kz[3:0] to f w/feedbk)* three-level lut delay (f5[a:d] to f w/feedbk) c in to c out delay (logic mode) 1.03 0.85 2.30 1.91 3.40 3.02 1.66 0.90 0.74 2.00 1.66 2.96 2.63 1.44 ns ns ns ns ns ns ns all devices discontinued 14 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 6. sequential pfu timing characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. * four-input variables (k z [3:0]) setup times are valid for luts in both f4 (four-input lut) and f5 (?e-input lut) modes. note: the table shows worst-case delays. orca foundry reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. symbol parameter -7 -8 unit min max min max input requirements clkl_mpw clock low time 1.00 0.87 ns clkh_mpw clock high time 0.76 0.66 ns gsr_mpw global s/r pulse width (gsrn) 1.00 0.87 ns lsr_mpw local s/r pulse width 1.00 0.87 ns f4_set f5_set din_set cindir_set ce1_set ce2_set lsr_set sel_set swl2_set swl2f5_set swl3_set swl3f5_set combinatorial setup times (t j = +85 ?, v dd = min, v dd 2 = min): four-input variables to clock (kz[3:0] to clk)* five-input variables to clock (f5[a:d] to clk) data in to clock (din[7:0] to clk) carry-in to clock, direct to regcout (cin to clk) clock enable to clock (ce to clk) clock enable to clock (aswe to clk) local set/reset to clock (sync) (lsr to clk) data select to clock (sel to clk) two-level lut to clock (kz[3:0] to clk w/feedbk)* two-level lut to clock (f5[a:d] to clk w/feedbk) three-level lut to clock (kz[3:0] to clk w/feedbk)* three-level lut to clock (f5[a:d] to clk w/feedbk) 0.90 0.51 0.21 0.68 1.41 1.11 0.69 0.64 1.79 1.46 3.06 2.67 0.78 0.44 0.18 0.59 1.23 0.97 0.60 0.55 1.55 1.27 2.66 2.32 ns ns ns ns ns ns ns ns ns ns ns ns din_hld cindir_hld ce1_hld ce2_hld lsr_hld sel_hld combinatorial hold times (t j = all, v dd = all): data in (din[7:0] from clk) carry-in from clock, direct to regcout (cin from clk) clock enable (ce from clk) clock enable from clock (aswe from clk) local set/reset from clock (sync) (lsr from clk) data select from clock (sel from clk) all others 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns ns ns ns ns ns output characteristics lsr_del gsr_del reg_del ltch_del ltchd_del sequential delays (t j = +85 ?, v dd = min, v dd 2 = min): local s/r (async) to pfu out (lsr to q[7:0], reg- cout) global s/r to pfu out (gsrn to q[7:0], regcout) clock to pfu out?egister (clk to q[7:0], reg- cout) clock to pfu out?atch (clk to q[7:0]) transparent latch (din[7:0] to q[7:0]) 2.82 2.21 1.22 1.30 1.43 2.46 1.92 1.06 1.13 1.25 ns ns ns ns ns all devices discontinued lattice semiconductor 15 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 7. ripple mode pfu timing characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. symbol parameter (t j = +85 ?, v dd = min, v dd 2 = min) -7 -8 unit min max min max rip_set frip_set fcin_set cin_set as_set riprc_set fcinrc_set cinrc_set asrc_set full ripple setup times (byte-wide): operands to clock (kz[1:0] to clk) bitwise operands to clock (kz[1:0] to clk at f[z]) fast carry-in to clock (fcin to clk) carry-in to clock (cin to clk) add/subtract to clock (aswe to clk) operands to clock (kz[1:0] to clk at regcout) fast carry-in to clock (fcin to clk at regcout) carry-in to clock (cin to clk at regcout) add/subtract to clock (aswe to clk at regcout) 1.58 0.90 1.21 1.68 4.70 1.02 1.03 1.48 4.51 1.37 0.78 1.05 1.46 4.09 0.89 0.90 1.29 3.92 ns ns ns ns ns ns ns ns ns fcinrc_hld full ripple hold times (t j = all, v dd = all): fast carry-in from clock (fcin from clk at reg- cout) all others 0.0 0.0 0.0 0.0 ns ns hrip_set hfrip_set hfcin_set hcin_set has_set hriprc_set hfcinrc_set hcinrc_set hasrc_set half ripple setup times (nibble wide): operands to clock (kz[1:0] to clk) bitwise operands to clock (kz[1:0] to clk at f[z]) fast carry-in to clock (fcin to clk) carry-in to clock (cin to clk) add/subtract to clock (aswe to clk) operands to clock (kz[1:0] to clk at regcout) fast carry-in to clock (fcin to clk at regcout) carry-in to clock (cin to clk at regcout) add/subtract to clock (aswe to clk at regcout) 1.74 0.90 1.21 1.68 4.70 1.37 1.03 1.48 4.51 1.51 0.78 1.05 1.46 4.09 1.19 0.90 1.29 3.92 ns ns ns ns ns ns ns ns ns hfcinrc_hld half ripple hold times (t j = all, v dd = all): fast carry-in from clock (hfcin from clk at re- cout) all others 0.0 0.0 0.0 0.0 ns ns note: the table shows worst-case delay for the ripple chain. orca foundry reports the delay for individual paths within the ripple chain that will be less than or equal to those listed above. all devices discontinued 16 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 7. ripple mode pfu timing characteristics (continued) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. symbol parameter (t j = +85 ?, v dd = min, v dd 2 = min) -7 -8 unit min max min max ripco_del ripfco_del rip_del frip_del fcinco_del fcinfco_del cinco_del cinfco_del fcin_del cin_del asco_del asfco_del as_del full ripple delays (byte-wide): operands to carry-out (kz[1:0] to cout) operands to carry-out (kz[1:0] to fcout) operands to pfu out (kz[1:0] to f[7:0]) bitwise operands to pfu out (kz[1:0] to f[z]) fast carry-in to carry-out (fcin to cout) fast carry-in to fast carry-out (fcin to fcout) carry-in to carry-out (cin to cout) carry-in to fast carry-out (cin to fcout) fast carry-in pfu out (fcin to f[7:0]) carry-in pfu out (cin to f[7:0]) add/subtract to carry-out (aswe to cout) add/subtract to carry-out (aswe to fcout) add/subtract to pfu out (aswe to f[7:0]) 2.26 2.23 3.21 1.03 1.36 1.33 1.66 1.61 2.03 2.65 4.67 4.58 5.61 1.97 1.94 2.79 0.90 1.18 1.15 1.44 1.40 1.77 2.31 4.06 3.98 4.88 ns ns ns ns ns ns ns ns ns ns ns ns ns hripco_del hripfco_del hrip_del hfrip_del hfcinco_del hfcinfco_del hcinco_del hcinfco_del hfcin_del hcin_del hasco_del hasfco_del has_del half ripple delays (nibble wide): operands to carry-out (kz[1:0] to cout) operands to fast carry-out (kz[1:0] to fcout) operands to pfu out (kz[1:0] to f[3:0]) bitwise operands to pfu out (kz[1:0] to f[z]) fast carry-in to carry-out (fcin to cout) fast carry-in to fast carry-out (fcin to fcout) carry-in to carry-out (cin to cout) carry-in to carry-out (cin to fcout) fast carry-in pfu out (fcin to f[3:0]) carry-in pfu out (cin to f[3:0]) add/subtract to carry-out (aswe to cout) add/subtract to carry-out (aswe to fcout) add/subtract to pfu out (aswe to f[3:0]) 2.26 2.23 2.61 1.03 1.36 1.33 1.66 1.61 1.72 2.40 4.67 4.58 5.00 1.97 1.94 2.27 0.90 1.18 1.15 1.44 1.40 1.50 2.09 4.06 3.98 4.34 ns ns ns ns ns ns ns ns ns ns ns ns ns note: the table shows worst-case delay for the ripple chain. orca foundry reports the delay for individual paths within the ripple chain that will be less than or equal to those listed above. all devices discontinued lattice semiconductor 17 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 8. synchronous memory write characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. * the ram is written on the inactive clock edge following the active edge that latches the address, data, and control signals. note: the table shows worst-case delays. orca foundry reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. 5-4621 (f)b figure 4. synchronous memory write characteristics symbol parameter -7 -8 unit min max min max write operation for ram mode smclk_frq smclkl_mpw smclkh_mpw mem_del maximum frequency clock low time clock high time clock to data valid (clk to f[6, 4, 2, 0])* 1.03 1.96 266.4 4.39 0.90 1.71 333.0 3.82 mhz ns ns ns write operation setup time wa4_set wa_set wd_set we_set wpe0_set wpe1_set address to clock (cin to clk) address to clock (din[7, 5, 3, 1] to clk) data to clock (din[6, 4, 2, 0] to clk) write enable (wren) to clock (aswe to clk) write-port enable 0 (wpe0) to clock (ce to clk) write-port enable 1 (wpe1) to clock (lsr to clk) 0.68 0.35 0.21 0.37 0.87 1.10 0.59 0.30 0.18 0.32 0.75 0.95 ns ns ns ns ns ns write operation hold time wa4_hld wa_hld wd_hld we_hld wpe0_hld wpe1_hld address from clock (cin from clk) address from clock (din[7, 5, 3, 1] from clk) data from clock (din[6, 4, 2, 0] from clk) write enable (wren) from clock (aswe from clk) write-port enable 0 (wpe0) from clock (ce from clk) write-port enable 1 (wpe1) from clock (lsr from clk) 0.0 0.0 0.33 0.0 0.0 0.0 0.0 0.0 0.29 0.0 0.0 0.0 ns ns ns ns ns ns ck f[6, 4, 2, 0] cin, din[7, 5, 3, 1] din[6, 4, 2, 0] mem_del wa4_set aswe (wren) ce (wpe0), smclkh_mpw smclkl_mpw wa4_hld wd_set wd_hld we_set we_hld wpe0_set wpe0_hld wa_set wa_hld wpe1_set wpe1_hld lsr(wpe1) all devices discontinued 18 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 9. synchronous memory read characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. note: the table shows worst-case delays. orca foundry reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. 5-4622(f) figure 5. synchronous memory read cycle symbol parameter (t j = 85 ?, v dd = min, v dd 2 = min) -7 -8 unit min max min max read operation ra_del ra4_del data valid after address (kz[3:0] to f[6, 4, 2, 0]) data valid after address (f5[a:d] to f[6, 4, 2, 0]) 1.03 0.85 0.90 0.74 ns ns read operation, clocking data into latch/ff ra_set ra4_set ra_hld ra4_hld reg_del smrd_cyc address to clock setup time (kz[3:0] to clk) address to clock setup time (f5[a:d] to clk) address from clock hold time (kz[3:0] from clk) address from clock hold time (f5[a:d] from clk) clock to pfu output?egister (clk to q[6, 4, 2, 0]) read cycle delay 0.90 0.51 0.0 0.0 1.22 5.38 0.78 0.44 0.0 0.0 1.06 4.68 ns ns ns ns ns ns kz[3:0], f5[a:d] f[6, 4, 2, 0] ck q[3:0] ra_del ra4_del ra_set ra4_set reg_del ra_hld ra4_hld all devices discontinued lattice semiconductor 19 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) plc timing table 10. pfu output mux and direct routing timing characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. * this is general feedback using switching segments. see the combinatorial pfu timing table for softwired look-up table feedback timing. slic timing table 11. supplemental logic and interconnect cell timing characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. symbol parameter (t j = 85 ?, v dd = min, v dd 2 = min) -7 -8 unit min max min max pfu output mux ( fan-out = 1) omux_del coo9_del rcoo8_del output mux delay (f[7:0]/q[7:0] to o[9:0]) carry-out mux delay (cout to o9) registered carry-out mux delay (regcout to o8) 0.76 0.74 0.74 0.66 0.64 0.64 ns ns ns direct routing fdbk_del odir_del ddir_del pfu feedback (xsw)* pfu to orthogonal pfu delay (xsw to xsw) pfu to diagonal pfu delay (xbid to xsw) 0.75 0.89 1.61 0.65 0.78 1.40 ns ns ns symbol parameter (t j = 85 ?, v dd = min, v dd 2 = min) -7 -8 unit min max min max 3-statable bidis buf_del obuf_del tri_del dectri_del bidi delay (brx to blx, blx to brx) bidi delay (ox to brx, ox to blx) bidi 3-state enable/disable delay (tri to bl, br) bidi 3-state enable/disable delay (bl, br via dec, tri to bl, br) 0.70 0.61 1.18 2.01 0.61 0.53 1.03 1.75 ns ns ns ns decoder dec98_del dec_del decoder delay (br[9:8], bl[9:8] to dec) decoder delay (br[7:0], bl[7:0] to dec) 1.16 1.29 1.01 1.12 ns ns all devices discontinued 20 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) pio timing. table 12. programmable i/o timing characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. symbol parameter -7 -8 unit min max min max input delays (t j = 85 ?, v dd = min, v dd 2 = min) in_ris input rise time 575 500 ns in_fal input fall time 575 500 ns ckin_del in_del ind_del pio direct delays: pad to in (pad to clk in) pad to in (pad to in1, in2) pad to in delayed (pad to in1, in2) 0.77 1.35 11.55 0.55 1.07 9.89 ns ns ns latch_del latchd_del pio transparent latch delays: pad to in (pad to in1, in2) pad to in delayed (pad to in1, in2) 2.79 12.46 2.42 10.87 ns ns inrege_set inreged_set inreg_set inregd_set ince_set inlsr_set input latch/ff setup timing: pad to expressclk (fast-capture latch/ff) pad delayed to expressclk (fast-capture latch/ff) pad to clock (input latch/ff) pad delayed to clock (input latch/ff) clock enable to clock (ce to clk) local set/reset (sync) to clock (lsr to clk) 4.54 14.53 0.65 10.90 0.92 0.81 2.62 11.63 0.46 9.50 0.82 0.73 ns ns ns ns ns ns inrege_hld inreged_hld inreg_hld inregd_hld ince_hld inlsr_hld input ff/latch hold timing: pad from expressclk (fast-capture latch/ff) pad delayed from expressclk (fast-capture latch/ff) pad from clock (input latch/ff) pad delayed from clock (input latch/ff) clock enable from clock (ce from clk) local set/reset (sync) from clock (lsr from clk) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns ns ns ns ns inreg_del inltch_del inlsr_del inlsrl_del ingsr_del clock-to-in delay (ff clk to in1, in2) clock-to-in delay (latch clk to in1, in2) local s/r (async) to in (lsr to in1, in2) local s/r (async) to in (lsr to in1, in2) latch/ff in latch mode global s/r to in (gsrn to in1, in2) 1.94 1.94 2.95 2.64 2.69 1.68 1.68 2.55 2.30 2.34 ns ns ns ns ns note: the delays for all input buffers assume an input rise/fall time of < 1 v/ns. all devices discontinued lattice semiconductor 21 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 12. programmable i/o timing characteristics (continued) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. note: the delays for all input buffers assume an input rise/fall time of <1 v/ns symbol parameter -7 -8 unit min max min max output delays (t j = 85 ?, v dd = min, c l = 50 pf) outf_del outsl_del outsi_del output to pad (out2, out1 direct to pad): fast slewlim sinklim 3.79 4.71 10.14 3.21 3.91 8.84 ns ns ns tsf_del tssl_del tssi_del 3-state enable/disable delay (ts to pad): fast slewlim sinklim 3.86 4.66 10.24 3.29 3.99 8.92 ns ns ns outlsrf_del outlsrsl_del outlsrsi_del local set/reset (async) to pad (lsr to pad): fast slewlim sinklim 5.70 6.58 12.09 4.90 5.60 10.52 ns ns ns outgsrf_del outgsrsl_del outgsrsi_del global set/reset to pad (gsrn to pad): fast slewlim sinklim 5.05 5.75 10.60 4.81 5.51 10.43 ns ns ns oute_set out_set outce_set outlsr_set output ff setup timing: out to expressclk (out[2:1] to eclk) out to clock (out[2:1] to clk) clock enable to clock (ce to clk) local set/reset (sync) to clock (lsr to clk) 0.0 0.0 0.44 0.05 0.0 0.0 0.39 0.04 ns ns ns ns oute_hld out_hld outce_hld outlsr_hld output ff hold timing: out from expressclk (out[2:1] from eclk) out from clock (out[2:1] from clk) clock enable from clock (ce from clk) local set/reset (sync) from clock (lsr from clk) 0.32 0.32 0.0 0.0 0.28 0.28 0.0 0.0 ns ns ns ns outregf_del outregsl_del outregsi_del clock to pad delay (eclk, sclk to pad): f ast slewlim sinklim 4.67 5.55 11.05 4.02 4.72 9.64 ns ns ns od_del additional delay if using open drain 0.11 0.09 ns all devices discontinued 22 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 12. programmable i/o timing characteristics (continued) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. note: the delays for all input buffers assume an input rise/fall time of < 1 v/ns. symbol parameter -7 -8 unit min max min max pio logic block delays outlf_del outlsl_del outlsi_del out to pad (out[2:1] via logic to pad): fast slewlim sinklim 3.79 4.71 10.14 3.21 3.91 8.84 ns ns ns outrf_del outrsl_del outrsi_del outreg to pad (outreg via logic to pad): fast slewlim sinklim 4.67 5.55 11.05 4.02 4.72 9.64 ns ns ns outcf_del outcsl_del outcsi_del clock to pad (eclk, clk via logic to pad): fast slewlim sinklim 4.54 5.44 10.92 3.90 4.60 9.53 ns ns ns 3-state ff delays tsf_del tssl_del tssi_del 3-state enable/disable delay (ts direct to pad): fast slewlim sinklim 3.86 4.66 10.24 3.29 3.99 8.92 ns ns ns tslsrf_del tslsrsl_del tslsrsi_del local set/reset (async) to pad (lsr to pad): fast slewlim sinklim 5.13 5.93 11.51 4.38 5.08 10.01 ns ns ns tsgsrf_del tsgsrsl_del tsgsrsi_del global set/reset to pad (gsrn to pad): fast slewlim sinklim 4.65 5.35 10.20 4.28 4.98 9.91 ns ns ns tse_set ts_set tslsr_set 3-state ff setup timing: ts to expressclk (ts to eclk) ts to clock (ts to clk) local set/reset (sync) to clock (lsr to clk) 0.0 0.0 0.0 0.0 0.0 0.0 ns ns ns tse_hld ts_hld tslsr_hld 3-state ff hold timing: ts from expressclk (ts from eclk) ts from clock (ts from clk) local set/reset (sync) from clock (lsr from clk) 0.34 0.34 0.0 0.30 0.30 0.0 ns ns ns tsregf_del tsregsl_del tsregsi_del clock to pad delay (eclk, sclk to pad): fast slewlim sinklim 4.09 4.90 10.48 3.49 4.19 9.12 ns ns ns all devices discontinued lattice semiconductor 23 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) special function blocks timing table 13. microprocessor interface (mp i) timing characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. 1. for user system ?xibility, cs0 and cs1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when mpi_strb is low. if both chip selects are valid and the setup time is met, the mpi will latch the chip select state, and cs0 and cs1 may go inactive before the end of the read/write cycle. 2. 0.5 mpi_clk. 3. write data and w/r have to be valid starting from the clock cycle after both ads and cs0 and cs1 are recognized. 4. write data and w/r have to be held until the microprocessor receives a valid rd yrcv . 5. user logic delay has no prede?ed value. the user must generate a uend signal to complete the cycle. 6. ustart_del is based on the falling clock edge. 7. there is no speci? time associated with this delay. the user must assert uend low to complete this cycle. 8. the user must assert interrupt request low until a service routine is executed. 9. this should be at least one mpi_clk cycle. 10. user should set up read data so that rds_set and rds_hld can be met for the microprocessor timing. notes: read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host ( powerpc , i960 ) from the fpga. powerpc and i960 timings to/from the clock are relative to the clock at the fpga microprocessor interface clock pin (mpi_clk). symbol parameter ? ? unit min max min max powerpc interface timing (t j = 85 ?, v dd = min, v dd 2 = min) ta_del bi_del ta_delz bi_delz wd_set wd_hld a_set a_hld rw_set rw_hld cs_set cs_hld ua_del urdwr_del transfer acknowledge delay (clk to t a ) burst inhibit delay (clk to bin) transfer acknowledge delay to high impedance 2 burst inhibit delay to high impedance 2 write data setup time (data to ts ) write data hold time (data from clk while mpi_ack low) address setup time (addr to ts ) address hold time (addr from clk while mpi_a ck low) read/write setup time (r/w to ts ) read/write hold time (r/w from clk while mpi_a ck low) chip select setup time (cs0 , cs1 to ts ) chip select hold time (cs0 , cs1 from clk) user address delay (pad to ua[3:0]) user read/write delay (pad to urdwr_del) 0.0 0.0 0.0 0.0 0.0 0.0 0.46 0.0 9.50 9.40 2.20 4.60 0.0 0.0 0.0 0.0 0.0 0.0 0.40 0.0 8.30 8.20 1.90 4.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns i960 interface timing (t j = 85 ?, v dd = min, v dd 2 = min) adsn_set adsn_hld rdyrcv_del rdyrcv_delz wd_set wd_hld a_set a_hld be_set be_hld addr/data select to ale (ads , to ale low) addr/data select to ale (ads , from ale low) ready/receive delay (clk to rd yrcv ) ready/receive delay to high impedance 2 write data setup time 3 write data hold time 4 address setup time (addr to ale low) address hold time (addr from ale low) byte enable setup time (be0 , be1 to ale low) byte enable hold time (be0 , be1 from ale low) 0.0 0.80 0.80 9.50 0.12 0.12 0.0 0.70 0.70 8.30 0.10 0.10 ns ns ns ns ns ns ns ns ns ns all devices discontinued 24 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 13. microprocessor interface (mp i) timing characteristics (continued) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. 1. for user system ?xibility, cs0 and cs1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when mpi_strb is low. if both chip selects are valid and the setup time is met, the mpi will latch the chip select state, and cs0 and cs1 may go inactive before the end of the read/write cycle. 2. 0.5 mpi_clk. 3. write data and w/r have to be valid starting from the clock cycle after both ads and cs0 and cs1 are recognized. 4. write data and w/r have to be held until the microprocessor receives a valid rd yrcv . 5. user logic delay has no prede?ed value. the user must generate a uend signal to complete the cycle. 6. ustart_del is based on the falling clock edge. 7. there is no speci? time associated with this delay. the user must assert uend low to complete this cycle. 8. the user must assert interrupt request low until a service routine is executed. 9. this should be at least one mpi_clk cycle. 10. user should set up read data so that rds_set and rds_hld can be met for the microprocessor timing. notes: read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host ( powerpc , i960 ) from the fpga. powerpc and i960 timings to/from the clock are relative to the clock at the fpga microprocessor interface clock pin (mpi_clk). symbol parameter ? ? unit min max min max i960 interface timing (t j = 85 ?, v dd = min, v dd 2 = min) (continued) rw_set rw_hld cs_set cs_hld ua_del urdwr_del read/write setup time 3 read/write hold time 4 chip select setup time (cs0 , cs1 to clk) 1 chip select hold time (cs0 , cs1 from clk) 1 user address delay (clk low to ua[3:0]) user read/write delay (pad to urdwr_del) 0.80 0.0 6.21 4.60 0.70 0.0 5.40 4.00 ns ns ns ns ns ns user logic delay 5 ustart_del user start delay (mpi_clk falling to ustart) 6 3.80 3.30 ns ustartclr_del user start clear delay (mpi_clk to ustart) 6.90 6.00 ns uend_del user end delay (ustart low to uend low) 7 ns synchronous user timing uend_set user end setup (uend to mpi_clk) 0.0 0.0 ns uend_hld user end hold (uend to mpi_clk) 1.40 1.20 ns rds_set data setup for read (d[7:0] to mpi_clk) 9 ns rds_hld data hold for read (d[7:0] from mpi_clk) 9 ns asynchronous user timing rda_del user end to read data delay (uend to d[7:0]) 10 ns rda_hld data hold from user start (low) 9 ns tuirq_pw interrupt request pulse width 8 ns all devices discontinued lattice semiconductor 25 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) clock timing table 14 . expressclk (eclk) and fast clock (fclk) timing characteristics or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. notes: the eclk delays are to all of the pics on one side of the device for middle pin input, or two sides of the device for corner pin input. the delay includes both the input buffer delay and the clock routing to the pic clock input. the fclk delays are for a fully routed clock tree that uses the expressclk input into the fast clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. symbol device (t j = 85 ?, v dd = min, v dd 2 = min) -7 -8 unit min max min max eclkc_del clock control timing delay through clkcntrl (input from corner) 0.31 0.27 ns eclkm_del delay through clkcntrl (input from internal clock controller pad) 1.06 0.92 ns offm_set offm_hld offc_set offc_hld clock shutoff timing: setup from middle eclk (shut off to clk) hold from middle eclk (shut off from clk) setup from corner eclk (shut off to clk) hold from corner eclk (shut off from clk) 0.41 0.0 0.41 0.0 0.36 0.0 0.36 0.0 ns ns ns ns eclkm_del eclk delay (middle pad): or3l165 or3l225 2.32 2.37 2.02 2.07 ns ns eclkc_del eclk delay (corner pad): or3l165 or3l225 5.02 5.27 4.23 4.45 ns ns fclkm_del fclk delay (middle pad): or3l165 or3l225 5.74 6.04 5.06 5.35 ns ns fclkc_del fclk delay (corner pad): or3l165 or3l225 8.41 8.89 7.24 7.68 ns ns all devices discontinued 26 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 15. general-purpose clock timing characteristics (internally generated clock) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. notes: this table represents the delay for an internally generated clock from the clock tree input in one of the four middle pics (using psw routing) on any side of the device which is then distributed to the pfu/pio clock inputs. if the clock tree input used is located at any other pic, see the results reported by orca foundry. this clock delay is for a fully routed clock tree that uses the general clock network. the delay will be reduced if any of the clock branches are not used. see pin-to-pin timing in table 18 for clock delays of clocks input on general i/o pins. symbol device (t j = 85 ?, v dd = min, v dd 2 = min) -7 -8 unit min max min max clk_del or3l165 4.56 3.98 ns clk_del or3l225 4.58 3.99 ns all devices discontinued lattice semiconductor 27 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 16. or3lxxx expressclk to output delay (pin-to-pin) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. notes: timing is without the use of the pcm. this clock delay is for a fully routed clock tree that uses the expressclk network. it includes both the input buffer delay, the clock routing to the pio clk input, the clock q of the ff, and the delay through the output buffer. the given timing requires that the input clock pin be located at one of the six expressclk inputs of the device, and that a pio ff be used. 5-4846 (f)c figure 6. expressclk to output delay description (t j = 85 ?, v dd = min, v dd 2 = min) device -7 -8 unit min max min max eclk middle input pin output pin (fast) or3l165 or3l225 6.94 6.99 5.84 5.89 ns ns eclk middle input pin output pin (slewlim) or3l165 or3l225 7.79 7.84 6.64 6.69 ns ns eclk middle input pin output pin (sinklim) or3l165 or3l225 12.91 12.96 11.08 11.13 ns ns additional delay if eclk corner pin used or3l165 or3l225 2.70 2.90 2.21 2.38 ns ns output (50 pf load) qd eclk pio ff all devices discontinued 28 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 17. or3lxxx fast clock (fclk) to output delay (pin-to-pin) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. notes: timing is without the use of the pcm. this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay, the clock routing to the pio clk input, the clock q of the ff, and the delay through the output buffer. the delay will be reduced if any of the clock branches are not used. the given timing requires that the input clock pin be located at one of the six expressclk inputs of the device and that a pio ff be used. 5-4846(f).b figure 7. fast clock to output delay description (t j = 85 ?, v dd = min, v dd 2 = min) device -7 -8 unit min max min max output not on same side of device as input clock (fast clock delays using expressclk inputs) eclk middle input pin output pin (fast) or3l165 or3l225 10.37 10.66 8.89 9.17 ns ns eclk middle input pin output pin (slewlim) or3l165 or3l225 11.22 11.54 9.69 9.97 ns ns eclk middle input pin output pin (sinklim) or3l165 or3l225 16.33 16.63 14.13 14.41 ns ns additional delay if eclk corner pin used or3l165 or3l225 2.66 2.85 2.17 2.33 ns ns output (50 pf load) qd eclk fclk pio ff clkcntrl all devices discontinued lattice semiconductor 29 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 18. or3lxxx general system clock (sclk) to output delay (pin-to-pin) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. note: this clock delay is for a fully routed clock tree that uses the primary clock network. it includes both the input buffer delay, the clock routing to the pio clk input, the clock q of the ff, and the delay through the output buffer. the delay will be reduced if any of the clock branches are not used. the given timing requires that the input clock pin be located at one of the four center pics on any side of the device and that a pio ff be used. for clock pins located at any other pio, see the results reported by orca foundry. 5-4846(f) figure 8. system clock to output delay description (t j = 85 ?, v dd = min, v dd 2 = min) device -7 -8 unit min max min max output on same side of device as input clock (system clock delays using general user i/o inputs) clock input pin (mid-pic) output pin (fast) or3l165 or3l225 11.81 12.32 10.06 10.54 ns ns clock input pin (mid-pic) output pin (slewlim) or3l165 or3l225 12.66 13.16 11.85 11.34 ns ns clock input pin (mid-pic) output pin (sinklim) or3l165 or3l225 17.78 18.28 15.29 15.78 ns ns additional delay if non-mid-pic used as clock pin or3l165 or3l225 1.04 1.43 1.03 1.43 ns ns output not on same side of device as input clock (system clock delays using general user i/o inputs) additional delay if output not on same side as input clock pin or3l165 or3l225 1.04 1.43 1.03 1.43 ns ns output (50 pf load) qd sclk pioff all devices discontinued 30 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 19 . or3lxxx input to expressclk (eclk) fast-capture setup/hold time (pin-to-pin) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. notes: the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. the eclk delays are to all of the pios on one side of the device for middle pin input, or two sides of the device for corner pin input. the delay includes both the input buffer delay and the clock routing to the pio clock input. description (t j = 85 ?, v dd = min, v dd 2 = min) device -7 -8 unit min max min max input to eclk setup time (middle eclk pin) or3l165 or3l225 2.63 2.61 0.96 0.95 ns ns input to eclk setup time (middle eclk pin, delayed data input) or3l165 or3l225 12.62 12.60 9.97 9.96 ns ns input to eclk setup time (corner eclk pin) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns input to eclk setup time (corner eclk pin, delayed data input) or3l165 or3l225 10.33 10.13 8.09 7.93 ns ns input to eclk hold time (middle eclk pin) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns input to eclk hold time (middle eclk pin, delayed data input) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns all devices discontinued lattice semiconductor 31 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 19. or3lxxx input to expressclk (eclk) fast-capture setup/hold time (pin-to-pin) (continued) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. notes: the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. the eclk delays are to all of the pios on one side of the device for middle pin input, or two sides of the device for corner pin input. the delay includes both the input buffer delay and the clock routing to the pio clock input. 5-4847(f).b figure 9. input to expressclk setup/hold time description (t j = 85 ?, v dd = min, v dd 2 = min) device -7 -8 unit min max min max input to eclk hold time (corner eclk pin) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns input to eclk hold time (corner eclk pin, delayed data input) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns qd clk input pio eclk latch clkcntrl eclk all devices discontinued 32 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 20. or3lxxx input to fast clock setup/hold time (pin-to-pin) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. notes: the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. the fclk delays are for a fully routed clock tree that uses the expressclk input into the fast clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. description (t j = 85 ?, v dd = min, v dd 2 = min) device -7 -8 unit min max min max output not on same side of device as input clock (fast clock delays using expressclk inputs) input to fclk setup time (middle eclk pin) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns input to fclk setup time (middle eclk pin, delayed data input) or3l165 or3l225 6.39 6.37 5.56 5.55 ns ns input to fclk setup time (corner eclk pin) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns input to fclk setup time (corner eclk pin, delayed data input) or3l165 or3l225 4.17 3.97 3.76 3.58 ns ns input to fclk hold time (middle eclk pin) or3l165 or3l225 4.93 5.22 4.44 4.72 ns ns all devices discontinued lattice semiconductor 33 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 20. or3lxxx input to fast clock setup/hold time (pin-to-pin) (continued) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. notes: the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. the fclk delays are for a fully routed clock tree that uses the expressclk input into the fast clock network. it includes both the input buffer delay and the clock routing to the pfu clk input. the delay will be reduced if any of the clock branches are not used. 5-4847(f).a figure 10. input to fast clock setup/hold time description (t j = 85 ?, v dd = min, v dd 2 = min) device -7 -8 unit min max min max input to fclk hold time (middle eclk pin, delayed data input) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns input to fclk hold time (corner eclk pin) or3l165 or3l225 7.59 8.08 6.61 7.06 ns ns input to fclk hold time (corner eclk pin, delayed data input) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns qd eclk input pio ff clkcntrl fclk all devices discontinued 34 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 21. or3lxxx input to general system clock (sclk) setup/hold time (pin-to-pin) or3lxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. notes: the pin-to-pin timing parameters in this table should be used instead of results reported by orca foundry. this clock delay is for a fully routed clock tree that uses the clock network. it includes both the input buffer delay and the clock routing to the pio ff clk input. the delay will be reduced if any of the clock branches are not used. the given setup (delayed and no delay) and hold (delayed) timing allows the input clock pin to be located in any pio on any side of the device, but a pio ff must be used. the hold (no delay) timing assumes the clock pin is located at one of the four middle pics on any side of the device and that a pio ff is used. if the clock pin is located elsewhere, then the last parameter in the table must be added to the hold (no delay) timing. 5-4847 (f) figure 11. input to system clock setup/hold time description (t j = 85 ?, v dd = min, v dd 2 = min) device -7 -8 unit min max min max input to sclk setup time or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns input to sclk setup time (delayed data input) or3l165 or3l225 5.69 5.57 5.07 4.96 ns ns input to sclk hold time or3l165 or3l225 6.46 6.96 5.67 6.16 ns ns input to sclk hold time (delayed data input) or3l165 or3l225 0.0 0.0 0.0 0.0 ns ns additional hold time if non-mid-pic used as sclk pin (no delay on data input) or3l165 or3l225 1.04 1.43 1.03 1.43 ns ns qd clk input pio eclk latch clkcntrl eclk all devices discontinued lattice semiconductor 35 data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) description to de?e speed grades, the orca series part number designation (see ordering information) uses a single- digit number to designate a speed grade. this number is not related to any single ac parameter. higher num- bers indicate a faster set of timing parameters. the actual speed sorting is based on testing the delay in a path consisting of an input buffer, combinatorial delay through all plcs in a row, and an output buffer. other tests are then done to verify other delay parameters, such as routing delays, setup times to ffs, etc. the most accurate timing characteristics are reported by the timing analyzer in the orca foundry develop- ment system. a timing report provided by the develop- ment system after layout divides path delays into logic and routing delays. the timing analyzer can also pro- vide logic delays prior to layout. while this allows rout- ing budget estimates, there is wide variance in routing delays associated with different layouts. the logic timing parameters noted in the electrical characteristics section of this data sheet are the same as those in the design tools. in the pfu timing, symbol names are generally a concatenation of the pfu oper- ating mode and the parameter type. the setup, hold, and propagation delay parameters, de?ed below, are designated in the symbol name by the set, hld, and del characters, respectively. the values given for the parameters are the same as those used during production testing and speed bin- ning of the devices. the junction temperature and sup- ply voltage used to characterize the devices are listed in the delay tables. actual delays at nominal tempera- ture and voltage for best-case processes can be much better than the values given. it should be noted that the junction temperature used in the tables is generally 85 ?. the junction temperature for the fpga depends on the power dissipated by the device, the package thermal characteristics ( ja ), and the ambient temperature, as calculated in the following equation and as discussed further in the package thermal characteristics section: t jmax = t amax + (p ? ja ) ? note : the user must determine this junction tempera- ture to see if the delays from orca foundry should be derated based on the following derat- ing tables. table 22 and table 23 provide approximate power sup- ply and junction temperature derating for or3lxxx commercial and industrial devices. the delay values in this data sheet and reported by orca foundry are shown as 1.00 in the tables. the method for determin- ing the maximum junction temperature is de?ed in the package thermal characteristics section. taken cumu- latively, the range of parameter values for best-case vs. worst-case processing, supply voltage, and junction temperature can approach three to one. all devices discontinued 36 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas timing characteristics (continued) table 22. derating for commercial/industrial or3lxxx devices (i/o supply v dd ) table 23. derating for commercial/industrial or3lxxx devices (i/o supply v dd 2) note: the derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. since the routing delay derates at a higher rate than the logic delay, paths with more than 66% routing delay will derate at a higher rate than shown in the table. the approximate derating values vs. temperature are 0.26% per ? for logic delay and 0.45% per ? for routing delay. the approximate derating values vs. voltage are 0.13% per mv for both logic and routing delays at 25 ?. in addition to supply voltage, process variation, and operating temperature, circuit and process improve- ments of the orca series fpgas over time will result in signi?ant improvement of the actual performance over those listed for a speed grade. even though lower speed grades may still be available, the distribution of yield to timing parameters may be several speed grades higher than that designated on a product brand. design practices need to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing. the routing delays are a function of fan-out and the capacitance associated with the cips and metal inter- connect in the path. the number of logic elements that can be driven (fan-out) by pfus is unlimited, although the delay to reach a valid logic level can exceed timing requirements. it is dif?ult to make accurate routing delay estimates prior to design compilation based on fan-out. this is because the cae software may delete redundant logic inserted by the designer to reduce fan- out, and/or it may also automatically reduce fan-out by net splitting. t j (?) power supply voltage 3.0 v 3.3 v 3.6 v ?0 0.82 0.72 0.66 0 0.91 0.80 0.72 25 0.98 0.85 0.77 85 1.00 0.99 0.90 100 1.23 1.07 0.94 125 1.34 1.15 1.01 t j (?) power supply voltage 2.3 v 2.5 v 2.6 v ?0 0.86 0.71 0.67 0 0.94 0.79 0.73 25 0.99 0.84 0.77 85 1.00 0.99 0.92 100 1.23 1.05 0.96 125 1.33 1.13 1.03 all devices discontinued lattice semiconductor 37 data addendum march 2002 orca or3lxxxb series fpgas estimating power dissipation or3lxxxb the total operating power dissipated is estimated by adding the standby (i ddsb ), internal, and external power dissipated. the internal and external power is the power consumed in the plcs and pics, respec- tively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = p plc + p pic the internal operating power is made up of two parts: clock generation and pfu output power. the pfu out- put power can be estimated based upon the number of pfu outputs switching when driving an average fan-out of two: p pfu = 0.078 mw/mhz for each pfu output that switches, 0.136 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be esti- mated by using one-half the clock rate, multiplied by some activity factor; for example, 20%. the power dissipated by the clock generation circuitry is based upon four parts: the ?ed clock power, the power/clock branch row or column, the clock power dis- sipated in each pfu that uses this particular clock, and the power from the subset of those pfus that are con- ?ured as synchronous memory. therefore, the clock power can be calculated for the four parts using the fol- lowing equations. or3l165b clock power p = [0.039 mw/mhz + (0.046 mw/mhz/branch) (# branches) + (0.008 mw/mhz/pfu) (# pfus) + (0.002 mw/mhz/pio (# pios)] for a quick estimate, the worst-case (typical circuit) or3l165b clock power = 9.8 mw/mhz or3l225b clock power p = [0.045 mw/mhz + (0.053 mw/mhz/branch) (# branches) + (0.008 mw/mhz/pfu) (# pfus) + (0.002 mw/mhz/pio (# pios)] for a quick estimate, the worst-case (typical circuit) or3l225b clock power = 13.5 mw/mhz the power dissipated in a pic is the sum of the power dissipated in the four pios in the pic. this consists of power dissipated by inputs and ac power dissipated by outputs. the power dissipated in each pio depends on whether it is con?ured as an input, output, or input/ output. if a pio is operating as an output, then there is a power dissipation component for p in , as well as p out . this is because the output feeds back to the input. the power dissipated by an input buffer is (v ih = v dd ? 0.3 v or higher) estimated as: p in = 0.09 mw/mhz the ac power dissipation from an output or bidirec- tional is estimated by the following: p out = (c l + 8.8 pf) v dd 2 f watts where the unit for c l is farads, and the unit for f is hz. all devices discontinued 38 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin information table 24. 208-pin sqfp2 pinout pin or3l165b function 1v ss v ss 2v ss v ss 3 pl1d i/o 4 pl3d i/o-a0/mpi_be0 5v dd 2v dd 2 6 pl6d i/o 7 pl8d i/o-a1/mpi_be1 8 pl9a i/o-a2 9 pl10d i/o 10 pl10b i/o 11 pl10a i/o-a3 12 v dd v dd 13 pl11d i/o 14 pl11a i/o 15 pl12d i/o 16 pl12a i/o-a4 17 pl13d i/o-a5 18 pl13a i/o 19 pl14d i/o 20 pl14a i/o-a6 21 v ss v ss 22 peckl i/o-eckl 23 pl15a i/o 24 pl16c i/o 25 pl16a i/o-a7/mpi_clk 26 v dd v dd 27 pl17d i/o 28 v dd 2v dd 2 29 pl18c i/o 30 pl18a i/o-a8/mpi_rw 31 v ss v ss 32 pl19d i/o-a9/mpi_a ck 33 pl19a i/o 34 pl20d i/o 35 pl20a i/o-a10/mpi_bi 36 pl21d i/o 37 pl21a i/o 38 pl22d i/o 39 pl22a i/o-a11/mpi_irq 40 v dd v dd 41 pl23d i/o-a12 42 pl23b i/o 43 pl24d i/o 44 pl24b i/o-a13 45 pl25d i/o 46 pl27a i/o-a14 47 pl29d i/o 48 pl30d i/o 49 pl30a i/o-seckll 50 pl32a i/o-a15 51 v ss v ss 52 pcclk cclk 53 v ss v ss 54 v ss v ss 55 pb1a i/o-a16 56 pb3a i/o 57 v dd 2v dd 2 58 pb4d i/o 59 pb5d i/o-a17 60 pb6d i/o 61 pb7d i/o 62 pb8d i/o 63 pb9d i/o 64 pb10d i/o 65 v dd v dd 66 pb11a i/o 67 pb11d i/o 68 pb12a i/o 69 pb12d i/o 70 pb13a i/o 71 pb13d i/o 72 pb14a i/o 73 pb14d i/o 74 v ss v ss 75 pb15a i/o 76 pb15d i/o 77 pb16b i/o 78 pb16d i/o 79 v ss v ss 80 peckb i/o-eckb 81 pb17d i/o 82 pb18b i/o 83 pb18d i/o 84 v ss v ss pin or3l165b function all devices discontinued lattice semiconductor 39 data addendum march 2002 orca or3lxxxb series fpgas 85 v dd 2v dd 2 86 pb19d i/o 87 pb20a i/o 88 pb20d i/o 89 pb21a i/o-hdc 90 pb21d i/o 91 pb22a i/o 92 pb22d i/o 93 v dd v dd 94 pb23a i/o-ldc 95 pb24d i/o 96 pb25a i/o 97 pb26d i/o 98 pb27a i/o-init 99 pb28a i/o 100 pb29a i/o 101 pb30d i/o 102 pb32d i/o 103 v ss v ss 104 pdone done 105 v ss v ss 106 presetn reset 107 pprgmn prgm 108 pr32a i/o-m0 109 pr30a i/o 110 pr29a i/o 111 pr28a i/o 112 pr25d i/o-m1 113 pr24a i/o 114 v dd 2v dd 2 115 pr23a i/o 116 v dd v dd 117 pr22a i/o-m2 118 pr22d i/o 119 pr21a i/o 120 pr21d i/o 121 pr20a i/o-m3 122 pr20d i/o 123 pr19a i/o 124 pr19d i/o 125 v ss v ss 126 pr18a i/o pin or3l165b function 127 pr18d i/o 128 pr17b i/o 129 pr17d i/o 130 v dd v dd 131 peckr i/o-eckr 132 pr16d i/o 133 pr15b i/o 134 pr15d i/o 135 v ss v ss 136 v dd 2v dd 2 137 pr14d i/o 138 pr13a i/o 139 pr13d i/o 140 pr12a i/o-cs1 141 pr12d i/o 142 pr11a i/o 143 pr11d i/o 144 v dd v dd 145 pr10a i/o-cs0 146 pr10b i/o 147 pr9b i/o 148 pr9d i/o 149 pr8a i/o-rd /mpi_strb 150 pr6a i/o 151 pr5a i/o 152 pr4a i/o-wr 153 pr3a i/o 154 pr2a i/o 155 v ss v ss 156 prd_cfgn rd_cfg 157 v ss v ss 158 v ss v ss 159 pt32d i/o-seckur 160 pt30a i/o-rdy/rclk/mpi_ale 161 pt28d i/o 162 pt28a i/o 163 pt27d i/o-d7 164 v dd 2v dd 2 165 pt25d i/o 166 pt24d i/o 167 pt23d i/o-d6 168 v dd v dd pin or3l165b function pin information (continued) table 24. 208-pin sqfp2 pinout (continued) all devices discontinued 40 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas 169 pt22d i/o 170 pt22a i/o 171 pt21d i/o 172 pt21a i/o-d5 173 pt20d i/o 174 pt20a i/o 175 pt19d i/o 176 pt19a i/o-d4 177 v ss v ss 178 peckt i/o-eckt 179 pt18b i/o 180 pt17d i/o 181 pt17a i/o-d3 182 v ss v ss 183 pt16d i/o 184 pt16c i/o 185 v dd 2v dd 2 186 pt15a i/o-d2 187 v ss v ss 188 pt14d i/o-d1 pin or3l165b function 189 pt14a i/o 190 pt13d i/o 191 pt13a i/o-d0/din 192 pt12d i/o 193 pt12a i/o 194 pt11d i/o 195 pt11a i/o-dout 196 v dd v dd 197 pt10d i/o 198 pt9a i/o 199 pt8a i/o 200 pt7a i/o-tdi 201 pt6a i/o 202 pt5a i/o-tms 203 pt4a i/o 204 pt3a i/o 205 pt2d i/o 206 pt1a i/o-tck 207 v ss v ss 208 prd_data rd_data/tdo pin or3l165b function pin information (continued) table 24. 208-pin sqfp2 pinout (continued) all devices discontinued lattice semiconductor 41 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b function 1v ss v ss 2v dd v dd 3 pl1d i/o 4 pl1a i/o 5 pl2d i/o 6 pl3d i/o-a0/mpi_be0 7v ss v ss 8v dd 2v dd 2 9 pl6d i/o 10 pl7d i/o 11 pl8d i/o-a1/mpi_be1 12 pl9a i/o-a2 13 pl10d i/o 14 pl10b i/o 15 pl10a i/o-a3 16 v dd v dd 17 pl11d i/o 18 pl11a i/o 19 pl12d i/o 20 pl12a i/o-a4 21 pl13d i/o-a5 22 pl13a i/o 23 pl14d i/o 24 pl14a i/o-a6 25 v ss v ss 26 peckl i/o-eckl 27 pl15a i/o 28 pl16c i/o 29 pl16a i/o-a7/mpi_clk 30 v dd v dd 31 pl17d i/o 32 v dd 2v dd 2 33 pl18c i/o 34 pl18a i/o-a8/mpi_rw 35 v ss v ss 36 pl19d i/o-a9/mpi_ack 37 pl19a i/o 38 pl20d i/o 39 pl20a i/o-a10/mpi_bi 40 pl21d i/o 41 pl21a i/o 42 pl22d i/o 43 pl22a i/o-a11/mpi_irq 44 v dd v dd 45 pl23d i/o-a12 46 pl23b i/o 47 pl24d i/o 48 pl24b i/o-a13 49 pl24a i/o 50 pl25d i/o 51 pl26d i/o 52 pl27a i/o-a14 53 v ss v ss 54 pl29d i/o 55 pl30d i/o 56 pl30a i/o-seckll 57 pl32a i/o-a15 58 v ss v ss 59 pcclk cclk 60 v dd v dd 61 v ss v ss 62 v ss v ss 63 pb1a i/o-a16 64 pb3a i/o 65 v dd 2v dd 2 66 pb4d i/o 67 v ss v ss 68 pb5d i/o-a17 69 pb6d i/o 70 pb7a i/o 71 pb7d i/o 72 pb8d i/o 73 pb9a i/o 74 pb9d i/o 75 pb10d i/o 76 v dd v dd 77 pb11a i/o 78 pb11d i/o 79 pb12a i/o 80 pb12d i/o 81 pb13a i/o 82 pb13d i/o pin or3l165b function pin information (continued) table 25. 240-pin sqfp2 pinout all devices discontinued 42 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas 83 pb14a i/o 84 pb14d i/o 85 v ss v ss 86 pb15a i/o 87 pb15d i/o 88 pb16b i/o 89 pb16d i/o 90 v ss v ss 91 peckb i/o-eckb 92 pb17d i/o 93 pb18b i/o 94 pb18d i/o 95 v ss v ss 96 v dd 2v dd 2 97 pb19d i/o 98 pb20a i/o 99 pb20d i/o 100 pb21a i/o-hdc 101 pb21d i/o 102 pb22a i/o 103 pb22d i/o 104 v dd v dd 105 pb23a i/o-ldc 106 pb24d i/o 107 pb25a i/o 108 pb26d i/o 109 pb27a i/o-init 110 pb27d i/o 111 pb28a i/o 112 pb28d i/o 113 v ss v ss 114 pb29a i/o 115 pb30a i/o 116 pb30d i/o 117 pb32d i/o 118 v ss v ss 119 pdone done 120 v dd v dd 121 v ss v ss 122 presetn reset 123 pprgmn prgm 124 pr32a i/o-m0 pin or3l165b function 125 pr31d i/o 126 pr30a i/o 127 pr29a i/o 128 v ss v ss 129 pr28a i/o 130 pr27a i/o 131 pr26a i/o 132 pr26d i/o 133 pr25d i/o-m1 134 pr24a i/o 135 v dd 2v dd 2 136 pr23a i/o 137 v dd v dd 138 pr22a i/o-m2 139 pr22d i/o 140 pr21a i/o 141 pr21d i/o 142 pr20a i/o-m3 143 pr20d i/o 144 pr19a i/o 145 pr19d i/o 146 v ss v ss 147 pr18a i/o 148 pr18d i/o 149 pr17b i/o 150 pr17d i/o 151 v dd v dd 152 peckr i/o-eckr 153 pr16d i/o 154 pr15b i/o 155 pr15d i/o 156 v ss v ss 157 v dd 2v dd 2 158 pr14d i/o 159 pr13a i/o 160 pr13d i/o 161 pr12a i/o-cs1 162 pr12d i/o 163 pr11a i/o 164 pr11d i/o 165 v dd v dd 166 pr10a i/o-cs0 pin or3l165b function pin information (continued) table 25. 240-pin sqfp2 pinout (continued) all devices discontinued lattice semiconductor 43 data addendum march 2002 orca or3lxxxb series fpgas 167 pr10b i/o 168 pr9b i/o 169 pr9d i/o 170 pr8a i/o-rd /mpi_strb 171 pr7a i/o 172 pr6a i/o 173 pr5a i/o 174 v ss v ss 175 pr4a i/o-wr 176 pr3a i/o 177 pr2a i/o 178 pr1d i/o 179 v ss v ss 180 prd_cfgn rd_cfg 181 v ss v ss 182 v dd v dd 183 v ss v ss 184 pt32d i/o-seckur 185 pt31a i/o 186 pt30d i/o 187 pt30a i/o-rdy/rclk/mpi_ale 188 v ss v ss 189 pt28d i/o 190 pt28c i/o 191 pt28a i/o 192 pt27d i/o-d7 193 v dd 2v dd 2 194 pt25d i/o 195 pt24d i/o 196 pt23d i/o-d6 197 v dd v dd 198 pt22d i/o 199 pt22a i/o 200 pt21d i/o 201 pt21a i/o-d5 202 pt20d i/o 203 pt20a i/o pin or3l165b function 204 pt19d i/o 205 pt19a i/o-d4 206 v ss v ss 207 peckt i/o-eckt 208 pt18b i/o 209 pt17d i/o 210 pt17a i/o-d3 211 v ss v ss 212 pt16d i/o 213 pt16c i/o 214 v dd 2v dd 2 215 pt15a i/o-d2 216 v ss v ss 217 pt14d i/o-d1 218 pt14a i/o 219 pt13d i/o 220 pt13a i/o-d0/din 221 pt12d i/o 222 pt12a i/o 223 pt11d i/o 224 pt11a i/o-dout 225 v dd v dd 226 pt10d i/o 227 pt9a i/o 228 pt8a i/o 229 pt7a i/o-tdi 230 pt6d i/o 231 pt6a i/o 232 pt5d i/o 233 pt5a i/o-tms 234 v ss v ss 235 pt4a i/o 236 pt3a i/o 237 pt2d i/o 238 pt1a i/o-tck 239 v ss v ss 240 prd_data rd_data/tdo pin or3l165b function pin information (continued) table 25. 240-pin sqfp2 pinout (continued) all devices discontinued 44 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin information (continued) table 26. 352-pin pbga pinout pin or3l165b function b1 pl1d i/o c2 pl1a i/o c1 pl2d i/o d2 pl2a i/o d3 pl3d i/o-a0/mpi_be0 d1 pl3a i/o e2 pl4d i/o e4 pl4b i/o e3 pl4a i/o e1 v dd 2v dd 2 f2 pl5c i/o g4 pl5b i/o f3 pl6d i/o f1 pl7d i/o g2 pl7c i/o g1 pl7b i/o g3 pl8d i/o-a1/mpi_be1 h2 pl9d i/o j4 pl9c i/o h1 pl9b i/o h3 pl9a i/o-a2 j2 pl10d i/o j1 pl10c i/o k2 pl10b i/o j3 pl10a i/o-a3 k1 pl11d i/o k4 pl11a i/o l2 pl12d i/o k3 pl12a i/o-a4 l1 pl13d i/o-a5 m2 pl13a i/o m1 pl14d i/o l3 pl14a i/o-a6 n2 peckl i/o-eckl m4 pl15a i/o n1 pl16c i/o m3 pl16a i/o-a7/mpi_clk pin or3l165b function p2 pl17d i/o p4 v dd 2v dd 2 p1 pl18c i/o n3 pl18a i/o-a8/mpi_rw r2 pl19d i/o-a9/mpi_ack p3 pl19a i/o r1 pl20d i/o t2 pl20a i/o-a10/mpi_bi r3 pl21d i/o t1 pl21a i/o r4 pl22d i/o u2 pl22a i/o-a11/mpi_irq t3 pl23d i/o-a12 u1 pl23c i/o u4 pl23b i/o v2 pl23a i/o u3 pl24d i/o v1 pl24c i/o w2 pl24b i/o-a13 w1 pl24a i/o v3 pl25d i/o y2 pl25c i/o w4 pl26d i/o y1 pl27d i/o w3 pl27a i/o-a14 aa2 pl28c i/o y4 pl28b i/o aa1 pl28a i/o y3 v dd 2v dd 2 ab2 pl29c i/o ab1 pl29a i/o aa3 pl30d i/o ac2 pl30c i/o ab4 pl30a i/o-seckll ac1 pl31a i/o ab3 pl32c i/o ad2 pl32b i/o all devices discontinued lattice semiconductor 45 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b function ac3 pl32a i/o-a15 ad1 pcclk cclk af2 pb1a i/o-a16 ae3 pb1b i/o af3 pb2a i/o ae4 pb2d i/o ad4 pb3a i/o af4 v dd 2v dd 2 ae5 pb4a i/o ac5 pb4c i/o ad5 pb4d i/o af5 pb5a i/o ae6 pb5b i/o ac7 pb5c i/o ad6 pb5d i/o-a17 af6 pb6a i/o ae7 pb6b i/o af7 pb6c i/o ad7 pb6d i/o ae8 pb7a i/o ac9 pb7d i/o af8 pb8a i/o ad8 pb8d i/o ae9 pb9a i/o af9 pb9d i/o ae10 pb10a i/o ad9 pb10d i/o af10 pb11a i/o ac10 pb11d i/o ae11 pb12a i/o ad10 pb12d i/o af11 pb13a i/o ae12 pb13d i/o af12 pb14a i/o ad11 pb14d i/o ae13 pb15a i/o ac12 pb15d i/o af13 pb16b i/o ad12 pb16d i/o pin or3l165b function ae14 peckb i/o-eckb ac14 pb17d i/o af14 pb18b i/o ad13 pb18d i/o ae15 v dd 2v dd 2 ad14 pb19d i/o af15 pb20a i/o ae16 pb20d i/o ad15 pb21a i/o-hdc af16 pb21d i/o ac15 pb22a i/o ae17 pb22d i/o ad16 pb23a i/o-ldc af17 pb23d i/o ac17 pb24a i/o ae18 pb24d i/o ad17 pb25a i/o af18 pb26a i/o ae19 pb26c i/o af19 pb26d i/o ad18 pb27a i/o-init ae20 pb27b i/o ac19 pb27c i/o af20 pb27d i/o ad19 v dd 2v dd 2 ae21 pb28b i/o ac20 pb28c i/o af21 pb28d i/o ad20 pb29a i/o ae22 pb29b i/o af22 pb29d i/o ad21 pb30a i/o ae23 pb30b i/o ac22 pb30d i/o af23 pb31a i/o ad22 pb31d i/o ae24 pb32c i/o ad23 pb32d i/o af24 pdone done pin information (continued) table 26. 352-pin pbga pinout (continued) all devices discontinued 46 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b function ae26 presetn reset ad25 pprgmn prgm ad26 pr32a i/o-m0 ac25 pr31a i/o ac24 pr31d i/o ac26 pr30a i/o ab25 pr30d i/o ab23 pr29a i/o ab24 pr29b i/o ab26 pr29d i/o aa25 pr28a i/o y23 pr28b i/o aa24 pr28c i/o aa26 pr27a i/o y25 pr26a i/o y26 pr26b i/o y24 pr26d i/o w25 pr25d i/o-m1 v23 pr24a i/o w26 pr24b i/o w24 pr24c i/o v25 v dd 2v dd 2 v26 pr23a i/o u25 pr23b i/o v24 pr23c i/o u26 pr23d i/o u23 pr22a i/o-m2 t25 pr22d i/o u24 pr21a i/o t26 pr21d i/o r25 pr20a i/o-m3 r26 pr20d i/o t24 pr19a i/o p25 pr19d i/o r23 pr18a i/o p26 pr18d i/o r24 pr17b i/o n25 pr17d i/o n23 peckr i/o-eckr pin or3l165b function n26 pr16d i/o p24 pr15b i/o m25 pr15d i/o n24 v dd 2v dd 2 m26 pr14d i/o l25 pr13a i/o m24 pr13d i/o l26 pr12a i/o-cs1 m23 pr12d i/o k25 pr11a i/o l24 pr11d i/o k26 pr10a i/o-cs0 k23 pr10b i/o j25 pr10c i/o k24 pr10d i/o j26 pr9a i/o h25 pr9b i/o h26 pr9c i/o j24 pr9d i/o g25 pr8a i/o-rd /mpi_strb h23 pr7a i/o g26 pr7c i/o h24 pr6a i/o f25 v dd 2v dd 2 g23 pr5b i/o f26 pr5c i/o g24 pr5d i/o e25 pr4a i/o-wr e26 pr4b i/o f24 pr4d i/o d25 pr3a i/o e23 pr3d i/o d26 pr2a i/o e24 pr2d i/o c25 pr1a i/o d24 pr1d i/o c26 prd_cfgn rd_cfg a25 pt32d i/o-seckur b24 pt32a i/o pin information (continued) table 26. 352-pin pbga pinout (continued) all devices discontinued lattice semiconductor 47 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b function a24 pt31b i/o b23 pt31a i/o c23 pt30d i/o a23 pt30a i/o-rdy/rclk/mpi_ale b22 pt29d i/o d22 pt29c i/o c22 pt29a i/o a22 pt28d i/o b21 pt28c i/o d20 pt28b i/o c21 pt28a i/o a21 pt27d i/o-d7 b20 pt27c i/o a20 pt27b i/o c20 pt27a i/o b19 v dd 2v dd 2 d18 pt26c i/o a19 pt26b i/o c19 pt25d i/o b18 pt24d i/o a18 pt24a i/o b17 pt23d i/o-d6 c18 pt23a i/o a17 pt22d i/o d17 pt22a i/o b16 pt21d i/o c17 pt21a i/o-d5 a16 pt20d i/o b15 pt20a i/o a15 pt19d i/o c16 pt19a i/o-d4 b14 peckt i/o-eckt d15 pt18b i/o a14 pt17d i/o c15 pt17a i/o-d3 b13 pt16d i/o d13 pt16c i/o a13 v dd 2v dd 2 c14 pt15a i/o-d2 pin or3l165b function b12 pt14d i/o-d1 c13 pt14a i/o a12 pt13d i/o b11 pt13a i/o-d0/din c12 pt12d i/o a11 pt12a i/o d12 pt11d i/o b10 pt11a i/o-dout c11 pt10d i/o a10 pt10a i/o d10 pt9d i/o b9 pt9a i/o c10 pt8d i/o a9 pt8a i/o b8 pt7d i/o a8 pt7a i/o-tdi c9 pt6d i/o b7 pt6c i/o d8 pt6b i/o a7 v dd 2v dd 2 c8 pt5d i/o b6 pt5c i/o d7 pt5b i/o a6 pt5a i/o-tms c7 pt4d i/o b5 pt4a i/o a5 pt3d i/o c6 pt3c i/o b4 pt3b i/o d5 pt3a i/o a4 pt2d i/o c5 pt2a i/o b3 pt1d i/o c4 pt1a i/o-tck a3 prd_data rd_data/tdo a1 v ss v ss a2 v ss v ss a26 v ss v ss ac13 v ss v ss pin information (continued) table 26. 352-pin pbga pinout (continued) all devices discontinued 48 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b function ac18 v ss v ss ac23 v ss v ss ac4 v ss v ss ac8 v ss v ss ad24 v ss v ss ad3 v ss v ss ae1 v ss v ss ae2 v ss v ss ae25 v ss v ss af1 v ss v ss af25 v ss v ss af26 v ss v ss b2 v ss v ss b25 v ss v ss b26 v ss v ss c24 v ss v ss c3 v ss v ss d14 v ss v ss d19 v ss v ss d23 v ss v ss d4 v ss v ss d9 v ss v ss h4 v ss v ss j23 v ss v ss n4 v ss v ss p23 v ss v ss v4 v ss v ss w23 v ss v ss l11 v ss v ss l12 v ss v ss l13 v ss v ss l14 v ss v ss l15 v ss v ss l16 v ss v ss m11 v ss v ss m12 v ss v ss m13 v ss v ss m14 v ss v ss m15 v ss v ss m16 v ss v ss pin or3l165b function n11 v ss v ss n12 v ss v ss n13 v ss v ss n14 v ss v ss n15 v ss v ss n16 v ss v ss p11 v ss v ss p12 v ss v ss p13 v ss v ss p14 v ss v ss p15 v ss v ss p16 v ss v ss r11 v ss v ss r12 v ss v ss r13 v ss v ss r14 v ss v ss r15 v ss v ss r16 v ss v ss t11 v ss v ss t12 v ss v ss t13 v ss v ss t14 v ss v ss t15 v ss v ss t16 v ss v ss aa23 v dd v dd aa4 v dd v dd ac11 v dd v dd ac16 v dd v dd ac21 v dd v dd ac6 v dd v dd d11 v dd v dd d16 v dd v dd d21 v dd v dd d6 v dd v dd f23 v dd v dd f4 v dd v dd l23 v dd v dd l4 v dd v dd t23 v dd v dd t4 v dd v dd pin information (continued) table 26. 352-pin pbga pinout (continued) all devices discontinued lattice semiconductor 49 data addendum march 2002 orca or3lxxxb series fpgas pin information (continued) table 27. 432-pin ebga pinout pin or3l165b or3l225b function e4 prd_cfgn prd_cfgn rd_cfg d3 pr1d pr1d i/o d2 pr1a pr1a i/o d1 pr2d pr2d i/o f4 pr2a pr2a i/o e3 pr3d pr3d i/o e2 pr3c pr3c i/o e1 pr3b pr3b i/o f3 pr3a pr3a i/o f2 pr4d pr4d i/o f1 pr4c pr4c i/o h4 pr4b pr4b i/o g3 pr4a pr4a i/o-wr g2 pr5d pr5d i/o g1 pr5c pr5c i/o j4 pr5b pr5b i/o h3 v dd 2v dd 2v dd 2 h2 pr6a pr6a i/o j3 pr7c pr7c i/o k4 pr7a pr7a i/o j2 pr8a pr8a i/o-rd /mpi_strb j1 pr9d pr9d i/o k3 pr9c pr9a i/o k2 pr9b pr10d i/o k1 pr9a pr10c i/o l3 pr10d pr10a i/o m4 pr10c pr11d i/o l2 pr10b pr11c i/o l1 pr10a pr11a i/o-cs0 m3 pr11d pr12d i/o n4 pr11a pr12a i/o m2 pr12d pr13d i/o n3 pr12a pr13a i/o-cs1 n2 pr13d pr14d i/o p4 pr13c pr14a i/o n1 pr13a pr15a i/o p3 pr14d pr16d i/o p2 pr14c pr16a i/o p1 v dd 2v dd 2v dd 2 r3 pr15d pr18d i/o r2 pr15b pr18b i/o all devices discontinued 50 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function r1 pr16d pr19d i/o t2 peckr peckr i/o-eckr t4 pr17d pr20d i/o t3 pr17b pr20b i/o u1 pr18d pr21d i/o u2 pr18a pr21a i/o u3 pr19d pr22d i/o v1 pr19b pr23d i/o v2 pr19a pr23a i/o v3 pr20d pr24d i/o w1 pr20a pr25a i/o-m3 v4 pr21d pr26d i/o w2 pr21b pr26b i/o w3 pr21a pr26a i/o y2 pr22d pr27d i/o w4 pr22a pr27a i/o-m2 y3 pr23d pr28d i/o aa1 pr23c pr28c i/o aa2 pr23b pr28b i/o y4 pr23a pr28a i/o aa3 v dd 2v dd 2v dd 2 ab1 pr24c pr29a i/o ab2 pr24b pr30d i/o ab3 pr24a pr30a i/o ac1 pr25d pr31d i/o-m1 ac2 pr26d pr32d i/o ab4 pr26b pr32b i/o ac3 pr26a pr32a i/o ad2 pr27a pr33a i/o ad3 pr28c pr34c i/o ac4 pr28b pr34b i/o ae1 pr28a pr34a i/o ae2 pr29d pr35d i/o ae3 pr29c pr35c i/o ad4 pr29b pr35b i/o af1 pr29a pr35a i/o af2 pr30d pr36d i/o af3 pr30c pr36c i/o ag1 pr30b pr36b i/o ag2 v dd 2v dd 2v dd 2 ag3 pr31d pr37d i/o pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued lattice semiconductor 51 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function af4 pr31a pr37a i/o ah1 pr32b pr38b i/o ah2 pr32a pr38a i/o-m0 ah3 pprgmn pprgmn prgm ag4 presetn presetn reset ah5 pdone pdone done aj4 pb32d pb38d i/o ak4 pb32c pb38c i/o al4 pb31d pb37d i/o ah6 pb31a pb37a i/o aj5 pb30d pb36d i/o ak5 pb30c pb36c i/o al5 pb30b pb36b i/o aj6 pb30a pb36a i/o ak6 pb29d pb35d i/o al6 pb29c pb35c i/o ah8 pb29b pb35b i/o aj7 pb29a pb35a i/o ak7 pb28d pb34d i/o al7 pb28c pb34c i/o ah9 pb28b pb34b i/o aj8 v dd 2v dd 2v dd 2 ak8 pb27d pb33d i/o aj9 pb27c pb33c i/o ah10 pb27b pb33b i/o ak9 pb27a pb33a i/o-init al9 pb26d pb32d i/o aj10 pb26c pb32c i/o ak10 pb26a pb32a i/o al10 pb25a pb31a i/o aj11 pb24d pb30d i/o ah12 pb24a pb30a i/o ak11 pb23d pb29d i/o al11 pb23a pb29a i/o-ldc aj12 pb22d pb28d i/o ah13 pb22b pb27d i/o ak12 pb22a pb27a i/o aj13 pb21d pb26d i/o ak13 pb21b pb25d i/o ah14 pb21a pb25a i/o-hdc al13 pb20d pb24d i/o pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued 52 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function aj14 pb20b pb24b i/o ak14 pb20a pb24a i/o al14 pb19d pb23d i/o aj15 v dd 2v dd 2v dd 2 ak15 pb18d pb22d i/o al15 pb18b pb21d i/o ak16 pb17d pb20d i/o ah16 peckb peckb i/o-eckb aj16 pb16d pb19d i/o al17 pb16b pb18d i/o ak17 pb15d pb17d i/o aj17 pb15a pb17a i/o al18 pb14d pb16d i/o ak18 pb14b pb15d i/o aj18 pb14a pb15a i/o al19 pb13d pb14d i/o ah18 pb13a pb13a i/o ak19 pb12d pb12d i/o aj19 pb12b pb12b i/o ak20 pb12a pb12a i/o ah19 pb11d pb11d i/o aj20 pb11b pb11b i/o al21 v dd 2v dd 2v dd 2 ak21 pb10d pb10d i/o ah20 pb10a pb10a i/o aj21 pb9d pb9d i/o al22 pb9a pb9a i/o ak22 pb8d pb8d i/o aj22 pb8a pb8a i/o al23 pb7d pb7d i/o ak23 pb7a pb7a i/o ah22 pb6d pb6d i/o aj23 pb6c pb6c i/o ak24 pb6b pb6b i/o aj24 pb6a pb6a i/o ah23 pb5d pb5d i/o-a17 al25 pb5c pb5c i/o ak25 pb5b pb5b i/o aj25 pb5a pb5a i/o ah24 pb4d pb4d i/o al26 pb4c pb4c i/o pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued lattice semiconductor 53 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function ak26 pb4b pb4b i/o aj26 pb4a pb4a i/o al27 v dd 2v dd 2v dd 2 ak27 pb3c pb3c i/o aj27 pb3b pb3b i/o ah26 pb3a pb3a i/o al28 pb2d pb2d i/o ak28 pb2a pb2a i/o aj28 pb1b pb1b i/o ah27 pb1a pb1a i/o-a16 ag28 pcclk pcclk cclk ah29 pl32a pl38a i/o-a15 ah30 pl32b pl38b i/o ah31 pl32c pl38c i/o af28 pl31a pl37a i/o ag29 pl30a pl36a i/o-seckll ag30 pl30b pl36b i/o ag31 pl30c pl36c i/o af29 pl30d pl36d i/o af30 pl29a pl35a i/o af31 pl29b pl35b i/o ad28 pl29c pl35c i/o ae29 v dd 2v dd 2v dd 2 ae30 pl28a pl34a i/o ae31 pl28b pl34b i/o ac28 pl28c pl34c i/o ad29 pl27a pl33a i/o-a14 ad30 pl27d pl33d i/o ac29 pl26d pl32d i/o ab28 pl25c pl31c i/o ac30 pl25d pl31d i/o ac31 pl24a pl30a i/o ab29 pl24b pl30b i/o-a13 ab30 pl24c pl30c i/o ab31 pl24d pl30d i/o aa29 pl23a pl29c i/o y28 pl23b pl29d i/o aa30 pl23c pl28b i/o aa31 pl23d pl28d i/o-a12 y29 pl22a pl27a i/o-a11/mpi_irq w28 pl22d pl27d i/o pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued 54 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function y30 pl21a pl26a i/o w29 pl21c pl26c i/o w30 pl21d pl26d i/o v28 pl20a pl25a i/o-a10/mpi_bi w31 pl20c pl24a i/o v29 pl20d pl24d i/o v30 pl19a pl23a i/o v31 pl19c pl22a i/o u29 pl19d pl22d i/o-a9/mpi_a ck u30 pl18a pl21a i/o-a8/mpi_rw u31 pl18c pl21c i/o t30 v dd 2v dd 2v dd 2 t28 pl17d pl20d i/o t29 pl16a pl19a i/o-a7/mpi_clk r31 pl16c pl19c i/o r30 pl15a pl18a i/o r29 peckl peckl i/o-eckl p31 pl14a pl17a i/o-a6 p30 pl14d pl16d i/o p29 pl13a pl15a i/o n31 pl13c pl14a i/o p28 pl13d pl14d i/o-a5 n30 pl12a pl13a i/o-a4 n29 pl12c pl13c i/o m30 pl12d pl13d i/o n28 pl11a pl12a i/o m29 pl11c pl12c i/o l31 v dd 2v dd 2v dd 2 l30 pl10a pl11a i/o-a3 m28 pl10b pl11d i/o l29 pl10c pl10a i/o k31 pl10d pl10d i/o k30 pl9a pl9a i/o-a2 k29 pl9b pl9b i/o j31 pl9c pl9c i/o j30 pl9d pl9d i/o k28 pl8d pl8d i/o-a1/mpi_be1 j29 pl7b pl7b i/o h30 pl7c pl7c i/o h29 pl7d pl7d i/o j28 pl6d pl6d i/o pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued lattice semiconductor 55 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function g31 pl5b pl5b i/o g30 pl5c pl5c i/o g29 v dd 2v dd 2v dd 2 h28 pl4a pl4a i/o f31 pl4b pl4b i/o f30 pl4c pl4c i/o f29 pl4d pl4d i/o e31 pl3a pl3a i/o e30 pl3b pl3b i/o e29 pl3c pl3c i/o f28 pl3d pl3d i/o-a0/mpi_be0 d31 pl2a pl2a i/o d30 pl2d pl2d i/o d29 pl1a pl1a i/o e28 pl1d pl1d i/o d27 prd_data prd_data rd_data/tdo c28 pt1a pt1a i/o-tck b28 pt1d pt1d i/o a28 pt2a pt2a i/o d26 pt2d pt2d i/o c27 pt3a pt3a i/o b27 pt3b pt3b i/o a27 pt3c pt3c i/o c26 pt3d pt3d i/o b26 pt4a pt4a i/o a26 pt4b pt4b i/o d24 pt4c pt4c i/o c25 pt4d pt4d i/o b25 pt5a pt5a i/o-tms a25 pt5b pt5b i/o d23 pt5c pt5c i/o c24 pt5d pt5d i/o b24 v dd 2v dd 2v dd 2 c23 pt6b pt6b i/o d22 pt6c pt6c i/o b23 pt6d pt6d i/o a23 pt7a pt7a i/o-tdi c22 pt7d pt7d i/o b22 pt8a pt8a i/o a22 pt8d pt8d i/o c21 pt9a pt9a i/o pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued 56 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function d20 pt9d pt9d i/o b21 pt10a pt10a i/o a21 pt10d pt10d i/o c20 pt11a pt11a i/o-dout d19 pt11d pt12d i/o b20 pt12a pt13a i/o c19 pt12c pt14a i/o b19 pt12d pt14d i/o d18 pt13a pt15a i/o-d0/din a19 pt13c pt15c i/o c18 pt13d pt15d i/o b18 pt14a pt16a i/o a18 pt14c pt16c i/o c17 pt14d pt16d i/o-d1 b17 pt15a pt17a i/o-d2 a17 v dd 2v dd 2v dd 2 b16 pt16c pt18d i/o d16 pt16d pt19d i/o c16 pt17a pt20a i/o-d3 a15 pt17d pt21a i/o b15 pt18b pt22a i/o c15 peckt peckt i/o-eckt a14 pt19a pt23a i/o-d4 b14 pt19b pt23d i/o c14 pt19d pt24d i/o a13 pt20a pt25a i/o d14 pt20b pt25d i/o b13 pt20d pt26d i/o c13 pt21a pt27a i/o-d5 b12 pt21b pt27b i/o d13 v dd 2v dd 2v dd 2 c12 pt22a pt28a i/o a11 pt22d pt28d i/o b11 pt23a pt29a i/o d12 pt23d pt29d i/o-d6 c11 pt24a pt30a i/o a10 pt24d pt30d i/o b10 pt25d pt31d i/o c10 pt26b pt32b i/o a9 pt26c pt32c i/o b9 v dd 2v dd 2v dd 2 pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued lattice semiconductor 57 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function d10 pt27a pt33a i/o c9 pt27b pt33b i/o b8 pt27c pt33c i/o c8 pt27d pt33d i/o-d7 d9 pt28a pt34a i/o a7 pt28b pt34b i/o b7 pt28c pt34c i/o c7 pt28d pt34d i/o d8 pt29a pt35a i/o a6 pt29b pt35b i/o b6 pt29c pt35c i/o c6 pt29d pt35d i/o a5 pt30a pt36a i/o-rdy/rclk/mpi_ale b5 pt30b pt36b i/o c5 pt30c pt36c i/o d6 pt30d pt36d i/o a4 pt31a pt37a i/o b4 pt31b pt37b i/o c4 pt32a pt38a i/o d5 pt32d pt38d i/o-seckur a12 v ss v ss v ss a16 v ss v ss v ss a2 v ss v ss v ss a20 v ss v ss v ss a24 v ss v ss v ss a29 v ss v ss v ss a3 v ss v ss v ss a30 v ss v ss v ss a8 v ss v ss v ss ad1 v ss v ss v ss ad31 v ss v ss v ss aj1 v ss v ss v ss aj2 v ss v ss v ss aj30 v ss v ss v ss aj31 v ss v ss v ss ak1 v ss v ss v ss ak29 v ss v ss v ss ak3 v ss v ss v ss ak31 v ss v ss v ss al12 v ss v ss v ss al16 v ss v ss v ss pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued 58 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function al2 v ss v ss v ss al20 v ss v ss v ss al24 v ss v ss v ss al29 v ss v ss v ss al3 v ss v ss v ss al30 v ss v ss v ss al8 v ss v ss v ss b1 v ss v ss v ss b29 v ss v ss v ss b3 v ss v ss v ss b31 v ss v ss v ss c1 v ss v ss v ss c2 v ss v ss v ss c30 v ss v ss v ss c31 v ss v ss v ss h1 v ss v ss v ss h31 v ss v ss v ss m1 v ss v ss v ss m31 v ss v ss v ss t1 v ss v ss v ss t31 v ss v ss v ss y1 v ss v ss v ss y31 v ss v ss v ss a1 v dd v dd v dd a31 v dd v dd v dd aa28 v dd v dd v dd aa4 v dd v dd v dd ae28 v dd v dd v dd ae4 v dd v dd v dd ah11 v dd v dd v dd ah15 v dd v dd v dd ah17 v dd v dd v dd ah21 v dd v dd v dd ah25 v dd v dd v dd ah28 v dd v dd v dd ah4 v dd v dd v dd ah7 v dd v dd v dd aj29 v dd v dd v dd aj3 v dd v dd v dd ak2 v dd v dd v dd ak30 v dd v dd v dd pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued lattice semiconductor 59 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function al1 v dd v dd v dd al31 v dd v dd v dd b2 v dd v dd v dd b30 v dd v dd v dd c29 v dd v dd v dd c3 v dd v dd v dd d11 v dd v dd v dd d15 v dd v dd v dd d17 v dd v dd v dd d21 v dd v dd v dd d25 v dd v dd v dd d28 v dd v dd v dd d4 v dd v dd v dd d7 v dd v dd v dd g28 v dd v dd v dd g4 v dd v dd v dd l28 v dd v dd v dd l4 v dd v dd v dd r28 v dd v dd v dd r4 v dd v dd v dd u28 v dd v dd v dd u4 v dd v dd v dd pin information (continued) table 27. 432-pin ebga pinout (continued) all devices discontinued 60 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin information (continued) table 28. 680-pin pbgam pinout pin or3l165b or3l225b function d1 pl1d pl1d i/o e2 pl1c pl1c i/o e1 pl1b pl1b i/o f4 pl1a pl1a i/o f3 pl2d pl2d i/o f2 pl2a pl2a i/o f1 pl3d pl3d i/o-a0/mpi_be0 g5 pl3c pl3c i/o g4 pl3b pl3b i/o g2 pl3a pl3a i/o g1 pl4d pl4d i/o h5 pl4c pl4c i/o h4 pl4b pl4b i/o h2 pl4a pl4a i/o h1 pl5c pl5c i/o j5 pl5b pl5b i/o j4 pl5a pl5a i/o j3 pl6d pl6d i/o j2 pl6c pl6c i/o j1 pl6b pl6b i/o k5 pl6a pl6a i/o k4 pl7d pl7d i/o k3 pl7c pl7c i/o k2 pl7b pl7b i/o k1 pl7a pl7a i/o l5 pl8d pl8d i/o-a1/mpi_be1 l4 pl8c pl8c i/o l2 pl8b pl8b i/o l1 pl8a pl8a i/o m5 pl9d pl9d i/o m4 pl9c pl9c i/o m2 pl9b pl9b i/o m1 pl9a pl9a i/o-a2 n5 pl10d pl10d i/o n4 pl10c pl10a i/o n3 pl10b pl11d i/o n2 pl10a pl11a i/o-a3 n1 pl11c pl12c i/o p5 pl11b pl12b i/o p4 pl11a pl12a i/o p3 pl12d pl13d i/o p2 pl12c pl13c i/o p1 pl12b pl13b i/o all devices discontinued lattice semiconductor 61 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function r5 pl12a pl13a i/o-a4 r4 pl13d pl14d i/o-a5 r2 pl13c pl14a i/o r1 pl13b pl15d i/o t5 pl14d pl16d i/o t4 pl14c pl16a i/o t2 pl14b pl17d i/o t1 pl14a pl17a i/o-a6 u5 peckl peckl i/o-eckl u4 pl15c pl18c i/o u3 pl15a pl18a i/o u2 pl16c pl19c i/o u1 pl16a pl19a i/o-a7/mpi_clk v1 pl17d pl20d i/o v2 pl18c pl21c i/o v3 pl18a pl21a i/o-a8/mpi_rw v4 pl19d pl22d i/o-a9/mpi_a ck v5 pl19c pl22a i/o w1 pl19b pl23d i/o w2 pl19a pl23a i/o w4 pl20d pl24d i/o w5 pl20c pl24a i/o y1 pl20b pl25d i/o y2 pl20a pl25a i/o-a10/mpi_b1 y4 pl21d pl26d i/o y5 pl21c pl26c i/o aa1 pl21b pl26b i/o aa2 pl21a pl26a i/o aa3 pl22d pl27d i/o aa4 pl22c pl27c i/o aa5 pl22b pl27b i/o ab1 pl22a pl27a i/o-a11/mpi_irq ab2 pl23d pl28d i/o-a12 ab3 pl23c pl28b i/o ab4 pl23a pl29c i/o ab5 pl24d pl30d i/o ac1 pl24c pl30c i/o ac2 pl24b pl30b i/o-a13 ac4 pl24a pl30a i/o ac5 pl25d pl31d i/o ad1 pl25c pl31c i/o ad2 pl25b pl31b i/o ad4 pl25a pl31a i/o pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued 62 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function ad5 pl26d pl32d i/o ae1 pl26c pl32c i/o ae2 pl26b pl32b i/o ae3 pl26a pl32a i/o ae4 pl27d pl33d i/o ae5 pl27c pl33c i/o af1 pl27b pl33b i/o af2 pl27a pl33a i/o-a14 af3 pl28d pl34d i/o af4 pl28c pl34c i/o af5 pl28b pl34b i/o ag1 pl28a pl34a i/o ag2 pl29c pl35c i/o ag4 pl29b pl35b i/o ag5 pl29a pl35a i/o ah1 pl30d pl36d i/o ah2 pl30c pl36c i/o ah4 pl30b pl36b i/o ah5 pl30a pl36a i/o-seckll aj1 pl31d pl37d i/o aj2 pl31c pl37c i/o aj3 pl31a pl37a i/o aj4 pl32c pl38c i/o ak1 pl32b pl38b i/o ak2 pl32a pl38a i/o-a15 al1 pcclk pcclk cclk ap4 pb1a pb1a i/o-a16 an5 pb1b pb1b i/o ap5 pb1c pb1c i/o al6 pb1d pb1d i/o am6 pb2a pb2a i/o an6 pb2d pb2d i/o ap6 pb3a pb3a i/o ak7 pb3b pb3b i/o al7 pb3c pb3c i/o an7 pb4a pb4a i/o ap7 pb4b pb4b i/o ak8 pb4c pb4c i/o al8 pb4d pb4d i/o an8 pb5a pb5a i/o ap8 pb5b pb5b i/o ak9 pb5c pb5c i/o al9 pb5d pb5d i/o-a17 pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued lattice semiconductor 63 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function am9 pb6a pb6a i/o an9 pb6b pb6b i/o ap9 pb6c pb6c i/o ak10 pb6d pb6d i/o al10 pb7a pb7a i/o am10 pb7b pb7b i/o an10 pb7c pb7c i/o ap10 pb7d pb7d i/o ak11 pb8a pb8a i/o al11 pb8b pb8b i/o an11 pb8c pb8c i/o ap11 pb8d pb8d i/o ak12 pb9a pb9a i/o al12 pb9b pb9b i/o an12 pb9c pb9c i/o ap12 pb9d pb9d i/o ak13 pb10a pb10a i/o al13 pb10b pb10b i/o am13 pb10c pb10c i/o an13 pb10d pb10d i/o ap13 pb11b pb11b i/o ak14 pb11c pb11c i/o al14 pb11d pb11d i/o am14 pb12a pb12a i/o an14 pb12b pb12b i/o ap14 pb12c pb12c i/o ak15 pb12d pb12d i/o al15 pb13a pb13a i/o an15 pb13b pb13d i/o ap15 pb13c pb14a i/o ak16 pb13d pb14d i/o al16 pb14a pb15a i/o an16 pb14b pb15d i/o ap16 pb14c pb16a i/o ak17 pb14d pb16d i/o al17 pb15b pb17b i/o am17 pb15d pb17d i/o an17 pb16a pb18a i/o ap17 pb16b pb18d i/o ap18 pb16d pb19d i/o an18 peckb peckb i/o-eckb am18 pb17d pb20d i/o al18 pb18b pb21d i/o pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued 64 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function ak18 pb18d pb22d i/o ap19 pb19b pb23b i/o an19 pb19c pb23c i/o al19 pb19d pb23d i/o ak19 pb20a pb24a i/o ap20 pb20b pb24b i/o an20 pb20c pb24c i/o al20 pb20d pb24d i/o ak20 pb21a pb25a i/o-hdc ap21 pb21b pb25d i/o an21 pb21c pb26a i/o am21 pb21d pb26d i/o al21 pb22a pb27a i/o ak21 pb22b pb27d i/o ap22 pb22c pb28a i/o an22 pb23a pb29a i/o-ldc am22 pb23b pb29b i/o al22 pb23c pb29c i/o ak22 pb23d pb29d i/o ap23 pb24a pb30a i/o an23 pb24b pb30b i/o al23 pb24c pb30c i/o ak23 pb24d pb30d i/o ap24 pb25a pb31a i/o an24 pb25b pb31b i/o al24 pb25c pb31c i/o ak24 pb25d pb31d i/o ap25 pb26a pb32a i/o an25 pb26b pb32b i/o am25 pb26c pb32c i/o al25 pb26d pb32d i/o ak25 pb27a pb33a i/o-init ap26 pb27b pb33b i/o an26 pb27c pb33c i/o am26 pb27d pb33d i/o al26 pb28b pb34b i/o ak26 pb28c pb34c i/o ap27 pb28d pb34d i/o an27 pb29a pb35a i/o al27 pb29b pb35b i/o ak27 pb29c pb35c i/o ap28 pb29d pb35d i/o an28 pb30a pb36a i/o pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued lattice semiconductor 65 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function al28 pb30b pb36b i/o ak28 pb30c pb36c i/o ap29 pb30d pb36d i/o an29 pb31a pb37a i/o am29 pb31d pb37d i/o al29 pb32a pb38a i/o ap30 pb32c pb38c i/o an30 pb32d pb38d i/o ap31 pdone pdone done al34 presetn presetn reset ak33 pprgmn pprgmn prgm ak34 pr32a pr38a i/o-m0 aj31 pr32b pr38b i/o aj32 pr31a pr37a i/o aj33 pr31d pr37d i/o aj34 pr30b pr36b i/o ah30 pr30c pr36c i/o ah31 pr30d pr36d i/o ah33 pr29a pr35a i/o ah34 pr29b pr35b i/o ag30 pr29c pr35c i/o ag31 pr29d pr35d i/o ag33 pr28a pr34a i/o ag34 pr28b pr34b i/o af30 pr28c pr34c i/o af31 pr28d pr34d i/o af32 pr27a pr33a i/o af33 pr27b pr33b i/o af34 pr27c pr33c i/o ae30 pr27d pr33d i/o ae31 pr26a pr32a i/o ae32 pr26b pr32b i/o ae33 pr26c pr32c i/o ae34 pr26d pr32d i/o ad30 pr25a pr31a i/o ad31 pr25b pr31b i/o ad33 pr25c pr31c i/o ad34 pr25d pr31d i/o-m1 ac30 pr24a pr30a i/o ac31 pr24b pr30d i/o ac33 pr24c pr29a i/o ac34 pr23a pr28a i/o ab30 pr23b pr28b i/o pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued 66 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function ab31 pr23c pr28c i/o ab32 pr23d pr28d i/o ab33 pr22a pr27a i/o-m2 ab34 pr22b pr27b i/o aa30 pr22c pr27c i/o aa31 pr22d pr27d i/o aa32 pr21a pr26a i/o aa33 pr21b pr26b i/o aa34 pr21c pr26c i/o y30 pr21d pr26d i/o y31 pr20a pr25a i/o-m3 y33 pr20b pr25d i/o y34 pr20c pr24a i/o w30 pr20d pr24d i/o w31 pr19a pr23a i/o w33 pr19b pr23d i/o w34 pr19c pr22b i/o v30 pr18a pr21a i/o v31 pr18b pr21b i/o v32 pr18d pr21d i/o v33 pr17b pr20b i/o v34 pr17d pr20d i/o u34 peckr peckr i/o-eckr u33 pr16d pr19d i/o u32 pr15b pr18b i/o u31 pr15d pr18d i/o u30 pr14b pr17d i/o t34 pr14c pr16a i/o t33 pr14d pr16d i/o t31 pr13a pr15a i/o t30 pr13b pr15d i/o r34 pr13c pr14a i/o r33 pr13d pr14d i/o r31 pr12a pr13a i/o-cs1 r30 pr12b pr13b i/o p34 pr12c pr13c i/o p33 pr12d pr13d i/o p32 pr11a pr12a i/o p31 pr11b pr12b i/o p30 pr11c pr12c i/o n34 pr10a pr11a i/o-cs0 n33 pr10b pr11c i/o n32 pr10c pr11d i/o pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued lattice semiconductor 67 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function n31 pr10d pr10a i/o n30 pr9a pr10c i/o m34 pr9b pr10d i/o m33 pr9c pr9a i/o m31 pr9d pr9d i/o m30 pr8a pr8a i/o-rd /mpi_strb l34 pr8b pr8b i/o l33 pr8c pr8c i/o l31 pr8d pr8d i/o l30 pr7a pr7a i/o k34 pr7b pr7b i/o k33 pr7c pr7c i/o k32 pr7d pr7d i/o k31 pr6a pr6a i/o k30 pr6b pr6b i/o j34 pr6c pr6c i/o j33 pr6d pr6d i/o j32 pr5b pr5b i/o j31 pr5c pr5c i/o j30 pr5d pr5d i/o h34 pr4a pr4a i/o-wr h33 pr4b pr4b i/o h31 pr4c pr4c i/o h30 pr4d pr4d i/o g34 pr3a pr3a i/o g33 pr3b pr3b i/o g31 pr3c pr3c i/o g30 pr3d pr3d i/o f34 pr2a pr2a i/o f33 pr2b pr2b i/o f32 pr2d pr2d i/o f31 pr1a pr1a i/o e34 pr1b pr1b i/o e33 pr1d pr1d i/o d34 prd_cfgn prd_cfgn rd_cfg a31 pt32d pt38d i/o-seckur b30 pt32c pt38c i/o a30 pt32a pt38a i/o d29 pt31d pt37d i/o c29 pt31b pt37b i/o b29 pt31a pt37a i/o a29 pt30d pt36d i/o e28 pt30c pt36c i/o pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued 68 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function d28 pt30b pt36b i/o b28 pt30a pt36a i/o-rdy/rclk/mpi_ale a28 pt29d pt35d i/o e27 pt29c pt35c i/o d27 pt29b pt35b i/o b27 pt29a pt35a i/o a27 pt28d pt34d i/o e26 pt28c pt34c i/o d26 pt28b pt34b i/o c26 pt28a pt34a i/o b26 pt27d pt33d i/o-d7 a26 pt27c pt33c i/o e25 pt27b pt33b i/o d25 pt27a pt33a i/o c25 pt26c pt32c i/o b25 pt26b pt32b i/o a25 pt26a pt32a i/o e24 pt25d pt31d i/o d24 pt25c pt31c i/o b24 pt25b pt31b i/o a24 pt25a pt31a i/o e23 pt24d pt30d i/o d23 pt24c pt30c i/o b23 pt24b pt30b i/o a23 pt24a pt30a i/o e22 pt23d pt29d i/o-d6 d22 pt23c pt29c i/o c22 pt23b pt29b i/o b22 pt23a pt29a i/o a22 pt22d pt28d i/o e21 pt22c pt28c i/o d21 pt22b pt28b i/o c21 pt22a pt28a i/o b21 pt21c pt27c i/o a21 pt21b pt27b i/o e20 pt21a pt27a i/o-d5 d20 pt20d pt26d i/o b20 pt20c pt26a i/o a20 pt20b pt25d i/o e19 pt20a pt25a i/o d19 pt19d pt24d i/o b19 pt19c pt24a i/o a19 pt19b pt23d i/o pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued lattice semiconductor 69 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function e18 pt19a pt23a i/o-d4 d18 peckt peckt i/o-eckt c18 pt17d pt21a i/o b18 pt17c pt20d i/o a18 pt17a pt20a i/o-d3 a17 pt16d pt19d i/o b17 pt16c pt18d i/o c17 pt15a pt17a i/o-d2 d17 pt14d pt16d i/o-d1 e17 pt14c pt16c i/o a16 pt14b pt16b i/o b16 pt14a pt16a i/o d16 pt13d pt15d i/o e16 pt13c pt15c i/o a15 pt13b pt15b i/o b15 pt13a pt15a i/o-d0/din d15 pt12d pt14d i/o e15 pt12c pt14a i/o a14 pt12b pt13d i/o b14 pt12a pt13a i/o c14 pt11d pt12d i/o d14 pt11c pt12a i/o e14 pt11b pt11d i/o a13 pt11a pt11a i/o-dout b13 pt10c pt10c i/o c13 pt10b pt10b i/o d13 pt10a pt10a i/o e13 pt9d pt9d i/o a12 pt9c pt9c i/o b12 pt9b pt9b i/o d12 pt9a pt9a i/o e12 pt8d pt8d i/o a11 pt8c pt8c i/o b11 pt8b pt8b i/o d11 pt8a pt8a i/o e11 pt7d pt7d i/o a10 pt7c pt7c i/o b10 pt7b pt7b i/o c10 pt7a pt7a i/o-tdi d10 pt6d pt6d i/o e10 pt6c pt6c i/o a9 pt6b pt6b i/o b9 pt5d pt5d i/o pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued 70 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function c9 pt5c pt5c i/o d9 pt5b pt5b i/o e9 pt5a pt5a i/o-tms a8 pt4d pt4d i/o b8 pt4c pt4c i/o d8 pt4b pt4b i/o e8 pt4a pt4a i/o a7 pt3d pt3d i/o b7 pt3c pt3c i/o d7 pt3b pt3b i/o e7 pt3a pt3a i/o a6 pt2d pt2d i/o b6 pt2c pt2c i/o c6 pt2a pt2a i/o d6 pt1d pt1d i/o a5 pt1c pt1c i/o b5 pt1a pt1a i/o-tck a4 prd_data prd_data rd_data/tdo a1 v ss v ss v ss a2 v ss v ss v ss a33 v ss v ss v ss a34 v ss v ss v ss b1 v ss v ss v ss b2 v ss v ss v ss b33 v ss v ss v ss b34 v ss v ss v ss c3 v ss v ss v ss c8 v ss v ss v ss c12 v ss v ss v ss c16 v ss v ss v ss c19 v ss v ss v ss c23 v ss v ss v ss c27 v ss v ss v ss c32 v ss v ss v ss d4 v ss v ss v ss d31 v ss v ss v ss h3 v ss v ss v ss h32 v ss v ss v ss m3 v ss v ss v ss m32 v ss v ss v ss n13 v ss v ss v ss n14 v ss v ss v ss n15 v ss v ss v ss pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued lattice semiconductor 71 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function n20 v ss v ss v ss n21 v ss v ss v ss n22 v ss v ss v ss p13 v ss v ss v ss p14 v ss v ss v ss p15 v ss v ss v ss p20 v ss v ss v ss p21 v ss v ss v ss p22 v ss v ss v ss r13 v ss v ss v ss r14 v ss v ss v ss r15 v ss v ss v ss r20 v ss v ss v ss r21 v ss v ss v ss r22 v ss v ss v ss t3 v ss v ss v ss t16 v ss v ss v ss t17 v ss v ss v ss t18 v ss v ss v ss t19 v ss v ss v ss t32 v ss v ss v ss u16 v ss v ss v ss u17 v ss v ss v ss u18 v ss v ss v ss u19 v ss v ss v ss v16 v ss v ss v ss v17 v ss v ss v ss v18 v ss v ss v ss v19 v ss v ss v ss w3 v ss v ss v ss w16 v ss v ss v ss w17 v ss v ss v ss w18 v ss v ss v ss w19 v ss v ss v ss w32 v ss v ss v ss y13 v ss v ss v ss y14 v ss v ss v ss y15 v ss v ss v ss y20 v ss v ss v ss y21 v ss v ss v ss y22 v ss v ss v ss aa13 v ss v ss v ss aa14 v ss v ss v ss pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued 72 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function aa15 v ss v ss v ss aa20 v ss v ss v ss aa21 v ss v ss v ss aa22 v ss v ss v ss ab13 v ss v ss v ss ab14 v ss v ss v ss ab15 v ss v ss v ss ab20 v ss v ss v ss ab21 v ss v ss v ss ab22 v ss v ss v ss ac3 v ss v ss v ss ac32 v ss v ss v ss ag3 v ss v ss v ss ag32 v ss v ss v ss al4 v ss v ss v ss al31 v ss v ss v ss am3 v ss v ss v ss am8 v ss v ss v ss am12 v ss v ss v ss am16 v ss v ss v ss am19 v ss v ss v ss am23 v ss v ss v ss am27 v ss v ss v ss am32 v ss v ss v ss an1 v ss v ss v ss an2 v ss v ss v ss an33 v ss v ss v ss an34 v ss v ss v ss ap1 v ss v ss v ss ap2 v ss v ss v ss ap33 v ss v ss v ss ap34 v ss v ss v ss c5 v dd 2v dd 2v dd 2 c30 v dd 2v dd 2v dd 2 d5 v dd 2v dd 2v dd 2 d30 v dd 2v dd 2v dd 2 e3 v dd 2v dd 2v dd 2 e4 v dd 2v dd 2v dd 2 e5 v dd 2v dd 2v dd 2 e6 v dd 2v dd 2v dd 2 e29 v dd 2v dd 2v dd 2 e30 v dd 2v dd 2v dd 2 e31 v dd 2v dd 2v dd 2 pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued lattice semiconductor 73 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function e32 v dd 2v dd 2v dd 2 f5 v dd 2v dd 2v dd 2 f30 v dd 2v dd 2v dd 2 n16 v dd 2v dd 2v dd 2 n17 v dd 2v dd 2v dd 2 n18 v dd 2v dd 2v dd 2 n19 v dd 2v dd 2v dd 2 p16 v dd 2v dd 2v dd 2 p17 v dd 2v dd 2v dd 2 p18 v dd 2v dd 2v dd 2 p19 v dd 2v dd 2v dd 2 r16 v dd 2v dd 2v dd 2 r17 v dd 2v dd 2v dd 2 r18 v dd 2v dd 2v dd 2 r19 v dd 2v dd 2v dd 2 t13 v dd 2v dd 2v dd 2 t14 v dd 2v dd 2v dd 2 t15 v dd 2v dd 2v dd 2 t20 v dd 2v dd 2v dd 2 t21 v dd 2v dd 2v dd 2 t22 v dd 2v dd 2v dd 2 u13 v dd 2v dd 2v dd 2 u14 v dd 2v dd 2v dd 2 u15 v dd 2v dd 2v dd 2 u20 v dd 2v dd 2v dd 2 u21 v dd 2v dd 2v dd 2 u22 v dd 2v dd 2v dd 2 v13 v dd 2v dd 2v dd 2 v14 v dd 2v dd 2v dd 2 v15 v dd 2v dd 2v dd 2 v20 v dd 2v dd 2v dd 2 v21 v dd 2v dd 2v dd 2 v22 v dd 2v dd 2v dd 2 w13 v dd 2v dd 2v dd 2 w14 v dd 2v dd 2v dd 2 w15 v dd 2v dd 2v dd 2 w20 v dd 2v dd 2v dd 2 w21 v dd 2v dd 2v dd 2 w22 v dd 2v dd 2v dd 2 y16 v dd 2v dd 2v dd 2 y17 v dd 2v dd 2v dd 2 y18 v dd 2v dd 2v dd 2 y19 v dd 2v dd 2v dd 2 pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued 74 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function aa16 v dd 2v dd 2v dd 2 aa17 v dd 2v dd 2v dd 2 aa18 v dd 2v dd 2v dd 2 aa19 v dd 2v dd 2v dd 2 ab16 v dd 2v dd 2v dd 2 ab17 v dd 2v dd 2v dd 2 ab18 v dd 2v dd 2v dd 2 ab19 v dd 2v dd 2v dd 2 aj5 v dd 2v dd 2v dd 2 aj30 v dd 2v dd 2v dd 2 ak3 v dd 2v dd 2v dd 2 ak4 v dd 2v dd 2v dd 2 ak5 v dd 2v dd 2v dd 2 ak6 v dd 2v dd 2v dd 2 ak29 v dd 2v dd 2v dd 2 ak30 v dd 2v dd 2v dd 2 ak31 v dd 2v dd 2v dd 2 ak32 v dd 2v dd 2v dd 2 al5 v dd 2v dd 2v dd 2 al30 v dd 2v dd 2v dd 2 am5 v dd 2v dd 2v dd 2 am30 v dd 2v dd 2v dd 2 a3 v dd v dd v dd a32 v dd v dd v dd b3 v dd v dd v dd b4 v dd v dd v dd b31 v dd v dd v dd b32 v dd v dd v dd c1 v dd v dd v dd c2 v dd v dd v dd c4 v dd v dd v dd c7 v dd v dd v dd c11 v dd v dd v dd c15 v dd v dd v dd c20 v dd v dd v dd c24 v dd v dd v dd c28 v dd v dd v dd c31 v dd v dd v dd c33 v dd v dd v dd c34 v dd v dd v dd d2 v dd v dd v dd d3 v dd v dd v dd d32 v dd v dd v dd pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued lattice semiconductor 75 data addendum march 2002 orca or3lxxxb series fpgas pin or3l165b or3l225b function d33 v dd v dd v dd g3 v dd v dd v dd g32 v dd v dd v dd l3 v dd v dd v dd l32 v dd v dd v dd r3 v dd v dd v dd r32 v dd v dd v dd y3 v dd v dd v dd y32 v dd v dd v dd ad3 v dd v dd v dd ad32 v dd v dd v dd ah3 v dd v dd v dd ah32 v dd v dd v dd al2 v dd v dd v dd al3 v dd v dd v dd al32 v dd v dd v dd al33 v dd v dd v dd am1 v dd v dd v dd am2 v dd v dd v dd am4 v dd v dd v dd am7 v dd v dd v dd am11 v dd v dd v dd am15 v dd v dd v dd am20 v dd v dd v dd am24 v dd v dd v dd am28 v dd v dd v dd am31 v dd v dd v dd am33 v dd v dd v dd am34 v dd v dd v dd an3 v dd v dd v dd an4 v dd v dd v dd an31 v dd v dd v dd an32 v dd v dd v dd ap3 v dd v dd v dd ap32 v dd v dd v dd pin information (continued) table 28. 680-pin pbgam pinout (continued) all devices discontinued 76 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series fpgas include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. table 29. absolute maximum ratings recommended operating conditions table 30. recommended operating conditions parameter symbol min max unit storage temperature t stg ?5 150 ? i/o supply voltage with respect to ground v dd < 4.2 v internal supply voltage v dd 2 < 3.2 v input signal with respect to ground cmos i/o 5 v tolerant i/o ?.5 ?.5 v dd + 0.3 5.8 v v signal applied to high-impedance output ?.5 v dd + 0.3 v maximum package body temperature 220 ? junction temperature t j ?0 125 ? mode or3lxxxb temperature range (ambient) i/o supply voltage (v dd ) internal supply voltage (v dd 2) commercial 0 ? to 70 ? 3.0 v to 3.6 v 2.5 v ?5% industrial ?0 ? to +85 ? 3.0 v to 3.6 v 2.5 v ?5% all devices discontinued lattice semiconductor 77 data addendum march 2002 orca or3lxxxb series fpgas electrical characteristics table 31 . electrical characteristics * on the series 3l devices, the pull-up resistor will externally pull the pin to a level 1.0 v below v dd . or3lxxxb commercial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, 0 ? < t a < 70 ?; industrial: v dd = 3.0 v to 3.6 v, v dd 2 = 2.38 v to 2.63 v, ?0 ? < t a < +85 ?. parameter symbol test conditions or3lxxxb unit min max input voltage: high low v ih v il input con?ured as cmos (clamped to v dd ) 50% v dd gnd ?0.5 v dd + 0.5 30% v dd v v input voltage: high low v ih v il input con?ured as ttl (5 v tolerant) 50% v dd gnd ?0.5 5.8 v 30% v dd v v output voltage: high low v oh v ol v dd = min, i oh = 6 ma or 3 ma v dd = min, i ol = 12 ma or 6 ma 2.4 0.4 v v input leakage current i l v dd = max, v in = v ss or v dd ?0 10 ? standby current: or3l165b or3l225b i ddsb (t a = 25 ?, v dd = 3.3 v, v dd 2 = 2.5 v) internal oscillator running, no output loads, inputs v dd or gnd v dd 2v dd m a m a 1.5 2.0 1.0 1.0 standby current: or3l165b or3l225b i ddsb (t a = 25 ?, v dd = 3.3 v, v dd 2 = 2.5 v) internal oscillator stopped, no output loads, inputs v dd or gnd (after con guration) 1.1 1.5 1.0 1.0 m a m a powerup current: or3l165b or3l225b i pp power supply current at approximately 1 v, within a recommended power supply ramp rate of 1 ms?00 ms 0.4 0.8 m a m a input capacitance c in t a = 25 ?, v dd = 3.3 v, v dd 2 = 2.5 v test frequency = 1 mhz ?pf output capacitance c out t a = 25 ?, v dd = 3.3 v, v dd 2 = 2.5 v test frequency = 1 mhz ?pf done pull-up resistor* r done 100 k m[3:0] pull-up resistors* r m 100 k i/o pad static pull-up current* i pu v dd = 3.6 v, v in = v ss , t a = 0 ? 14.4 50.9 ? i/o pad static pull-down current i pd v dd = 3.6 v, v in = v ss , t a = 0 ? 26 103 ? i/o pad pull-up resistor* r pu v dd = all, v in = v ss , t a = 0 ? 100 k i/o pad pull-down resistor r pd v dd = all, v in = v ss , t a = 0 ? 50 k all devices discontinued 78 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas package thermal characteristics there are four thermal parameters that are in common use: ja, jc, jc, and jb . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system air?w. table 32 contains the currently available thermal speci- ?ations for lattice s fpga packages mounted on both jedec and non-jedec test boards. the thermal val- ues for the newer package types correspond to those packages mounted on a jedec four-layer board. the values for the older packages, however, correspond to those packages mounted on a non-jedec, single- layer, sparse copper board (see note 2). it should also be noted that the values for the older packages are considered conservative. ? ? ja this is the thermal resistance from junction to ambient (a.k.a. - ja , r- , etc.). it is de?ed by the following: where t j is the junction temperature, t a is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced convection measurements. a controlled amount of power (q) is dissipated in the test chip s heater resistor, the chip s temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that ja is expressed in units of ?/watt. ? ? jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance, and it is de?ed by the following: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also expressed in units of ?/watt. ? ? jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is de?ed by the following: the parameters in this equation have been de?ed above. however, the measurements are performed with the case of the part pressed against a water-cooled heat sink so as to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc. jc is a true thermal resistance and is expressed in units of ?/watt. ? ? jb this is the thermal resistance from junction to board (a.k.a. jl ). it is de?ed by the following: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been de?ed above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board so as to draw most of the heat out of the leads. note that jb is expressed in units of ?/watt, and that this parameter and the way it is measured is still in jedec committee. ja t j t a q ------------------- - = jc t j t c q -------------------- = jc t j t c q -------------------- = jb t j t b q ------------------- - = all devices discontinued lattice semiconductor 79 data addendum march 2002 orca or3lxxxb series fpgas package thermal characteristics (continued) fpga maximum junction temperature once the power dissipated by the fpga has been determined (see the estimating power dissipation section), the maximum junction temperature of the fpga can be found. this is needed to determine if speed derating of the device from the 85 ? junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in ?), the maximum junction tempera- ture is approximated by the following: t jmax = t amax + (q ja ) table 32 lists the plastic package thermal characteristics for the orca series fpgas. table 32. plastic package thermal characteristics for the orca series 1 1. mounted on 4-layer jedec standard test board with two power/ground planes. 2. with thermal balls connected to board ground plane. 3. without thermal balls connected to board ground plane. package ja (?/w) t a = 70 ? max t j = 125 ? max at 0 fpm (w) 0 fpm 200 fpm 500 fpm 208-pin sqfp2 1 12.8 10.3 9.1 4.3 240-pin sqfp2 1 13.0 10.0 9.0 4.2 352-pin pbga 1, 2 19.0 16.0 15.0 2.9 352-pin pbga 1, 3 25.5 22.0 20.5 2.1 432-pin ebga 1 11.0 8.5 7.5 5.0 680-pin pbgam1 14.5 tbd tbd 3.8 all devices discontinued 80 80 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas package coplanarity the coplanarity limits of the orca series 3 packages are as follows. table 33. package coplanarity package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 34 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capaci- tance of the lead to the nearest neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capaci- tive crosstalk and the capacitive loading effect of the lead. the lead resistance value, r w , is in m . the parasitic values in table 34 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designer s model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. package type coplanarity limit (mils) ebga 8.0 pbga 8.0 sqfp2 3.15 pbgam1 8.0 table 34. package parasitics 5-3862(f).a figure 12. package parasitics package type l sw l mw r w c 1 c 2 c m l sl l ml 208-pin sqfp2 4 2 200 1 1 1 6? 4? 240-pin sqfp2 4 2 200 1 1 1 7?1 4? 352-pin pbga 5 2 220 1.5 1.5 1.5 7?2 3? 432-pin ebga 4 1.5 500 1 1 0.3 3?.5 0.5? 680-pin pbgam1 3.8 1.3 250 1 1 0.3 2.8?.0 0.5? pad n board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 pad n + 1 l sw r w l sl all devices discontinued lattice semiconductor 81 data addendum march 2002 orca or3lxxxb series fpgas package outline diagrams terms and de nitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for ? and tolerance. typical (typ): when speci?d after a dimension, this indicates the repeated design size if a tolerance is speci?d or repeated basic size if a tolerance is not speci?d. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension. all devices discontinued 82 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas package outline diagrams (continued) 208-pin sqfp2 dimensions are in millimeters. detail c (sqfp2 chip-up) 5-4946(f) 5-3828(f) chip chip bonded face up copper heat sink 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.2 0.1 0 m 0.090/0.200 156 105 30.60 0.20 157 208 53 104 28.00 0.20 exposed heat sink appears on bottom surface: chip bonded face up. (see detail c.) 28.00 0.20 30.60 0.20 pin #1 identifier zone 21.0 ref 21.0 ref 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a all devices discontinued lattice semiconductor 83 data addendum march 2002 orca or3lxxxb series fpgas package outline diagrams (continued) 240-pin sqfp2 dimensions are in millimeters. detail c (sqfp2 chip-up) 5-4946(f) 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 chip chip bonded face up copper heat sink 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail a detail b 180 121 181 240 34.60 0.20 1 32.00 0.20 60 61 120 pin # 1 identi fier zone 32.00 0.20 34.60 0.20 exposed heat sink appears on bottom surface: chip bonded face up. (see detail c.) 24 .2 re f 24. 2 ref 4.10 max 5-3825 (f).a all devices discontinued 84 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas package outline diagrams (continued) 352-pin pbga dimensions are in millimeters. 5-4407(f) note: although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 fpga package. 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 35.00 +0.70 ?.00 30.00 a1 ball identifier zone af ae ad ac ab aa y w v u t r g 25 spaces @ 1.27 = 31.75 p n m l k j h 12345678910 12 14 16 18 22 24 26 20 11 13 15 17 2119 23 25 f e d c b a center array 25 spaces a1 ball 0.75 0.15 35.00 0.20 30.00 +0.70 ?.00 0.20 @ 1.27 = 31.75 for thermal enhancement (optional) corner (see note below) all devices discontinued lattice semiconductor 85 data addendum march 2002 orca or3lxxxb series fpgas package outline diagrams (continued) 432-pin ebga dimensions are in millimeters. 5-4409(f) 0.91 0.06 1.54 0.13 seating plane solder ball 0.63 0.07 0.20 40.00 0.10 40.00 a1 ball m d ag b f k h g e ad l t j n aj c y p ah ae ac aa w u r ak af ab v al a 19 30 26 5 28 2422 23 25 7 20 3129 15 21 18 32 7 11 17 4 6 8 10 12 14 16 2 913 1 30 spaces @ 1.27 = 38.10 30 spaces a1 ball 0.75 0.15 identifier zone 0.10 @ 1.27 = 38.10 corner all devices discontinued 86 lattice semiconductor data addendum march 2002 orca or3lxxxb series fpgas package outline diagrams (continued) 680-pin pbgam dimensions are in millimeters. 5-4406(f) seating plane solder ball 0.50 ?0.10 0.20 35.00 t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 222018 4 6 8 10121416 2 34 52 3 2 5 73 1 29 15 21 32 7 11 17 913 1 33 33 spaces @ 1.00 = 33.00 33 spaces a1 ball 0.64 ?0.15 a1 ball @ 1.00 = 33.00 corner 30.00 1.170 + 0.70 ?0.00 35.00 30.00 + 0.70 ?0.00 identifier zone 2.51 max 0.61 ?0.08 all devices discontinued lattice semiconductor 87 data addendum march 2002 orca or3lxxxb series fpgas ordering information table 35. voltage options table 36. ordering information 1. discontinued per pcn #06-07. contact rochester electronics for available inventory. device voltage or3lxxxb 2.5 v internal/3.3 v i/o commercial device family part number speed grade package type pin/ball count grade packing designator or3l165b or3l165b8ps208-db 1 8 sqfp2 208 c db or3l165b8ps240-db 1 8 sqfp2 240 c db or3l165b8ba352-db 8 pbga 352 c db OR3L165B8BC432-DB 8 ebga 432 c db or3l165b8bm680-db 8 pbgam 680 c db or3l165b7ps208-db 1 7 sqfp2 208 c db or3l165b7ps240-db 1 7 sqfp2 240 c db or3l165b7ba352-db 7 pbga 352 c db or3l165b7bc432-db 7 ebga 432 c db or3l165b7bm680-db 7 pbgam 680 c db or3l225b or3l225b8bc432-db 1 8 ebga 432 c db or3l225b8bm680-db 1 8 pbgam 680 c db or3l225b7bc432-db 1 7 ebga 432 c db or3l225b7bm680-db 1 7 pbgam 680 c db device family or3l165b or3l225b or3lxxxb x x xx xx xxx packing designator db = dry packed tray speed grade package type ba = plastic ball grid array (pbga) bc = enhanced ball grid array (ebga) bm = fine-pitch ball grid array, multilayer (pbgam) ps = power quad shrink flat package (sqfp2) pin/ball count grade blank = commercial i = industrial all devices discontinued www.latticesemi.com copyright ?2002 lattice semiconductor all rights reserved march 2002 da99-011fpga (replaces da99-008fpga and must accompany ds99-087fpga) 1. discontinued per pcn #06-07. contact rochester electronics for available inventory industrial device family part number speed grade package type pin/ball count grade packing designator or3l165b or3l165b7ps208i-db 1 7 sqfp2 208 i db or3l165b7ps240i-db 1 7 sqfp2 240 i db or3l165b7ba352i-db 7 pbga 352 i db or3l165b7bc432i-db 7 ebga 432 i db or3l165b7bm680i-db 7 pbgam 680 i db or3l225b or3l225b7bc432i-db 1 7 ebga 432 i db or3l225b7bm680i-db 1 7 pbgam 680 i db all devices discontinued |
Price & Availability of OR3L165B8BC432-DB
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |