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1 ? 2004 integrated device technology, inc. all rights reserved. dsc-6528/- single channel e1 short haul line interface unit preliminary IDT82V2051E features: ? single channel e1short haul line interfaces supports hps (hitless protection switching) for 1+1 protection without external relays single 3.3 v power supply with 5 v tolerance on digital interfaces meets or exceeds specifications in - itu i.431, g.703,g.736, g.775 and g.823 - etsi 300-166, 300-233 and tbr12/13 software programmable or hardware selectable on: - line terminating impedance (75 ? / 120 ?) - adjustment of arbitrary pulse shape - ja (jitter attenuator) position (receive path or transmit path) - single rail/dual rail system interfaces - hdb3/ami line encoding/decoding - active edge of transmit clock (tclk) and receive clock (rclk) - active level of transmit data (tdata) and receive data (rdata) - receiver or transmitter power down industrial temperature ranges june 2004 the idt logo is a registered trademark of integrated device technology, inc. description: the IDT82V2051E is a single channel line interface unit for e1. in the transmit path, there is an ami/hdb3 encoder, and waveform shaper, line driver, and impedance matching circuit. there is one jitter attenuator, which can be placed in either the receive path or the transmit path. the jitter attenuator can also be disabled. the IDT82V2051E supports both single rail and dual rail system interfaces. to facilitate the network maintenance, a prbs generation/detection circuit is integrated in the chip, and different types of loopbacks can be set according to the applications. two different kinds of e1line termination, 75 ? , and 120 ? are selectable. the chip also provides driver short-circuit protec tion and internal protection diode. the chip can be controlled by either software or hardware. the IDT82V2051E can be used in lan, wan, routers, wireless base stations, iads, imas, imaps, gateways, frame relay access devices, csu/dsu equipment, etc. - high impedance setting for line drivers - prbs (pseudo random bit sequence) generation and detection with 2 15 -1 prbs polynomials for e1 - 16-bit bpv (bipolar pulse violation) /excess zero/prbs error counter - analog loopback, digital loopback, remote loopback cable attenuation indication short circuit protection and internal protection diode for line drivers los (loss of signal) & ais (alarm indication signal) detection supports serial control interface, motorola and intel multiplexed interfaces and hardware control mode package: IDT82V2051E: 44-pin tqfp
2 industrial temperature ranges single channel e1 short haul line interface unit functional block diagram figure-1 block diagram los rclk rd/rdp cv/rdn rtip rring tclk td/tdp tdn ttip tring jitter attenuator prbs generator taos prbs detector data and clock recovery data slicer los/ais detector hdb3/ami decoder digital loopback remote loopback jitter attenuator hdb3/ami decoder waveform shaper line driver analog loopback receiver internal termination transmitter internal termination clock generator register files software control interface pin control mode[1:0] term rxtxm[1:0] puls patt[1:0] ja[1:0] mont lp[1:0] thz rclke rpd r s t vddio vddd vdda vddt mclk in t c s sdo / a c k / rdy sclk/ale/as r d / d s / sclke sdi/ w r /r/ w ad[7:0] 3 industrial temperature ranges single channel e1 short haul line interface unit table of contents 1 IDT82V2051E pin configurations ....................................................................................... 4 2 pin description .............................................................................................................. ......... 5 3 functional description .................................................................................................... 11 3.1 control mode selection ....................................................................................... 11 3.2 transmit path ............................................................................................................. 1 1 3.2.1 transmit path system interface.............................................................. 11 3.2.2 encoder .............................................................................................................. 11 3.2.3 pulse shaper .................................................................................................... 11 3.2.4 transmit path line interface..................................................................... 13 3.2.5 transmit path power down ........................................................................ 13 3.3 receive path ............................................................................................................... 14 3.3.1 receive internal termination.................................................................... 14 3.3.2 line monitor ...................................................................................................... 15 3.3.3 receive sensitivity ......................................................................................... 15 3.3.4 data slicer ........................................................................................................ 15 3.3.5 cdr (clock & data recovery)................................................................................ 15 3.3.6 decoder .............................................................................................................. 15 3.3.7 receive path system interface ................................................................ 15 3.3.8 receive path power down........................................................................... 15 3.4 jitter attenuator .................................................................................................... 16 3.4.1 jitter attenuation function description ............................................ 16 3.4.2 jitter attenuator performance ............................................................. 16 3.5 los and ais detection ............................................................................................. 17 3.5.1 los detection ................................................................................................... 17 3.5.2 ais detection .................................................................................................... 18 3.6 transmit and detect internal patterns ........................................................ 18 3.6.1 transmit all ones ........................................................................................... 18 3.6.2 transmit all zeros......................................................................................... 18 3.6.3 prbs generation and detection ............................................................... 18 3.7 loopback ................................................................................................................... ... 18 3.7.1 analog loopback ............................................................................................ 18 3.7.2 digital loopback ............................................................................................. 19 3.7.3 remote loopback............................................................................................ 19 3.8 error detection/counting and in sertion ...................................................... 21 3.8.1 definition of line coding error ............................................................... 21 3.8.2 error detection and counting ................................................................ 21 3.8.3 bipolar violation and prbs error insertion ...................................... 22 3.9 line driver failure monitoring ........................................................................... 22 3.10 mclk and tclk ............................................................................................................. 23 3.10.1 master clock (mclk) ...................................................................................... 23 3.10.2 transmit clock (tclk)........... ......................................................................... 23 table of contents 4 industrial temperature ranges single channel e1 short haul line interface unit 3.11 microcontroller interfaces ............................................................................. 24 3.11.1 parallel microcontroller interface................................................... 24 3.11.2 serial microcontroller interface ........................................................ 24 3.12 interrupt handling .................................................................................................. 25 3.13 5v tolerant i/o pins .................................................................................................. 25 3.14 reset operation ........................................................................................................ 25 3.15 power supply ............................................................................................................. 2 5 4 programming information .............................................................................................. 26 4.1 register list and map ............................................................................................. 26 4.2 register description .............................................................................................. 27 4.2.1 control registers......................................................................................... 27 4.2.2 transmit path control registers........................................................... 28 4.2.3 receive path control registers ............................................................. 30 4.2.4 network diagnostics control registers ........................................... 31 4.2.5 interrupt control registers ................................................................... 33 4.2.6 line status registers ................................................................................... 35 4.2.7 interrupt status registers ...................................................................... 36 5 hardware control pin summary .................................................................................. 38 6 test specifications .......................................................................................................... .. 40 7 microcontroller interface timing characteristics ......................................... 47 7.1 serial interface timing .......................................................................................... 47 7.2 parallel interface timing ..................................................................................... 48 1 industrial temperature ranges single channel e1 short haul line interface unit list of tables table-1 pin description ......................................................................................................... ....... 5 table-2 transmit waveform value for e1 75 ? ......................................................................... 12 table-3 transmit waveform value for e1 120 ? ....................................................................... 13 table-4 impedance matching for transmitter ............................................................................ 13 table-5 impedance matching for receiver ................................................................................ 14 table-6 criteria of starting speed adjustment........................................................................... 16 table-7 los declare and clear criteria ... ................................................................................. 17 table-8 ais condition ........................................................................................................... ..... 18 table-9 criteria for setting/clearing the prbs_s bit ................................................................ 18 table-10 exz definition ......................................................................................................... ...... 21 table-11 interrupt event........................................................................................................ ....... 25 table-12 register list and map .................................................................................................. . 26 table-13 id: device revision register ....... ................................................................................. 27 table-14 rst: reset register .................................................................................................... . 27 table-15 gcf: global configuration register ............................................................................. 27 table-16 term: transmit and receive terminati on configuration register .............................. 27 table-17 jacf: jitter attenuation configuratio n register ........................................................... 28 table-18 tcf0: transmitter conf iguration register 0 ................................................................. 28 table-19 tcf1: transmitter conf iguration register 1 ................................................................. 29 table-20 tcf2: transmitter conf iguration register 2 ................................................................. 29 table-21 tcf3: transmitter conf iguration register 3 ................................................................. 29 table-22 tcf4: transmitter conf iguration register 4 ................................................................. 30 table-23 rcf0: receiver configuration regist er 0..................................................................... 30 table-24 rcf1: receiver configuration regist er 1..................................................................... 30 table-25 rcf2: receiver configuration regist er 2..................................................................... 31 table-26 maint0: maintenance function control register 0...................................................... 31 table-27 maint1: maintenance function control register 1...................................................... 32 table-28 maint2: maintenance function control register 2...................................................... 32 table-29 maint3: maintenance function control register 3...................................................... 32 table-30 maint4: maintenance function control register 4...................................................... 32 table-31 maint5: maintenance function control register 5...................................................... 32 table-32 maint6: maintenance function control register 6...................................................... 33 table-33 intm0: interrupt ma sk register 0 ................................................................................. 33 table-34 intm1: interrupt ma sked register 1 ............................................................................. 34 table-35 intes: interrupt trigger edge sele ct register ............................................................. 34 table-36 stat0: line status r egister 0 (real time status m onitor)............................................. 35 table-37 stat1: line status r egister 1 (real time status m onitor)............................................. 35 table-38 ints0: interrupt stat us register 0 ................................................................................ 36 table-39 ints1: interrupt stat us register 1 ................................................................................ 36 table-40 cnt0: error counter l-byte register............................................................................ 37 table-41 cnt1: error counter h-byte register1 ......................................................................... 37 table-42 hardware control pin summary ................................................................................... 38 table-43 absolute maximum rating ............................................................................................ 40 table-44 recommended operation conditions ........................................................................... 40 table-45 power consumption...................................................................................................... 40 table-46 dc characteristics ..................................................................................................... ... 41 2 industrial temperature ranges single channel e1 short haul line interface unit table-47 receiver electrical characteristic s................................................................................ 41 table-48 transmitter electrical characterist ics............................................................................ 42 table-49 transmitter and receiver timing ch aracteristics ......................................................... 43 table-50 jitter tolerance ....................................................................................................... ...... 44 table-51 jitter attenuator characteristics .................................................................................... 4 5 table-52 serial interface ti ming characteristics ......................................................................... 47 table-53 multiplexed motorola read timing characteristics....................................................... 48 table-54 multiplexed motorola write timing c haracteristics ....................................................... 49 table-55 multiplexed intel read timing characteristics .............................................................. 50 table-56 multiplexed intel write timing charac teristics .............................................................. 51 3 industrial temperature ranges single channel e1 short haul line interface unit list of figures figure-1 block diagram ......................................................................................................... ........ 2 figure-1 IDT82V2051E tqfp44 package pin assignment .......................................................... 4 figure-2 waveform template diagram ....................................................................................... 11 figure-3 pulse template test circuit .......................................................................................... 1 2 figure-4 receive path function block diagram .......................................................................... 14 figure-5 transmit/receive line circuit ....................................................................................... 14 figure-6 monitoring receive line in another chip ...................................................................... 15 figure-7 monitor transmit line in another chip .......................................................................... 15 figure-8 jitter attenuator ..................................................................................................... ........ 16 figure-9 los declare and clear ................................................................................................. 17 figure-10 analog loopback ...................................................................................................... .... 19 figure-11 digital loopback ..................................................................................................... ....... 19 figure-12 remote loopback ...................................................................................................... ... 20 figure-13 auto report mode ..................................................................................................... .... 21 figure-14 manual report mode ................................................................................................... .. 22 figure-15 tclk operation flowchart .......... .................................................................................. 2 3 figure-16 serial microc ontroller interface function timing ........................................................... 24 figure-17 transmit system interface timing ................................................................................ 44 figure-18 receive system interface timing ................................................................................. 44 figure-19 e1 jitter tolerance performance .................................................................................. 45 figure-20 e1 jitter transfer performance ..................................................................................... 46 figure-21 serial interface write timing ........................................................................................ .47 figure-22 serial interface read timing with sclke=1 ................................................................ 47 figure-23 serial interface read timing with sclke=0 ................................................................ 47 figure-24 multiplexed motorola read timing ................................................................................ 48 figure-25 multiplexed motorola write timing ................................................................................ 49 figure-26 multiplexed intel read timing ....................................................................................... 5 0 figure-27 multiplexed intel write timing ....................................................................................... 51 4 industrial temperature ranges single channel e1 short haul line interface unit 1 IDT82V2051E pin configurations figure-1 IDT82V2051E tqfp44 package pin assignment tclk tdp / td tdn rclk rdp / rd rdn / cv los vddd mclk gndd rclke IDT82V2051E 1 2 3 4 5 6 7 8 9 10 11 14 12 13 15 18 16 17 19 22 20 21 44 41 43 42 40 37 39 38 36 35 34 ad7 ad6 ad5 ad4 /puls ad3 ad2 / rpd ad1 / patt1 ad0 / patt0 ale / as / sclk/ lp1 w r / r/ w / sdi / lp0 rdy / ack / sdo / term ic vddt tring ttip gndt gnda rring rtip vdda ref ic 33 32 31 30 29 28 27 26 25 24 23 rd / ds / sclke / mont cs / rxtxm1 int / rxtxm0 vddio gndio mode1 mode0 ja1 ja0 thz rst 5 industrial temperature ranges single channel e1 short haul line interface unit notes: 1. tclk missing: the state of tclk continues to be high level or low level over 70 mclk cycles. 2 pin description table-1 pin description name type pin no. description ttip tring analog output 37 36 ttip/tring: transmit bipolar tip/ring these pins are the differential line driver outputs. they will be in high impedance state under the following conditions: ? thz pin is high; thz bit is set to 1; loss of mclk; loss of tclk (exceptions: remote loopback; transmit internal pattern by mclk); transmit path power down; after software reset; pin reset and power on. rtip rring analog input 41 40 rtip/rring: receive bipolar tip/ring these signals are the differential receiver inputs. td/tdp tdn i2 3 td: transmit data when the device is in single rail mode, the nrz data to be transmitted is input on this pin. data on td pin is sampled into the device on the active edge of tclk and is encoded by ami, hdb3 line code rules before being transmitted. in this mode, tdn should be connected to ground. tdp/tdn: positive/negative transmit data when the device is in dual rail mode, the nrz data to be transmitted for positive/negative pulse is input on these pins. data on tdp/tdn pin is sampled into the device on the active edge of tclk. the line code in dual rail mode is as follows: tclk i 1 tclk: transmit clock input this pin outputs 2.048 mhz. the transmit data at td/tdp or tdn is sampled into the device on the active edge of tclk. if tclk is missing 1 and the tclk missing interrupt is not masked, an interrupt will be generated. rd/rdp cv/rdn o5 6 rd: receive data output in single rail mode, this pin outputs nrz data. the data is decoded according to ami, hdb3 code rules. cv: code violation indication in single rail mode, the bpv/cv code violation will be reported by driving the cv pin to high level for a full clock cycle. hdb 3 line code violation can be indicated if the hdb3 decoder is enabled. when ami decoder is selected, bipolar violation will be in di- cated. in hardware control mode, the exz, bpv/cv errors in received data stream are always monitored by the cv pin if single rail mode is chosen. rdp/rdn: positive/negative receive data output in dual rail mode, this pin outputs the re-timed nrz data when cdr is enabled, or directly outputs the raw rz slicer data if cd r is bypassed. active edge and level select: data on rdp/rdn or rd is clocked with either the rising or the falling edge of rclk. the active polarity is also selectable. rclk o 4 rclk: receive clock output this pin outputs 2.048 mhz. under los condition with ais enabled (bit aise=1), rclk is derived from mclk. in clock recovery mode, this signal provides the clock recovered from the rtip/rring signal. the receive data (rd in single rail mode or rdp and rdn in dual rail mode) is clocked out of the device on the active edge of rclk. if clock recovery is bypassed, rclk is the exclusive or (xor) output of the dual rail slicer data rdp and rdn. this signal can be used in applications with external clock recovery circuitry. tdp tdn output pulse 00space 0 1 positive pulse 1 0 negative pulse 11space 6 industrial temperature ranges single channel e1 short haul line interface unit mclk i 9 mclk: master clock input mclk is a 2.048 mhz master input clock. this reference clock is used to generate several internal reference signals: timing reference for the integrated clock recovery unit. timing reference for the integrated digital jitter attenuator. timing reference for microcontroller interface. generation of rclk signal during a loss of signal condition. reference clock to transmit all ones, all zeros, prbs pattern as well as activate or deactivate inband loopback code if mclk is selected as the reference clock. note that for atao and ais, mclk is always used as the reference clock. reference clock during the transmit all ones (tao) condition or sending prbs in hardware control mode. the loss of mclk will put ttip/tring output into high impedance. los o 7 los: loss of signal output this is an active high signal used to indicate the loss of received signal. when los pin becomes high, it indicates the loss of received signal. the los pin will become low automatically when valid received signal is detected again. the criteria of loss of signal are described in 3.6 los and ais detection . ref i 43 ref: reference resistor an external resistor (3k ? , 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit. mode1 mode0 i17 16 mode[1:0]: operation mode of control interface select the level on these two pins determines which control mode is used to control the device as follows: the serial microcontroller interface consists of cs , sclk, sclke, sdi, sdo and int pins. sclke is used for the selection of the active edge of sclk. the parallel multiplexed microcontroller interface consists of cs , ad[7:0], ds / rd , r/ w / wr , ale/as, ack /rdy and int pins. (refer to section 3.12 microcontroller interfaces for details) hardware interface consists of puls, thz, rclke, lp[1 :0], patt[1:0], ja[1:0], mont, term, eq, rpd, mode[1:0] and rxtxm[1:0] rclke i 11 rclke: the active edge of rclk select in hardware control mode, this pin selects the active edge of rclk l= select the rising edge as the active edge of rclk h= select the falling edge as the active edge of rclk in software control mode, this pin should be connected to gndio. cs rxtxm1 i21 cs : chip select in serial or parallel microcontroller interface mode, this is the active low enable signal. a low level on this pin enables ser ial or parallel microcontroller interface. rxtxm[1:0]: receive and transmit path operation mode select in hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as ami or hdb3 lin e coding: 00= single rail with hdb3 coding 01= single rail with ami coding 10= dual rail interface with cdr enabled 11= slicer mode (dual rail interface with cdr disabled) table-1 pin description (continued) name type pin no. description mode[1:0] control interface mode 00 hardware interface 01 serial microcontroller interface 10 parallel ?multiplexed -motorola interface 11 parallel ?multiplexed -intel interface 7 industrial temperature ranges single channel e1 short haul line interface unit int rxtxm0 o i 20 int : interrupt request in software control mode, this pin outputs the general interrupt request for all interrupt sources. these interrupt sources can be masked individually via registers ( intm0, 14h ) and ( intm1, 15h ). the interrupt status is reported via the registers ( ints0, 19h ) and ( ints1, 1ah ). output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by set ting int_pin[1:0] ( gcf, 02h ). rxtxm0 see rxtxm1 above. sclk ale as lp1 i 25 sclk: shift clock in serial microcontroller interface mode, this signal is the shift clock for the serial interface. configuration data on sdi pi n is sam- pled on the rising edge of sclk. configuration and status data on sdo pin is clocked out of the device on the falling edge of sclk if sclke pin is high, or on the rising edge of sclk if sclke pin is low. ale: address latch enable in parallel microcontroller interface mode with multiplexed intel interface, the address on ad[7:0] is sampled into the device on the falling edge of ale. as: address strobe in parallel microcontroller interface mode with multiplexed motorola interface, the address on ad[7:0] is latched into the devi ce on the falling edge of as. lp[1:0]: loopback mode select when the chip is configured by hardware, this pin is used to select loopback operation modes 00= no loopback 01= analog loopback 10= digital loopback 11= remote loopback sdi wr r/ w lp0 i 24 sdi: serial data input in serial microcontroller interface mode, this signal is the input data to the serial interface. configuration data at sdi pin is sam- pled by the device on the rising edge of sclk. wr : write strobe in intel parallel multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. the da ta on ad[7:0] is sampled into the device in a write operation. r/ w : read/write select in motorola parallel multiplexed interface mode, this pin is low for write operation and high for read operation. lp0 see lp1 above. table-1 pin description (continued) name type pin no. description 8 industrial temperature ranges single channel e1 short haul line interface unit sdo ack rdy term o i 23 sdo: serial data output in serial microcontroller interface mode, this signal is the output data of the serial interface. configuration or status data at sdo pin is clocked out of the device on the falling edge of sclk if sclke pin is high, or on the rising edge of sclk if sclke pin is low. ack : acknowledge output in motorola parallel mode interface, the low level on this pin means: the valid information is on the data bus during a read operation. the write data has been accepted during a write cycle. rdy: ready signal output in intel parallel mode interface, the low level on this pin means a read or write operation is in progress; a high acknowledges a read or write operation has been completed. term: internal or external termination select in hardware mode this pin selects internal or external impedance matching for both receiver and transmitter. 0 = ternary interface with external impedance matching network 1 = ternary interface with internal impedance matching network sclke rd ds mont i 22 sclke: serial clock edge select in serial microcontroller interface mode, this signal selects the active edge of sclk for outputting sdo. the output data is va lid after some delay from the active clock edge. it can be sampled on the opposite edge of the clock. the active clock edge which clocks the data out of the device is selected as shown below: rd : read strobe in intel parallel multiplexed interface mode, the data is driven to ad[7:0] by the device during low level of rd in a read operation. ds : data strobe in motorola parallel multiplexed interface mode, this signal is the data strobe of the parallel interface. in a write operation (r/ w = 0), the data on ad[7:0] is sampled into the device. in a read operation (r/ w = 1), the data is driven to ad[7:0] by the device. mont: receive monitor gain select in hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver: 0= 0db 1= 26db ad7 i/o 33 ad7: address/data bus bit7 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor in hardware control mode, this pin should be tied to ground. ad6 i/o 32 ad6: address/data bus bit6 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. in hardwar control mode, this pin should be tied to ground. ad5 i/o 31 ad5: address/data bus bit5 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. in hardware control mode, this pin should be tied to ground. table-1 pin description (continued) name type pin no. description sclke sclk low rising edge is the active edge. high falling edge is the active edge. 9 industrial temperature ranges single channel e1 short haul line interface unit ad4 puls i/o i 30 ad4: address/data bus bit4 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor.. in hardware control mode this pin is used to select the internal termination impedance 75 ? /120 ? .refer to hardware control pin summary for details. ad3 i/o 29 ad3: address/data bus bit3 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. in hardware control mode, this pin should be tied to ground ad2 rpd i/o i 28 ad2: address/data bus bit2 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. rpd: receiver power down control in hardware control mode 0= normal operation 1= receiver power down ad1 patt1 i/o i 27 ad1: address/data bus bit1 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. patt[1:0]: transmit pattern select in hardware control mode, this pin selects the transmit pattern 00 = normal 01= all ones 10= prbs 11= transmitter power down ad0 patt0 i/o i 26 ad0: address/data bus bit0 in intel/motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontro ller interface. in serial microcontroller interface mode, this pin should be connected to ground through a 10 k ? resistor. see above. table-1 pin description (continued) name type pin no. description 10 industrial temperature ranges single channel e1 short haul line interface unit ja1 i 15 ja[1:0]: jitter attenuation position, bandwidth and the depth of fifo select (only used for hardware control mode) 00 = ja is disabled 01 = ja in receiver, broad bandwidth, fifo=64 bits 10 = ja in receiver, narrow bandwidth, fifo=128 bits 11 = ja in transmitter, narrow bandwidth, fifo=128 bits in software control mode, this pin should be connected to ground. ja0 i 14 see above. rst i12 rst : hardware reset the chip is forced to reset state if a low signal is input on this pin for more than 100ns. thz i 13 thz: transmitter driver high impedance enable this signal enables or disables transmitter driver. a low level on this pin enables the driver while a high level on this pin p laces driver in high impedance state. note that the functionality of the internal circuits is not affected by this signal. power supplies and grounds vddio - 19 3.3 v i/o power supply gndio - 18 i/o ground vddt - 35 3.3 v power supply for transmitter driver gndt - 38 analog ground for transmitter driver vdda - 42 3.3 v analog core power supply gnda - 39 analog core ground vddd - 8 digital core power supply gndd - 10 digital core ground others ic - 34 ic: internal connection internal use. this pin should be left open when in normal operation. ic - 44 ic: internal connection internal use. this pin should be connected to ground when in normal operation. table-1 pin description (continued) name type pin no. description 11 industrial temperature ranges single channel e1 short haul line interface unit 3 functional description 3.1 control mode selection the IDT82V2051E can be configured by software or by hardware. the software control mode supports serial control interface, motorola multi- plexed control interface and intel multiplexed control interface. the con- trol mode is selected by mode1 and mode0 pins as follows: the serial microcontroller interface consists of cs , sclk, sclke, sdi, sdo and int pins. sclke is used for the selection of active edge of sclk. the parallel multiplexed microcontroller interface consists of cs , ad[7:0], ds / rd , r/ w / wr , ale/as, ack /rdy and int pins. hardware interface consists of puls,thz, rclke, lp[1:0], patt[1:0], ja[1:0], mont, term, rpd, mode[1:0] and rxtxm[1:0]. refer to 5 hardware control pin summary for details about hardware control. 3.2 transmit path the transmit path of IDT82V2051E consists of an encoder, an optional jitter attenuator, a waveform shaper, a line driver and a programmable transmit termination. 3.2.1 transmit path system interface the transmit path system interface consists of tclk pin, td/tdp pin and tdn pin. tclk input clock frequency is a 2.048 mhz . if tclk is missing for more than 70 mclk cycles, an interrupt will be generated if it is not masked. transmit data is sampled on the td/tdp and tdn pins by the active edge of tclk. the active edge of tclk can be selected by the tclk_sel bit ( tcf0, 05h ). and the active level of the data on td/tdp and tdn can be selected by the td_inv bit ( tcf0, 05h ). in hardware control mode, the falling edge of tclk and the active high of transmit data are always used. the transmit data from the system side can be provided in two different ways: single rail and dual rail. in single rail mode, only td pin is used for transmitting data and the t_md[1] bit ( tcf0, 05h ) should be set to ?0?. in dual rail mode, both tdp pin and tdn pin are used for transmitting data, the t_md[1] bit ( tcf0, 05h ) should be set to ?1?. 3.2.2 encoder in single rail mode, the encoder can be configured to be a hdb3 encoder or an ami encoder by setting t_md[0] bit ( tcf0, 05h ). when dual rail mode is selected (bit t_md[1] is ?1?), the encoder is by- passed. in dual rail mode, a logic ?1? on the tdp pin and a logic ?0? on the tdn pin results in a negative pulse on the ttip/tring; a logic ?0? on tdp pin and a logic ?1? on tdn pin results in a positive pulse on the ttip/tring. if both tdp and tdn are high or low, the ttip/tring outputs a space (refer to td/tdp, tdn pin description ). in hardware control mode, the operation mode of receive and transmit path can be selected by setting rxtxm1 and rxtxm0 pins. refer to 5 hardware control pin summary for details. 3.2.3 pulse shaper the IDT82V2051E provides either a preset e1 pulse template or a user- programmable arbitrary waveform template. in software control mode, the pulse shape can be selected by setting the related registers. 3.2.3.1 e1 pulse template the e1 pulse is shown in figure-3 according to the g.703 and the mea- suring diagram is shown in figure-4 . in internal impedance matching mode, if the cable impedance is 75 ? , the puls[3:0] bits ( tcf1, 06h ) should be set to ?0000?; if the cable impedance is 120 ? , the puls[3:0] bits ( tcf1, 06h ) should be set to ?0001?. in exte rnal impedance matching mode, for both e1/75 ? and e1/120 ? cable impedance, puls[3:0] should be set to ?0001?. figure-2 e1 waveform template diagram control interface mode 00 hardware interface 01 serial microcontroller interface. 10 parallel ?multiplexed -motorola interface 11 parallel ?multiplexed -intel interface -0 .6 -0 .4 -0 .2 0 0 .2 0 .4 0.6 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 tim e in u nit intervals normalized amplitude 12 industrial temperature ranges single channel e1 short haul line interface unit figure-3 e1 pulse template test circuit 3.2.3.2 user-programmable arbitrary waveform when the puls[3:0] bits are set to ?11xx?, user-programmable arbitrary waveform generator mode can be used. this allows the transmitter perfor- mance to be tuned for a wide variety of line condition or special application. each pulse shape can extend up to 4 uis (unit interval), addressed by ui[1:0] bits ( tcf3, 08h ) and each ui is divided into 16 sub-phases, addressed by the samp[3:0] bits ( tcf3, 08h ). the pulse amplitude of each phase is represented by a binary byte, within the range from +63 to -63, stored in wdat[6:0] bits ( tcf4, 09h ) in signed magnitude form. the most positive number +63 (d) represents the positive maximum amplitude of the transmit pulse while the most negative number -63 (d) represents the max- imum negative amplitude of the transmit pulse. therefore, up to 64 bytes are used. the e1 standard templates are stored in an on-chip rom. user can select one of them as reference and make some changes to get the desired wave- form. user can change the wave shape and the amplitude to get the desired pulse shape. in order to do this, firstly, users can choose a set of waveform value from the following two tables, which is the most similar to the desired pulse shape. table-2 , and table-3 , list the sample data and scaling data of each of the two templates. then modify the corresponding sample data to get the desired transmit pulse shape. secondly, through the value of scal[5:0] bits increased or decreased by 1, the pulse amplitude can be scaled up or down at the percentage ratio against the standard pulse amplitude if needed. for different pulse shapes, the value of scal[5:0] bits and the scaling percentage ratio are different. the following twelve tables list these values. do the followings step by step, the desired waveform can be pro- grammed, based on the selected waveform template: (1).select the ui by ui[1:0] bits ( tcf3, 08h ) (2).specify the sample address in the selected ui by samp [3:0] bits ( tcf3, 08h ) (3).write sample data to wdat[6:0] bits ( tcf4, 09h ). it contains the data to be stored in the ram, addressed by the selected ui and the corresponding sample address. (4).set the rw bit ( tcf3, 08h ) to ?0? to implement writing data to ram, or to ?1? to implement read data from ram (5).implement the read from ram/write to ram by setting the done bit ( tcf3, 08h ) repeat the above steps until all the sample data are written to or read from the internal ram. (6).write the scaling data to scal[5:0] bits ( tcf2, 07h ) to scale the amplitude of the waveform based on the selected standard pulse amplitude when more than one ui is used to compose the pulse template, the over- lap of two consecutive pulses could make the pulse amplitude overflow (exceed the maximum limitation) if the pulse amplitude is not set properly. this overflow is captured by dac_ov_is bit ( ints1, 1ah ), and, if enabled by the dac_ov_im bit ( intm1, 15h ), an interrupt will be generated. the following tables give all the sample data based on the preset pulse templates in detail for reference. for preset pulse templates scaling up/ down against the pulse amplitude is not supported. 1. table-2 transmit waveform value for e1 75 ? 2. table-3 transmit waveform value for e1 120 ? IDT82V2051E v out r load ttip tring note: 1. for r load = 75 ? (nom), v out (peak)=2.37v (nom) 2. for r load =120 ? (nom), v out (peak)=3.00v (nom) table-2 transmit waveform value for e1 75 ? sample ui 1 ui 2 ui 3 ui 4 1 0000000 0000000 0000000 0000000 2 0000000 0000000 0000000 0000000 3 0000000 0000000 0000000 0000000 4 0001100 0000000 0000000 0000000 5 0110000 0000000 0000000 0000000 6 0110000 0000000 0000000 0000000 7 0110000 0000000 0000000 0000000 8 0110000 0000000 0000000 0000000 9 0110000 0000000 0000000 0000000 10 0110000 0000000 0000000 0000000 11 0110000 0000000 0000000 0000000 12 0110000 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 scal[5:0] = 100001 (default), one step change of this value of scal[5:0] results in 3% scaling up/down against the pulse amplitude. 13 industrial temperature ranges single channel e1 short haul line interface unit 3.2.4 transmit path line interface the transmit line interface consists of ttip pin and tring pin. the impedance matching can be realized by the internal impedance matching circuit or the external impedance matc hing circuit. if t_term[2] is set to ?0?, the internal impedance matching circuit will be selected. in this case, the t_term[1:0] bits ( term, 03h ) can be set to choose 75 ? , or 120 ? internal impedance of ttip/tring. if t_term[2] is set to ?1?, the internal impedance matching circuit will be disabled. in this case, the external impedance matching circuit will be used to realize the impedance matching. figure-5 shows the appropriate external components to connect with the cable. table-4 is the list of the recommended impedance matching for transmitter. in hardware control mode, term pin can be used to select impedance matching for both receiver and transmitter. if term pin is low, external impedance network will be used for impedance matching. if term pin is high, internal impedance will be used for impedance matching and puls pin will be set to select the specific internal impedance. refer to 5 hard- ware control pin summary for details. the ttip/tring pins can also be turned into high impedance by setting the thz bit ( tcf1, 06h ) to ?1?. in this state, the internal transmit circuits are still active. in hardware control mode, ttip/tring can be turned into high imped- ance by pulling thz pin to high. refer to 5 hardware control pin summary for details. besides, in the following cases, both ttip/tring pins will also become high impedance: loss of mclk; loss of tclk (exceptions: remote loopback; transmit internal pattern by mclk); transmit path power down; after software reset; pin reset and power on. note : the precision of the resistors should be better than 1% 3.2.5 transmit path power down the transmit path can be powered dow n by setting the t_off bit ( tcf0, 05h ) to ?1?. in this case, the ttip/tring pins are turned into high imped- ance. in hardware control mode, the transmit path can be powered down by pulling both patt1 and patt0 pins to high. refer to 5 hardware con- trol pin summary for details. table-3 transmit waveform value for e1 120 ? sample ui 1 ui 2 ui 3 ui 4 1 0000000 0000000 0000000 0000000 2 0000000 0000000 0000000 0000000 3 0000000 0000000 0000000 0000000 4 0001111 0000000 0000000 0000000 5 0111100 0000000 0000000 0000000 6 0111100 0000000 0000000 0000000 7 0111100 0000000 0000000 0000000 8 0111100 0000000 0000000 0000000 9 0111100 0000000 0000000 0000000 10 0111100 0000000 0000000 0000000 11 0111100 0000000 0000000 0000000 12 0111100 0000000 0000000 0000000 13 0000000 0000000 0000000 0000000 14 0000000 0000000 0000000 0000000 15 0000000 0000000 0000000 0000000 16 0000000 0000000 0000000 0000000 scal[5:0] = 100001 (default), one step change of this value of scal[5:0] results in 3% scaling up/down against the pulse amplitude. table-4 impedance matching for transmitter cable configuration internal termination external termination t_term[2:0] puls r t t_term[2:0] puls r t e1/75 ? 000 0 0 ? 1xx 1 9.4 ? e1/120 ? 001 1 0 ? 1 14 industrial temperature ranges single channel e1 short haul line interface unit 3.3 receive path the receive path consists of receiv e internal termination, monitor gain, amplitude/wave shape detector, digital tuning controller, data slicer, cdr (clock & data recovery), optional jitter attenuator, decoder and los/ais detector. refer to figure-4 . 3.3.1 receive internal termination the impedance matching can be realized by the internal impedance matching circuit or the external impedance matching circuit. if r_term[2] is set to ?0?, the internal impedance matching circuit will be selected. in this case, the r_term[1:0] bits ( term, 03h ) can be set to choose 75 ? , or 120 ? internal impedance of rtip/rring. if r_term[2] is set to ?1?, the internal impedance matching circuit will be disabled. in this case, the exter- nal impedance matching circuit will be used to realize the impedance matching. figure-5 shows the appropriate external components to connect with the cable. table-5 is the list of the recommended impedance matching for receiver. figure-4 receive path function block diagram figure-5 transmit/receive line circuit table-5 impedance matching for receiver cable configuration internal termination external termination r_term[2:0] r r r_term[2:0] r r e1/75 ? 000 120 ? 1xx 75 ? e1/120 ? 001 120 ? los/ais detector data slicer decoder los rclk rdp rdn clock and data recovery jitter attenuator monitor gain rtip receive internal termination rring a b ? ? ?? r x line r r ? ? t x line r t r t rtip rring tring ttip IDT82V2051E vddt vddt d4 d3 d2 d1 1 : 1 2 : 1 d6 d5 d8 d7 cp vdda vdda ? 0.1 f gndt vddt 68 f 1 3.3 v ? 0.1 f gnda vdda 68 f 3.3 v 1 note : 1. common decoupling capacitor 2. cp 0-560 (pf) 3. d1 - d8, motorola - mbr0540t1; international rectifier - 11dq04 or 10bq060 ? ? ? ? 15 industrial temperature ranges single channel e1 short haul line interface unit in hardware control mode, term, puls pins can be used to select impedance matching for both receiver and transmitter. if term pin is low, external impedance network will be used for impedance matching. if term pin is high, internal impedance will be used for impedance matching and puls pin can be set to select the specific internal impedance. refer to 5 hardware control pin summary for details. 3.3.2 line monitor the non-intrusive monitoring on channels located in other chips can be performed by tapping the monitored channel through a high impedance bridging circuit. refer to figure-6 and figure-8 . after a high resistance bridging circui t, the signal arriving at the rtip/ rring is dramatically attenuated. to compensate this attenuation, the monitor gain can be used to boost the signal by 22 db, 26 db and 32 db, selected by mg[1:0] bits ( rcf2, 0ch ). for normal operation, the monitor gain should be set to 0 db. in hardware control mode, mont pin can be used to set the monitor gain. when mont pin is low, the monitor gain is 0 db. when mont pin is high, the monitor gain is 26 db. refer to 5 hardware control pin summary for details. figure-6 monitoring receive line in another chip figure-7 monitor transmit line in another chip 3.3.3 data slicer the data slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. the threshold can be 40%, 50%, 60% or 70%, as selected by the slice[1:0] bits ( rcf2, 0ch ). the output of the data slicer is forwarded to the cdr (clock & data recov- ery) unit or to the rdp/rdn pins directly if the cdr is disabled. 3.3.4 cdr (clock & data recovery) the cdr is used to recover the clock and data from the received signal. the recovered clock tracks the jitter in the data output from the data slicer and keeps the phase relationship between data and clock during the absence of the incoming pulse. the cdr can also be by-passed in the dual rail mode. when cdr is by-passed, the data from the data slicer is output to the rdp/rdn pins directly. 3.3.5 decoder the r_md[1:0] bits ( rcf0, 0ah ) are used to select the ami decoder or hdb3 decoder. when the chip is configured by hardware, the operation mode of receive and transmit path can be selected by setting rxtxm1 and rxtxm0 pins. refer to 5 hardware control pin summary for details. 3.3.6 receive path system interface the receive path system interface consists of rclk pin, rd/rdp pin and rdn pin. the rclk outputs a recovered 2.048 mhz clock. the received data is updated on the rd/rdp and rdn pins on the active edge of rclk. the active edge of rclk can be selected by the rclk_sel bit ( rcf0, 0ah ). and the active level of the data on rd/rdp and rdn can be selected by the rd_inv bit ( rcf0, 0ah ). in hardware control mode, only the active edge of rclk can be selected. if rclke is set to high, the falling edge will be chosen as the active edge of rclk. if rclke is set to low, the rising edge will be chosen as the active edge of rclk. the active level of the data on rd/rdp and rdn is the same as that in software control mode. the received data can be output to the system side in two different ways: single rail or dual rail, as selected by r_md bit [1] ( rcf0, 0ah ). in single rail mode, only rd pin is used to output data and the rdn/cv pin is used to report the received errors. in dual rail mode, both rdp pin and rdn pin are used for outputting data. in the receive dual rail mode, the cdr unit can be by-passed by setting r_md[1:0] to ?11? (binary). in this situation, the output data from the data slicer will be output to the rdp/rdn pins directly, and the rclk outputs the exclusive or (xor) of the rdp and rdn. this is called receiver slicer mode. in this case, the transmit path is still operating in dual rail mode. 3.3.7 receive path power down the receive path can be powered down by setting r_off bit ( rcf0, 0ah ) to ?1?. in this case, the rclk, rd/rdp, rdn and los will be logic low. in hardware control mode, receiver power down can be selected by pull- ing rpd pin to high. refer to 5 hardware control pin summary for more details. rtip rring rtip rring normal receive mode monitor mode dsx cross connect point r monitor gain =22/26/32db monitor gain=0db ttip tring rtip rring normal transmit mode monitor mode dsx cross connect point r monitor gain monitor gain =22/26/32db 16 industrial temperature ranges single channel e1 short haul line interface unit 3.4 jitter attenuator there is one jitter attenuator in the IDT82V2051E. the jitter attenuator can be deployed in the transmit path or the receive path, and can also be disabled. this is selected by the jacf[1:0] bits ( jacf, 04h ). in hardware control mode, jitter attenuator position, bandwidth and the depth of fifo can be selected by ja[1:0] pins. refer to 5 hardware control pin summary for details. 3.4.1 jitter attenuation function description the jitter attenuator is composed of a fifo and a dpll, as shown in figure-8 . the fifo is used as a pool to buffer the jittered input data, then the data is clocked out of the fifo by a de-jittered clock. the depth of the fifo can be 32 bits, 64 bits or 128 bits, as selected by the jadp[1:0] bits ( jacf, 04h ). in hardware control mode, the depth of fifo can be selected by ja[1:0] pins. refer to 5 hardware control pin summary for details. consequently, the constant delay of the jitter attenuator will be 16 bits, 32 bits or 64 bits. deeper fifo can tolerate larger jitter, but at the cost of increasing data latency time. figure-8 jitter attenuator the corner frequency of the dpll can be 0.9 hz or 6.8 hz, as selected by the jabw bit ( jacf, 04h ). the lower the corner frequency is, the longer time is needed to achieve synchronization. when the incoming data moves faster than the outgoing data, the fifo will overflow. this overflow is captured by the jaov_is bit ( ints1, 1ah ). if the incoming data moves slower than the outgoing data, the fifo will underflow. this underflow is captured by the jaud_is bit ( ints1, 1ah ). for some applications that are sensitive to data corruption, the ja limit mode can be enabled by setting ja_limit bit ( jacf, 04h ) to ?1?. in the ja limit mode, the speed of the outgoing data will be adjusted automatically when the fifo is close to its full or emptiness. the criteria of starting speed adjust- ment are shown in table-6 . the ja limit mode can reduce the possibility of fifo overflow and underflow, but the quality of jitter attenuation is deteri- orated. 3.4.2 jitter attenuator performance the performance of the jitter attenuator in the IDT82V2051E meets the itu-t i.431, g.703, g.736-739, g.823, etsi 300011, etsi tbr12/13, specifications. details of the jitter attenuator performance is shown in table-46 jitter tolerance and table-47 jitter attenuator characteristics . fifo 32/64/128 dpll jittered data de-jittered data jittered clock de-jittered clock mclk w r rclk rd/rdp rdn table-6 criteria of starting speed adjustment fifo depth criteria for adjusting data outgoing speed 32 bits 2 bits close to its full or emptiness 64 bits 3 bits close to its full or emptiness 128 bits 4 bits close to its full or emptiness 17 industrial temperature ranges single channel e1 short haul line interface unit 3.5 los and ais detection 3.5.1 los detection the loss of signal detector monitors the amplitude of the incoming sig- nal level and pulse density of the received signal on rtip and rring. los declare (los=1) a los is detected when the incoming signal has ?no transitions?, i.e., when the signal level is less than q db below nominal for n consecutive pulse intervals. here n is defined by lac bit ( maint0, 0dh ). los will be declared by pulling los pin to high (los=1) and los interrupt will be gen- erated if it is not masked. los clear (los=0) the los is cleared when the incoming signal has ?transitions?, i.e., when the signal level is greater than p db below nominal and has an aver- age pulse density of at least 12.5% for m consecutive pulse intervals, start- ing with the receipt of a pulse. here m is defined by lac bit ( maint0, 0dh ). los status is cleared by pulling los pin to low. figure-9 los declare and clear los detect level threshold the amplitude threshold q is fixed on 800 mvpp, while p=q+200 mvpp (200 mvpp is the los level detect hysteresis). criteria for declare and clear of a los detect the detection supports the g.775 and etsi 300233/i.431. the criteria can be selected by lac bit ( maint0, 0dh ) table-7 summarizes los declare and clear criteria all ones output during los on the system side, the rdp/rdn will reflect the input pulse ?transition? at the rtip/rring side and output recovered clock (but the quality of the output clock can not be guaranteed when the input level is lower than the maximum receive sensitivity) when aise bit ( maint0, 0dh ) is 0; or output all ones as ais when aise bit ( maint0, 0dh ) is 1. in this case, rclk out- put is replaced by mclk. on the line side, the ttip/tring will output all ones as ais when atao bit ( maint0, 0dh ) is 1. the all ones pattern uses mclk as the reference clock. los indicator is always active for all kinds of loopback modes. signal level p density=ok los=1 los=0 table-7 los declare and clear criteria control bit los declare threshold los clear threshold lac 0=g.775 level < 800 mvpp n=32 bits level > 1 vpp m=32 bits 12.5% mark density <16 consecutive zeroes 1=i.431/etsi level < 800 mvpp n=2048 bits level > 1 vpp m=32 bits 12.5% mark density <16 consecutive zeroes |
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