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preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 604 .415.6000 pm4318 octliu octal e1/t1/j1 line interface device datasheet proprietary and confidential preliminary issue 3: april 2001
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use i contents 1 features...................................................................................................................... .. 1 1.1 each receiver section: .............................................................................. 2 1.2 each transmitter section:....................................................................... 2 2 applications................................................................................................................. 4 3 references .................................................................................................................. 5 4 application examples............................................................................................... 7 5 block diagram............................................................................................................. 9 6 description ................................................................................................................ 11 7 pin diagram................................................................................................................. 12 8 pin description......................................................................................................... 13 9 functional description ........................................................................................ 35 9.1 octants........................................................................................................... 35 9.2 receive interface ...................................................................................... 35 1.3 clock and data recovery (cdrc).......................................................... 36 1.4 receive jitter attenuator (rjat) ......................................................... 38 1.5 t1 inband loopback code detector (ibcd) ....................................... 38 1.6 t1 pulse density violation detector (pdvd) ................................... 39 1.7 performance monitor counters (pmon).......................................... 39 1.8 pseudo random binary sequence generation and detection (prbs) ............................................................................................................... 39 1.9 t1 inband loopback code generator (xibc)..................................... 39 1.10 pulse density enforcer (xpde)............................................................. 39 1.11 transmit jitter attenuator (tjat) ....................................................... 40 1.12 line transmitter......................................................................................... 44 1.13 timing options (tops) ................................................................................ 44
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use ii 1.14 scaleable bandwidth interconnect (sbi) interface ................... 44 1.14.1 interfacing octlius to a high density framer.................. 45 1.15 sbi extracter and piso............................................................................. 46 1.16 sbi inserter and sipo ................................................................................ 46 1.17 sbi to clk/data converter ...................................................................... 46 1.18 serial prom interface.............................................................................. 46 1.19 jtag test access port .............................................................................. 48 1.20 microprocessor interface ................................................................... 48 2 normal mode register description ................................................................ 49 2.1 normal mode register memory map................................................... 50 3 test features description................................................................................ 169 3.1 jtag test port............................................................................................ 169 4 operation.................................................................................................................. 172 4.1 configuring the octliu from reset................................................. 172 4.2 servicing interrupts.............................................................................. 172 4.3 using the performance monitoring features ............................ 173 4.4 using the transmit line pulse generator ..................................... 173 4.5 using the line receiver ......................................................................... 194 4.6 using the prbs generator and detector ...................................... 201 4.7 loopback modes ....................................................................................... 201 4.7.1 line loopback................................................................................ 201 4.7.2 diagnostic digital loopback .................................................. 202 4.8 jtag support .............................................................................................. 202 4.8.1 tap controller ............................................................................ 204 5 functional timing .................................................................................................. 210 5.1 sbi bus interface timing ........................................................................ 210
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use iii 5.2 line code violation insertion ............................................................. 211 5.3 alarm interface........................................................................................ 213 6 absolute maximum ratings ................................................................................ 214 7 d.c. characteristics ............................................................................................ 215 8 microprocessor interface timing characteristics ............................. 217 9 octliu timing characteristics......................................................................... 221 9.1 rstb timing (figure 33) ............................................................................ 221 9.2 xclk input timing (figure 34)................................................................. 221 9.3 transmit serial interface (figure 35) .............................................. 222 9.4 receive serial interface (figure 36)................................................. 223 9.5 sbi interface (figure 37 to figure 39)............................................... 224 9.6 serial prom (spi) interface (figure 40) ............................................ 227 9.7 alarm interface (figure 41).................................................................. 228 9.8 ingress clk/data interface (figure 42)............................................ 228 9.9 egress clk/data interface (figure 43) ............................................. 229 9.10 jtag port interface (figure 44) .......................................................... 230 10 ordering and thermal information .............................................................. 232 11 mechanical information ..................................................................................... 233
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use iv list of figures figure 1 ? t1/e1 framer/transceiver application................................................. 7 figure 2 ? high density t1/e1 framer/transceiver application ...................... 7 figure 3 ? high density leased line circuit emulation application.............. 7 figure 4 ? metro optical access equipment .......................................................... 8 figure 5 ? octliu block diagram ? lius enabled ................................................... 9 figure 6 ? octliu block diagram ? sbi to clk/data converter, lius disabled .......................................................................................................... 10 figure 7 ? pin diagram.................................................................................................... 12 figure 8 ? external analogue interface circuits ............................................ 35 figure 9 ? t1 jitter tolerance ................................................................................... 37 figure 10 ? compliance with itu-t specification g.823 for e1 input jitter . 38 figure 11 ? tjat jitter tolerance ............................................................................... 41 figure 12 ? tjat minimum jitter tolerance vs. xclk accuracy........................ 42 figure 13 ? tjat jitter transfer.................................................................................. 43 figure 14 ? sbi to framer line side interface ........................................................ 45 figure 15 ? serial prom cascade interface ........................................................... 46 figure 16 ? serial prom command format ............................................................... 47 figure 17 ? transmit timing options........................................................................... 75 figure 18 ? line loopback............................................................................................. 202 figure 19 ? diagnostic digital loopback................................................................ 202 figure 20 ? boundary scan architecture ............................................................. 203 figure 21 ? tap controller finite state machine ............................................... 205 figure 22 ? input observation cell (in_cell) ........................................................ 208 figure 23 ? output cell (out_cell) or enable cell (enable).......................... 208 figure 24 ? bidirectional cell (io_cell) .................................................................. 209
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use v figure 25 ? layout of output enable and bidirectional cells ..................... 209 figure 26 ? sbi bus functional timing ...................................................................... 210 figure 27 ? b8zs line code violation insertion ................................................... 211 figure 28 ? hdb3 line code violation insertion................................................... 212 figure 29 ? ami line code violation insertion ...................................................... 213 figure 30 ? los alarm serial output........................................................................ 213 figure 31 ? microprocessor interface read timing......................................... 218 figure 32 ? microprocessor interface write timing ....................................... 220 figure 33 ? rstb timing................................................................................................... 221 figure 34 ? xclk input timing ....................................................................................... 221 figure 35 ? transmit serial interface timing diagram..................................... 222 figure 36 ? receive serial interface timing diagram ....................................... 223 figure 37 ? sbi frame pulse timing............................................................................ 224 figure 38 ? sbi add bus timing ..................................................................................... 225 figure 39 ? sbi drop bus timing .................................................................................. 226 figure 40 ? spi interface timing ................................................................................. 227 figure 41 ? alarm interface timing........................................................................... 228 figure 42 ? ingress clk/data interface timing diagram................................... 229 figure 43 ? egress clk/data interface timing diagram.................................... 229 figure 44 ? jtag port interface timing ................................................................... 231
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use vi list of tables table 1 ? external component descriptions .................................................... 36 table 2 ? serial prom commands ? code bits ..................................................... 47 table 3 ? serial prom special commands ............................................................ 47 table 4 ? normal mode register memory map ................................................... 50 table 5 ? clock synthesis mode .............................................................................. 65 table 6 ? tjat fifo output clock source ............................................................ 74 table 7 ? tjat pll source............................................................................................ 74 table 8 ? insbi tributary characteristics .......................................................... 89 table 9 ? exsbi tributary characteristics....................................................... 105 table 10 ? exsbi clock generation options........................................................ 106 table 11 ? transmit in-band code length ............................................................ 114 table 12 ? loopback code configurations......................................................... 126 table 13 ? loss of signal thresholds .................................................................. 131 table 14 ? transmit output amplitude .................................................................. 148 table 15 ? alos detection/clearance thresholds.......................................... 154 table 16 ? equalization feedback frequencies................................................ 161 table 17 ? valid period................................................................................................. 162 table 18 ? boundary scan register....................................................................... 170 table 19 ? default settings....................................................................................... 172 table 20 ? t1.102 transmit waveform values for t1 long haul (lbo 0 db)175 table 21 ? t1.102 transmit waveform values for t1 long haul (lbo 7.5 db) .......................................................................................................................... 176 table 22 ? t1.102 transmit waveform values for t1 long haul (lbo 15 db) .......................................................................................................................... 177 table 23 ? t1.102 transmit waveform values for t1 long haul (lbo 22.5 db) .......................................................................................................................... 178
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use vii table 24 ? t1.102 transmit waveform values for t1 short haul (0 ? 110 ft.) .......................................................................................................................... 179 table 25 ? t1.102 transmit waveform values for t1 short haul (110 ? 220 ft.) ............................................................................................................. 180 table 26 ? t1.102 transmit waveform values for t1 short haul (220 ? 330 ft.) ............................................................................................................. 181 table 27 ? t1.102 transmit waveform values for t1 short haul (330 ? 440 ft.)............................................................................................................. 182 table 28 ? t1.102 transmit waveform values for t1 short haul (440 ? 550 ft.) ............................................................................................................. 183 table 29 ? t1.102 transmit waveform values for t1 short haul (550 ? 660 ft.) ............................................................................................................. 184 table 30 ? tr62411 transmit waveform values for t1 long haul (lbo 0 db) .......................................................................................................................... 185 table 31 ? tr62411 transmit waveform values for t1 short haul (0 ? 110 ft.)186 table 32 ? tr62411 transmit waveform values for t1 short haul (110 ? 220 ft.) ............................................................................................................. 187 table 33 ? tr62411 transmit waveform values for t1 short haul (220 ? 330 ft.) ............................................................................................................. 188 table 34 ? tr62411 transmit waveform values for t1 short haul (330 ? 440 ft.) ............................................................................................................. 189 table 35 ? tr62411 transmit waveform values for t1 short haul (440 ? 550 ft.) ............................................................................................................. 190 table 36 ? tr62411 transmit waveform values for t1 short haul (550 ? 660 ft.) ............................................................................................................. 191 table 37 ? transmit waveform values for e1 120 ohm.................................... 192 table 38 ? transmit waveform values for e1 75 ohm...................................... 193 table 39 ? rlps register programming................................................................ 194 table 40 ? rlps equalizer ram table (t1 mode) .................................................. 195 table 41 ? rlps equalizer ram table (e1 mode) .................................................. 198 table 42 ? rlps equalizer ram table (monitor mode) ..................................... 201 table 43 ? absolute maximum ratings ................................................................... 214
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use viii table 44 ? d.c. characteristics ............................................................................... 215 table 45 ? microprocessor interface read access ...................................... 217 table 46 ? microprocessor interface write access..................................... 219 table 47 ? rtsb timing................................................................................................... 221 table 48 ? xclk input timing ....................................................................................... 221 table 49 ? transmit serial interface .................................................................... 222 table 50 ? receive serial interface....................................................................... 223 table 51 ? clocks and sbi frame pulse ................................................................. 224 table 52 ? sbi add bus ................................................................................................... 225 table 53 ? sbi drop bus ................................................................................................ 225 table 54 ? spi interface............................................................................................... 227 table 55 ? alarm interface ........................................................................................ 228 table 56 ? ingress clk/data interface .................................................................. 228 table 57 ? engress clk/data interface................................................................. 229 table 58 ? jtag port interface................................................................................. 230 table 59 ? ordering information ............................................................................ 232 table 60 ? octliu theta jc........................................................................................... 232 table 61 ? octliu junction temperature ............................................................. 232 table 62 ? octliu theta ja vs. airflow ................................................................... 232
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 1 1 features ? monolithic device which integrates eight t1/j1 or e1 short haul and long haul line interface circuits. ? software switchable between t1/j1 and e1 operation on a per-device basis. ? meets or exceeds t1/j1 and e1 shorthaul and longhaul network access specifications including ansi t1.102, t1.403, t1.408, at&t tr 62411, itu-t g.703, g.704 as well as etsi 300-011, ctr-4, ctr- 12 and ctr-13. ? provides encoding and decoding of b8zs, hdb3 and ami line codes. ? provides receive equalization, clock recovery and line performance monitoring. ? provides transmit and receive jitter attenuation. ? provides digitally programmable long haul and short haul line build out. ? provides a selectable, per channel independent de-jittered t1 or e1 recovered clock for system timing and redundancy. ? provides prbs generators and detectors on each tributary for error testing at ds1 and e1 rates as recommended in itu-t o.151. ? provides either serial clock/data or parallel scaleable bandwidth interconnect (sbi) interfaces on the system side. ? can be configured to act as a converter between the sbi interfaces and serial clock/data. in this mode, the lius are unused. ? provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring. ? provides a hardware-only (no microprocessor) mode in which configuration data is read from an spi- compatible serial prom. the prom interface can be cascaded such that multiple octliu devices can be configured simultaneously from a single prom. ? uses line rate system clock. ? provides an ieee 1149.1 (jtag) compliant test access port (tap) and controller for boundary scan test. ? implemented in a low power 3.3 v tolerant 1.8/3.3 v cmos technology. ? available in a high density 288-pin tape-sbga (23 mm by 23 mm) package. ? provides a ?40c to +85c industrial temperature operating range.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 2 1.1 each receiver section: ? supports t1 signal reception for distances with up to 36 db of cable attenuation at nominal conditions using pic 22 gauge cable emulation. ? supports e1 signal reception for distances with up to 36 db of cable attenuation at nominal conditions using pic 22 gauge cable emulation. ? supports g.772 compliant non-intrusive protected monitoring points. ? recovers clock and data using a digital phase locked loop for high jitter tolerance. ? tolerates more than 0.3 ui peak-to-peak; high frequency jitter as required by at&t tr 62411 and bellcore tr-tsy-000170. ? outputs either dual rail recovered line pulses, a single rail ds-1/e1 signal or parallel data in sbi bus format. ? performs b8zs or ami decoding when processing a bipolar ds-1 signal and hdb3 or ami decoding when processing a bipolar e1 signal. ? detects line code violations (lcvs), b8zs/hdb3 line code signatures, and 4 (e1+hdb3), 8 (t1+b8zs) or 16 (ami) successive zeros. ? accumulates up to 8191 line code violations (lcvs), for performance monitoring purposes, over accumulation intervals defined by the period between software write accesses to the lcv register. ? detects loss of signal (los), which is defined as 10, 15, 31, 63, or 175 successive zeros. ? detects programmable inband loopback activate and deactivate code sequences received in the ds- 1 data stream when they are present for 5.1 seconds. optionally, enters loopback mode automatically on detection of an inband loopback code. ? detects violations of the ansi t1.403 12.5% pulse density rule over a moving 192-bit window. ? a pseudo-random sequence user selectable from 2 11 ?1, 2 15 ?1 or 2 20 ?1, may be detected in the t1/e1 stream in either the receive or transmit directions. the detector counts pattern errors using a 24-bit saturating prbs error counter. 1.2 each transmitter section: ? supports transfer of transmitted single rail pcm and signaling data from 1.544 mbit/s and 2.048 mbit/s backplane buses. ? generates dsx-1 shorthaul and ds-1 longhaul pulses with programmable pulse shape compatible with at&t, ansi and itu requirements. ? generates e1 pulses compliant to g.703 recommendations.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 3 ? provides a digitally programmable pulse shape extending up to 5 transmitted bit periods for custom long haul pulse shaping applications. ? provides line outputs that are current limited and may be tristated for protection or in redundant applications. ? provides a digital phase locked loop for generation of a low jitter transmit clock complying with all jitter attenuation, jitter transfer and residual jitter specifications of at&t tr 62411 and etsi tbr 12 and tbr 13. ? provides a fifo buffer for jitter attenuation and rate conversion in the transmit path. ? allows bipolar violation (bpv) transparent operation for error restoring regenerator applications. ? allows bipolar violation (bpv) insertion for diagnostic testing purposes. ? supports all ones transmission for alarm indication signal (ais) generation. ? accepts either dual rail or single rail ds-1/e1 signals or parallel data from the sbi interface. ? performs b8zs or ami encoding when processing a single rail or sbi-sourced ds-1 signal and hdb3 or ami encoding when processing a single rail or sbi-sourced e1 signal. ? a pseudo-random sequence user selectable from 2 11 ?1, 2 15 ?1 or 2 20 ?1, may be inserted into or detected from the t1 or e1 stream in either the receive or transmit directions. ? detects violations of the ansi t1.403 12.5% pulse density rule over a moving 192-bit window and optionally stuffs ones to maintain minimum ones density. ? supports transmission of a programmable unframed inband loopback code sequence.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 4 2 applications ? metro optical access equipment ? edge router linecards ? multiservice atm switch linecards ? 3g base station controllers (bsc) ? 3g base transceiver stations (bts) ? digital private branch exchanges (pbx) ? digital access cross-connect systems (dacs) and electronic dsx cross-connect systems (edsx) ? t1/e1 repeaters ? test equipment ? sbi to clk/data converter in multi-service access equipment.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 5 3 references 1. ansi ? t1.102-1993 ? american national standard for telecommunications ? digital hierarchy ? electrical interfaces. 2. ansi ? t1.107-1995 ? american national standard for telecommunications ? digital hierarchy ? formats specification. 3. ansi ? t1.403-1999 ? american national standard for telecommunications ? carrier to customer installation ? ds-1 metallic interface specification. 4. ansi ? t1.408-1990 ? american national standard for telecommunications ? integrated services digital network (isdn) primary rate ? customer installation metallic interfaces layer 1 specification. 5. at&t ? tr 62411 ? accunet t1.5 ? service description and interface specification, december 1990. 6. at&t ? tr 62411 ? accunet t1.5 ? service description and interface specification, addendum 1, march 1991. 7. at&t ? tr 62411 ? accunet t1.5 ? service description and interface specification, addendum 2, october 1992. 8. tr-tsy-000170 ? bellcore ? digital cross-connect system requirements and objectives, issue 1, november 1985. 9. tr-n1wt-000233 ? bell communications research ? wideband and broadband digital cross-connect systems generic criteria, issue 3, november 1993. 10. tr-nwt-000303 ? bell communications research ? integrated digital loop carrier generic requirements, objectives, and interface, issue 2, december, 1992. 11. tr-tsy-000499 ? bell communications research ? transport systems generic requirements (tsgr): common requirement, issue 5, december, 1993. 12. etsi ? ets 300 011 ? isdn primary rate user-network interface specification and test principles, 1992. 13. etsi ? ets 300 233 ? access digital section for isdn primary rates. 14. etsi ? ctr 4 ? integrated services digital network (isdn); attachment requirements for terminal equipment to connect to an isdn using isdn primary rate access, november 1995. 15. etsi ? ctr 12 ? business telecommunications (bt); open network provision (onp) technical requirements; 2 048 kbit/s digital unstructured leased lines (d2048u) attachment requirements for terminal equipment interface, december 1993. 16. etsi ? ctr 13 ? business telecommunications (btc); 2 048 kbit/s digital structured leased lines (d2048s); attachment requirements for terminal equipment interface, january 1996.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 6 17. fcc rules ? part 68.308 ? signal power limitations. 18. itu-t ? recommendation g.703 ? physical/electrical characteristics of hierarchical digital interface, geneva, 1998. 19. itu-t ? recommendation g.704 ? synchronous frame structures used at primary hierarchical levels, july 1998. 20. itu-t recommendation g.772 ? protected monitoring points provided on digital transmission systems, 1992. 21. itu-t ? recommendation g.775 ? loss of signal (los), november 1998. 22. itu-t recommendation g.823, - the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy, 1993. 23. itu-t ? recommendation i.431 ? primary rate user-network interface ? layer 1 specification, 1993. 24. itu-t recommendation o.151, - error performance measuring equipment for digital systems at the primary bit rate and above, 1992. 25. ttc standard jt-g703 ? physical/electrical characteristics of hierarchical digital interfaces, 1995. 26. ttc standard jt-g704 ? frame structures on primary and secondary hierarchical digital interfaces, 1995. 27. ttc standard jt-i431 ? isdn primary rate user-network interface layer 1 ? specification, 1995. 28. nippon telegraph and telephone corporation ? technical reference for high-speed digital leased circuit services, third edition, 1990.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 7 4 application examples figure 1 ? t1/e1 framer/transceiver application octliu pm4318 8 x t1 lines toctl pm4388 backplane octliu pm4318 backplane eoctl pm6388 octal t1 framer octal e1 framer clock and data clock and data 8 x e1 lines figure 2 ? high density t1/e1 framer/transceiver application t1/j1/e1 framer sbi octliu pm4318 octliu pm4318 4xoctliu octliu pm4318 octliu pm4318 h-mvip or sbi te32 pm4332 32 t1/j1 or e1 lines figure 3 ? high density leased line circuit emulation application octliu pm4318 octliu pm4318 4xoctliu octliu pm4318 octliu pm4318 atm backbone utopia l2 aal1gator 32 pm73122 sbi aal1 sar 32 t1/j1 or e1 lines
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 8 figure 4 ? metro optical access equipment octliu pm4318 octliu pm4318 octliu pm4318 octliu pm4318 octliu pm4318 octliu pm4318 octliu pm4318 octliu pm4318 octliu pm4318 octliu pm4318 sbi 11xoctliu or 8xoctliu octliu pm4318 t1/e1 vt/tu mapper telecom bus temap-84 pm5366 84 t1/j1 or 63 e1 lines cross connect
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 9 5 block diagram figure 5 ? octliu block diagram ? lius enabled refclk ac1fp dc1fp xlpg transmit liu txtip1[8:1] txtip2[8:1] txring1[8:1] txring2[8:1] tjat digital jitter attenuator lcode ami / b8zs / hdb3 line encoder xpde pulse density enforcer xibc inband loop- back code generator prbs pattern generator / detector rlps receive liu cdrc clk/data recovery pdvd pulse density viol. detector ibcd inband loop - back code detector rxtip[8:1] rxring[8:1] rjat digital jitter attenuator liu octant x 8 csd clock synthesis / distribution tops timing options pmon performance monitor xclk jtag up interface h/w only auto-config insbi-8 sbi insert exsbi-8 sbi extract tdn[8:1] tdp[8:1] tclk[8:1] adata[7:0] adp apl av5 ddata[7:0] ddp dpl dv5 c1fpout rdp[8:1] rdn/rlcv[8:1] rclk[8:1] vclk (line loopback) (diagnostic digital loopback) rsync fblow rstb sbi_en dactive los serial output len1[2:0] len2[2:0] len3[2:0] len4[2:0] len5[2:0] len6[2:0] len7[2:0] len8[2:0] hw_only srcode srcen srcclk srcdo srcasc sren srclk srdi srdo intb rdb wrb csb ale a[10:0] d[7:0] trstb tdo tdi tms tck los los_l1 sbi2clk
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 10 figure 6 ? octliu block diagram ? sbi to clk/data converter, lius disabled refclk ac1fp dc1fp iclk_out idata[8:1] csd clock synthesis / distribution xclk jtag up interface h/w only auto-config insbi-8 sbi insert exsbi-8 sbi extract adata[7:0] adp apl av5 ddata[7:0] ddp dpl dv5 c1fpout vclk rstb sbi_en dactive hw _only srcode srcen srcclk srcdo srcasc sren srclk srdi srdo intb rdb wrb csb ale a[10:0] d[7:0] trstb tdo tdi tms tck sbi2clk ifp_out iclk_in ifp_in elst elastic store x8 edata[8:1] eclk efp
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 11 6 description the pm4318 octal e1/t1/j1 line interface device (octliu) is a monolithic integrated circuit suitable for use in long haul and short haul t1, j1 and e1 systems with a minimum of external circuitry. the octliu is configurable via microprocessor control or spi-compatible serial prom interface, allowing feature selection without changes to external wiring. analogue circuitry is provided to allow direct reception of long haul e1 and t1 compatible signals with up to 36 db cable loss (at 1.024 mhz) in e1 mode or up to 36 db cable loss (at 772 khz) in t1 mode using a minimum of external components. typically, only line protection, a transformer and a line termination resistor are required. the octliu recovers clock and data from the line. decoding of ami, hdb3 and b8zs line codes is supported. in t1 mode, the octliu also detects the presence of in-band loop back codes. the octliu supports detection of loss of signal, pulse density violation and line code violation alarm conditions. line code violations are accumulated for performance monitoring purposes. internal analogue circuitry allows direct transmission of long haul and short haul t1 and e1 compatible signals using a minimum of external components. typically, only line protection, a transformer and an optional line termination resistor are required. digitally programmable pulse shaping allows transmission of dsx-1 compatible signals up to 655 feet from the cross-connect, e1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, e1 long haul pulses into 120 ohm twisted pair as well as long haul ds-1 pulses into 100 ohm twisted pair with integrated support for lbo filtering as required by the fcc rules. in addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. each channel of the octliu can generate a low jitter transmit clock from the input clock source and also provide jitter attenuation in the receive path. a low jitter recovered t1 clock can be routed outside the octliu for network timing applications. serial pcm interfaces to each t1/e1 liu allow 1.544 mbit/s or 2.048 mbit/s backplane receive/backplane transmit system interfaces to be directly supported. data may be transferred either as dual rail line pulses or single rail ds-1/e1 data. alternatively, the octliu supports an 8-bit parallel sbi interface for interfacing to high-density framers. the octliu may be configured to operate in a mode in which the lius are disabled and the device acts as a converter between the sbi interface and serial clock and data. up to 8 serial data streams (sharing a common clock and frame pulse) may be mapped on to the sbi bus in this mode. the octliu may be configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. alternatively, the device may be operated in a ?hardware only? mode in which no microprocessor is required. in this case, the octliu reads configuration information from an spi-compatible serial prom interface on power up. multiple octlius can be configured from a single serial prom via a cascade interface on the octliu.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 12 7 pin diagram the octliu is packaged in a 288-pin tape-sbga package having a body size of 23mm by 23mm. figure 7 ? pin diagram 22212019181716151413121110987654321 a ale/ len4[2] vss d[1]/ len6[2] d[2]/ len7[0] d[4]/ len7[2] vss vdd1v8 tavs2[1] txring2 [1] txring1 [1] txtip1[1] txtip2[1] txtip2 [8] txtip1 [8] txring1 [8] txring2 [8] rstb los srcclk srclk vdd3v3 tdi a b vdd3v3 vdd3v3 csb/ len5[2] d[0]/ len6[1] d[3]/ len7[1] d[6]/ len8[1] sbi_en qavs[4] res[5] tavd3[1] tavs3[8] tavd2[8] qavd[4] vdd1v8 vdd3v3 res[1] res[6] srcdo srdo srcasc tdo hw_only b c a[8]/ len3[2] a[9]/ len4[0] a[10]/ len4[1] rdb/ len5[1] vdd3v3 vdd3v3 vss d[7]/ len8[2] cavd tavd2[1] tavs3[1] tavd3[8] tavs2[8] vss vss los_l1 srcode srcen sren vss tck sbi2clk c d a[4]/ len2[1] a[5]/ len2[2] a[6]/ len3[0] vss wrb/ len5[0] intb/ len6[0] vss d[5]/ len8[0] cavs tavs1[1] tavd1[1] tavd1[8] tavs1[8] xclk rsync/ iclk_out vdd3v3 srdi vss nc tms vdd3v3 ravs1[8] d e a[0]/ len1[0] a[1]/ len1[1] a[2]/ len1[2] a[7]/ len3[1] trstb vss ravd2[8] ravd2[7] e f ravs1[1] ravd2[1] qavd[1] a[3]/ len2[0] qavs[3] res[4] ravs2[7] txring2 [7] f g ravd1[1] rxtip[1] ravs2[1] vdd3v3 ravs2[8] rxtip[8] ravs1[7] txring1 [7] g h txring2 [2] ravd2[2] ravs2[2] rxring[1] rxring [8] ravd1[8] ravd1[7] txtip1 [7] h j txring1 [2] rxtip[2] ravs1[2] rxring [2] rxring [7] rxtip[7] tavs2[7] txtip2 [7] j k txtip1[2] ravd1[2] tavs2[2] tavs1[2] tavs1[7] tavd2[7] tavd3[7] txtip2 [6] k l txtip2 [2] tavd2[2] tavd3[2] tavd1[2] bottom view tavd1[7] tavs3[7] tavs3[6] txtip1[6] l m txtip2 [3] tavs3[2] tavs3[3] tavd1[3] tavd1[6] tavd3[6] tavd2[6] txring1 [6] m n txtip1 [3] tavd3[3] tavd2[3] tavs1[3] tavs1[6] tavs2[6] ravd1[6] txring2 [6] n p txring1 [3] tavs2[3] ravd1[3] rxring [3] rxring [6] ravs1[6] ravd2[6] rxtip[6] p r txring2 [3] rxtip[3] ravd2[3] rxtip[4] rxtip[5] rxring [5] ravd1[5] ravs2[6] r t ravs1[3] ravs2[3] ravd1[4] ravs2[4] qavd[3] ravs2[5] ravd2[5] ravs1[5] t u rxring [4] ravs1[4] ravd2[4] tclk[1]/ idata[1] tclk[7]/ idata[7] tdn[8]/ ifp_in tdp[8]/ adata[7] vss u v res[1] qavs[1] vss tdp[2]/ adata[1] tdn[6]/ av5 tclk[6]/ idata[6] tdn[7]/ iclk_in tclk[8]/ idata[8] v w tdp[1]/ adata[0] tdn[1]/ refclk tclk[2]/ idata[2] vdd3v3 tdn[4]/ adp vdd3v3 vdd3v3 rdn[3]/ rlcv[3]/ c1fpout vss tavs1[4] tavd1[4] tavd1[5] tavs1[5] vdd1v8 rdp[5]/ ddata[4] rclk[6]/ edata[6] rclk[7]/ edata[7] rdp[8]/ ddata[7] nc vdd3v3 tclk[5]/ idata[5] tdp[7]/ adata[6] w y tdn[2]/ ac1fp tdp[3]/ adata[2] vdd3v3 tdp[4]/ adata[3] vss rdp[2]/ ddata[1] rclk[3]/ edata[3] vdd3v3 rdn[4]/ rlcv[4]/ ddp tavs2[4] tavd3[4] tavs3[5] tavd2[5] res[3] rdn[5]/ rlcv[5]/ dpl vdd3v3 vss rdp[7]/ ddata[6] rdn[8]/ rlcv[8]/ dactive vss tdp[5]/ adata[4] tdp[6]/ adata[5] y aa tclk[3]/ idata[3] tdn[3]/ dc1fp tclk[4]/ idata[4] rclk[1]/ edata[1] rclk[2]/ edata[2] vss vss rclk[4]/ edata[4] vdd1v8 qavd[2] tavd2[4] tavs3[4] tavd3[5] tavs2[5] qavs[2] vss vss rdp[6]/ ddata[5] rdn[7]/ rlcv[7]/ eclk vdd3v3 vss tdn[5]/ apl aa ab vss vss vss rdp[1]/ ddata[0] rdn[1]/ rlcv[1]/ ifp_out rdn[2]/ rlcv[2]/ efp rdp[3]/ ddata[2] rdp[4]/ ddata[3] txring2 [4] txring1 [4] txtip1[4] txtip2 [4] txtip2 [5] txtip1[5] txring1 [5] txring2 [5] rclk[5]/ edata[5] rdn[6]/ rlcv[6]/ dv5 vdd3v3 vss rclk[8]/ edata[8] vdd3v3 ab 22212019181716151413121110987654321
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 13 8 pin description by convention, where a bus of eight pins indexed [8:1] is present, the index indicates to which octant the pin applies. with tclk[8:1], for example, tclk[1] applies to octant #1, tclk[2] applies to octant #2, etc. pin name type pin no. function t1 and e1 system side serial clock and data interface tclk[1]/idata[1] tclk[2]/idata[2] tclk[3]/idata[3] tclk[4]/idata[4] tclk[5]/idata[5] tclk[6]/idata[6] tclk[7]/idata[7] tclk[8]/idata[8] input u19 w20 aa22 aa20 w2 v3 u4 v1 the transmit clock inputs (tclk[8:1]) should be 1.544 mhz for ds1 or 2.048 mhz for e1 data streams and are used to sample the corresponding tdp[8:1] and tdn[8:1] signals. tclk[8:1] share the same pins as the idata[8:1] inputs. tclk[8:1] are selected when sbi2clk is tied low. tdp[1]/adata[0] tdp[2]/adata[1] tdp[3]/adata[2] tdp[4]/adata[3] tdp[5]/adata[4] tdp[6]/adata[5] tdp[7]/adata[6] tdp[8]/adata[7] input w22 v19 y21 y19 y2 y1 w1 u2 transmit positive data (tdp[8:1]). when in single-rail mode, these inputs are the nrz data signals to be transmitted. these inputs can be configured to be active high or active low. when in dual-rail mode, these inputs are the nrz positive data signals to be transmitted. tdp[8:1] can be sampled on either the rising or falling edges of the corresponding tclk[8:1]. tdp[8:1] share the same pins as the adata[7:0] inputs. tdp[8:1] are selected when sbi_en and sbi2clk are both tied low. tdn[1]/refclk tdn[2]/ac1fp tdn[3]/dc1fp tdn[4]/adp tdn[5]/apl tdn[6]/av5 tdn[7]/iclk_in tdn[8]/ifp_in input w21 y22 aa21 w18 aa1 v4 v2 u3 transmit negative data (tdn[8:1]). when in dual-rail mode, these inputs are the nrz negative data signals to be transmitted. these inputs can be sampled on either the rising or falling edges of the corresponding tclk[8:1]. these input pins are ignored if the device is configured for single-rail (unipolar) transmit mode. tdn[8:1] share the same pins as the refclk, ac1fp, dc1fp, adp, apl, av5, iclk_in and ifp_in inputs. tdn[8:1] are selected when sbi_en and sbi2clk are both tied low.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 14 pin name type pin no. function rclk[1]/edata[1] rclk[2]/edata[2] rclk[3]/edata[3] rclk[4]/edata[4] rclk[5]/edata[5] rclk[6]/edata[6] rclk[7]/edata[7] rclk[8]/edata[8] output aa19 aa18 y16 aa15 ab6 w7 w6 ab2 recovered clock output (rclk[8:1]). rclk[8:1] is the clock recovered from the rxtip[8:1] and rxring[8:1] input signals. rclk[8:1] share the same pins as the edata[8:1] outputs. rclk[8:1] are selected when sbi2clk is tied low. rdp[1]/ddata[0] rdp[2]/ddata[1] rdp[3]/ddata[2] rdp[4]/ddata[3] rdp[5]/ddata[4] rdp[6]/ddata[5] rdp[7]/ddata[6] rdp[8]/ddata[7] output ab19 y17 ab16 ab15 w8 aa5 y5 w5 receive digital positive data (rdp[8:1]). when in single rail mode, rdp[8:1] output nrz sampled ds-1 or e1 data which has been decoded by ami, b8zs, or hdb3 line code rules. when in dual rail mode, rdp[8:1] output nrz sampled bipolar positive pulses. rdp[8:1] can be updated on either the falling or rising rclk[8:1] edge. rdp[8:1] share the same pins as the ddata[7:0] outputs. rdp[8:1] are selected when sbi_en and sbi2clk are both tied low. rdn/rlcv[1]/ifp_out rdn/rlcv[2]/efp rdn/rlcv[3]/c1fpout rdn/rlcv[4]/ddp rdn/rlcv[5]/dpl rdn/rlcv[6]/dv5 rdn/rlcv[7]/eclk rdn/rlcv[8]/dactive output ab18 ab17 w15 y14 y8 ab5 aa4 y4 receive digital negative data/line code violation indication (rdn/rlcv[8:1]). when in dual rail mode, rdn/rlcv[8:1] output nrz sampled bipolar negative pulses. when in single rail mode, rdn/rlcv[8:1] output a nrz pulse whenever a line code violation or excess zeros condition is detected. rdn/rlcv[8:1] can be updated on either the falling or rising rclk[8:1] edge. rdn/rlcv[8:1] share the same pins as the ifp_out, efp, c1fpout, ddp, dpl, dv5, eclk and dactive outputs. rdn/rlcv[8:1] are selected when sbi_en and sbi2clk are both tied low. sbi system side interface refclk/tdn[1] input w21 the sbi reference clock signal (refclk) provides reference timing for the sbi add and drop busses. refclk is nominally a 50% duty cycle clock of frequency 19.44 mhz 50ppm. refclk shares the same pin as the tdn[1] input. refclk is selected when sbi_en or sbi2clk is tied high.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 15 pin name type pin no. function ac1fp/tdn[2] input y22 the sbi add bus c1 octet frame pulse signal (ac1fp) provides frame synchronisation for devices connected via an sbi interface. ac1fp must be asserted for 1 refclk cycle every 500 s or multiples thereof (i.e. every 9720 n refclk cycles, where n is a positive integer). all devices connected to the sbi add bus must be synchronised to a ac1fp signal from a single source. ac1fp is sampled on the rising edge of refclk. ac1fp shares the same pin as the tdn[2] input. ac1fp is selected when sbi_en or sbi2clk is tied high. dc1fp/tdn[3] input aa21 the sbi drop bus c1 octet frame pulse signal (dc1fp) provides frame synchronisation for devices connected via an sbi interface. dc1fp must be asserted for 1 refclk cycle every 500 s or multiples thereof (i.e. every 9720 n refclk cycles, where n is a positive integer). all devices connected to the sbi drop bus must be synchronised to a dc1fp signal from a single source. dc1fp is sampled on the rising edge of refclk. dc1fp shares the same pin as the tdn[3] input. dc1fp is selected when sbi_en or sbi2clk is tied high. c1fpout/rdn/rlcv[3] output w15 the c1 octet frame pulse output signal (c1fpout) may be used to provide frame synchronisation for devices interconnected via an sbi interface. c1fpout is asserted for 1 refclk cycle every 500 s (i.e. every 9720 refclk cycles). if c1fpout is used for synchronisation, it must be connected to the a/dc1fp inputs of all the devices connected to the sbi add or drop bus. c1fpout is updated on the rising edge of refclk. c1fpout shares the same pin as the rdn/rlcv[3] output. c1fpout is selected when sbi_en or sbi2clk is tied high. adata[0]/tdp[1] adata[1]/tdp[2] adata[2]/tdp[3] adata[3]/tdp[4] adata[4]/tdp[5] adata[5]/tdp[6] adata[6]/tdp[7] adata[7]/tdp[8] input w22 v19 y21 y19 y2 y1 w1 u2 the sbi add bus data signals (adata[7:0]) contain time division multiplexed transmit data from up to 84 independently timed links. link data is transported as t1 or e1 tributaries within the sbi tdm bus structure. the octliu may be configured to extract data from up to 8 tributaries within the structure. adata[7:0] are sampled on the rising edge of refclk. adata[7:0] share the same pins as the tdp[8:1] inputs. adata[7:0] are selected when sbi_en or sbi2clk is tied high.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 16 pin name type pin no. function adp/tdn[4] input w18 the sbi add bus parity signal (adp) carries the even or odd parity for the add bus signals. the parity calculation encompasses the adata[7:0], apl and av5 signals. multiple devices can drive the sbi add bus at uniquely assigned tributary column positions. this parity signal is intended to detect accidental driver clashes in the column assignment. adp is sampled on the rising edge of refclk. adp shares the same pin as the tdn[4] input. adp is selected when sbi_en or sbi2clk is tied high. apl/tdn[5] input aa1 the sbi add bus payload signal (apl) indicates valid data within the sbi tdm bus structure. this signal is asserted during all octets making up a tributary. this signal may be asserted during the v3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed tdm bus structure. this signal may be deasserted during the octet following the v3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed tdm bus structure. apl is sampled on the rising edge of refclk. apl shares the same pin as the tdn[5] input. apl is selected when sbi_en or sbi2clk is tied high. av5/tdn[6] input v4 the sbi add bus payload indicator signal (av5) locates the position of the floating payloads for each tributary within the sbi tdm bus structure. timing differences between the port timing and the tdm bus timing are indicated by adjustments of this payload indicator relative to the fixed tdm bus structure. all movements indicated by this signal must be accompanied by appropriate adjustments in the apl signal. av5 is sampled on the rising edge of refclk. av5 shares the same pin as the tdn[6] input. av5 is selected when sbi_en or sbi2clk is tied high.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 17 pin name type pin no. function ddata[0]/rdp[1] ddata[1]/rdp[2] ddata[2]/rdp[3] ddata[3]/rdp[4] ddata[4]/rdp[5] ddata[5]/rdp[6] ddata[6]/rdp[7] ddata[7]/rdp[8] tristate output ab19 y17 ab16 ab15 w8 aa5 y5 w5 the sbi drop bus data signals (ddata[7:0]) contain time division multiplexed receive data from up to 84 independently timed links. link data is transported as t1 or e1 tributaries within the sbi tdm bus structure. the octliu may be configured to insert data into up to 8 tributaries within the structure. multiple liu devices can drive the sbi drop bus at uniquely assigned tributary column positions. ddata[7:0] are tristated when the octliu is not outputting data on a particular tributary column. ddata[7:0] are updated on the rising edge of refclk. ddata[7:0] share the same pins as the rdp[8:1] outputs. ddata[7:0] are selected when sbi_en or sbi2clk is tied high. ddp/rdn/rlcv[4] tristate output y14 the sbi drop bus parity signal (ddp) carries the even or odd parity for the drop bus signals. the parity calculation encompasses the ddata[7:0], dpl and dv5 signals. multiple liu devices can drive this signal at uniquely assigned tributary column positions. ddp is tristated when the octliu is not outputting data on a particular tributary column. this parity signal is intended to detect accidental source clashes in the column assignment. ddp is updated on the rising edge of refclk. ddp shares the same pin as the rdn/rlcv[4] output. ddp is selected when sbi_en or sbi2clk is tied high. dpl/rdn/rlcv[5] tristate output y8 the sbi drop bus payload signal (dpl) indicates valid data within the sbi tdm bus structure. this signal is asserted during all octets making up a tributary. this signal may be asserted during the v3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed tdm bus structure. this signal may be deasserted during the octet following the v3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed tdm bus structure. multiple liu devices can drive this signal at uniquely assigned tributary column positions. dpl is tristated when the octliu is not outputting data on a particular tributary column. dpl is updated on the rising edge of refclk. dpl shares the same pin as the rdn/rlcv[5] output. dpl is selected when sbi_en or sbi2clk is tied high.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 18 pin name type pin no. function dv5/rdn/rlcv[6] tristate output ab5 the sbi drop bus payload indicator signal (dv5) locates the position of the floating payloads for each tributary within the sbi tdm bus structure. timing differences between the port timing and the tdm bus timing are indicated by adjustments of this payload indicator relative to the fixed tdm bus structure. multiple liu devices can drive this signal at uniquely assigned tributary column positions. dv5 is tristated when the octliu is not outputting data on a particular tributary column. dv5 is updated on the rising edge of refclk. dv5 shares the same pin as the rdn/rlcv[6] output. dv5 is selected when sbi_en or sbi2clk is tied high. dactive/rdn/rlcv[8] output y4 the sbi drop bus active indicator signal (dactive) is asserted whenever the octliu is driving the sbi drop bus signals, ddata[7:0], ddp, dpl and dv5. dactive is updated on the rising edge of refclk. dactive shares the same pin as the rdn/rlcv[8] output. dactive is selected when sbi_en or sbi2clk is tied high. transmit line interface txtip1[1] txtip1[2] txtip1[3] txtip1[4] txtip1[5] txtip1[6] txtip1[7] txtip1[8] txtip2[1] txtip2[2] txtip2[3] txtip2[4] txtip2[5] txtip2[6] txtip2[7] txtip2[8] analogue output a12 k22 n22 ab12 ab9 l1 h1 a9 a11 l22 m22 ab11 ab10 k1 j1 a10 transmit analogue positive pulse (txtip1[8:1] and txtip2[8:1]). when the transmit analogue line interface is enabled, the txtip1[x] and txtip2[x] analogue outputs drive the transmit line pulse signal through an external matching transformer. both txtip1[x] and txtip2[x] are normally connected to the positive lead of the transformer primary. two outputs are provided for better signal integrity and must be shorted together on the board. after a reset, txtip1[x] and txtip2[x] are high impedance. the highz bit of the octant?s xlpg line driver configuration register must be programmed to logic 0 to remove the high impedance state.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 19 pin name type pin no. function txring1[1] txring1[2] txring1[3] txring1[4] txring1[5] txring1[6] txring1[7] txring1[8] txring2[1] txring2[2] txring2[3] txring2[4] txring2[5] txring2[6] txring2[7] txring2[8] analogue output a13 j22 p22 ab13 ab8 m1 g1 a8 a14 h22 r22 ab14 ab7 n1 f1 a7 transmit analogue negative pulse (txring1[8:1] and txring2[8:1]). when the transmit analogue line interface is enabled, the txring1[x] and txring2[x] analogue outputs drive the transmit line pulse signal through an external matching transformer. both txring1[x] and txring2[x] are normally connected to the negative lead of the transformer primary. two outputs are provided for better signal integrity and must be shorted together on the board. after a reset, txring1[x] and txring2[x] are high impedance. the highz bit of the octant?s xlpg line driver configuration register must be programmed to logic 0 to remove the high impedance state. receive line interface rxtip[1] rxtip[2] rxtip[3] rxtip[4] rxtip[5] rxtip[6] rxtip[7] rxtip[8] analogue input g21 j21 r21 r19 r4 p1 j3 g3 receive analogue positive pulse (rxtip[8:1]). when the analogue receive line interface is enabled, rxtip[x] samples the received line pulse signal from an external isolation transformer. rxtip[x] is normally connected directly to the positive lead of the receive transformer secondary. rxring[1] rxring[2] rxring[3] rxring[4] rxring[5] rxring[6] rxring[7] rxring[8] analogue input h19 j19 p19 u22 r3 p4 j4 h4 receive analogue negative pulse (rxring[8:1]). when the analogue receive line interface is enabled, rxring[x] samples the received line pulse signal from an external isolation transformer. rxring[x] is normally connected directly to the negative lead of the receive transformer secondary.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 20 pin name type pin no. function sbi to clk/data converter interface sbi_en sbi2clk input b16 c1 the sbi interface enable signals (sbi_en, sbi2clk) select between the sbi and serial clock/data system side interfaces and allow selection of an operating mode in which the lius are disabled and the octliu functions as a converter between the sbi interface and serial clk/data. the signals select the device operating mode as follows: sbi_en sbi2clk mode 0 0 lius enabled, clk/data selected on system side. 1 0 lius enabled, sbi interface selected on system side. 0 1 lius disabled, converter mode. 1 1 unused idata[1]/tclk[1] idata[2]/tclk[2] idata[3]/tclk[3] idata[4]/tclk[4] idata[5]/tclk[5] idata[6]/tclk[6] idata[7]/tclk[7] idata[8]/tclk[8] input u19 w20 aa22 aa20 w2 v3 u4 v1 the ingress data inputs (idata[8:1]) carry eight serial 1.544 mbps or 2.048 mbps data streams to be mapped on to the sbi interface when the device is operating as a sbi to clk/data converter. the eight serial data streams are sampled on the rising edge of iclk_in. idata[8:1] share the same pins as the tclk[8:1] inputs. idata[8:1] are selected when sbi2clk is tied high. iclk_in/tdn[7] input v2 the ingress input clock (iclk_in) should be 1.544 mhz for ds1 or 2.048 mhz for e1 data streams and is used to sample the idata[8:1] and ifp_in signals. iclk_in shares the same pin as the tdn[7] input. iclk_in is selected when sbi_en or sbi2clk is tied high. ifp_in/tdn[8] input u3 the ingress frame pulse input (ifp_in) should be set high during the framing bits of ds1 streams or during the first bit of the framing octet of e1 data streams. ifp_in is sampled on the rising edge of iclk_in. ifp_in shares the same pin as the tdn[8] input. ifp_in is selected when sbi_en or sbi2clk is tied high. iclk_out/rsync output d8 the ingress output clock (iclk_out) is a nominal 1.544 mhz (for ds1) or 2.048 mhz (for e1) clock and may be used as a source for the iclk_in clock if desired. iclk_out shares the same pin as the rsync output. iclk_out is selected when sbi2clk is tied high.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 21 pin name type pin no. function ifp_out/rdn/rlcv[1] output ab18 the ingress frame pulse output (ifp_out) is pulsed high every 193 iclk_out cycles for ds1 and every 256 iclk_out cycles for e1. it may be used as a framing reference and as a source for ifp_in if desired. ifp_out is updated on the falling edge of iclk_out. ifp_out shares the same pin as the rdn/rlcv[1] output. ifp_out is selected when sbi_en or sbi2clk is tied high. edata[1]/rclk[1] edata[2]/rclk[2] edata[3]/rclk[3] edata[4]/rclk[4] edata[5]/rclk[5] edata[6]/rclk[6] edata[7]/rclk[7] edata[8]/rclk[8] output aa19 aa18 y16 aa15 ab6 w7 w6 ab2 the egress data outputs (edata[8:1]) carry eight serial 1.544 mbps or 2.048 mbps data streams de-mapped from the sbi interface when the device is operating as a sbi to clk/data converter. the eight serial data streams are updated on the falling edge of eclk. edata[8:1] share the same pins as the rclk[8:1] outputs. edata[8:1] are selected when sbi2clk is tied high. eclk/rdn/rlcv[7] output aa4 the egress clock output (eclk) is a 1.544 mhz (for ds1) or 2.048 mhz (for e1) clock, recovered from one of the sbi tributaries. the sbi tributary used to recover timing is selectable. eclk shares the same pin as the rdn/rlcv[7] output. eclk is selected when sbi_en or sbi2clk is tied high. efp/rdn/rlcv[2] output ab17 the egress frame pulse output (efp) is set high during the framing bits of ds1 streams or during the first bit of the framing octet of e1 data streams. efp is updated on the falling edge of eclk. efp shares the same pin as the rdn/rlcv[2] output. efp is selected when sbi_en or sbi2clk is tied high.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 22 pin name type pin no. function timing options control xclk input d9 crystal clock input (xclk). this signal provides a stable, global timing reference for the octliu internal circuitry via an internal clock synthesizer. xclk is a nominally jitter free clock at 1.544 mhz in t1 mode and 2.048 mhz in e1 mode. in t1 mode, a 2.048 mhz clock may be used as a reference. when used in this way, however, the intrinsic jitter specifications in at&t tr62411 may not be met. rsync/iclk_out output d8 recovered clock synchronization signal (rsync). this output signal is the recovered, jitter attenuated, receiver line rate clock (1.544 or 2.048 mhz) of one of the eight t1 or e1 channels or, optionally, the recovered, jitter attenuated clock synchronously divided by 193 (t1 mode) or 256 (e1 mode) to create a 8 khz timing reference signal. the default is to source rsync from octant #1. when the octliu is in a loss of signal state, rsync is derived from the xclk input or, optionally, is held high. rsync shares the same pin as the iclk_out output. rsync is selected when sbi2clk is tied low. alarm interface los output a5 loss of signal alarm (los). this signal outputs the los status of the 8 liu octants in a serial format which repeats every 8 xclk cycles. the presence of the los status for liu #1 on this output is indicated by the los_l1 output pulsing high. on the following xclk cycle, the los status for liu #2 is output, then liu #3, and so on. this signal is intended for use in hardware only mode. when the microprocessor interface is enabled, the status of the los alarm can also be determined by reading the losv bit in the cdrc interrupt status register. los is updated on the falling edge of xclk. los_l1 output c7 loss of signal liu #1 indicator (los_l1). this signal is pulsed high for one xclk cycle every 8 xclk cycles and indicates that the los status for liu #1 is being output on los. los_l1 is updated on the falling edge of xclk.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 23 pin name type pin no. function misc. control signals rstb input a6 active low reset (rstb). this signal provides an asynchronous octliu reset. rstb is a schmidt triggered input with an internal pull up resistor. res[1] input b7 this pin must be tied low for normal operation. res[2] res[3] res[4] res[5] analogue i/o v22 y9 f3 b14 these pins must be connected to an analogue ground for normal operation. res[6] input b6 this pin must be tied to ground for normal operation.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 24 pin name type pin no. function microprocessor interface a[0]/len1[0] a[1]/len1[1] a[2]/len1[2] a[3]/len2[0] a[4]/len2[1] a[5]/len2[2] a[6]/len3[0] a[7]/len3[1] a[8]/len3[2] a[9]/len4[0] a[10]/len4[1] input e22 e21 e20 f19 d22 d21 d20 e19 c22 c21 c20 address bus (a[10:0]). this bus selects specific registers during octliu register accesses. signal a[10] selects between normal mode and test mode register access. a[10] has an internal pull down resistor. a[10:0] share the same pins as some of the lenx[2:0] inputs. a[10:0] are selected when hw_only is tied low. ale/len4[2] input a22 address latch enable (ale). this signal is active high and latches the address bus contents, a[10:0], when low. when ale is high, the internal address latches are transparent. ale allows the octliu to interface to a multiplexed address/data bus. the ale input has an internal pull up resistor. ale shares the same pin as the len4[2] input. ale is selected when hw_only is tied low. wrb/len5[0] input d18 active low write strobe (wrb). this signal is low during a octliu register write access. the d[7:0] bus contents are clocked into the addressed register on the rising wrb edge while csb is low. wrb shares the same pin as the len5[0] input. wrb is selected when hw_only is tied low. rdb/len5[1] input c19 active low read enable (rdb). this signal is low during octliu register read accesses. the octliu drives the d[7:0] bus with the contents of the addressed register while rdb and csb are low. rdb shares the same pin as the len5[1] input. rdb is selected when hw_only is tied low. csb/len5[2] input b20 active low chip select (csb). csb must be low to enable octliu register accesses. csb must go high at least once after power up to clear internal test modes. if csb is not used, it should be tied to an inverted version of rstb, in which case, rdb and wrb determine register accesses. csb shares the same pin as the len5[2] input. csb is selected when hw_only is tied low.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 25 pin name type pin no. function intb/len6[0] open- drain output d17 active low open-drain interrupt (intb). this signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. note that intb will remain low until all active, unmasked interrupt sources are acknowledged at their source at which time, intb will tristate. intb shares the same pin as the len6[0] input. intb is selected when hw_only is tied low. d[0]/len6[1] d[1]/len6[2] d[2]/len7[0] d[3]/len7[1] d[4]/len7[2] d[5]/len8[0] d[6]/len8[1] d[7]/len8[2] i/o b19 a20 a19 b18 a18 d15 b17 c15 bidirectional data bus (d[7:0]). this bus provides octliu register read and write accesses. d[7:0] share the same pins as some of the lenx[2:0] inputs. d[7:0] are selected when hw_only is tied low. hardware-only control interface hw_only input b1 the hardware only mode enable signal (hw_only) selects between the microprocessor-controlled and hardware-only modes of operation. when hw_only is tied low, the microprocessor interface is enabled. when hw_only is tied high, the hardware- only control interface is enabled and the microprocessor interface is unused. srcasc input b3 serial prom cascade control (srcasc). when srcasc is tied low, the octliu acts as the serial prom master controller and the sren, srclk, srdi and srdo pins should be connected to the serial prom. when srcasc is tied high, the octliu acts as a serial prom cascade slave and the sren, srclk and srdo pins should be connected to the srcen, srcclk and srcdo pins of another octliu device upstream in the cascade. sren i/o c4 serial prom enable (sren). when operating as a serial prom master (srcasc tied low), the sren pin functions as an output and generates an active low chip select signal for the serial prom. when operating as a serial prom slave (srcasc tied high), the sren pin functions as an input and indicates the validity of cascade data on the srdo input. when configured as an output, sren is updated on the falling edge of srclk. when configured as an input, sren is sampled on the rising edge of srclk.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 26 pin name type pin no. function srclk i/o a3 serial prom clock (srclk). when operating as a serial prom master (srcasc tied low), the srclk pin functions as an output and generates a clock for the serial prom. when operating as a serial prom slave (srcasc tied high), the srclk pin functions as an input and is connected to the srcclk output of an octliu device upstream in the serial prom cascade. srdi output d6 serial prom data in (srdi). when operating as a serial prom master (srcasc tied low), the srdi output is used to send read commands to the serial prom. when operating as a serial prom slave (srcasc tied high), srdi is unused. srdi is updated on the falling edge of srclk. srdo input b4 serial prom data out (srdo). when operating as a serial prom master (srcasc tied low), the srdo input receives data from the serial prom. when operating as a serial prom slave (srcasc tied high), the srdo input receives data from the srcdo output of an octliu device upstream in the serial prom cascade. srdo is sampled on the rising edge of srclk. srcen output c5 serial prom cascade enable (srcen). the srcen output is asserted when valid data is being output on srcdo. srcen is updated on the falling edge of srcclk. srcclk output a4 serial prom cascade clock (srcclk). when operating as a serial prom master (srcasc tied low), the srcclk output is a copy of the srclk output. when operating as a serial prom slave (srcasc tied high), the srcclk output is a copy of the srclk input. srcdo output b5 serial prom cascade data out (srcdo). the srcdo output is a buffered, retimed copy of the srdo input. srcdo is updated on the falling edge of srcclk. srcode input c6 serial prom code (srcode). the srcode input provides a means for controlling the execution of configuration instructions stored in the serial prom. instructions can be coded to execute only if srcode is logic 0, only if srcode is logic 1 or unconditionally. the srcode input thus allows the selection of two different configuration sequences within a single prom load. this could be used, for example, to store two configurations for t1 and e1 operation within one serial prom.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 27 pin name type pin no. function len1[0]/a[0] len1[1]/a[1] len1[2]/a[2] len2[0]/a[3] len2[1]/a[4] len2[2]/a[5] len3[0]/a[6] len3[1]/a[7] len3[2]/a[8] len4[0]/a[9] len4[1]/a[10] len4[2]/ale len5[0]/wrb len5[1]/rdb len5[2]/csb len6[0]/intb len6[1]/d[0] len6[2]/d[1] len7[0]/d[2] len7[1]/d[3] len7[2]/d[4] len8[0]/d[5] len8[1]/d[6] len8[2]/d[7] input e22 e21 e20 f19 d22 d21 d20 e19 c22 c21 c20 a22 d18 c19 b20 d17 b19 a20 a19 b18 a18 d15 b17 c15 line length build-out select (lenn[2:0]). these signals can be preset to select one of eight different pulse templates to be used by the line transmitters, depending on line length, etc. lenn[2:0] selects the pulse template for the line transmitter of octant #n. lenn[2:0] share the same pins as the microprocessor interface signals. lenn[2:0] are selected when hw_only is tied high. the lenn[2:0] inputs are latched following reset of the octliu and any changes to their value will have no effect on the operation of octliu until a subsequent reset.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 28 pin name type pin no. function jtag interface tdo tristate output b2 test data output (tdo). this signal carries test data out of the octliu via the ieee 1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tri-state output that is tri- stated except when scanning of data is in progress. tdi input a1 test data input (tdi). this signal carries test data into the octliu via the ieee 1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an internal pull up resistor. tck input c2 test clock (tck). this signal provides timing for test operations that can be carried out using the ieee 1149.1 test access port. tms input d3 test mode select (tms). this signal controls the test operations that can be carried out using the ieee 1149.1 test access port. tms is sampled on the rising edge of tck. tms has an internal pull up resistor. trstb input e4 active low test reset (trstb). this signal provides an asynchronous octliu test access port reset via the ieee 1149.1 test access port. trstb is a schmidt triggered input with an internal pull up resistor. trstb must be asserted during the power up sequence. note that if not used, trstb should be connected to the rstb input. analogue power and ground pins tavd1[1] tavd1[2] tavd1[3] tavd1[4] tavd1[5] tavd1[6] tavd1[7] tavd1[8] analogue power d12 l19 m19 w12 w11 m4 l4 d11 transmit analogue power (tavd1[8:1]). tavd1[8:1] provide power for the transmit liu analogue circuitry. tavd1[8:1] should be connected to analogue +3.3 v.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 29 pin name type pin no. function tavd2[1] tavd2[2] tavd2[3] tavd2[4] tavd2[5] tavd2[6] tavd2[7] tavd2[8] tavd3[1] tavd3[2] tavd3[3] tavd3[4] tavd3[5] tavd3[6] tavd3[7] tavd3[8] analogue power c13 l21 n20 aa12 y10 m2 k3 b11 b13 l20 n21 y12 aa10 m3 k2 c11 transmit analogue power (tavd2[8:1], tavd3[8:1]). tavd2[8:1] and tavd3[8:1] supply power for the transmit liu current dacs. they should be connected to analogue +3.3 v. cavd analogue power c14 clock synthesis unit analogue power (cavd). cavd supplies power for the transmit clock synthesis unit. cavd should be connected to analogue +3.3 v. tavs1[1] tavs1[2] tavs1[3] tavs1[4] tavs1[5] tavs1[6] tavs1[7] tavs1[8] analogue ground d13 k19 n19 w13 w10 n4 k4 d10 transmit analogue ground (tavs1[8:1]). tavs1[8:1] provide ground for the transmit liu analogue circuitry. tavs1[8:1] should be connected to analogue gnd.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 30 pin name type pin no. function tavs2[1] tavs2[2] tavs2[3] tavs2[4] tavs2[5] tavs2[6] tavs2[7] tavs2[8] tavs3[1] tavs3[2] tavs3[3] tavs3[4] tavs3[5] tavs3[6] tavs3[7] tavs3[8] analogue ground a15 k20 p21 y13 aa9 n3 j2 c10 c12 m21 m20 aa11 y11 l2 l3 b12 transmit analogue ground (tavs2[8:1], tavs3[8:1]). tavs2[8:1] and tavs3[8:1] supply ground for the transmit liu current dacs. they should be connected to analogue gnd. cavs analogue ground d14 clock synthesis unit analogue ground (cavs). cavs supplies ground for the transmit clock synthesis unit. cavs should be connected to analogue gnd. ravd1[1] ravd1[2] ravd1[3] ravd1[4] ravd1[5] ravd1[6] ravd1[7] ravd1[8] analogue power g22 k21 p20 t20 r2 n2 h2 h3 receive analogue power (ravd1[8:1]). ravd1[8:1] supplies power for the receive liu input equalizer. ravd1[8:1] should be connected to analogue +3.3 v. ravd2[1] ravd2[2] ravd2[3] ravd2[4] ravd2[5] ravd2[6] ravd2[7] ravd2[8] analogue power f21 h21 r20 u20 t2 p2 e1 e2 receive analogue power (ravd2[8:1]). ravd2[8:1] supplies power for the receive liu peak detect and slicer. ravd2[8:1] should be connected to analogue +3.3 v.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 31 pin name type pin no. function ravs1[1] ravs1[2] ravs1[3] ravs1[4] ravs1[5] ravs1[6] ravs1[7] ravs1[8] analogue ground f22 j20 t22 u21 t1 p3 g2 d1 receive analogue ground (ravs1[8:1]). ravs1[8:1] supplies ground for the receive liu input equalizer. ravs1[8:1] should be connected to analogue gnd. ravs2[1] ravs2[2] ravs2[3] ravs2[4] ravs2[5] ravs2[6] ravs2[7] ravs2[8] analogue ground g20 h20 t21 t19 t3 r1 f2 g4 receive analogue ground (ravs2[8:1]). ravs2[8:1] supplies ground for the receive liu peak detect and slicer. ravs2[8:1] should be connected to analogue gnd. qavd[1] qavd[2] qavd[3] qavd[4] analogue power f20 aa13 t4 b10 quiet analogue power (qavd[4:1]). qavd[4:1] supplies power for the core analogue circuitry. qavd[4:1] should be connected to analogue +3.3 v. qavs[1] qavs[2] qavs[3] qavs[4] analogue ground v21 aa8 f4 b15 quiet analogue ground (qavs[4:1]). qavs[4:1] supplies ground for the core analogue circuitry. qavs[4:1] should be connected to analogue gnd. digital power and ground pins vdd1v8[1] vdd1v8[2] vdd1v8[3] vdd1v8[4] power a16 b9 w9 aa14 core power (vdd1v8[4:1]). the vdd1v8[4:1] pins should be connected to a well decoupled +1.8v dc power supply.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 32 pin name type pin no. function vdd3v3[1] vdd3v3[2] vdd3v3[3] vdd3v3[4] vdd3v3[5] vdd3v3[6] vdd3v3[7] vdd3v3[8] vdd3v3[9] vdd3v3[10] vdd3v3[11] vdd3v3[12] vdd3v3[13] vdd3v3[14] vdd3v3[15] vdd3v3[16] vdd3v3[17] vdd3v3[18] vdd3v3[19] power a2 b8 b21 b22 c17 c18 d2 d7 g19 w3 w16 w17 w19 y7 y15 y20 aa3 ab1 ab4 i/o power (vdd3v3[19:1]). the vdd3v3[19:1] pins should be connected to a well decoupled +3.3v dc power supply.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 33 pin name type pin no. function vss[1] vss[2] vss[3] vss[4] vss[5] vss[6] vss[7] vss[8] vss[9] vss[10] vss[11] vss[12] vss[13] vss[14] vss[15] vss[16] vss[17] vss[18] vss[19] vss[20] vss[21] vss[22] vss[23] vss[24] vss[25] ground a17 a21 c3 c8 c9 c16 d5 d16 d19 e3 u1 v20 w14 y3 y6 y18 aa2 aa6 aa7 aa16 aa17 ab3 ab20 ab21 ab22 ground (vss [25:1]). the vss[25:1] pins should be connected to ground. nc1 nc2 open d4 w4 these pins must be left unconnected. notes on pin descriptions: 1. all octliu inputs and bi-directionals present minimum capacitive loading. 2. all octliu inputs and bi-directionals, when configured as inputs, tolerate ttl logic levels. 3. all octliu outputs and bi-directionals have at least 8 ma drive capability, except the los, los_l1, tdo and serial prom interface outputs, which have at least 6 ma drive capability. the transmit analogue outputs (txtip and txring) have built-in short circuit current limiting. 4. inputs rstb, ale, tms, tdi and trstb have internal pull-up resistors. 5. inputs a[10], res[1], and res[6] have internal pull-down resistors. 6. all unused inputs should be connected to ground.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 34 7. the 3.3 volt power pins (i.e., tavd1, tavd2, tavd3, cavd, ravd1, ravd2, qavd, and vdd3v3) will be collectively referred to as v ddall33 in this document. 8. power to v ddall33 should be applied before power to the vdd1v8 pins is applied. similarly, power to the vdd1v8 pins should be removed before power to v ddall33 is removed. 9. the v ddall33 voltage level should not be allowed to drop below the vdd1v8 voltage level except when vdd1v8 is not powered.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 35 9 functional description 9.1 octants the octliu?s eight e1/t1 line interface units operate independently and can be configured to operate uniquely. the octants do share a common xclk clock input and internal clock synthesizer; hence only a single csu configuration register is present. additionally, all octants share a common e1/t1b mode register bit to select between t1 and e1 operation. 9.2 receive interface the analogue receive interface is configurable to operate in both e1 and t1 short-haul and long- haul applications. short-haul t1 is defined as transmission over less than 655 ft of cable. short- haul e1 is defined as transmission on any cable that attenuates the signal by less than 6 db. for long-haul signals, unequalized long- or short-haul bipolar alternate mark inversion (ami) signals are received as the differential voltage between the rxtip and rxring inputs. the octliu typically accepts unequalized signals that are attenuated for both t1 and e1 signals and are non-linearly distorted by typical cables. for short-haul, the slicing threshold is set to a fraction of the input signal?s peak amplitude, and adapts to changes in this amplitude. the slicing threshold is programmable, but is typically 67% and 50% for dsx-1 and e1 applications, respectively. abnormally low input signals are detected when the input level is below a programmable threshold, which is typically 140 mv for e1 and 105 mv for t1. figure 8 ? external analogue interface circuits chassis gnd z2 z1 f1 f2 f3 chassis gnd z4 z3 f4 rtip rring ttip tring z5 phantom feed circuit or vsupply as required z6 outb outa center tap inb ina 1:n t2 outb outa center tap inb ina 1:n gnd vdd vdd d1 r1 r2 gnd gnd txtip txring rxtip rxring atb one of eight t1 or e1 lius t1 l1 l2
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 36 figure 8 gives the recommended external protection circuitry for designs required to meet the major surge immunity and electrical safety standards including fcc part 68, ul1950, and bellcore tr-nwt-001089. this circuit has not been tested as of december, 1999. please refer to an upcoming pmc application note for more details. for systems not requiring phantom feed or inter-building line protection, the bi-directional transient surge suppressors (z1-z4), their associated ground connection and the center tap of the transformer can be removed from the circuit. see table 1 for the descriptions of components for figure 8. note that the crowbar devices (z1 ? z4) are not required if the transformer?s isolation rating is not exceeded. table 1 ? external component descriptions component description part # source r1 36.0 ? 1%, 0.25w resistor r2 27.0 ? 1%, 0.25w resistor d1 surge protector diode array srda3.3-4 semtech t1 & t2 1:1.58 ct transformers (e1 75 ? cable) 1:2 ct transformers (otherwise) pulse z1 ? z4 bi-directional transient surge suppressors p1800sc teccor z5 ? z6 bi-directional transient surge suppressors p0720sc teccor l1 & l2 dual choke, 27h pe-68624 pulse f1 ? f4 telecom/time lag fuses f1250t teccor when operating in e1 mode with 75 ? cable, a 1:1.58 turns ratio transformer is specified in the above table. it is in fact also possible to use a 1:2 turns ratio transformer, in which case the value of r1 must be changed to 22.0 ? 1% and the value of r2 must be changed to 18.0 ? 1%. 9.3 clock and data recovery (cdrc) the clock and data recovery function is provided by the clock and data recovery (cdrc) block. the cdrc provides clock and pcm data recovery, b8zs and hdb3 decoding, line code violation detection, and loss of signal detection. it recovers the clock from the incoming rz data pulses using a digital phase-locked-loop and reconstructs the nrz data. loss of signal is indicated after a programmable threshold of consecutive bit periods of the absence of pulses on both the positive and negative line pulse inputs and is cleared after the occurrence of a single line pulse. an alternate loss of signal indication is provided which is cleared upon meeting an 1-in-8 pulse density criteria for t1 and a 1-in-4 pulse density criteria for e1. if enabled, a microprocessor interrupt is generated when a loss of signal is detected and when the signal returns. a line code violation is defined as a bipolar violation (bpv) for ami-coded signals, is
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 37 defined as a bpv that is not part of a zero substitution code for b8zs-coded signals, and is defined as a bipolar violation of the same polarity as the last bipolar violation for hdb3-coded signals. in t1 mode, the input jitter tolerance of the octliu complies with the bellcore document ta-tsy-000170 and with the at&t specification tr62411, as shown in figure 9. the tolerance is measured with a qrss sequence (2 20 -1 with 14 zero restriction). the cdrc block provides two algorithms for clock recovery that result in differing jitter tolerance characteristics. the first algorithm (when the algsel register bit is logic 0) provides good low frequency jitter tolerance, but the high frequency tolerance is close to the tr62411 limit. the second algorithm (when algsel is logic 1) provides much better high frequency jitter tolerance at the expense of the low frequency tolerance; the low frequency tolerance of the second algorithm is approximately 80% that of the first algorithm. figure 9 ? t1 jitter tolerance 100 10 1.0 1.0 10 sine wave jitter amplitude p. to p. (ui) log scale sine w ave jitter frequency (khz) log scale 0.31 0.30 0.2 0.3 at&t spec. bellcore spec. acceptable range 0.1 0.1 for e1 applications, the input jitter tolerance complies with the itu-t recommendation g.823 ?the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy.? figure 10 illustrates this specification and the performance of the phase-locked loop when the algsel register bit is logic 0.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 38 figure 10 ? compliance with itu-t specification g.823 for e1 input jitter 10 10 10 34 5 sinewave jitter frequency, hz - log scale 10 1 0.1 1.5 1.8 2.4 in spec region rec. g823 jitter tolerance specification 0.2 sinewave jitter amplitude p. to p. (ui) log scale dpll tolerance with hdb3 encoded 2 -1 prbs 15 dpll tolerance with ami encoded 2 -1 prbs 15 9.4 receive jitter attenuator (rjat) the receive jitter attenuator (rjat) digital pll attenuates the jitter present on the rxtip/rxring inputs. the attenuation is only performed when the rjatbyp register bit is a logic 0. the jitter characteristics of the receive jitter attenuator (rjat) are the same as the transmit jitter attenuator (tjat). 9.5 t1 inband loopback code detector (ibcd) the t1 inband loopback code detection function is provided by the ibcd block. this block detects the presence of either of two programmable inband loopback activate and deactivate code sequences in the receive data stream. each inband loopback code sequence is defined as the repetition of the programmed code in the pcm stream for at least 5.1 seconds. the code sequence detection and timing is compatible with the specifications defined in t1.403-1993, ta-tsy-000312, and tr-tsy-000303. loopback activate and deactivate code indication is provided through internal register bits. an interrupt is generated to indicate when either code status has changed.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 39 9.6 t1 pulse density violation detector (pdvd) the pulse density violation detection function is provided by the pdvd block. the block detects pulse density violations of the requirement that there be n ones in each and every time window of 8(n+1) data bits (where n can equal 1 through 23). the pdvd also detects periods of 16 consecutive zeros in the incoming data. pulse density violation detection is provided through an internal register bit. an interrupt is generated to signal a 16 consecutive zero event, and/or a change of state on the pulse density violation indication. 9.7 performance monitor counters (pmon) the performance monitor block accumulates line code violation events with a saturating counter over consecutive intervals as defined by the period between writes to trigger registers (typically 1 second). when the trigger is applied, the pmon transfers the counter value into holding registers and resets the counter to begin accumulating events for the interval. the counter is reset in such a manner that error events occurring during the reset are not missed. if the holding registers are not read between successive triggers, an overrun register bit is asserted. triggering a counter transfer within an octant is performed by writing to any counter register location within the octant or by writing to the ?line interface interrupt source #1 / pmon update? register. 9.8 pseudo random binary sequence generation and detection (prbs) the pseudo random binary sequence generator/detector (prbs) block is a software selectable prbs generator and checker for 2 11 -1, 2 15 -1 or 2 20 -1 prbs polynomials for use in the t1 and e1 links. prbs patterns may be generated and detected in either the transmit or receive directions. the prbs block can perform an auto synchronization to the expected prbs pattern and accumulates the total number of bit errors in two 24-bit counters. the error count accumulates over the interval defined by successive writes to the line interface interrupt source #1 / pmon update register. when an accumulation is forced, the holding register is updated, and the counter reset to begin accumulating for the next interval. the counter is reset in such a way that no events are missed. the data is then available in the error count registers until the next accumulation. 9.9 t1 inband loopback code generator (xibc) the t1 inband loopback code generator (xibc) block generates a stream of inband loopback codes (ibc) to be inserted into a t1 data stream. the ibc stream consists of continuous repetitions of a specific code. the contents of the code and its length are programmable from 3 to 8 bits. 9.10 pulse density enforcer (xpde) the pulse density enforcer function is provided by the xpde block. pulse density enforcement is enabled by a register bit within the xpde.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 40 this block monitors the digital output of the transmitter and detects when the stream is about to violate the ansi t1.403 12.5% pulse density rule over a moving 192-bit window. if a density violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure the resultant output no longer violates the pulse density requirement. when the xpde is disabled from inserting logic 1s, the digital stream from the transmitter is passed through unaltered. 9.11 transmit jitter attenuator (tjat) the transmit jitter attenuation function is provided by a digital phase lock loop and 80-bit deep fifo. the tjat receives jittery, dual-rail data in nrz format on two separate inputs, which allows bipolar violations to pass through the block uncorrected. the incoming data streams are stored in a fifo timed to the transmit clock. the respective input data emerges from the fifo timed to the jitter attenuated clock. the jitter attenuator generates the jitter-free 1.544 mhz or 2.048 mhz transmit clock output by adjusting the transmit clock?s phase in 1/96 ui increments to minimize the phase difference between the generated transmit clock and input data clock to tjat. jitter fluctuations in the phase of the input data clock are attenuated by the phase-locked loop within tjat so that the frequency of transmit clock is equal to the average frequency of the input data clock. for t1 applications, to best fit the jitter attenuation transfer function recommended by tr 62411, phase fluctuations with a jitter frequency above 5.7 hz are attenuated by 6 db per octave of jitter frequency. wandering phase fluctuations with frequencies below 5.7 hz are tracked by the generated transmit clock. in e1 applications, the corner frequency is 7.6 hz. to provide a smooth flow of data out of tjat, the transmit clock is used to read data out of the fifo. if the fifo read pointer (timed to the transmit clock) comes within one bit of the write pointer (timed to the input data clock), tjat will track the jitter of the input clock. this permits the phase jitter to pass through unattenuated, inhibiting the loss of data. jitter characteristics the tjat block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. it can accommodate up to 61 uipp of input jitter at jitter frequencies above 5.7 hz (7.6 hz for e1). for jitter frequencies below 5.7 hz (7.6 hz for e1), more correctly called wander, the tolerance increases 20 db per decade. in most applications the tjat block will limit jitter tolerance at lower jitter frequencies only. for high frequency jitter, above 10 khz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. for low frequency wander, below 10 hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. the tjat block meets the stringent low frequency jitter tolerance requirements of at&t tr 62411 and thus allows compliance with this standard and the other less stringent jitter tolerance standards cited in the references. tjat exhibits negligible jitter gain for jitter frequencies below 5.7 hz (7.6 hz for e1), and attenuates jitter at frequencies above 5.7 hz (7.6 hz for e1) by 20 db per decade. in most applications, the tjat block will determine jitter attenuation for higher jitter frequencies only. wander, below 10 hz for example, will essentially be passed unattenuated through tjat. jitter, above 10 hz for example, will be attenuated as specified, however, outgoing jitter may be
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 41 dominated by the generated residual jitter in cases where incoming jitter is insignificant. this generated residual jitter is directly related to the use of a 1/96 ui phase adjustment quantum. tjat meets the jitter attenuation requirements of at&t tr 62411. the block allows the implied jitter attenuation requirements for a te or nt1 given in ansi standard t1.408, and the implied jitter attenuation requirements for a type ii customer interface given in ansi t1.403 to be met. jitter tolerance jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. for tjat, the input jitter tolerance is 61 unit intervals peak-to-peak (uipp) with a worst case frequency offset of 354 hz. it is 80 uipp with no frequency offset. the frequency offset is the difference between the frequency of xclk and that of the input data clock. figure 11 ? tjat jitter tolerance 100 10 1.0 0.1 1 10 100 1k 10k jitter frequency, hz jitter amplitude, ui pp 0.01 100k 28 61 acceptable unacceptable jat min.toler ance 0.4 the accuracy of the xclk frequency and that of the tjat pll reference input clock used to generate the jitter-free transmit clock output have an effect on the minimum jitter tolerance. given that the tjat pll reference clock accuracy can be 200 hz and that the xclk input accuracy can be 100 ppm, the minimum jitter tolerance for various differences between the frequency of pll reference clock and xclk are shown in figure 12.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 42 figure 12 ? tjat minimum jitter tolerance vs. xclk accuracy 100 200 300 354 jat min. jitter tolerance, ui pp 70 65 60 55 0 100 32 max. frequency offset xclk accuracy hz , ppm 250 61 68 66 jitter transfer for t1 applications, the output jitter for jitter frequencies from 0 to 5.7 hz (7.6 hz for e1) is no more than 0.1 db greater than the input jitter, excluding residual jitter. jitter frequencies above 5.7 hz (7.6 hz for e1) are attenuated at a level of 6 db per octave, as shown in figure 13. the figure is valid for the case where the n1 = 2fh in the tjat jitter attenuator divider n1 control register and n2 = 2fh in the tjat divider n2 control register.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 43 figure 13 ? tjat jitter transfer 0 -10 -20 -30 -40 -50 1 10 100 1k 10k jitter frequency hz jitter gain db 5.7 62411 max 62411 min jat response 43802 max t1 in the non-attenuating mode, when the fifo is within one ui of overrunning or underrunning, the tracking range is 1.48 mhz to 1.608 mhz. the guaranteed linear operating range for the jittered input clock is 1.544 mhz 200 hz with worst case jitter (61 uipp), and maximum system clock frequency offset ( 100 ppm). the nominal range is 1.544 mhz 963 hz with no jitter or system clock frequency offset. e1 in the non-attenuating mode, when the fifo is within one ui of overrunning or underrunning, the tracking range is 2.13 mhz to 1.97 mhz. the guaranteed linear operating range for the jittered input clock is 2.048 mhz 300 hz with worst case jitter (61 uipp), and maximum system clock frequency offset ( 100 ppm). the nominal range is 2.048 mhz 1277 hz with no jitter or system clock frequency offset. jitter generation in the absence of input jitter, the output jitter shall be less than 0.025 uipp. this complies with the at&t tr 62411 requirement of less than 0.025 uipp of jitter generation.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 44 9.12 line transmitter the line transmitter generates alternate mark inversion (ami) transmit pulses suitable for use in the dsx-1 (short haul t1), short haul e1, long haul t1 and long haul e1 environments. the voltage pulses are produced by applying a current to a known termination (termination resistor plus line impedance). the use of current (instead of a voltage driver) simplifies transmit input return loss (irl), transmit short circuit protection (none needed) and transmit tri-stating. the output pulse shape is synthesized digitally with current digital-to-analogue (dac) converters, which produce 24 samples per symbol. the current dac?s produce differential bipolar outputs that directly drive the txtip1[x], txtip2[x], txring1[x] and txring2[x] pins. the current output is applied to a terminating resistor and line-coupling transformer in a differential manner, which when viewed from the line side of the transformer produce the output pulses at the required levels and ensures a small positive to negative pulse imbalance. the pulse shape is user programmable. for t1 short haul, the cable length between the octliu and the cross-connect (where the pulse template specifications are given) greatly affects the resulting pulse shapes. hence, the data applied to the converter must account for different cable lengths. for cept e1 applications the pulse template is specified at the transmitter, thus only one setting is required. for t1 long haul with a lbo of 7.5 db the previous bits effect what the transmitter must drive to compensate for inter-symbol interference; for lbo?s of 15 db or 22.5 db the previous 3 or 4 bits effect what the transmitter must send out. refer to the operation section for details on creating the synthesized pulse shape. 9.13 timing options (tops) the timing options block provides a means of selecting the source of the internal input clock to the tjat block, and the reference clock for the tjat digital pll. 9.14 scaleable bandwidth interconnect (sbi) interface the scaleable bandwidth interconnect is a synchronous, time-division multiplexed bus designed to transfer, in a pin-efficient manner, data belonging to a number of independently timed links of varying bandwidth. the bus is timed to a reference 19.44mhz clock and a 2 khz (or fraction thereof) frame pulse. all sources and sinks of data on the bus are timed to the reference clock and frame pulse. timing is communicated across the scaleable bandwidth interconnect by floating data structures. payload indicator signals in the sbi control the position of the floating data structure and therefore the timing. when sources are running faster than the sbi the floating payload structure is advanced by an octet by passing an extra octet in the v3 octet locations (h3 octet for ds3 mappings which are not used by the octliu). when the source is slower than the sbi the floating payload is retarded by leaving the octet after the v3 or h3 octet unused. both these rate adjustments are indicated by the sbi control signals.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 45 the sbi multiplexing structure is modeled on the sonet/sdh standards. the sonet/sdh virtual tributary structure is used to carry t1/j1 and e1 links. unchannelized ds3 payloads (not used by octliu) follow a byte synchronous structure modeled on the sonet/sdh format. the sbi structure uses a locked sonet/sdh structure fixing the position of the tug-3/tu-3 relative to the sts-3/stm-1 transport frame. the sbi is also of fixed frequency and alignment as determined by the reference clock (refclk) and frame indicator signal (c1fp). frequency deviations are compensated by adjusting the location of the t1/j1/e1/ds3 channels using floating tributaries as determined by the v5 indicator and payload signals (dv5, av5, dpl and apl). note that the octliu always operates as a clock slave on the sbi add bus and as a clock master on the sbi drop bus, i.e. it does not support the ajust_req and djust_req timing adjustment request signals defined in the sbi bus specification. the multiplexed links are separated into three synchronous payload envelopes (spe). each envelope may be configured independently to carry up to 28 t1/j1s, 21 e1s or a ds3. the octliu may be configured to use any eight t1/j1 tributaries or any eight e1 tributaries from any of the three spe?s. the eight tributaries need not all be selected from the same spe. a single octliu device cannot, however, use t1/j1 and e1 tributaries simultaneously. 9.14.1 interfacing octlius to a high density framer figure 14 ? sbi to framer line side interface framer octlius c1fpout refclk adata[7:0] ac1fp lrefclk lac1 19.44mhz adp av5 apl ddata[7:0] dc1fp ddp dv5 dpl lac1j1v1 ladata[7:0] ladp latpl lav5 ldc1j1v1 lddata[7:0] lddp ldtpl ldv5 ldpl ldais lapl figure 14 shows how the sbi interfaces of multiple octliu?s may be connected to the line side interface of a high density framer. with the exception of c1fpout, all signals on the octliu side are simply bussed in parallel to the multiple devices. the c1fpout port of a single octliu is used to provide a frame reference for all the devices. alternatively, the c1 frame pulse can be generated by external circuitry if desired. the framer?s interface must be configured such that vt pointer processors are bypassed, vt?s are byte synchronously mapped, and that the sts-1 spe?s are locked to the sts-3 transport envelope with a fixed pointer offset of 522.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 46 9.15 sbi extracter and piso the sbi extract block receives data from the sbi add bus and converts it to serial bit streams for transmission. the sbi extract block may be configured to enable or disable extraction of individual tributaries within the sbi add bus. it may also be configured to generate an all-1s output to the transmit liu when an alarm indication is signalled for a particular tributary via the sbi bus. 9.16 sbi inserter and sipo the sbi insert block receives serial data from the liu octants and inserts it on the sbi drop bus. the sbi insert block may be configured to enable or disable transmission of individual tributaries on to the sbi drop bus. 9.17 sbi to clk/data converter the octliu may be configured (by setting the sbi_en and sbi2clk inputs) to operate in a mode in which the lius are disabled and the device performs conversion between the sbi interface and serial clock and data (see figure 6). up to eight tributaries may be converted to serial format. the serial data streams are required to share a common clock and frame pulse. in the egress direction (from sbi add bus to egress clk/data), elastic stores are provided to align the tributary outputs to a common clock and frame alignment. 9.18 serial prom interface the serial prom interface is used to configure the octliu in the absence of a microprocessor. a single spi-compatible serial prom can be used to configure a number of octliu devices simultaneously (provided all such devices are intended to be configured identically) by connecting the devices in a cascade as shown in figure 15. figure 15 ? serial prom cascade interface wp hold cs sck si so vcc spi prom octliu - cascade master octliu - cascade slave srclk sren srdo srdi srcen srcclk srcdo srclk sren srdo srdi srcen srcdo srcclk vcc srcasc srcasc n.c. spi-compatible proms are organised as n x 8-bit words. the contents of the prom are read sequentially starting at address 0 and continuing until a specially coded stop command is encountered. each configuration command is coded in 3-bytes as follows:
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 47 figure 16 ? serial prom command format code1 code0 reg[13:8] reg[7:0] data[7:0] reg[13:0] specifies one of the octliu registers defined in table 4. data[7:0] is the value to be written to the specified register. commands are interpreted depending on the code1 and code0 bits as follows: table 2 ? serial prom commands ? code bits code1 code0 action 0 0 special command 0 1 write data[7:0] to reg[13:0] only if srcode = 0 1 0 write data[7:0] to reg[13:0] only if srcode = 1 1 1 write data[7:0] to reg[13:0] regardless of value of srcode the srcode input to octliu provides a means to execute configuration instructions conditionally. two different configuration sequences can be stored in a single prom (for t1 or e1 operation, for example) and the srcode input used to select which one will be applied. different octliu devices in a cascade can have their srcode inputs set to different values. when code1 = code0 = ?0?, the reg[13:0] and data[7:0] fields are interpreted as a special command, not as a register/data pair. the following special commands are defined: table 3 ? serial prom special commands reg[13:0] action 3ffb resume acting upon register write commands. only meaningfull if a 3ffd command (see below) has previously been received. 3ffc no-op. 3ffd ignore subsequent register write commands. this command is only acted upon by the first octliu in the cascade which receives it and which is not already ignoring register write commands. the octliu which acts upon this command does not propagate the command down the cascade, but instead substitutes the 3ffc special command.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 48 reg[13:0] action 3ffe pause for data[7:0] x 4096 xclk periods before reading next prom command. 3fff stop, i.e. configuration of octliu has finished. the ?ignore subsequent register write commands? command can be used to configure multiple octliu?s in a cascade individually (for example, to allocate different sbi tributaries to different octliu devices). it provides a means to progressively ?switch off? each device in the cascade once it has been configured. consider for example the following sequence of configuration commands: command (hex) explanation c00102 write 02 to register 01 of all devices in the cascade, regardless of srcode. : : (subsequent configuration commands are acted upon by all devices in the cascade.) 3ffd00 first device in cascade ignores all further register writes. c00103 : write 03 to register 01 of all devices in the cascade except the first, regardless of srcode. : : (subsequent configuration commands are acted upon by all devices in the cascade except the first.) 3ffd00 second device in cascade ignores all further register writes. c00104 : write 04 to register 01 of all devices in the cascade except the first two, regardless of srcode. : : (subsequent configuration commands are acted upon by all devices in the cascade except the first and second.) the pause command can be used, for example, to allow the clock synthesis circuitry within the csd block time to stablise before configuring the rest of the device. 9.19 jtag test access port the jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode and stctest instructions are supported. 9.20 microprocessor interface the microprocessor interface block provides normal and test mode registers, the interrupt logic, and the logic required to connect to the microprocessor interface. the normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the octliu.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 49 10 normal mode register description normal mode registers are used to configure and monitor the operation of the octliu. normal mode registers (as opposed to test mode registers) are selected when a[10] is low. the register memory map in table 4 below shows where the normal mode registers are accessed. the octliu contains 1 set of master configuration, sbi, and csu registers and 8 sets of t1/e1 liu registers. where only 1 set is present, the registers apply to the entire device. where 8 sets are present, each set of registers apply to a single octant of the octliu. by convention, where 8 sets of registers are present, address space 000h ? 07fh applies to octant #1, 080h ? 0ffh applies to octant #2, etc, up to 380h ? 3ffh for octant #8. on reset the octliu defaults to t1 mode. for proper operation some register configuration is expected. by default interrupts will not be enabled, and automatic alarm generation is disabled. notes on normal mode register bits: 1. writing values into unused register bits has no effect. reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the octliu to determine the programming state of the chip. 3. writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect octliu operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with functions that are unused in this application. to ensure that the octliu operates as intended, reserved register bits must only be written with their default values unless otherwise stated. similarly, writing to reserved registers should be avoided unless otherwise stated.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 50 10.1 normal mode register memory map table 4 ? normal mode register memory map addr register 000h reset / revision id / device id 080h, 100h, 180h, 200h, 280h, 300h, 380h reserved 001h global configuration / clock monitor 081h, 101h, 181h, 201h, 281h, 301h, 381h reserved 002h master interrupt source #1 082h, 102h, 182h, 202h, 282h, 302h, 382h reserved 003h master interrupt source #2 083h, 103h, 183h, 203h, 283h, 303h, 383h reserved 004h master test control #1 084h, 104h, 184h, 204h, 284h, 304h, 384h reserved 005h master test control #2 085h, 105h, 185h, 205h, 285h, 305h, 385h reserved 006h csu configuration 086h, 106h, 186h, 206h, 286h, 306h, 386h reserved 007h csu reserved 087h, 107h, 187h, 207h, 287h, 307h, 387h reserved 008h, 088h, 108h, 188h, 208h, 288h, 308h, 388h receive line interface configuration #1 009h, 089h, 109h, 189h, 209h, 289h, 309h, 389h receive line interface configuration #2 00ah, 08ah, 10ah, 18ah, 20ah, 28ah, 30ah, 38ah transmit line interface configuration 00bh, 08bh, 10bh, 18bh, 20bh, 28bh, 30bh, 38bh transmit line interface timing options / clock monitor / pulse template selection
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 51 addr register 00ch, 08ch, 10ch, 18ch, 20ch, 28ch, 30ch, 38ch line interface interrupt source #1 / pmon update 00dh, 08dh, 10dh, 18dh, 20dh, 28dh, 30dh, 38dh line interface interrupt source #2 00eh, 08eh, 10eh, 18eh, 20eh, 28eh, 30eh, 38eh line interface diagnostics 00fh, 08fh, 10fh, 18fh, 20fh, 28fh, 30fh, 38fh line interface prbs position 010h ? 03fh reserved 090h ? 0bfh reserved 110h ? 13fh reserved 190h ? 1bfh reserved 210h ? 23fh reserved 290h ? 2bfh reserved 310h insbi control 311h insbi fifo underrun interrupt status 312h insbi fifo overrun interrupt status 313h insbi page a octant to tributary mapping #1 314h insbi page a octant to tributary mapping #2 315h insbi page a octant to tributary mapping #3 316h insbi page a octant to tributary mapping #4 317h insbi page a octant to tributary mapping #5 318h insbi page a octant to tributary mapping #6 319h insbi page a octant to tributary mapping #7 31ah insbi page a octant to tributary mapping #8 31bh insbi page b octant to tributary mapping #1 31ch insbi page b octant to tributary mapping #2 31dh insbi page b octant to tributary mapping #3 31eh insbi page b octant to tributary mapping #4 31fh insbi page b octant to tributary mapping #5 320h insbi page b octant to tributary mapping #6 321h insbi page b octant to tributary mapping #7
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 52 addr register 322h insbi page b octant to tributary mapping #8 323h insbi link enable 324h insbi link enable busy 325h insbi tributary control #1 326h insbi tributary control #2 327h insbi tributary control #3 328h insbi tributary control #4 329h insbi tributary control #5 32ah insbi tributary control #6 32bh insbi tributary control #7 32ch insbi tributary control #8 32dh insbi minimum depth 32eh insbi fifo thresholds 32fh ? 330h insbi reserved 331h insbi depth check interrupt status 332h insbi master interrupt status 333h ? 33fh insbi reserved 390h exsbi control 391h exsbi fifo underrun interrupt status 392h exsbi fifo overrun interrupt status 393h exsbi parity error interrupt reason 394h exsbi depth check interrupt status 395h exsbi master interrupt status 396h exsbi minimum depth 397h exsbi fifo thresholds 398h exsbi link enable 399h exsbi link enable busy 39ah ? 39fh exsbi reserved 3a0h exsbi tributary control #1 3a1h exsbi tributary control #2
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 53 addr register 3a2h exsbi tributary control #3 3a3h exsbi tributary control #4 3a4h exsbi tributary control #5 3a5h exsbi tributary control #6 3a6h exsbi tributary control #7 3a7h exsbi tributary control #8 3a8h exsbi page a octant to tributary mapping #1 3a9h exsbi page a octant to tributary mapping #2 3aah exsbi page a octant to tributary mapping #3 3abh exsbi page a octant to tributary mapping #4 3ach exsbi page a octant to tributary mapping #5 3adh exsbi page a octant to tributary mapping #6 3aeh exsbi page a octant to tributary mapping #7 3afh exsbi page a octant to tributary mapping #8 3b0h exsbi page b octant to tributary mapping #1 3b1h exsbi page b octant to tributary mapping #2 3b2h exsbi page b octant to tributary mapping #3 3b3h exsbi page b octant to tributary mapping #4 3b4h exsbi page b octant to tributary mapping #5 3b5h exsbi page b octant to tributary mapping #6 3b6h exsbi page b octant to tributary mapping #7 3b7h exsbi page b octant to tributary mapping #8 3b8h ? 3bfh exsbi reserved 040h, 0c0h, 140h, 1c0h, 240h, 2c0h, 340h, 3c0h elst configuration 041h, 0c1h, 141h, 1c1h, 241h, 2c1h, 341h, 3c1h elst interrupt enable/status 042h, 0c2h, 142h, 1c2h, 242h, 2c2h, 342h, 3c2h t1 pdvd reserved 043h, 0c3h, 143h, 1c3h, 243h, 2c3h, 343h, 3c3h t1 pdvd interrupt enable/status
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 54 addr register 044h, 0c4h, 144h, 1c4h, 244h, 2c4h, 344h, 3c4h t1 xpde reserved 045h, 0c5h, 145h, 1c5h, 245h, 2c5h, 345h, 3c5h t1 xpde interrupt enable/status 046h, 0c6h, 146h, 1c6h, 246h, 2c6h, 346h, 3c6h t1 xibc control 047h, 0c7h, 147h, 1c7h, 247h, 2c7h, 347h, 3c7h t1 xibc loopback code 048h, 0c8h, 148h, 1c8h, 248h, 2c8h, 348h, 3c8h rjat interrupt status 049h, 0c9h, 149h, 1c9h, 249h, 2c9h, 349h, 3c9h rjat reference clock divisor (n1) control 04ah, 0cah, 14ah, 1cah, 24ah, 2cah, 34ah, 3cah rjat output clock divisor (n2) control 04bh, 0cbh, 14bh, 1cbh, 24bh, 2cbh, 34bh, 3cbh rjat configuration 04ch, 0cch, 14ch, 1cch, 24ch, 2cch, 34ch, 3cch tjat interrupt status 04dh, 0cdh, 14dh, 1cdh, 24dh, 2cdh, 34dh, 3cdh tjat reference clock divisor (n1) control 04eh, 0ceh, 14eh, 1ceh, 24eh, 2ceh, 34eh, 3ceh tjat output clock divisor (n2) control 04fh, 0cfh, 14fh, 1cfh, 24fh, 2cfh, 34fh, 3cfh tjat configuration 050h, 0d0h, 150h, 1d0h, 250h, 2d0h, 350h, 3d0h ibcd configuration 051h, 0d1h, 151h, 1d1h, 251h, 2d1h, 351h, 3d1h ibcd interrupt enable/status 052h, 0d2h, 152h, 1d2h, 252h, 2d2h, 352h, 3d2h ibcd activate code 053h, 0d3h, 153h, 1d3h, 253h, 2d3h, 353h, 3d3h ibcd deactivate code 054h, 0d4h, 154h, 1d4h, 254h, 2d4h, 354h, 3d4h cdrc configuration 055h, 0d5h, 155h, 1d5h, 255h, 2d5h, 355h, 3d5h cdrc interrupt control
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 55 addr register 056h, 0d6h, 156h, 1d6h, 256h, 2d6h, 356h, 3d6h cdrc interrupt status 057h, 0d7h, 157h, 1d7h, 257h, 2d7h, 357h, 3d7h cdrc alternate loss of signal 058h, 0d8h, 158h, 1d8h, 258h, 2d8h, 358h, 3d8h pmon interrupt enable/status 059h, 0d9h, 159h, 1d9h, 259h, 2d9h, 359h, 3d9h pmon reserved 05ah, 0dah, 15ah, 1dah, 25ah, 2dah, 35ah, 3dah pmon reserved 05bh, 0dbh, 15bh, 1dbh, 25bh, 2dbh, 35bh, 3dbh pmon reserved 05ch, 0dch, 15ch, 1dch, 25ch, 2dch, 35ch, 3dch pmon reserved 05dh, 0ddh, 15dh, 1ddh, 25dh, 2ddh, 35dh, 3ddh pmon reserved 05eh, 0deh, 15eh, 1deh, 25eh, 2deh, 35eh, 3deh pmon lcv count (lsb) 05fh, 0dfh, 15fh, 1dfh, 25fh, 2dfh, 35fh, 3dfh pmon lcv count (msb) 060h, 0e0h, 160h, 1e0h, 260h, 2e0h, 360h, 3e0h prbs generator/checker control 061h, 0e1h, 161h, 1e1h, 261h, 2e1h, 361h, 3e1h prbs checker interrupt enable/status 062h, 0e2h, 162h, 1e2h, 262h, 2e2h, 362h, 3e2h prbs pattern select 063h, 0e3h, 163h, 1e3h, 263h, 2e3h, 363h, 3e3h prbs reserved 064h, 0e4h, 164h, 1e4h, 264h, 2e4h, 364h, 3e4h prbs error count #1 065h, 0e5h, 165h, 1e5h, 265h, 2e5h, 365h, 3e5h prbs error count #2 066h, 0e6h, 166h, 1e6h, 266h, 2e6h, 366h, 3e6h prbs error count #3 067h, 0e7h, 167h, 1e7h, 267h, 2e7h, 367h, 3e7h prbs reserved
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 56 addr register 068h, 0e8h, 168h, 1e8h, 268h, 2e8h, 368h, 3e8h xlpg control/status 069h, 0e9h, 169h, 1e9h, 269h, 2e9h, 369h, 3e9h xlpg pulse waveform scale 06ah, 0eah, 16ah, 1eah, 26ah, 2eah, 36ah, 3eah xlpg pulse waveform storage write address #1 06bh, 0ebh, 16bh, 1ebh, 26bh, 2ebh, 36bh, 3ebh xlpg pulse waveform storage write address #2 06ch, 0ech, 16ch, 1ech, 26ch, 2ech, 36ch, 3ech xlpg pulse waveform storage data 06dh, 0edh, 16dh, 1edh, 26dh, 2edh, 36dh, 3edh xlpg reserved 06eh, 0eeh, 16eh, 1eeh, 26eh, 2eeh, 36eh, 3eeh xlpg reserved 06fh, 0efh, 16fh, 1efh, 26fh, 2efh, 36fh, 3efh xlpg reserved 070h, 0f0h, 170h, 1f0h, 270h, 2f0h, 370h, 3f0h rlps configuration and status 071h, 0f1h, 171h, 1f1h, 271h, 2f1h, 371h, 3f1h rlps alos detection/clearance threshold 072h, 0f2h, 172h, 1f2h, 272h, 2f2h, 372h, 3f2h rlps alos detection period 073h, 0f3h, 173h, 1f3h, 273h, 2f3h, 373h, 3f3h rlps alos clearance period 074h, 0f4h, 174h, 1f4h, 274h, 2f4h, 374h, 3f4h rlps equalization indirect address 075h, 0f5h, 175h, 1f5h, 275h, 2f5h, 375h, 3f5h rlps equalization read/writeb select 076h, 0f6h, 176h, 1f6h, 276h, 2f6h, 376h, 3f6h rlps equalizer loop status and control 077h, 0f7h, 177h, 1f7h, 277h, 2f7h, 377h, 3f7h rlps equalizer configuration 078h, 0f8h, 178h, 1f8h, 278h, 2f8h, 378h, 3f8h rlps equalization indirect data register 079h, 0f9h, 179h, 1f9h, 279h, 2f9h, 379h, 3f9h rlps equalization indirect data register
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 57 addr register 07ah, 0fah, 17ah, 1fah, 27ah, 2fah, 37ah, 3fah rlps indirect data register 07bh, 0fbh, 17bh, 1fbh, 27bh, 2fbh, 37bh, 3fbh rlps indirect data register 07ch, 0fch, 17ch, 1fch, 27ch, 2fch, 37ch, 3fch rlps voltage thresholds #1 07dh, 0fdh, 17dh, 1fdh, 27dh, 2fdh, 37dh, 3fdh rlps voltage thresholds #2 07eh, 0feh, 17eh, 1feh, 27eh, 2feh, 37eh, 3feh rlpsreserved 07fh, 0ffh, 17fh, 1ffh, 27fh, 2ffh, 37fh, 3ffh rlps reserved 400h ? 7ffh reserved for test
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 58 register 000h: reset / revision id / device id bit type function default bit 7 r/w reset 0 bit 6 r type[2] 1 bit 5 r type[1] 0 bit 4 r type[0] 0 bit 3 r id[3] 0 bit 2 r id[2] 0 bit 1 r id[1] 0 bit 0 r id[0] 0 reset: the reset bit implements a software reset. if the reset bit is a logic 1, the octliu is held in reset. this bit is not self-clearing; therefore, a logic 0 must be written to bring the octliu out of reset. holding the octliu in a reset state effectively puts it into a low-power, stand-by mode. a hardware reset clears the reset bit, thus deasserting the software reset. type: the device identification bits, type[2:0], are set to a fixed value of ?100? id: the version identification bits, id[3:0], are set to a fixed value representing the version number of the octliu.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 59 register 001h: global configuration / clock monitor bit type function default bit 7 r xclka x bit 6 r refclka x bit 5 r/w simul_regwr 0 bit 4 r/w sbi_synch 0 bit 3 r/w rsync_sel[2] / elst_sel[2] 0 bit 2 r/w rsync_sel[1] / elst_sel[1] 0 bit 1 r/w rsync_sel[0] / elst_sel[0] 0 bit 0 r/w e1/t1b 0 xclka: the xclk active (xclka) bit detects low to high transitions on the xclk input. xclka is set high on a rising edge of xclk, and is set low when this register is read. a lack of transitions is indicated by the register bit reading low. this register bit may be read at periodic intervals to detect clock failures. refclka: the refclk active (refclka) bit detects low to high transitions on the refclk input. refclka is set high on a rising edge of refclk, and is set low when this register is read. a lack of transitions is indicated by the register bit reading low. this register bit may be read at periodic intervals to detect clock failures. simul_regwr: the simultaneous register write (simul_regwr) bit enables registers for all 8 octants to be written simultaneously. when simul_regwr is set high, a write to an octant register will result in the same data also being written simultaneously to the corresponding registers belonging to the other 7 octants. when simul_regwr is set low, a write to a register will result in the addressed register, and that register only, being written. note ? simul_regwr must be set low prior to reading any octliu register. sbi_synch: the sbi synchronous mode (sbi_synch) bit configures the insbi to operate in sbi synchronous mode when set to 1. synchronous mode should only be selected when the device is operating as a sbi to clk/data converter (sbi2clk input tied high). when operating in synchronous mode, the iclk_out and ifp_out outputs must be used as clock and
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 60 frame pulse references, but need not be looped back to the iclk_in and ifp_in inputs. (in synchronous mode, the loopback is done internally and the iclk_in and ifp_in inputs are ignored.) rsync_sel[2:0]: when the sbi2clk input is tied low, the rsync select register bits, rsync_sel[2:0], select the source of the rsync octliu output. when rsync_sel[2:0] = ?000?, octant #1 is selected as the source. when rsync_sel[2:0] = ?001?, octant #2 is selected as the source. when rsync_sel[2:0] = ?010?, octant #3 is selected as the source. when rsync_sel[2:0] = ?011?, octant #4 is selected as the source. when rsync_sel[2:0] = ?100?, octant #5 is selected as the source. when rsync_sel[2:0] = ?101?, octant #6 is selected as the source. when rsync_sel[2:0] = ?110?, octant #7 is selected as the source. when rsync_sel[2:0] = ?111?, octant #8 is selected as the source. elst_sel[2:0]: when the sbi2clk input is tied high, the elastic store select register bits, elst_sel[2:0], select the source of the clock and frame pulse used to read data from the elastic stores. the clock and frame pulse are derived from one of the sbi tributaries de-mapped from the sbi bus and are output on eclk and efp respectively. when elst_sel[2:0] = ?000?, exsbi link #1 is selected as the source. when elst_sel[2:0] = ?001?, exsbi link #2 is selected as the source. when elst_sel[2:0] = ?010?, exsbi link #3 is selected as the source. when elst_sel[2:0] = ?011?, exsbi link #4 is selected as the source. when elst_sel[2:0] = ?100?, exsbi link #5 is selected as the source. when elst_sel[2:0] = ?101?, exsbi link #6 is selected as the source. when elst_sel[2:0] = ?110?, exsbi link #7 is selected as the source. when elst_sel[2:0] = ?111?, exsbi link #8 is selected as the source. e1/t1b: the global e1/t1b bit selects the operating mode of all eight of the octliu octants. if e1/t1b is logic 1, the 2.048 mbit/s e1 mode is selected for all eight octants. if e1/t1b is logic 0, the 1.544 mbit/s t1 mode is selected for all eight octants.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 61 register 002h: master interrupt source #1 bit type function default bit 7 r liu[8] x bit 6 r liu[7] x bit 5 r liu[6] x bit 4 r liu[5] x bit 3 r liu[4] x bit 2 r liu[3] x bit 1 r liu[2] x bit 0 r liu[1] x liu[8:1]: the liu[8:1] register bits allow software to determine which octant?s liu(s) is/are producing an interrupt on the intb output pin. a logic 1 indicates an interrupt is being produced from the corresponding octant. reading this register does not remove the interrupt indication; within the corresponding octant, the corresponding block?s interrupt status register must be read to remove the interrupt indication.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 62 register 003h: master interrupt source #2 bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r exsbi x bit 0 r insbi x insbi, exsbi: the insbi and exsbi register bits allow software to determine whether the insbi and/or exsbi blocks are producing an interrupt on the intb output pin. a logic 1 indicates an interrupt is being produced from the corresponding block. reading this register does not remove the interrupt indication; the corresponding block?s interrupt status register must be read to remove the interrupt indication.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 63 register 004h: master test control #1 bit type function default bit 7 w reserved x bit 6 w reserved x bit 5 w reserved x bit 4 w reserved x bit 3 w reserved 0 bit 2 r/w reserved 0 bit 1 w hizdata 0 bit 0 r/w hizio 0 this register is used to select octliu test features. all bits, except for 7,6,5 and 4 are reset to zero by a hardware reset of the octliu, a software reset of the octliu does not affect the state of the bits in this register. hizio, hizdata: the hizio and hizdata bits control the tri-state modes of the octliu. while the hizio bit is a logic 1, all output pins of the octliu except tdo and the data bus are held in a high- impedance state. the microprocessor interface is still active. while the hizdata bit is a logic 1, the data bus is held in a high-impedance state which inhibits microprocessor read cycles.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 64 register 005h: master test control #2 bit type function default bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 unused x bit 2 r/w unused x bit 1 r/w unused x bit 0 r/w unused x reserved: these bits must be 0 for correct operation.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 65 register 006h: csu configuration bit type function default bit 7 r/w csu_reset 0 bit 6 r/w iddq_en 0 bit 5 unused x bit 4 unused x bit 3 r csu_lock x bit 2 r/w mode[2] 0 bit 1 r/w mode[1] 0 bit 0 r/w mode[0] 0 mode[2:0]: the mode[2:0] selects the mode of the csu. table 5 indicates the required xclk frequency, and output frequencies for each mode. table 5 ? clock synthesis mode mode[2:0] xclk frequency transmit clock frequency 000 2.048 mhz 2.048 mhz 001 1.544 mhz 1.544 mhz 01x reserved reserved 10x reserved reserved 110 reserved reserved 111 2.048 mhz 1.544 mhz csu_lock: the csu_lock bit can be used to determine whether or not the embedded clock synthesis unit (csu) has achieved phase and frequency lock to xclk. if the csu_lock bit is polled repetitively and is persistently a logic 1, then the divided down synthesized clock frequency is within 244 ppm of the xclk frequency. a persistent logic 0 may indicate a mismatch between the actual and expected xclk frequency or a problem with the analogue supplies (cavs and cavd). iddq_en: the iddq enable bit (iddq_en) is used to configure the embedded csu for iddq tests. when iddq_en is a logic 1, or the iddqen bit in the master test control #1 register is a
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 66 logic 1, the digital outputs of the csu are pulled to ground. when either the iddq_en bit or iddqen bit is set to logic 1, the highz bit in the xlpg line driver configuration register must also be set to logic 1. csu_reset: setting the csu_reset bit to logic 1 causes the embedded csu to be forced to a frequency much lower than normal operation.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 67 register 008h, 088h, 108h, 188h, 208h, 288h, 308h, 388h: receive line interface configuration #1 bit type function default bit 7 r/w llb_ais 0 bit 6 r/w auto_llb 0 bit 5 r/w los_sbi 0 bit 4 r/w los_ais 0 bit 3 r/w rdual 0 bit 2 r/w bpv 0 bit 1 r/w rinv 0 bit 0 r/w rfall 1 llb_ais: when the llb_ais bit is set to logic 1, the liu will generate ais on the receive data output whenever line loopback is active. when the llb_ais bit is set to logic 0, the liu receive path will operate normally, regardless of whether or not line loopback is active. if llb_ais is logic 0, ais may be inserted manually via the rais register bit. auto_llb: when the auto_llb bit is set to logic 1, the liu will activate and deactivate line loopback automatically upon detection of the line loopback activate/deactivate codes by the ibcd. the auto_llb bit is only valid in t1 mode and must be set to logic 0 in e1 mode. los_sbi: the los_sbi bit enables the indication of loss of signal over the sbi interface. when los_sbi is set to logic 1, loss of signal will result in the alm (alarm) bit of the affected tributary being asserted on the sbi interface. when los_sbi is set to logic 0, the tributary?s alm bit will be set to 0. los_ais: if the los_ais bit is logic 1, ais is inserted in the receive path for the duration of a loss of signal condition. [ref: t1.403-1995 annex h]. if los_ais is logic 0, ais may be inserted manually via the rais register bit. rdual: the rdual bit configures the liu receive path for dual-rail (bipolar) operation. when rdual is set to logic 1, nrz sampled bipolar positive and negative pulses are output on rdp[n] and rdn[n] respectively. when rdual is set to logic 0, nrz sampled unipolar data
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 68 is output on rdp[n] (decoded according to ami, b8zs or hdb3) and line code violations / excessive zeros are signalled on rlcv[n]. if rdual is set to logic 1, the pdvd, ibcd and prbs blocks, and also the ability to generate ais, are disabled in the liu receive path. bpv: in t1 mode, the bpv bit enables only bipolar violations to indicate line code violations and be accumulated in the pmon lcv count registers. when bpv is set to logic 1, bpvs (provided they are not part of a valid b8zs signature if b8zs line coding is used) generate an lcv indication and increment the pmon lcv counter. when bpv is set to logic 0, both bpvs (provided they are not part of a valid b8zs signature if b8zs line coding is used) and excessive zeros (exz) generate an lcv indication and increment the pmon lcv counter. excessive zeros is a sequence of zeros greater than fifteen bits long for an ami-coded signal and greater than seven bits long for a b8zs-coded signal. in e1 mode, the bpv bit enables only bipolar violations to indicate line code violations and be accumulated in the pmon lcv count registers. (the o162 bit in the cdrc configuration register provides two e1 lcv definitions.) when bpv is set to logic 1, bpvs (provided they are not part of a valid hdb3 signature if hdb3 line coding is used) generate an lcv indication and increment the pmon lcv counter. when bpv is set to logic 0, both bpvs (provided they are not part of a valid hdb3 signature if hdb3 line coding is used) and excessive zeros (exz) generate an lcv indication and increment the pmon lcv counter. excessive zeros is a sequence of zeros greater than fifteen bits long for an ami-coded signal and greater than four bits long for an hdb3-coded signal. rinv: when rinv is set to logic 1, the receive digital outputs rdp[n] and rdn/rlcv[n] are assumed to be active low and all output data and lcv indications are inverted. when rinv is set to logic 0, the receive digital outputs rdp[n] and rdn/rlcv[n] are assumed to be active high. rinv must be set to 0 when the sbi interface is enabled (sbi_en = 1). rfall: when rfall is set to logic 1, the rdp[n] and rdn/rlcv[n] outputs are updated on falling edges of rclk[n]. when rfall is set to logic 0, the outputs are updated on rising edges of rclk[n]. rfall must be set to 1 when the sbi interface is enabled (sbi_en = 1).
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 69 register 009h, 089h, 109h, 189h, 209h, 289h, 309h, 389h: receive line interface configuration #2 bit type function default bit 7 r/w rjatbyp 1 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w rsync_alosb 0 bit 1 r/w rsync_mem 0 bit 0 r/w rsyncsel 0 rjatbyp: the rjatbyp bit disables jitter attenuation in the receive direction. when receive jitter attenuation is not being used, setting rjatbyp to logic 1 will reduce the latency through the receiver section by typically 40 bits. when rjatbyp is set to logic 0, the liu?s rsync output is jitter attenuated. when the rjat is bypassed, the octant?s rsync is not jitter attenuated. rsync_alosb: the rsync_alosb bit controls the source of the loss of signal condition used to control the behaviour of the receive reference presented on the rsync output. if rsync_alosb is a logic 0, analogue loss of signal is used. if rsync_alosb is a logic 1, digital loss of signal is used. when the liu is in a loss of signal state, the rsync output is derived from xclk or held high, as determined by the rsync_mem bit. when the liu is not in a loss of signal state, the rsync output is derived from the receive recovered clock of the selected octant. the octant to be used as the source of rsync is determined by the rsync_sel[2:0] bits. rsync_mem: the rsync_mem bit controls the octant?s rsync output under a loss of signal condition (as determined by the rsync_alosb register bit). when rsync_mem is a logic 1, the octant?s rsync output is held high during a loss of signal condition. when rsync_mem is a logic 0, the octant?s rsync output is derived from the csu 1x line rate clock during a loss of signal condition. rsyncsel: the rsyncsel bit selects the frequency of the receive reference presented on the octant?s rsync output. if rsyncsel is a logic 1, the octant?s rsync will be an 8 khz clock. if
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 70 rsyncsel is a logic 0, the octant?s rsync will be an 1.544 mhz (t1) or 2.048 mhz (e1) clock.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 71 register 00ah, 08ah, 10ah, 18ah, 20ah, 28ah, 30ah, 38ah: transmit line interface configuration bit type function default bit 7 r/w tjatbyp 0 bit 6 r/w taisen 0 bit 5 r/w tauxp 0 bit 4 r/w sbi_ais 1 bit 3 r/w tdual 0 bit 2 r/w ami 0 bit 1 r/w tinv 0 bit 0 r/w trise 1 tjatbyp: the tjatbyp bit enables the transmit jitter attenuator to be removed from the transmit data path. when the transmit jitter attenuator is bypassed, the latency through the transmitter section is reduced by typically 40 bits. taisen: the taisen bit enables the interface to generate an unframed all-ones ais alarm on the txtip[n] and txring[n]. when taisen is set to logic 1, the bipolar txtip[n] and txring[n] outputs are forced to pulse alternately, creating an all-ones signal. the transition to transmitting ais on the txtip[n] and txring[n] outputs is done in such a way as to avoid introducing any bipolar violations. the diagnostic digital loopback point is prior to the ais insertion point. (implementation note. taisen has priority over tauxp, which in turn has priority over tdatinv.). tauxp: the tauxp bit enables the interface to generate an unframed alternating zeros and ones (i.e. 010101?) auxiliary pattern (auxp) on the txtip[n] and txring[n]. when tauxp is set to logic 1, the bipolar txtip[n] and txring[n] outputs are forced to pulse alternately every other cycle. the transition to transmitting auxp on the txtip[n] and txring[n] outputs is done in such a way as to avoid introducing any bipolar violations. the diagnostic digital loopback point is prior to the auxp insertion point. sbi_ais: the sbi_ais bit enables the insertion of ais in the transmit path in response to an alarm indication from the sbi interface. when sbi_ais is set to logic 1, setting the alm (alarm) bit
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 72 of a tributary on the sbi interface causes the bipolar txtip[n] and txring[n] outputs to be forced to pulse alternately, creating an all-ones signal. the transition to transmitting ais on the txtip[n] and txring[n] outputs is done in such a way as to avoid introducing any bipolar violations. the diagnostic digital loopback point is prior to the ais insertion point. tdual: the tdual bit configures the liu transmit path for dual-rail (bipolar) operation. when tdual is set to logic 1, nrz bipolar positive and negative data is input on tdp[n] and tdn[n] respectively. when tdual is set to logic 0, nrz unipolar data is input on tdp[n] and tdn[n] is ignored. tdual must be set to logic 0 when operating in sbi mode (i.e. when the sbi_en input is logic 1). if tdual is set to logic 1, the xibc, xpde, lcode and prbs blocks are disabled in the liu transmit path. ami: the ami bit enables ami line coding. if ami is set to a logic 1, the liu will perform ami line encoding on the tdp[n] single-rail input data stream. if ami is set to a logic 0, the liu will perform b8zs (if operating in t1 mode) or hdb3 (if operating in e1 mode) line encoding on the tdp[n] data stream. the ami bit is ignored if the tdual bit is set to logic 1. tinv: when tinv is set to logic 1, the transmit digital inputs tdp[n] and tdn[n] are assumed to be active low and all input data is inverted. when tinv is set to logic 0, the transmit digital inputs tdp[n] and tdn[n] are assumed to be active high. trise: when trise is set to logic 1, the tdp[n] and tdn[n] inputs are sampled on rising edges of tclk[n]. when trise is set to logic 0, the inputs are sampled on falling edges of tclk[n].
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 73 register 00bh, 08bh, 10bh, 18bh, 20bh, 28bh, 30bh, 38bh: transmit timing options / clock monitor / pulse template selection bit type function default bit 7 r/w pt_sel[3] 0 bit 6 r/w pt_sel[2] 0 bit 5 r/w pt_sel[1] 0 bit 4 r/w pt_sel[0] 0 bit 3 r tclka x bit 2 r/w oclksel 0 bit 1 r/w pllref[1] 0 bit 0 r/w pllref[0] 0 pt_sel[3:0]: the pulse template selection (pt_sel[3:0]) bits determine which of the twelve pulse template waveforms stored in the xlpg is used to generate transmit data pulses on the txtip[n] and txring[n] outputs. pt_sel[3:0] must be set to a value between 0 and 11. pt_sel[3:0] are not used when operating in hardware-only mode (hw_only input = 1). in hardware-only mode, the lenx[2:0] inputs select which pulse template is to be used and only pulse templates 0 to 7 may be selected. tclka: the tclk[n] active (tclka) bit detects low to high transitions on the tclk[n] input. tclka is set high on a rising edge of tclk[n], and is set low when this register is read. a lack of transitions is indicated by the register bit reading low. this register bit may be read at periodic intervals to detect clock failures. oclksel: the oclksel bit selects the source of the transmit jitter attenuator fifo output clock signal.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 74 table 6 ? tjat fifo output clock source oclksel source of fifo output clock 0 the tjat fifo output clock is connected to the internal jitter-attenuated 1.544 mhz or 2.048 mhz clock. 1 the tjat fifo output clock is connected to the fifo input clock. in this mode the jitter attenuation is disabled and the input clock must be jitter-free. pllref[1:0] must be set to ?00? in this mode. pllref: the pllref bit selects the source of the transmit jitter attenuator phase locked loop reference signal as follows: table 7 ? tjat pll source pllref[1:0] source of pll reference 00 tjat fifo input clock (either the transmit clock or the receive recovered clock, as selected by linelb) 01 receive recovered clock 1x csu transmit clock (see table 5) upon reset of the octliu, the oclksel and pllref bits are cleared to zero, selecting jitter attenuation with transmit line clock referenced to the transmit clock, tclk[n] (or the sbi tributary clock). figure 17 illustrates the various bit setting options, with the reset condition highlighted.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 75 figure 17 ? transmit timing options tjat fifo 1 linelb fifo input data clock tjat pll pllref "jitter-free" line rate clock (1.544mhz or 2.048mhz) fifo output data clock 0 00 1 0 oclksel or tja tby p receive recovered clock tclk[n] / sbi transmit clock 01 transmit line cloc k 1x csu trans mit c loc k tr ans mit data in transmit data out 1 tja tby p 0 24x line rate clock for pulse generation
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 76 register 00ch, 08ch, 10ch, 18ch, 20ch, 28ch, 30ch, 38ch: line interface interrupt source #1 / pmon update bit type function default bit 7 r pmon x bit 6 r prbs x bit 5 r ibcd x bit 4 r pdvd x bit 3 r xpde x bit 2 r tjat x bit 1 r rjat x bit 0 r cdrc x this register allows software to determine the block which produced the interrupt on the intb output pin. a logic 1 indicates an interrupt was produced from the block. reading this register does not remove the interrupt indication; the corresponding block?s interrupt status register must be read to remove the interrupt indication. writing any value to this register causes the octant?s performance monitor lcv counter and prbs error counter to be updated.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 77 register 00dh, 08dh, 10dh, 18dh, 20dh, 28dh, 30dh, 38dh: line interface interrupt source #2 bit type function default bit 7 r elst x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r rlps x this register allows software to determine the block that produced the interrupt on the intb output pin. a logic 1 indicates an interrupt was produced from the block. reading this register does not remove the interrupt indication; the corresponding block?s interrupt status register must be read to remove the interrupt indication.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 78 register 00eh, 08eh, 10eh, 18eh, 20eh, 28eh, 30eh, 38eh: line interface diagnostics bit type function default bit 7 unused x bit 6 unused x bit 5 r/w lcvins 0 bit 4 r/w linelb 0 bit 3 r/w rais 0 bit 2 r/w ddlb 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 lcvins: the lcvins bit introduces a single line code violation on the transmitted data stream. in b8zs, the violation is generated by masking the first violation pulse of a b8zs signature. in ami, one pulse is sent with the same polarity as the previous pulse. in hdb3, the violation is generated by causing the next hdb3-code generated bipolar violation pulse to be of the same polarity as the previous bipolar violation. to generate another violation, this bit must first be written to 0 and then to logic 1 again. at least one bit period should elapse between writing lcvins 0 and writing it 1 again, or vice versa, if an error is to be successfully inserted. lcvins has no effect when tdual is set to logic 1. linelb: the linelb bit selects the line loopback mode, where the recovered data are internally directed to the digital inputs of the transmit jitter attenuator. the data sent to the tjat is the recovered data from the output of the cdrc block. when linelb is set to logic 1, the line loopback mode is enabled. when linelb is set to logic 0, the line loopback mode is disabled. note that when line loopback is enabled, to correctly attenuate the jitter on the receive clock, the contents of the tjat reference clock divisor and output clock divisor registers should be programmed to 2fh in t1 mode / ffh in e1 mode and the transmit timing options register should be cleared to all zeros. only one of linelb and ddlb can be enabled at any one time. rais: when the rais bit is set to logic 1, the receive output data stream of the octant is forced to all ones. ddlb: the ddlb bit selects the diagnostic digital loopback mode, where the octant is configured to internally direct the output of the tjat to the inputs of the receiver section. the dual-rail rz
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 79 outputs of the tjat are directed to the dual-rail inputs of the cdrc. when ddlb is set to logic 1, the diagnostic digital loopback mode is enabled. when ddlb is set to logic 0, the diagnostic digital loopback mode is disabled. only one of linelb and ddlb can be enabled at any one time. reserved: these bits must be a logic 0 for correct operation.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 80 register 00fh, 08fh, 10fh, 18fh, 20fh, 28fh, 30fh, 38fh: line interface prbs position bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w tx_gen 0 bit 1 r/w rx_gen 0 bit 0 r/w tx_det 0 tx_gen: the transmit path generate, tx_gen, bit controls the output of the prbs generator. when tx_gen is set to logic 1, the prbs generator output is inserted into the transmit path. when tx_gen is set to logic 0, the transmit path functions normally. rx_gen: the receive path generate, rx_gen, bit controls the output of the prbs generator. when rx_gen is set to logic 1, the prbs generator output is inserted into the receive path. when rx_gen is set to logic 0, the receive path functions normally. tx_det: the transmit path detect, tx_det, bit controls the input of the prbs checker. when tx_det is set to logic 1, the prbs checker monitors the transmit path. when tx_det is set to logic 0, the prbs detector monitors the receive path.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 81 register 310h: insbi control bit type function default bit 7 r/w apage 0 bit 6 r/w dc_enbl 1 bit 5 r/w dc_int_en 0 bit 4 r/w fifo_ovre 0 bit 3 r/w fifo_udre 0 bit 2 r/w ts_en 0 bit 1 unused x bit 0 r/w sbi_par_ctl 1 sbi_par_ctl: the sbi_par_ctl bit is used to configure the parity mode for generation of the sbi data parity signal, ddp as follows: ? when sbi_par_ctl is a ?0? parity will be even. ? when sbi_par_ctl is a ?1? parity will be odd. ts_en: the ts_en bit is used to enable the sbi tributary to liu octant data stream mapping capability. ? when ts_en is a ?0?, the mapping is fixed to a one to one mapping and is not programmable. the 8 liu data streams are mapped to tributaries 1 to 8 of spe #1 within the sbi structure. ? when ts_en is a ?1?, sbi tributary to liu octant data stream mapping is enabled and is specified by the contents of the insbi tributary mapping registers. fifo_udre: the fifo_udre bit is used to enable/disable the generation of an interrupt when a fifo underrun is detected. ? when fifo_udre is a ?0? underrun interrupt generation is disabled. ? when fifo_udre is a ?1? underrun interrupt generation is enabled. fifo_ovre: the fifo_ovre bit is used to enable/disable the generation of an interrupt when a fifo overrun is detected. ? when fifo_ovre is a ?0? overrun interrupt generation is disabled.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 82 ? when fifo_ovre is a ?1? overrun interrupt generation is enabled. dc_int_en: this bit is set to enable the generation of an interrupt when either of the following events occurs: ? a depth check error ? an external resynchronization event occurs on the dc1fp signal dc_enbl: this bit enables depth check resets. the depth checker periodically monitors the link fifo depths and compares them against the read and write pointers. discrepancies are reported in the depth checker interrupt status register. if dc_enbl is ?1?, the affected link is automatically reset. if dc_enbl is ?0?, the link is not reset. apage: the tributary mapping register active page select bit (apage) controls the selection of one of two pages of tributary mapping registers. when apage is set low, the configuration in page a of the tributary mapping registers is used to associate sbi tributaries to liu octant data streams. when apage is set high, the configuration in page b of the tributary mapping registers is used to associate sbi tributaries to liu octant data streams. when apage changes state, any data streams where the mapping registers do not match are automatically reset.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 83 register 311h: insbi fifo underrun interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r link[3] 0 bit 3 r link[2] 0 bit 2 r link[1] 0 bit 1 r link[0] 0 bit 0 r fifo_udri 0 fifo_udri: this bit is set when a fifo underrun is detected. it is cleared when the register is read (but may be set again immediately thereafter if a further underrun report is pending). link[3:0]: the link[3:0] field is used to specify the liu octant data stream associated with the fifo buffer in which the underrun was detected. link[3:0] should only be looked at when fifo_udri is a ?1?. valid values of link[3:0] are from 1 to 8. this register will contain the interrupt status even if the corresponding interrupt enable is not set.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 84 register 312h: insbi fifo overrun interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r link[3] 0 bit 3 r link[2] 0 bit 2 r link[1] 0 bit 1 r link[0] 0 bit 0 r fifo_ovri 0 fifo_ovri: this bit is set when a fifo overrun is detected. it is cleared when the register is read (but may be set again immediately thereafter if a further overrun report is pending). link[3:0]: the link[3:0] field is used to specify the liu octant data stream associated with the fifo buffer in which the overrun was detected. link[3:0] should only be looked at when fifo_ovri is a ?1?. valid values of link[3:0] are from 1 to 8. this register will contain the interrupt status even if the corresponding interrupt enable is not set.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 85 register 313h ? 31ah: insbi page a octant to tributary mapping #1 - #8 bit type function default bit 7 unused x bit 6 r/w spe[1] 0 bit 5 r/w spe[0] 0 bit 4 r/w trib[4] 0 bit 3 r/w trib[3] 0 bit 2 r/w trib[2] 0 bit 1 r/w trib[1] 0 bit 0 r/w trib[0] 0 spe[1:0] and trib[4:0]: the spe[1:0] and trib[4:0] fields are used to specify the liu octant data stream to sbi tributary mapping when apage is set to 0. the output of the octant corresponding to the register (1-8) is mapped to the spe and tributary specified by the value of spe[1:0] and trib[4:0]. valid values of spe[1:0] are from 1 to 3. valid values of trib[4:0] are from 1 to 28 in t1 mode and from 1 to 21 in e1 mode. note: the mapping of more than one tributary to the same liu octant data stream or more than one liu octant data stream to the same tributary is not allowed. special care must be taken to ensure that all liu octants and tributaries are uniquely mapped when using multiple octliu?s on the same sbi bus. failure to do so will result in bus contention.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 86 register 31bh ? 322h: insbi page b octant to tributary mapping #1 - #8 bit type function default bit 7 unused x bit 6 r/w spe[1] 0 bit 5 r/w spe[0] 0 bit 4 r/w trib[4] 0 bit 3 r/w trib[3] 0 bit 2 r/w trib[2] 0 bit 1 r/w trib[1] 0 bit 0 r/w trib[0] 0 spe[1:0] and trib[4:0]: the spe[1:0] and trib[4:0] fields are used to specify the liu octant data stream to sbi tributary mapping when apage is set to 1. the output of the octant corresponding to the register (1-8) is mapped to the spe and tributary specified by the value of spe[1:0] and trib[4:0]. valid values of spe[1:0] are from 1 to 3. valid values of trib[4:0] are from 1 to 28 in t1 mode and from 1 to 21 in e1 mode. note: the mapping of more than one tributary to the same liu octant data stream or more than one liu octant data stream to the same tributary is not allowed. special care must be taken to ensure that all liu octants and tributaries are uniquely mapped when using multiple octliu?s on the same sbi bus. failure to do so will result in bus contention.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 87 register 323h: insbi link enable bit type function default bit 7 r/w enbl8 0 bit 6 r/w enbl7 0 bit 5 r/w enbl6 0 bit 4 r/w enbl5 0 bit 3 r/w enbl4 0 bit 2 r/w enbl3 0 bit 1 r/w enbl2 0 bit 0 r/w enbl1 0 enbl1 ? enbl8: the enblx bits are used to enable the liu octant data streams. setting the enbl bit for a particular liu octant data stream enables the insbi8 to take data from the octant and transmit that data to the sbi tributary mapped to that stream.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 88 register 324h: insbi link enable busy bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r busy 0 busy: a write to the insbi link enable register sets busy to ?1?. busy is cleared to ?0? approximately three refclk cycles later after the register contents have been synchronized to refclk. the user must check that busy is ?0? before writing to the insbi link enable register. following a reset, busy will be ?1? until startup circuitry has finished automatically initializing certain rams within insbi.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 89 register 325h ? 32ch: insbi tributary control #1 ? #8 bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w trib_typ[1] 1 bit 1 r/w trib_typ[0] 0 bit 0 r/w reserved 0 a tributary control register should only be written when the associated enblx bit is ?0?. reserved: the reserved bits must be set to 0 for correct operation of the octliu device. trib_typ[1:0]: the trib_typ[1:0] field specifies the characteristics of the sbi tributary, as shown in table 8. table 8 ? insbi tributary characteristics trib_typ[1:0] description 00 reserved. 01 framed (ifp_in determines frame alignment). 10 unframed (ifp_in ignored). 11 reserved. the trib_typ[1:0] bits must be set to ?10? whenever the lius are enabled (sbi2clk tied low).
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 90 register 32dh: insbi minimum depth bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w min_dep[3] 0 bit 2 r/w min_dep[2] 1 bit 1 r/w min_dep[1] 1 bit 0 r/w min_dep[0] 1 min_dep [3:0]: the min_depth[3:0] bits specify the tributary fifo minimum depth, i.e. the depth that must be reached before the fifo reader starts to take data from the fifo.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 91 register 32eh: insbi fifo thresholds bit type function default bit 7 r/w min_thr[3] 0 bit 6 r/w min_thr[2] 1 bit 5 r/w min_thr[1] 1 bit 4 r/w min_thr[0] 0 bit 3 r/w max_thr[3] 1 bit 2 r/w max_thr[2] 1 bit 1 r/w max_thr[1] 1 bit 0 r/w max_thr[0] 0 min_thr[3:0]: the min_thr[3:0] bits specify the tributary fifo minimum threshold, i.e. the fifo depth below which a positive justification is performed. note ? the default value of this register is the recommended value when operating in t1 mode. when operating in e1 mode, it is recommended that min_thr[3:0] be set to ?0010?. max_thr[3:0]: the max_thr[3:0] bits specify the tributary fifo maximum threshold, i.e. the fifo depth which when exceeded will cause a negative justification.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 92 register 331h: insbi depth check interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r link[3] 0 bit 3 r link[2] 0 bit 2 r link[1] 0 bit 1 r link[0] 0 bit 0 r dcr_inti 0 dcr_inti: this bit is set when a depth check error is detected. it is cleared when the register is read (but may be set again immediately thereafter if a further depth check error report is pending). link[3:0]: the link[3:0] field is used to specify the liu octant data stream associated with the fifo buffer in which the depth check error was detected. link[3:0] should only be looked at when dcr_inti is a ?1?. valid values for link[3:0] are from 1 to 8. this register will contain the interrupt status even if the corresponding interrupt enable is not set.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 93 register 332h: insbi master interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 r dcr_inti_shdw 0 bit 4 unused x bit 3 r fifo_udri_shdw 0 bit 2 r fifo_ovri_shdw 0 bit 1 unused x bit 0 r c1fp_sync_inti 0 c1fp_sync_inti: this bit is set when a dc1fp realignment has been detected. it is cleared when the register is read. fifo_ovri_shdw: this bit is a shadow of the fifo_ovri bit in the insbi fifo over run interrupt status register. it is set when the fifo_ovri bit is set and the interrupt enable fifo_ovre is set. reading this register has no affect on the interrupt status. fifo_udri_shdw: this bit is a shadow of the fifo_udri bit in the insbi fifo under run interrupt status register. it is set when the fifo_udri bit is set and the interrupt enable fifo_udre is set. reading this register has no affect on the interrupt status. dcr_inti_shdw: this bit is a shadow of the dcr_inti bit in the insbi depth check interrupt status register. it is set when the dcr_inti bit is set and the interrupt enable dcr_int_en is set. reading this register has no affect on the interrupt status.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 94 register 390h: exsbi control bit type function default bit 7 r/w apage 0 bit 6 r/w dc_enbl 1 bit 5 r/w dc_int_en 0 bit 4 r/w fifo_ovre 0 bit 3 r/w fifo_udre 0 bit 2 r/w ts_en 0 bit 1 r/w sbi_perr_en 0 bit 0 r/w sbi_par_ctl 1 sbi_par_ctl: the sbi_par_ctl bit is used to configure the parity mode for checking of the sbi data parity signal, adp as follows: ? when sbi_par_ctl is a ?0? parity will be even. ? when sbi_par_ctl is a ?1? parity will be odd. sbi_perr_en: the sbi_perr_en bit is used to enable the sbi parity error interrupt generation ? when sbi_perr_en is ?0? sbi parity error interrupts will be disabled ? when sbi_perr_en is ?1? sbi parity error interrupts will be enabled in both cases the sbi parity checker logic will update the sbi parity error interrupt reason register. ts_en: the ts_en bit is used to enable the sbi tributary to liu octant data stream mapping capability. ? when ts_en is a ?0?, the mapping is fixed to a one to one mapping and is not programmable. the 8 liu data streams are mapped to tributaries 1 to 8 of spe #1 within the sbi structure. ? when ts_en is a ?1?, sbi tributary to liu octant data stream mapping is enabled and is specified by the contents of the exsbi tributary mapping registers. fifo_udre: the fifo_udre bit is used to enable/disable the generation of an interrupt when a fifo underrun is detected.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 95 ? when fifo_udre is a ?0? underrun interrupt generation is disabled. ? when fifo_udre is a ?1? underrun interrupt generation is enabled. fifo_ovre: the fifo_ovre bit is used to enable/disable the generation of an interrupt when a fifo overrun is detected. ? when fifo_ovre is a ?0? overrun interrupt generation is disabled. ? when fifo_ovre is a ?1? overrun interrupt generation is enabled. dc_int_en: this bit is set to enable the generation of an interrupt when either of the following events occurs: ? a depth check error ? an external resynchronization event occurs on the ac1fp signal dc_enbl: this bit enables depth check resets. the depth checker periodically monitors the link fifo depths and compares them against the read and write pointers. discrepancies are reported in the depth checker interrupt status register. if dc_enbl is ?1?, the affected link is automatically reset. if dc_enbl is ?0?, the link is not reset. apage: the tributary mapping active page select bit (apage) controls the group of mapping registers used to associate sbi tributaries and liu octant data streams. when mapping is enabled and apage is low, the a set of mapping registers (0x3a8 to 0x3af) is used. when mapping is enabled and apage is high, the b set of mapping registers (0x3b0 to 0x3b7) is used. when apage changes state, any data streams where the mapping registers do not match are automatically reset.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 96 register 391h: exsbi fifo underrun interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r link[3] 0 bit 3 r link[2] 0 bit 2 r link[1] 0 bit 1 r link[0] 0 bit 0 r fifo_udri 0 fifo_udri: this bit is set when a fifo underrun is detected. it is cleared when the register is read. link[3:0]: the link[3:0] field is used to specify the liu octant data stream associated with the fifo buffer in which the underrun was detected. link[3:0] should only be looked at when fifo_udri is a ?1?. valid values of link[3:0] are from 1 to 8. this register will contain the interrupt status even if the corresponding interrupt enable is not set.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 97 register 392h: exsbi fifo overrun interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r link[3] 0 bit 3 r link[2] 0 bit 2 r link[1] 0 bit 1 r link[0] 0 bit 0 r fifo_ovri 0 fifo_ovri: this bit is set when a fifo overrun is detected. it is cleared when the register is read. link[3:0]: the link[3:0] field is used to specify the liu octant data stream associated with the fifo buffer in which the over-run was detected. link[3:0] should only be looked at when fifo_ovri is a ?1?. valid values of link[3:0] are from 1 to 8. this register will contain the interrupt status even if the corresponding interrupt enable is not set.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 98 register 393h: exsbi parity error interrupt reason bit type function default bit 7 r spe[1] 0 bit 6 r spe[0] 0 bit 5 r trib[4] 0 bit 4 r trib[3] 0 bit 3 r trib[2] 0 bit 2 r trib[1] 0 bit 1 r trib[0] 0 bit 0 r perri 0 perri: when set perri indicates that an sbi parity error has been detected. it is cleared when the register is read. trib[4:0] and spe[1:0]: the trib[4:0] and spe[1:0] field are used to specify the sbi tributary for which a parity error was detected. these fields are only valid only when perri is set. when a parity error has not been detected the trib[4:0] field may contain an out of range tributary value. if the type of the spe where the parity error occurred does not correspond to the operating mode of the octliu (e.g. a parity error in a spe containing e1s when the octliu is operating in t1 mode), spe[1:0] will be valid but trib[4:0] will be invalid. values in these fields should only be looked at when perri is a ?1?.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 99 register 394h: exsbi depth check interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r link[3] 0 bit 3 r link[2] 0 bit 2 r link[1] 0 bit 1 r link[0] 0 bit 0 r dcri 0 dcri: this bit is set when a depth check error is detected. it is cleared when the register is read. link[3:0]: the link[3:0] field is used to specify the liu octant data stream associated with the fifo buffer in which the depth check error was detected. link[3:0] should only be looked at when dcri is a ?1?. valid values for link[3:0] are from 1 to 8. this register will contain the interrupt status even if the corresponding interrupt enable is not set.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 100 register 395h: exsbi master interrupt status bit type function default bit 7 r/w reserved 0 bit 6 unused x bit 5 r dcri_shdw 0 bit 4 r perri_shdw 0 bit 3 r fifo_udri_shdw 0 bit 2 r fifo_ovri_shdw 0 bit 1 unused x bit 0 r c1fp_synci 0 c1fp_synci: this bit is set when a ac1fp realignment has been detected. reading this register clears this interrupt source. fifo_ovri_shdw: this bit is a shadow of the fifo_ovri bit in the exsbi fifo overrun interrupt status register. it is set when the fifo_ovri bit is set and the interrupt enable fifo_ovre is set. reading this register has no affect on this interrupt source. fifo_udri_shdw: this bit is a shadow of the fifo_udri bit in the exsbi fifo underrun interrupt status register. it is set when the fifo_udri bit is set and the interrupt enable fifo_udre is set. reading this register has no affect on this interrupt source. perri_shdw: this bit is a shadow of the perri bit in the exsbi parity error interrupt reason register. it is set when the perri bit is set and the interrupt enable sbi_perr_en is set. reading this register has no affect on this interrupt source. dcri_shdw: this bit is a shadow of the dcri bit in the exsbi depth check interrupt status register. it is set when the dcri bit is set and the interrupt enable dcr_int_en is set. reading this register has no affect on this interrupt source. reserved: the reserved bit must be set to 0 for correct operation of the octliu device.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 101 register 396h: exsbi minimum depth bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w min_dep[3] 0 bit 2 r/w min_dep[2] 1 bit 1 r/w min_dep[1] 1 bit 0 r/w min_dep[0] 1 min_dep[3:0]: the min_depth[3:0] bits specify the tributary fifo minimum depth, i.e. the depth that must be reached before the fifo reader starts to take data from the fifo.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 102 register 397h: exsbi fifo thresholds bit type function default bit 7 r/w min_thr[3] 0 bit 6 r/w min_thr[2] 0 bit 5 r/w min_thr[1] 1 bit 4 r/w min_thr[0] 0 bit 3 r/w max_thr[3] 1 bit 2 r/w max_thr[2] 1 bit 1 r/w max_thr[1] 0 bit 0 r/w max_thr[0] 1 min_thr[3:0]: the min_thr[3:0] bits specify the tributary fifo minimum threshold, i.e. the fifo depth below which the serial data stream to the liu octant is slowed down (when clk_mode[1:0] = ?00? in the exsbi tributary control register for the octant). max_thr[3:0]: the max_thr[3:0] bits specify the tributary fifo maximum threshold, i.e. the fifo depth above which the serial data stream to the liu octant is sped up (when clk_mode[1:0] = ?00? in the exsbi tributary control register for the octant).
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 103 register 398h: exsbi link enable bit type function default bit 7 r/w link_enbl[8] 0 bit 6 r/w link_enbl[7] 0 bit 5 r/w link_enbl[6] 0 bit 4 r/w link_enbl[5] 0 bit 3 r/w link_enbl[4] 0 bit 2 r/w link_enbl[3] 0 bit 1 r/w link_enbl[2] 0 bit 0 r/w link_enbl[1] 0 link_enbl[8:1]: the link_enbl[8:1] bits enable the operation of the corresponding liu octant data streams. when link_enbl is ?1? for a stream, the exsbi8 will take data from an sbi tributary and transmit that data to the liu octant. the tributary to octant mapping is determined by the octant to tributary mapping registers and apage.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 104 register 399h: exsbi link enable busy bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r busy 0 busy: a write to the exsbi link enable register sets busy to ?1?. busy is cleared to ?0? approximately three refclk cycles later after the register contents have been synchronized to refclk. the user must check that busy is ?0? before writing to the exsbi link enable register. following a reset, busy will be ?1? until startup circuitry has finished automatically initializing certain rams within exsbi.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 105 register 3a0h ? 3a7h: exsbi tributary control #1 ? #8 bit type function default bit 7 unused x bit 6 r/w clk_mode[1] 0 bit 5 r/w clk_mode[0] 0 bit 4 r/w reserved 0 bit 3 r/w trib_typ[1] 1 bit 2 r/w trib_typ[0] 0 bit 1 r/w reserved 0 bit 0 unused x a tributary control register should only be written when the associated link_enbl bit is ?0?. reserved: the reserved bits must be set to 0 for correct operation of the octliu device. trib_typ[1:0]: the trib_typ[1:0] field specifies the characteristics of the sbi tributary, as shown in table 9. table 9 ? exsbi tributary characteristics trib_typ[1:0] description 00 reserved. 01 framed (efp indicates frame alignment). 10 unframed (efp remains low). 11 reserved. the trib_typ[1:0] bits must be set to ?10? whenever the lius are enabled (sbi2clk tied low). clk_mode[1:0]: the clk_mode[1:0] field selects one of three different methods whereby the frequency of the serial data stream output to the liu octant is determined, as shown in table 10.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 106 table 10 ? exsbi clock generation options clk_mode[1:0] description 00 speed up and slow down the output serial clock depending on the fifo fill level and the thresholds specified in the exsbi thresholds register. 01 speed up and slow down the output serial clock depending on the ?clkrate? field of the tributary?s link rate octet on the sbi bus. 10 speed up and slow down the output serial clock depending on the ?phase? field of the tributary?s link rate octet on the sbi bus. 11 reserved.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 107 register 3a8h ? 3afh: exsbi page a octant to tributary mapping #1 - #8 bit type function default bit 7 unused x bit 6 r/w spe[1] 0 bit 5 r/w spe[0] 0 bit 4 r/w trib[4] 0 bit 3 r/w trib[3] 0 bit 2 r/w trib[2] 0 bit 1 r/w trib[1] 0 bit 0 r/w trib[0] 0 spe[1:0] and trib[4:0]: the spe[1:0] and trib[4:0] fields are used to specify the liu octant data stream to sbi tributary mapping when apage is set to 0. the input of the octant corresponding to the register (1-8) is sourced from the spe and tributary specified by the value of spe[1:0] and trib[4:0]. valid values of spe[1:0] are from 1 to 3. valid values of trib[4:0] are from 1 to 28 in t1 mode and from 1 to 21 in e1 mode.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 108 register 3b0h to 3b7h: exsbi page b octant to tributary mapping #1 - #8 bit type function default bit 7 unused x bit 6 r/w spe[1] 0 bit 5 r/w spe[0] 0 bit 4 r/w trib[4] 0 bit 3 r/w trib[3] 0 bit 2 r/w trib[2] 0 bit 1 r/w trib[1] 0 bit 0 r/w trib[0] 0 spe[1:0] and trib[4:0]: the spe[1:0] and trib[4:0] fields are used to specify the liu octant data stream to sbi tributary mapping when apage is set to 1. the input of the octant corresponding to the register (1-8) is sourced from the spe and tributary specified by the value of spe[1:0] and trib[4:0]. valid values of spe[1:0] are from 1 to 3. valid values of trib[4:0] are from 1 to 28 in t1 mode and from 1 to 21 in e1 mode. note: the mapping of more than one tributary to the same liu octant data stream or more than one liu octant data stream to the same tributary is not allowed. special care must be taken to ensure that all liu octants and tributaries are uniquely mapped when using multiple octliu?s on the same sbi bus. failure to do so will result in bus contention.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 109 register 040h, 0c0h, 140h, 1c0h, 240h, 2c0h, 340h, 3c0h: elst configuration bit type function default bit 7 r/w reserved 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w ir 1 bit 0 r/w or 1 ir: the ir bit selects the data rate to be used at the input of the elastic store. this bit should be set to 0 for t1/j1 operation and to 1 for e1 operation. or: the or bit selects the data rate to be used at the output of the elastic store. this bit should be set to 0 for t1/j1 operation and to 1 for e1 operation.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 110 register 041h, 0c1h, 141h, 1c1h, 241h, 2c1h, 341h, 3c1h: elst interrupt enable/status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w slipee 0 bit 1 r slipd x bit 0 r slipi x slipe: the slipe bit enables an interrupt to be generated on the microprocessor intb pin when a frame slip occurs in the elastic store. when slipe is set to logic 1, interrupt generation is enabled. when slipe is set to logic 0, interrupt generation is disabled. slipd: the slipd bit indicates the direction of the last frame slip. when slipd is set to logic 1, the last frame slip was a write slip (frame skipped due to buffer becoming full). when slipe is set to logic 0, the last frame slip was a read slip (frame repeated due to buffer becoming empty). slipi: the slipi bit indicates the occurrence of a frame slip when set to 1. slipi is cleared to 0 when this register is read. note that the slipi interrupt indication operates regardless of whether interrupts are enabled or disabled.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 111 register 043h, 0c3h, 143h, 1c3h, 243h, 2c3h, 343h, 3c3h: t1 pdvd interrupt enable/status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r pdv x bit 3 r z16di x bit 2 r pdvi x bit 1 r/w z16de 0 bit 0 r/w pdve 0 when the e1/t1b bit of the global configuration register is a logic 1, this register is held reset. pdv: the pdv bit indicates the current state of the pulse density violation indication. when pdv is a logic 1, a violation of the pulse density rule exists. when pdv is a logic 0, no violation of the pulse density rule exists. note: the pdv indication persists for the duration of the pulse density violation. at its minimum, pdv may be asserted for only 1 bit time, therefore, reading this bit may not return a logic 1 even though a pulse density violation has occurred. pdvi, z16di: the pdvi and z16di bits identify the source of a generated interrupt. pdvi is a logic 1 whenever a change in the pulse density violation indication generated an interrupt. pdvi is cleared to 0 when this register is read. z16di is a logic 1 whenever 16 consecutive zeros are detected. z16di is cleared to 0 when this register is read. note that the pdvi and z16di interrupt indications operate regardless of whether interrupts are enabled or disabled. z16de: the z16de bit enables an interrupt to be generated on the microprocessor intb pin when 16 consecutive zeros are detected. when z16de is set to logic 1, interrupt generation is enabled. when z16de is set to logic 0, interrupt generation is disabled. pdve: the pdve bit enables an interrupt to be generated on the microprocessor intb pin when a change in the pulse density is detected. when pdve is set to logic 1, an interrupt is generated whenever a pulse density violation occurs or when the pulse density ceases to exist. when pdve is set to logic 0, interrupt generation by pulse density violations is disabled.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 112 register 045h, 0c5h, 145h, 1c5h, 245h, 2c5h, 345h, 3c5h: t1 xpde interrupt enable/status bit type function default bit 7 r/w stufe 0 bit 6 r/w stuff 0 bit 5 r stufi x bit 4 r pdv x bit 3 r z16di x bit 2 r pdvi x bit 1 r/w z16de 0 bit 0 r/w pdve 0 when the e1/t1b bit of the global configuration register is a logic 1, this register is held reset. stufe: the stufe bit enables the occurrence of pulse stuffing to generate an interrupt on intb. when stufe is set to logic 1, an interrupt is generated on the occurrence of a bit stuff. when stufe is a logic 0, bit stuffing occurrences do not generate an interrupt on intb. stuff: the stuff bit enables pulse stuffing to occur upon detection of a violation of the pulse density rule. bit stuffing is performed in such a way that the resulting data stream no longer violates the pulse density rule. when stuff is set to logic 1, bit stuffing is enabled and the stufi bit indicates the occurrence of bit stuffs. when stuff is a logic 0, bit stuffing is disabled and the pdvi bit indicates occurrences of pulse density violation. also, when stuff is a logic 0, pcm data passes through xpde unaltered. stufi: the stufi bit is valid when pulse stuffing is active. this bit indicates when a bit stuff occurred to eliminate a pulse density violation and that an interrupt was generated due to the bit stuff (if stufe is logic 1). when pulse stuffing is active, pdvi remains logic 0, indicating that the stuffing has removed the density violation. the stufi bit is reset to logic 0 once this register is read. if the stufe bit is also logic 1, the interrupt is also cleared once this register is read. pdv: the pdv bit indicates the current state of the pulse density violation indication. when pdv is a logic 1, a violation of the pulse density rule exists. when pdv is a logic 0, no violation of the pulse density rule exists. note: the pdv indication persists for the duration of the pulse density violation. at its minimum, pdv may be asserted for only 1 bit time, therefore, reading
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 113 this bit may not return a logic 1 even though a pulse density violation has occurred. when the xpde is enabled for pulse stuffing, pdv remains logic 0. pdvi, z16di: the pdvi and z16di bits identify the source of a generated interrupt. pdvi is a logic 1 whenever a change in the pulse density violation indication generated an interrupt. pdvi is cleared to 0 when this register is read. z16di is a logic 1 whenever 16 consecutive zeros are detected. z16di is cleared to 0 when this register is read. note that the pdvi and z16di interrupt indications operate regardless of whether the corresponding interrupt enables are enabled or disabled. when stuff is set to logic 1, the pdvi and z16di bits are forced to logic 0. z16de: the z16de bit enables an interrupt to be generated on the microprocessor intb pin when 16 consecutive zeros are detected. when z16de is set to logic 1, interrupt is generation is enabled. when z16de is set to logic 0, interrupt generation is disabled. pdve: the pdve bit enables an interrupt to be generated on the microprocessor intb pin when a change in the pulse density is detected. when pdve is set to logic 1, an interrupt is generated whenever a pulse density violation occurs or when the pulse density ceases to exist (if stufe is logic 0). when pdve is set to logic 0, interrupt generation by pulse density violations is disabled.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 114 register 046h, 0c6h, 146h, 1c6h, 246h, 2c6h, 346h, 3c6h: t1 xibc control bit type function default bit 7 r/w en 0 bit 6 r/w reserved 0 bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w cl1 0 bit 0 r/w cl0 0 when the e1/t1b bit of the global configuration register is a logic 1, this register is held reset. en: the en bit controls whether the inband code is transmitted or not. a logic 1 in the en bit position enables transmission of inband codes; a logic 0 in the en bit position disables inband code transmission. reserved: the reserved bit must be set to 0 for correct operation of the octliu device. cl1, cl0: the bit positions cl1 and cl0 of this register indicate the length of the inband loopback code sequence, as follows: table 11 ? transmit in-band code length cl1 cl0 code length 00 5 01 6 10 7 11 8 codes of 3 or 4 bits in length may be accommodated by treating them as half of a double-sized code (i.e., a 3-bit code would use the 6-bit code length setting).
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 115 register 047h, 0c7h, 147h, 1c7h, 247h, 2c7h, 347h, 3c7h: t1 xibc loopback code bit type function default bit 7 r/w ibc7 x bit 6 r/w ibc6 x bit 5 r/w ibc5 x bit 4 r/w ibc4 x bit 3 r/w ibc3 x bit 2 r/w ibc2 x bit 1 r/w ibc1 x bit 0 r/w ibc0 x when the e1/t1b bit of the global configuration register is a logic 1, this register is held reset. this register contains the inband loopback code pattern to be transmitted. the code is transmitted most significant bit (ibc7) first, followed by ibc6 and so on. the code, regardless of the length, must be aligned with the msb always in the ibc7 position (e.g., a 5-bit code would occupy the ibc7 through ibc2 bit positions). to transmit a 3-bit or a 4-bit code pattern, the pattern must be paired to form a double-sized code (i.e., the 3-bit code ?011? would be written as the 6-bit code ?011011?). when the octliu is reset, the contents of this register are not affected.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 116 register 048h, 0c8h, 148h, 1c8h, 248h, 2c8h, 348h, 3c8h: rjat interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r ovri x bit 0 r undi x undi: the undi bit is asserted when an attempt is made to read data from the receive fifo when the fifo is already empty. when undi is a logic 1, an underrun event has occurred. reading this register will clear the undi bit to logic 0. ovri: the ovri bit is asserted when an attempt is made to write data into the receive fifo when the fifo is already full. when ovri is a logic 1, an overrun event has occurred. reading this register will clear the ovri bit to logic 0.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 117 register 049h, 0c9h, 149h, 1c9h, 249h, 2c9h, 349h, 3c9h: rjat reference clock divisor (n1) control bit type function default bit 7 r/w n1[7] 0 bit 6 r/w n1[6] 0 bit 5 r/w n1[5] 1 bit 4 r/w n1[4] 0 bit 3 r/w n1[3] 1 bit 2 r/w n1[2] 1 bit 1 r/w n1[1] 1 bit 0 r/w n1[0] 1 this register contains an 8-bit binary number, n1, which is one less than the magnitude of the reference clock divisor. the reference divisor magnitude, (n1+1), is the ratio between the frequency of the recovered clock (or the transmit clock if a diagnostic loopback is enabled) and the frequency at the phase discriminator input. writing to this register will reset the pll. if the fiforst bit of the rjat configuration register is set high, a write to this register will reset both the pll and fifo. the default value of n1 after a device reset is 47 = 2fh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 118 register 04ah, 0cah, 14ah, 1cah, 24ah, 2cah, 34ah, 3cah: rjat output clock divisor (n2) control bit type function default bit 7 r/w n2[7] 0 bit 6 r/w n2[6] 0 bit 5 r/w n2[5] 1 bit 4 r/w n2[4] 0 bit 3 r/w n2[3] 1 bit 2 r/w n2[2] 1 bit 1 r/w n2[1] 1 bit 0 r/w n2[0] 1 this register contains an 8-bit binary number, n2, which is one less than the magnitude of the output clock divisor. the output clock divisor magnitude, (n2+1), is the ratio between the frequency of the smooth output clock, rclk[n], and the frequency applied to the phase discriminator input. writing to this register will reset the pll. if the fiforst bit of the rjat configuration register is set high, a write to this register will reset both the pll and fifo. the default value of n2 after a device reset is 47 = 2fh. recommendations in general, the relationship n1 = n2 must always be true in order for the pll to operate correctly. in order to meet jitter transfer specifications for some modes, such as basic e1 operation, n1 and n2 must be large in order to reduce the pll transfer cutoff frequency. in general, for e1 operation, n2 is set to ffh to meet etsi jitter transfer specifications. for t1 mode, the recommended values are n1 = n2 = 2fh. for e1 mode, the recommended values are n1 = n2 = ffh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 119 register 04bh, 0cbh, 14bh, 1cbh, 24bh, 2cbh, 34bh, 3cbh: rjat configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w cent 0 bit 3 r/w unde 0 bit 2 r/w ovre 0 bit 1 r/w fiforst 0 bit 0 r/w limit 1 cent: the cent bit allows the fifo to self-center its read pointer, maintaining the pointer at least 4 ui away from the fifo being empty or full. when cent is set to logic 1, the fifo is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. if an empty or full alarm occurs during this 384 ui period, the period will be extended by the number of ui that the empty or full alarm persists. during the empty or full alarm conditions, data is lost. when cent is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during empty or full alarm conditions. the recommended value of cent is logic 1. unde: setting the unde bit to logic 1 enables an underrun event to assert the intb output low. ovre: setting the ovre bit to logic 1 enables an overrun event to assert the intb output low. fiforst: setting the fiforst bit allows the fifo to reset when the pll is reset by software. when fiforst is logic 1, writing to the pll divider control registers n1 and n2 will cause both the pll and fifo to reset. when fiforst is logic 0, writing to the divider control registers n1 and n2 will cause only the pll to reset. limit: setting the limit bit to logic 1 will limit the pll jitter attenuation by enabling the fifo to increase or decrease the frequency of the smooth output clock whenever the fifo is within one ui of overflowing or underflowing. this limiting of jitter ensures that no data is lost during
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 120 high phase shift conditions. when limit is set to logic 0, underflows and overflows may occur. the recommended value of limit is logic 0.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 121 register 04ch, 0cch, 14ch, 1cch, 24ch, 2cch, 34ch, 3cch: tjat interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r ovri x bit 0 r undi x undi: the undi bit is asserted when an attempt is made to read data from the transmit fifo when the fifo is already empty. when undi is a logic 1, an underrun event has occurred. reading this register will clear the undi bit to logic 0. ovri: the ovri bit is asserted when an attempt is made to write data into the transmit fifo when the fifo is already full. when ovri is a logic 1, an overrun event has occurred. reading this register will clear the ovri bit to logic 0.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 122 register 04dh, 0cdh, 14dh, 1cdh, 24dh, 2cdh, 34dh, 3cdh: tjat reference clock divisor (n1) control bit type function default bit 7 r/w n1[7] 0 bit 6 r/w n1[6] 0 bit 5 r/w n1[5] 1 bit 4 r/w n1[4] 0 bit 3 r/w n1[3] 1 bit 2 r/w n1[2] 1 bit 1 r/w n1[1] 1 bit 0 r/w n1[0] 1 this register contains an 8-bit binary number, n1, which is one less than the magnitude of the reference clock divisor. the reference divisor magnitude, (n1+1), is the ratio between the frequency of the reference clock (as selected by the pllref1 and pllref0 bits of the transmit line interface timing options register) and the frequency at the phase discriminator input. writing to this register will reset the pll. if the fiforst bit of the tjat configuration register is set high, a write to this register will reset both the pll and fifo. the default value of n1 after a device reset is 47 = 2fh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 123 register 04eh, 0ceh, 14eh, 1ceh, 24eh, 2ceh, 34eh, 3ceh: tjat output clock divisor (n2) control bit type function default bit 7 r/w n2[7] 0 bit 6 r/w n2[6] 0 bit 5 r/w n2[5] 1 bit 4 r/w n2[4] 0 bit 3 r/w n2[3] 1 bit 2 r/w n2[2] 1 bit 1 r/w n2[1] 1 bit 0 r/w n2[0] 1 this register contains an 8-bit binary number, n2, which is one less than the magnitude of the output clock divisor. the output clock divisor magnitude, (n2+1), is the ratio between the frequency of the smooth output clock and the frequency applied to the phase discriminator input. writing to this register will reset the pll. if the fiforst bit of the tjat configuration register is set high, a write to this register will reset both the pll and fifo. the default value of n2 after a device reset is 47 = 2fh. recommendations in general, the relationship n1 = n2 must always be true in order for the pll to operate correctly. in order to meet jitter transfer specifications for some modes, such as basic e1 operation, n1 and n2 must be large in order to reduce the pll transfer cutoff frequency. in general, for e1 operation, n2 is set to ffh to meet etsi jitter transfer specifications. for t1 mode, the recommended values are n1 = n2 = 2fh. for e1 mode, the recommended values are n1 = n2 = ffh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 124 register 04fh, 0cfh, 14fh, 1cfh, 24fh, 2cfh, 34fh, 3cfh: tjat configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w cent 0 bit 3 r/w unde 0 bit 2 r/w ovre 0 bit 1 r/w fiforst 0 bit 0 r/w limit 1 cent: the cent bit allows the fifo to self-center its read pointer, maintaining the pointer at least 4 ui away from the fifo being empty or full. when cent is set to logic 1, the fifo is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. if an empty or full alarm occurs during this 384 ui period, the period will be extended by the number of ui that the empty or full alarm persists. during the empty or full alarm conditions, data is lost. when cent is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during empty or full alarm conditions. the recommended value of cent is logic 1. unde: setting the unde bit to logic 1 enables an underrun event to assert the intb output low. ovre: setting the ovre bit to logic 1 enables an overrun event to assert the intb output low. fiforst: setting the fiforst bit allows the fifo to reset when the pll is reset by software. when fiforst is logic 1, writing to the pll divider control registers n1 and n2 will cause both the pll and fifo to reset. when fiforst is logic 0, writing to the divider control registers n1 and n2 will cause only the pll to reset. limit: setting the limit bit to logic 1 will limit the pll jitter attenuation by enabling the fifo to increase or decrease the frequency of the smooth output clock whenever the fifo is within one ui of overflowing or underflowing. this limiting of jitter ensures that no data is lost during
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 125 high phase shift conditions. when limit is set to logic 0, underflows and overflows may occur. the recommended value of limit is logic 0.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 126 register 050h, 0d0h, 150h, 1d0h, 250h, 2d0h, 350h, 3d0h: ibcd configuration bit type function default bit 7 r/w reserved 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w dsel1 0 bit 2 r/w dsel0 0 bit 1 r/w asel1 0 bit 0 r/w asel0 0 when the e1/t1b bit of the global configuration register is a logic 1, this register is held reset. this register provides the selection of the activate and de-activate loopback code lengths (from 3 bits to 8 bits) as follows: table 12 ? loopback code configurations deactivate code activate code dsel1 dsel0 asel1 asel0 code length 0 0 0 0 5 bits 0 1 0 1 6 (or 3*) bits 1 0 1 0 7 bits 1 1 1 1 8 (or 4*) bits note: 3-bit and 4-bit code sequences can be accommodated by configuring the ibcd for 6 or 8 bits and by programming two repetitions of the code sequence. the reserved bit is used for production test purposes only. the reserved bit must be logic 0 for normal operation.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 127 register 051h, 0d1h, 151h, 1d1h, 251h, 2d1h, 351h, 3d1h: ibcd interrupt enable/status bit type function default bit 7 r lbacp x bit 6 r lbdcp x bit 5 r/w lbae 0 bit 4 r/w lbde 0 bit 3 r lbai x bit 2 r lbdi x bit 1 r lba x bit 0 r lbd x when the e1/t1b bit of the global configuration register is a logic 1, this register is held reset. lbacp, lbdcp: the lbacp and lbdcp bits indicate when the corresponding loopback code is present during a 39.8 ms interval. lbae: the lbae bit enables the assertion or deassertion of the inband loopback activate (lba) detect indication to generate an interrupt on the microprocessor intb pin. when lbae is set to logic 1, any change in the state of the lba detect indication generates an interrupt. when lbae is set to logic 0, no interrupt is generated by changes in the lba detect state. lbde: the lbde bit enables the assertion or deassertion of the inband loopback deactivate (lbd) detect indication to generate an interrupt on the microprocessor intb pin. when lbde is set to logic 1, any change in the state of the lbd detect indication generates an interrupt. when lbde is set to logic 0, no interrupt is generated by changes in the lbd detect state. lbai, lbdi: the lbai and lbdi bits indicate which of the two expected loopback codes generated the interrupt when their state changed. a logic 1 in these bit positions indicates that a state change in that code has generated an interrupt; a logic 0 in these bit positions indicates that no state change has occurred. after the enable/status register has been read, the lbai and lbdi bits are set to logic 0. lba, lbd: the lba and lbd bits indicate the current state of the corresponding loopback code detect indication. a logic 1 in these bit positions indicates the presence of that code has been detected; a logic 0 in these bit positions indicates the absence of that code.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 128 register 052h, 0d2h, 152h, 1d2h, 252h, 2d2h, 352h, 3d2h: ibcd activate code bit type function default bit 7 r/w act7 0 bit 6 r/w act6 0 bit 5 r/w act5 0 bit 4 r/w act4 0 bit 3 r/w act3 0 bit 2 r/w act2 0 bit 1 r/w act1 0 bit 0 r/w act0 0 when the e1/t1b bit of the global configuration register is a logic 1, this register is held reset. this 8-bit register selects the activate code sequence that is to be detected. if the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8-bit register. for example, if code sequence is a repeating 00001, the first 8 bits of two repetitions (0000100001) is programmed into the register, i.e.00001000. note that bit act7 corresponds to the first code bit received.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 129 register 053h, 0d3h, 153h, 1d3h, 253h, 2d3h, 353h, 3d3h: ibcd deactivate code bit type function default bit 7 r/w dact7 0 bit 6 r/w dact6 0 bit 5 r/w dact5 0 bit 4 r/w dact4 0 bit 3 r/w dact3 0 bit 2 r/w dact2 0 bit 1 r/w dact1 0 bit 0 r/w dact0 0 when the e1/t1b bit of the global configuration register is a logic 1, this register is held reset. this 8-bit register selects the deactivate code sequence that is to be detected. if the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8-bit register. for example, if code sequence is a repeating 001, the first 8 bits of three repetitions (001001001) is programmed into the register, i.e.00100100. note that bit dact7 corresponds to the first code bit received.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 130 register 054h, 0d4h, 154h, 1d4h, 254h, 2d4h, 354h, 3d4h: cdrc configuration bit type function default bit 7 r/w ami 0 bit 6 r/w los[1] 0 bit 5 r/w los[0] 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w algsel 0 bit 1 r/w o162 0 bit 0 r/w reserved 0 reserved: these bits must be a logic 0 for correct operation. o162: if the ami bit is logic 0 in e1 mode, the recommendation o.162 compatibility select bit (o162) allows selection between two line code violation definitions: if o162 is a logic 0, a line code violation is indicated if the serial stream does not match the verbatim hdb3 definition given in recommendation g.703. a bipolar violation that is not part of an hdb3 signature or a bipolar violation in an hdb3 signature that is the same polarity as the last bipolar violation results in a line code violation indication. if o162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same polarity as the last bipolar violation, as per recommendation o.162. the o162 bit has no effect in t1 mode. algsel: the algorithm select (algsel) bit specifies the algorithm used by the dpll for clock and data recovery. the choice of algorithm determines the high frequency input jitter tolerance of the cdrc. when algsel is set to logic 1, the cdrc jitter tolerance is increased to approach 0.5 uipp for jitter frequencies above 20 khz. when algsel is set to logic 0, the jitter tolerance is increased for frequencies below 20 khz (i.e. the tolerance is improved by 20% over that of algsel=1 at these frequencies), but the tolerance approaches 0.4 uipp at the higher frequencies. ami: the alternate mark inversion (ami) bit specifies the line coding of the incoming signal. a logic 1 selects ami line coding by disabling hdb3 decoding in e1 mode and b8zs in t1 mode. in e1 mode, a logic 0 selects hdb3 line decoding which entails substituting an hdb3
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 131 signature with four zeros. in t1 mode, a logic 0 selects b8zs line decoding which entails substituting an b8zs signature with eight zeros. los[1:0]: the loss of signal threshold is set by the operating mode and the state of the ami, los[1] and los[0] bits: table 13 ? loss of signal thresholds mode ami los[1] los[0] threshold (pcm periods) e100010 t100015 x10015 xx0131 xx1063 x x 1 1 175 when the number of consecutive zeros on the incoming pcm line exceeds the programmed threshold, the losv status bit is set. for example, if the threshold is set to 10, the 11th zero causes the losv bit to be set.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 132 register 055h, 0d5h, 155h, 1d5h, 255h, 2d5h, 355h, 3d5h: cdrc interrupt control bit type function default bit 7 r/w lcve 0 bit 6 r/w lose 0 bit 5 r/w lcsde 0 bit 4 r/w znde 0 bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x the bit positions lcve, lose, lcsde and znde (bits 7 to 4) of this register are interrupt enables to select which of the status events (line code violation , loss of signal, hdb3 signature, b8zs signature or n zeros), either singly or in combination, are enabled to generate an interrupt on the microprocessor intb pin when they are detected. a logic 1 bit in the corresponding bit position enables the detection of these signals to generate an interrupt; a logic 0 bit in the corresponding bit position disables that signal from generating an interrupt.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 133 register 056h, 0d6h, 156h, 1d6h, 256h, 2d6h, 356h, 3d6h: cdrc interrupt status bit type function default bit 7 r lcvi x bit 6 r losi x bit 5 r lcsdi x bit 4 r zndi x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r losv x the zndi, lcsdi, losi and lcvi (bits 4 to 7) of this register indicate which of the status events have occurred since the last time this register was read. a logic 1 in any of these bit positions indicates that the corresponding event was detected. bits zndi, lcsdi, losi and lcvi are cleared to logic 0 by reading this register. losv: the losv bit reflects the status of the los alarm. zndi: the consecutive zeros detection interrupt (zndi) indicates that n consecutive spaces have occurred, where n is four for e1 and eight for t1. this bit can be used to detect an ami coded signal. lcsdi: the line code signature detection interrupt (lcsdi) indicates that a valid line code signature has occurred. in t1 mode, the b8zs signature is defined as 000+-0-+ if the previous impulse is positive, or 000-+0+- if it is negative. in e1 mode, a valid hdb3 signature is defined as a bipolar violation preceded by two zeros. this bit can be used to detect an hdb3 coded signal in e1 mode and b8zs coded signal in t1. losi: the losi bit is set to a logic 1 when the losv bit changes state. lcvi: the line code violation interrupt (lcvi) indicates a series of marks and spaces has occurred in contradiction to the defined line code (ami, b8zs or hdb3).
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 134 register 057h, 0d7h, 157h, 1d7h, 257h, 2d7h, 357h, 3d7h: cdrc alternate loss of signal status bit type function default bit 7 r/w altlose 0 bit 6 r altlosi x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r altlosv x the alternate loss of signal status provides a more stringent criteria for the deassertion of the alarm than the los indication in the cdrc interrupt status register. altlose: if the altlose bit is a logic 1, the intb output is asserted low when the altlosv status bit changes state. altlosi: the altlosi bit is set high when the altlosv status bit changes state. it is cleared when this register is read. altlosv: the altlosv bit is asserted upon the absence of marks for the threshold of bit periods specified by the los[1:0] register bits. the altlosv bit is deasserted only after pulse density requirements have been met. in t1 mode, there must be n ones in each and every time window of 8(n+1) data bits (where n can equal 1 through 23). in e1 mode, altlosv is deasserted only after 255 bit periods during which no sequence of four zeros has been received.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 135 register 058h, 0d8h, 158h, 1d8h, 258h, 2d8h, 358h, 3d8h: pmon interrupt enable/status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w inte 0 bit 1 r xfer 0 bit 0 unused x this register contains status information indicating when counter data has been transferred into the holding registers and indicating whether the holding registers have been overrun. inte: the inte bit controls the generation of a microprocessor interrupt when the transfer clock has caused the counter values to be stored in the holding registers. a logic 1 bit in the inte position enables the generation of an interrupt via the intb output; a logic 0 bit in the inte position disables the generation of an interrupt. xfer: the xfer bit indicates that a transfer of counter data has occurred. a logic 1 in this bit position indicates that a latch request, initiated by writing to one of the counter register locations or the octant pmon update register, was received and a transfer of the counter values has occurred. a logic 0 indicates that no transfer has occurred. the xfer bit is cleared (acknowledged) by reading this register.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 136 register 05eh, 0deh, 15eh, 1deh, 25eh, 2deh, 35eh, 3deh: pmon lcv count (lsb) bit type function default bit 7 r lcv[7] x bit 6 r lcv[6] x bit 5 r lcv[5] x bit 4 r lcv[4] x bit 3 r lcv[3] x bit 2 r lcv[2] x bit 1 r lcv[1] x bit 0 r lcv[0] x
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 137 register 05fh, 0dfh, 15fh, 1dfh, 25fh, 2dfh, 35fh, 3dfh: pmon lcv count (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r lcv[12] x bit 3 r lcv[11] x bit 2 r lcv[10] x bit 1 r lcv[9] x bit 0 r lcv[8] x lcv[12:0]: the lcv[12:0] bits indicate the number of lcv error events that occurred during the previous accumulation interval. an lcv event is defined as the occurrence of a bipolar violation or excessive zeros. the counting of excessive zeros can be disabled by the bpv bit of the receive line interface configuration #1 register. the lcv count registers for a octant are updated by writing to the pmon lcv count (lsb) register. a write to this location loads count data located in the pmon into the internal holding registers. alternatively, the lcv count registers for the octant are updated by writing to the line interface interrupt source #1 / pmon update register. the data contained in the holding registers can then be subsequently read by microprocessor accesses into the pmon count register address space. the latching of count data, and subsequent resetting of the counters, is synchronized to the internal event timing so that no events are missed. the pmon is loaded with new count data within 3.5 recovered clock periods of the triggering register write. with nominal line rates, the pmon registers should not be polled until 2.3 sec have elapsed from the triggering register write. when the octliu is reset, the contents of the pmon count registers are unknown until the first latching of performance data is performed.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 138 register 060h, 0e0h, 160h, 1e0h, 260h, 2e0h, 360h, 3e0h: prbs generator/checker control bit type function default bit 7 unused x bit 6 unused x bit 5 r/w qrss 0 bit 4 unused x bit 3 r/w tinv 0 bit 2 r/w rinv 0 bit 1 r/w autosync 1 bit 0 r/w mansync 0 qrss: the quasi-random signal source (qrss) bit enables the zero suppression feature required when generating a qrss sequence. when qrss is a logic 1, a one is forced in the generated prbs stream when the following 14 bit positions are all zeros. when qrss is a logic 0, the zero suppression feature is disabled. note that in order to generate the at&t tr 62411 qrss sequence, or the 2 20 -1 sequence as specified in itu-t o.151, the patsel[1:0] field in the prbs pattern select register must be set to ?01? and qrss set to 1. tinv: the tinv bit controls the logical inversion of the generated data stream. when tinv is a logic 1, the data is inverted. when tinv is a logic 0, the data is not inverted. rinv: the rinv bit controls the logical inversion of the received stream before processing. when rinv is a logic 1, the received data is inverted before being processed by the pattern detector. when rinv is a logic 0, the data is not inverted autosync: the autosync bit enables the automatic resynchronization of the pattern detector. the automatic resynchronization is activated when 10 or more bit errors are detected in a fixed 48-bit window. when autosync is a logic 1, the auto resync feature is enabled. when autosync is a logic 0, the auto sync feature is disabled, and pattern resynchronization is accomplished using the mansync bit.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 139 mansync: the mansync bit is used to initiate a manual resynchronization of the pattern detector. a low to high transition on mansync initiates the resynchronization.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 140 register 061h, 0e1h, 161h, 1e1h, 261h, 2e1h, 361h, 3e1h: prbs checker interrupt enable/status bit type function default bit 7 r/w synce 0 bit 6 r/w bee 0 bit 5 r/w xfere 0 bit 4 r syncv x bit 3 r synci x bit 2 r bei x bit 1 r xferi x bit 0 unused x synce: the synce bit enables the generation of an interrupt when the prbs checker changes synchronization state. when synce is set to logic 1, the interrupt is enabled. bee: the bee bit enables the generation of an interrupt when a bit error is detected in the receive data. when bee is set to logic 1, the interrupt is enabled. xfere: the xfere bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the error counter holding registers. when xfere is set to logic 1, the interrupt is enabled. syncv: the syncv bit indicates the synchronization state of the prbs checker. when syncv is a logic 1 the prbs checker is synchronized (the prbs checker has observed at least 32 consecutive error free bit periods). when syncv is a logic 0, the prbs checker is out of sync (the prbs checker has detected 6 or more bit errors in a 64 bit period window). synci: the synci bit indicates that the detector has changed synchronization state since the last time this register was read. if synci is logic 1, the pattern detector has gained or lost synchronization at least once. synci is set to logic 0 when this register is read.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 141 bei: the bei bit indicates that one or more bit errors have been detected since the last time this register was read. when bei is set to logic 1, at least one bit error has been detected. bei is set to logic 0 when this register is read. xferi: the xferi bit indicates that a transfer of the error count has occurred. a logic 1 in this bit position indicates that the error counter holding registers has been updated. this update is initiated by writing to one of the prbs error count register locations, or by writing to the line interface interrupt source #1 / pmon update register. xferi is set to logic 0 when this register is read.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 142 register 062h, 0e2h, 162h, 1e2h, 262h, 2e2h, 362h, 3e2h: prbs pattern select bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w patsel[1] 0 bit 0 r/w patsel[0] 0 patsel[1:0]: patsel[1:0] determines which of the three prbs patterns are generated and checked for errors. patsel[1:0] pattern 00 2 15 -1 01 2 20 -1 10 2 11 -1 11 reserved
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 143 register 064h, 0e4h, 164h, 1e4h, 264h, 2e4h, 364h, 3e4h: prbs error count #1 bit type function default bit 7 r errcnt[7] x bit 6 r errcnt[6] x bit 5 r errcnt[5] x bit 4 r errcnt[4] x bit 3 r errcnt[3] x bit 2 r errcnt[2] x bit 1 r errcnt[1] x bit 0 r errcnt[0] x
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 144 register 065h, 0e5h, 165h, 1e5h, 265h, 2e5h, 365h, 3e5h: prbs error count #2 bit type function default bit 7 r errcnt[15] x bit 6 r errcnt[14] x bit 5 r errcnt[13] x bit 4 r errcnt[12] x bit 3 r errcnt[11] x bit 2 r errcnt[10] x bit 1 r errcnt[9] x bit 0 r errcnt[8] x
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 145 register 066h, 0e6h, 166h, 1e6h, 266h, 2e6h, 366h, 3e6h: prbs error count #3 bit type function default bit 7 r errcnt[23] x bit 6 r errcnt[22] x bit 5 r errcnt[21] x bit 4 r errcnt[20] x bit 3 r errcnt[19] x bit 2 r errcnt[18] x bit 1 r errcnt[17] x bit 0 r errcnt[16] x errcnt[23:0]: errcnt[23:0] contain the error counter holding register. the value in this register represents the number of bit errors that have been accumulated since the last accumulation interval, up to a maximum (saturation) value of 2 24 -1. note that bit errors are not accumulated while the pattern detector is out of sync. the error count registers for each individual prbs generator/checker are updated by writing to any one of the error count registers. alternatively, the error count registers are updated with all other octant counter registers by writing to the line interface interrupt source #1 / pmon update register.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 146 register 068h, 0e8h, 168h, 1e8h, 268h, 2e8h, 368h, 3e8h: xlpg control/status bit type function default bit 7 r/w highz 1 bit 6 r/w arst 0 bit 5 unused x bit 4 r/w initram 0 bit 3 r ovrflw x bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 1 highz: the highz bit controls tristating of the txtip[x] and txring[x] outputs. when the highz bit is set to a logic 0, the outputs are enabled. when the highz bit is set to a logic 1, the outputs are put into high impedance. setting highz to logic 1 has the same effect as setting scale[4:0] to 00h. arst: the analogue reset bit (arst) resets the analogue portion of the xlpg (without affecting the digital portion) when set to logic 1. initram: the waveform storage ram initialisation bit (initram) causes the xplg waveform storage ram to be initialised to 12 standard waveform patterns when set to logic 1. this bit remains at logic 1 while the initialisation is in progress and is cleared to logic 0 when the initialisation has completed. the 12 waveform patterns to which the ram is initialised are listed in table 20 thru table 29, table 37 and table 38. ovrflw: the overflow detection value bit (ovrflw) indicates the presence or absence of an overflow condition in the waveform computation pipeline. an overflow occurs when the sum of the five unit interval (ui) samples exceeds the maximum d/a value. the xlpg detects overflows and saturates the output value to minimize their impact on the output signal. overflows can easily be eliminated by changing the waveform programming. this status bit is set to logic 1 when an overflow condition is detected and it is reset to logic 0 only when this register is read. it is suggested that this register be read twice after the programming of a new waveform and transmission of data to ensure the maximum output amplitude is never exceeded.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 147 reserved: the reserved bits must remain in their default state for correct operation.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 148 register 069h, 0e9h, 169h, 1e9h, 269h, 2e9h, 369h, 3e9h: xlpg pulse waveform scale bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w scale[4] 0 bit 3 r/w scale[3] 0 bit 2 r/w scale[2] 0 bit 1 r/w scale[1] 0 bit 0 r/w scale[0] 0 scale[4:0]: the scale[4:0] bits specify a scaling factor to be applied to the amplitude of the d/a output waveform. each of the 12 waveforms stored in the xlpg?s pulse template ram may have a different scaling factor. when a particular waveform is selected for use (by the pt_sel[3:0] register bits or lenx[2:0] inputs), the scaling factor corresponding to that waveform is chosen automatically. when this register is written to, the value of scale[4:0] is stored in one of 12 storage locations indexed by the waveform[3:0] bits of the pulse waveform storage write address #2 register. thus to set up scaling factors for more than one waveform, this register should be written to a number of times, with waveform[3:0] set to the different waveform numbers, as appropriate. the scale[4:0] bits scale the maximum output amplitude by increments of 11.14 ma. a value of 0 (00h) tristates the output while the maximum value of 21 (15h) sets the full scale current to 234 ma. table 14 ? transmit output amplitude scale[4:0] decimal equiv. output amplitude 00000 0 0 ma (tristate) 00001-10100 1-20 increments of 11.14 ma for each scale step 10101 21 234 ma total 10110-11111 >21 reserved
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 149 register 06ah, 0eah, 16ah, 1eah, 26ah, 2eah, 36ah, 3eah: xlpg pulse waveform storage write address #1 bit type function default bit 7 r/w sample[4] 0 bit 6 r/w sample[3] 0 bit 5 r/w sample[2] 0 bit 4 r/w sample[1] 0 bit 3 r/w sample[0] 0 bit 2 r/w ui[2] 0 bit 1 r/w ui[1] 0 bit 0 r/w ui[0] 0 ui[2:0]: the pulse waveform write address is composed of a unit interval selector, a sample selector and a waveform number. the unit interval selector (ui[2:0]) specifies the unit interval portion of the address. there are 5 unit intervals, numbered from 0 to 4. ui[2:0] can take the values 0h, 1h, 2h, 3h and 4h. the values 5h, 6h and 7h are undefined. sample[4:0]: the pulse waveform write address is composed of a unit interval selector, a sample selector and a waveform number. the sample selector (sample[4:0]) specifies the sample portion of the address. there are 24 samples, numbered from 0 to 23. sample[4:0] can thus have any value from 00h to 17h. the values from 18h to 1fh are undefined. note ? the pulse waveform storage write indirect address registers #1 and #2 must be written to before the pulse waveform storage data register. in addition, waveform samples must be written in groups of 5. within each group of 5 writes, the waveform number and sample selector must remain constant and the unit interval selector must be set to 0x0, 0x1, 0x2, 0x3 and 0x4 in sequence. see the operation section for more details on setting up waveform templates.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 150 register 06bh, 0ebh, 16bh, 1ebh, 26bh, 2ebh, 36bh, 3ebh: xlpg pulse waveform storage write address #2 bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w waveform[3] 0 bit 2 r/w waveform[2] 0 bit 1 r/w waveform[1] 0 bit 0 r/w waveform[0] 0 waveform[3:0]: the pulse waveform write address is composed of a unit interval selector, a sample selector and a waveform number. the waveform number (waveform[3:0]) specifies the waveform portion of the address. there are 12 waveforms, numbered from 0 to 11. waveform[3:0] can thus have any value from 0h to bh. the values from ch to fh are undefined. note ? the pulse waveform storage write indirect address registers #1 and #2 must be written to before the pulse waveform storage data register. in addition, waveform samples must be written in groups of 5. within each group of 5 writes, the waveform number and sample selector must remain constant and the unit interval selector must be set to 0x0, 0x1, 0x2, 0x3 and 0x4 in sequence. see the operation section for more details on setting up waveform templates.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 151 register 06ch, 0ech, 16ch, 1ech, 26ch, 2ech, 36ch, 3ech: xlpg pulse waveform storage data bit type function default bit 7 unused x bit 6 w wdat[6] x bit 5 w wdat[5] x bit 4 w wdat[4] x bit 3 w wdat[3] x bit 2 w wdat[2] x bit 1 w wdat[1] x bit 0 w wdat[0] x wdat[6:0]: the wdat[6:0] bits contain the write data to be stored in the pulse template ram, as addressed by the ui[2:0], sample[4:0] and waveform[3:0] bits in the pulse waveform storage write address registers. when writing to the ram, the address must first be written to the pulse waveform storage write address registers. writing to the pulse waveform storage data register triggers the transfer of data. if the ui portion of the address is 0, 1, 2 or 3, wdat[6:0] are transferred to internal holding registers. if the ui portion of the address is 4, wdat[6:0] are combined with the contents of the holding registers to form a 35-bit long word which is then stored in the pulse template ram. waveform samples must therefore be written in groups of 5 and within each group of 5 writes, the waveform number and sample selector must remain constant and the unit interval selector must be set to 0x0, 0x1, 0x2, 0x3 and 0x4 in sequence. wdat[6:0] are coded in signed magnitude representation. wdat[6] is the sign bit, wdat[5] is the most significant data bit and wdat[0] is the least significant data bit. the data values thus can range from ?63 to +63. see the operation section for more details on setting up custom waveform templates.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 152 register 070h, 0f0h, 170h, 1f0h, 270h, 2f0h, 370h, 3f0h: rlps configuration and status bit type function default bit 7 r alosi x bit 6 r alosv x bit 5 r/w alose 0 bit 4 r/w squelche 0 bit 3 r/w iddq_en 0 bit 2 r db_valid x bit 1 unused x bit 0 r/w reserved 1 reserved: the reserved bit must be logic 1 for correct operation. db_valid: the db_valid bit indicates if the adaptive equalizer has stabilized. this bit is set if the equalisation has not changed by more than 2db (or +/-8 steps in the ram table) in more than a selectable count of sampling periods. iddq_en: the iddq enable bit (iddq_en) is used to configure the analogue receiver for iddq tests. when iddq_en is a logic 1, or the iddqen bit in the master test control #1 register (004h) is a logic 1, the digital outputs of the analogue receiver are pulled to ground. squelche: the output data squelch enable (squelche) allows control of data squelching in response to an analogue loss of signal (alos) condition. when squelche is set to logic 1, the recovered data are forced to all-zeros if the alosv register bit is asserted. when squelche is set to logic 0, squelching is disabled. alose: the loss of signal interrupt enable bit (alose) enables the generation of device level interrupt on a change of loss of signal status. when alose is a logic 1, an interrupt is generated by asserting intb low when there is a change of the alosv status. when alose is set to logic 0, interrupts are disabled. alosv: the loss of signal value bit (alosv) indicates the loss of signal alarm state.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 153 alosi: the loss of signal interrupt bit (alosi) is a logic 1 whenever the loss of signal indicator state (alosv) changes. this bit is cleared when this register is read.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 154 register 071h, 0f1h, 171h, 1f1h, 271h, 2f1h, 371h, 3f1h: rlps alos detection/clearance threshold bit type function default bit 7 r/w clr_thr[3] 0 bit 6 r/w clr_thr[2] 0 bit 5 r/w clr_thr[1] 0 bit 4 r/w clr_thr[0] 0 bit 3 r/w det_thr[3] 0 bit 2 r/w det_thr[2] 0 bit 1 r/w det_thr[1] 0 bit 0 r/w det_thr[0] 0 table 15 ? alos detection/clearance thresholds thr signal level (db) applicable standard detection/clearance 0000 8 0001 9 0010 10 g.775(e1) clearance (if <= 9db) 0011 11 0100 20 0101 21 i.431 (e1) etsi 300 233 detection (if > 20db) and clearance 0110 22 0111 30 1000 31 i.431 (t1) detection (if > 30db) and clearance 1001 32 1010 33 1011 34 1100 35 g.775 (e1) detection (if >= 35db) 1101 36 1110 37 1111 38
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 155 det_thr[3:0]: det_thr[3:0] references one of the threshold settings in table 15 as the alos detection criteria. if the equalised cable loss is greater than or equal to the threshold for n consecutive pulse periods, where n = 16 * det_per stored in the rlps alos detection period register, alos is declared and interrupt set. clr_thr[3:0]: clr_thr[3:0] references one of the threshold settings listed in table 15 as the alos clearance criteria. alos is cleared when the equalised cable loss is less than the threshold for n consecutive pulse intervals, where n = 16 * clr_per stored in the rlps alos clearance period register.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 156 register 072h, 0f2h, 172h, 1f2h, 272h, 2f2h, 372h, 3f2h: rlps alos detection period bit type function default bit 7 r/w det_per[7] 0 bit 6 r/w det_per[6] 0 bit 5 r/w det_per[5] 0 bit 4 r/w det_per[4] 0 bit 3 r/w det_per[3] 0 bit 2 r/w det_per[2] 0 bit 1 r/w det_per[1] 0 bit 0 r/w det_per[0] 1 det_per[7:0]: this register specifies the time duration that the equalised cable loss has to remain above the detection threshold in order for the alos to be issued. this duration is equal to det_per * 16 number of pulse intervals, the resulting range is from 16 to 4080 and thus compliant with all the presently available e1/t1 alos detection standards/recommendations.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 157 register 073h, 0f3h, 173h, 1f3h, 273h, 2f3h, 373h, 3f3h: rlps alos clearance period bit type function default bit 7 r/w clr_per[7] 0 bit 6 r/w clr_per[6] 0 bit 5 r/w clr_per[5] 0 bit 4 r/w clr_per[4] 0 bit 3 r/w clr_per[3] 0 bit 2 r/w clr_per[2] 0 bit 1 r/w clr_per[1] 0 bit 0 r/w clr_per[0] 1 clr_per[7:0]: this register specifies the time duration that the equalised cable loss has to remain below the clearance threshold in order for the alos to be cleared. this duration is equal to clr_per * 16 number of pulse intervals resulting in a range from 16 to 4080 and thus compliant with all the presently available e1/t1 alos clearance standards/ recommendations.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 158 register 074h, 0f4h, 174h, 1f4h, 274h, 2f4h, 374h, 3f4h: rlps equalization indirect address bit type function default bit 7 r/w eq_addr[7] 0 bit 6 r/w eq_addr[6] 0 bit 5 r/w eq_addr[5] 0 bit 4 r/w eq_addr[4] 0 bit 3 r/w eq_addr[3] 0 bit 2 r/w eq_addr[2] 0 bit 1 r/w eq_addr[1] 0 bit 0 r/w eq_addr[0] 0 eq_addr [7:0]: writing to this register initiates an internal up access request cycle to the ram. depending on the setting of the rwb bit inside the rlps equalization read/writeb select, a read or a write will be performed. during a write cycle, the indirect data bits located in the rlps equalization indirect data registers are written into the ram. for a read request, the content of the addressed ram location is written into the rlps equalization indirect data registers. this register should be the last register to be written for a up access. a waiting period of at least three line rate cycles is needed from when this register is written until the next indirect data bits are written into any of the respective octant?s rlps equalization indirect data registers.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 159 register 075h, 0f5h, 175h, 1f5h, 275h, 2f5h, 375h, 3f5h: rlps equalization read/writeb select bit type function default bit 7 r/w rwb 1 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x rw b: this bit selects the operation to be performed on the ram: when rwb is ?1?, a read from the equalization ram is requested; when rwb is set to ?0?, a write to the ram is desired.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 160 register 076h, 0f6h, 176h, 1f6h, 276h, 2f6h, 376h, 3f6h: rlps equalizer loop status and control bit type function default bit 7 r/w location[7] 0 bit 6 r/w location[6] 0 bit 5 r/w location[5] 0 bit 4 r/w location[4] 0 bit 3 r/w location[3] 0 bit 2 r/w location[2] 0 bit 1 r/w location[1] 0 bit 0 r/w location[0] 0 location[7:0]: writing to this register overwrites a counter which serves as the read address to the equalization ram. reading this register returns the current value of the counter and thus an indication of the cable loss as estimated by the equaliser.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 161 register 077h, 0f7h, 177h, 1f7h, 277h, 2f7h, 377h, 3f7h: rlps equalizer configuration bit type function default bit 7 r/w valid_per[1] 0 bit 6 r/w valid_per[0] 0 bit 5 unused x bit 4 r/w reserved 0 bit 3 r/w eq_en 0 bit 2 r/w eq_freq[2] 0 bit 1 r/w eq_freq[1] 1 bit 0 r/w eq_freq[0] 1 eq_freq[2:0]: the eq_freq[2:0] field selects the frequency of the eq feedback loop as indicated by table 16. table 16 ? equalization feedback frequencies eq feedback frequency eq_freq[2:0] t1 mode e1 mode how frequency derived 000 24.125 khz 32.000 khz line rate 64 001 12.063 khz 16.000 khz line rate 128 010 8.0417 khz 10.667 khz line rate 192 011 6.0313 khz 8.0000 khz line rate 256 100 4.8250 khz 6.40 khz line rate 320 101 4.0208 khz 5.333 khz line rate 384 110 3.4464 khz 4.5714 khz line rate 448 111 3.0156 khz 4.0 khz line rate 512 eq_en: the eq_en bit enables operation of the equaliser when set to logic 1. this bit defaults to logic 0 after reset and must be set to logic 1, but only after the equalisation ram has been initialised. reserved: this bit must be programmed to logic 0 for normal operation.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 162 valid_per[1:0]: the valid_per[1:0] bits select the length of time that the db loss counter must be stable before db_valid is asserted. the duration is measured in number of periods of the eq feedback loop (specified by the eq_freq bits) as indicated by table 17. table 17 ? valid period valid_per number of periods 00 32 01 64 10 128 11 256
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 163 register 078h, 0f8h, 178h, 1f8h, 278h, 2f8h, 378h, 3f8h: rlps equalization indirect data bit type function default 7 r/w eq_data[31] 0 6 r/w eq_data[30] 0 5 r/w eq_data[29] 0 4 r/w eq_data[28] 0 3 r/w eq_data[27] 0 2 r/w eq_data[26] 0 1 r/w eq_data[25] 0 0 r/w eq_data[24] 0 eq_data[31:24]: this register consists of 2-parts: read-only and write-only. writing this register affects the most significant byte of the input-data to the equalization ram. reading it returns the msb of the ram location indexed by the rlps equalization indirect address register.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 164 register 079h, 0f9h, 179h, 1f9h, 279h, 2f9h, 379h, 3f9h: rlps equalization indirect data bit type function default 7 r/w eq_data[23] 0 6 r/w eq_data[22] 0 5 r/w eq_data[21] 0 4 r/w eq_data[20] 0 3 r/w eq_data[19] 0 2 r/w eq_data[18] 0 1 r/w eq_data[17] 0 0 r/w eq_data[16] 0 eq_data[23:16]: this register consists of 2-parts: read-only and write-only. writing this register affects the second most significant byte of the input-data to the equalization ram. reading it returns the second msb of the ram location indexed by the rlps equalization indirect address register.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 165 register 07ah, 0fah, 17ah, 1fah, 27ah, 2fah, 37ah, 3fah: rlps equalization indirect data bit type function default 7 r/w eq_data[15] 0 6 r/w eq_data[14] 0 5 r/w eq_data[13] 0 4 r/w eq_data[12] 0 3 r/w eq_data[11] 0 2 r/w eq_data[10] 0 1 r/w eq_data[9] 0 0 r/w eq_data[8] 0 eq_data[15:8]: this register consists of 2-parts: read-only and write-only. writing this register affects the second least significant byte of the input-data to the equalization ram. reading it returns the corresponding bits of the ram location indexed by the rlps equalization indirect address register.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 166 register 07bh, 0fbh, 17bh, 1fbh, 27bh, 2fbh, 37bh, 3fbh: rlps equalization indirect data bit type function default 7 r/w eq_data[7] 0 6 r/w eq_data[6] 0 5 r/w eq_data[5] 0 4 r/w eq_data[4] 0 3 r/w eq_data[3] 0 2 r/w eq_data[2] 0 1 r/w eq_data[1] 0 0 r/w eq_data[0] 0 eq_data[7:0]: this register consists of 2-parts: read-only and write-only. writing this register affects the least significant byte of the input-data to the equalization ram. reading it returns the lsb of the ram location indexed by the rlps equalization indirect address register.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 167 register 07ch, 0fch, 17ch, 1fch, 27ch, 2fch, 37ch, 3fch: rlps equalizer voltage thresholds #1 bit type function default 7 unused x 6 unused x 5 r/w vref[5] 1 4 r/w vref[4] 1 3 r/w vref[3] 0 2 r/w vref[2] 1 1 r/w vref[1] 0 0 r/w vref[0] 1 vref[5:0]: the vref[5:0] bits set the voltage thresholds of amplitude comparators within the rlps. for t1 mode, the vref[5:0] bits must be programmed to 35h (?b110101). for e1 mode, the vref[5:0] bits must be programmed to 35h (?b110101).
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 168 register 07dh, 0fdh, 17dh, 1fdh, 27dh, 2fdh, 37dh, 3fdh: rlps equalizer voltage thresholds #2 bit type function default 7 r/w cutoff[1] 0 6 r/w cutoff[0] 0 5 unused x 4 unused x 3 unused x 2 r/w vref[8] 0 1 r/w vref[7] 1 0 r/w vref[6] 1 cutoff[1:0]: the cutoff[1:0] bits control cutoff frequencies of the bandlimiter and equaliser within the rlps. for t1 mode, the cutoff[1:0] bits must be programmed to 3h (?b11). for e1 mode, the cutoff[1:0] bits must be programmed to 0h (?b00). vref[8:6]: the vref[8:6] bits set the voltage thresholds of amplitude comparators within the rlps. for t1 mode, the vref[8:6] bits must be programmed to 3h (?b011). for e1 mode, the vref[8:6] bits must be programmed to 3h (?b011).
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 169 11 test features description simultaneously asserting the csb, rdb and wrb inputs causes all output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. 11.1 jtag test port the octliu jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. for more details on the jtag port, please refer to the operations section. instruction register length ? 3 bits instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111 identification register length ? 32 bits version number ? 0h for rev a. part number ? 4318h manufacturer?s identification code ? 0cdh device identification ? 043180cdh for rev. a boundary scan register length ? 131
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 170 table 18 ? boundary scan register pin/enable scan register bit cell type device id pin/enable scan register bit cell type a[10] 130 in_cell 0 rdn[8] 64 out_cell - a[9] 129 in_cell 0 oeb_rdp[8] 63 out_cell - a[8] 128 in_cell 0 rdp[8] 62 out_cell - a[7] 127 in_cell 0 oeb_rclk[8] 61 out_cell - a[6] 126 in_cell 0 rclk[8] 60 out_cell - a[5] 125 in_cell 1 tdn[5] 59 in_cell - a[4] 124 in_cell 0 tdp[5] 58 in_cell - a[3] 123 in_cell 0 tclk[5] 57 in_cell - a[2] 122 in_cell 0 tdn[6] 56 in_cell - a[1] 121 in_cell 0 tdp[6] 55 in_cell - a[0] 120 in_cell 1 tclk[6] 54 in_cell - tclk[1] 119 in_cell 1 tdn[7] 53 in_cell - tdp[1] 118 in_cell 0 tdp[7] 52 in_cell - tdn[1] 117 in_cell 0 tclk[7] 51 in_cell - tclk[2] 116 in_cell 0 tdn[8] 50 in_cell - tdp[2] 115 in_cell 1 tdp[8] 49 in_cell - tdn[2] 114 in_cell 1 tclk[8] 48 in_cell - tclk[3] 113 in_cell 0 hw_only 47 in_cell - tdp[3] 112 in_cell 0 srcasc 46 in_cell - tdn[3] 111 in_cell 0 oeb_sren 45 out_cell - tclk[4] 110 in_cell 0 sren 44 io_cell - tdp[4] 109 in_cell 0 oeb_srclk 43 out_cell - tdn[4] 108 in_cell 0 srclk 42 io_cell - oeb_rclk[1] 107 out_cell 0 oeb_srdi 41 out_cell - rclk[1] 106 out_cell 1 srdi 40 out_cell - oeb_rdp[1] 105 out_cell 1 srdo 39 in_cell - rdp[1] 104 out_cell 0 oeb_srcen 38 out_cell - oeb_rdn[1] 103 out_cell 0 srcen 37 out_cell - rdn[1] 102 out_cell 1 oeb_srcclk 36 out_cell - oeb_rclk[2] 101 out_cell 1 srcclk 35 out_cell - rclk[2] 100 out_cell 0 oeb_srcdo 34 out_cell - oeb_rdp[2] 99 out_cell 1 srcdo 33 out_cell - rdp[2] 98 out_cell - srcode 32 in_cell - oeb_rdn[2] 97 out_cell - oeb_los_l1 31 out_cell - rdn[2] 96 out_cell - los_l1 30 out_cell - oeb_rclk[3] 95 out_cell - oeb_los 29 out_cell - rclk[3] 94 out_cell - los 28 out_cell -
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 171 oeb_rdp[3] 93 out_cell - oeb_rsync 27 out_cell - rdp[3] 92 out_cell - rsync 26 out_cell - oeb_rdn[3] 91 out_cell - res[1] 25 in_cell - rdn[3] 90 out_cell - rstb 24 in_cell - oeb_rclk[4] 89 out_cell - xclk 23 in_cell - rclk[4] 88 out_cell - sbi_en 22 in_cell - oeb_rdp[4] 87 out_cell - oeb_d[7] 21 out_cell - rdp[4] 86 out_cell - d[7] 20 io_cell - oeb_rdn[4] 85 out_cell - oeb_d[6] 19 out_cell - rdn[4] 84 out_cell - d[6] 18 io_cell - oeb_rdn[5] 83 out_cell - oeb_d[5] 17 out_cell - rdn[5] 82 out_cell - d[5] 16 io_cell - oeb_rdp[5] 81 out_cell - oeb_d[4] 15 out_cell - rdp[5] 80 out_cell - d[4] 14 io_cell - oeb_rclk[5] 79 out_cell - oeb_d[3] 13 out_cell - rclk[5] 78 out_cell - d[3] 12 io_cell - oeb_rdn[6] 77 out_cell - oeb_d[2] 11 out_cell - rdn[6] 76 out_cell - d[2] 10 io_cell - oeb_rdp[6] 75 out_cell - oeb_d[1] 9 out_cell - rdp[6] 74 out_cell - d[1] 8 io_cell - oeb_rclk[6] 73 out_cell - oeb_d[0] 7 out_cell - rclk[6] 72 out_cell - d[0] 6 io_cell - oeb_rdn[7] 71 out_cell - oeb_intb 5 out_cell - rdn[7] 70 out_cell - intb 4 io_cell - oeb_rdp[7] 69 out_cell - csb 3 in_cell - rdp[7] 68 out_cell - rdb 2 in_cell - oeb_rclk[7] 67 out_cell - wrb 1 in_cell - rclk[7] 66 out_cell - ale 0 in_cell - oeb_rdn[8] 65 out_cell - notes: 1. oeb signals, when set low, will set the corresponding bidirectional signal to an output. 2. oeb signals, when set high, will set the corresponding output to high impedance. 3. ale is the first bit in the boundary scan chain scanned in and out. it is closest to tdo in the scan chain.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 172 12 operation 12.1 configuring the octliu from reset after a system reset (either via the rstb pin or via the reset register bit), the octliu will default to the following settings: table 19 ? default settings setting receiver section transmitter section t1/e1 mode t1 t1 line code b8zs b8zs line interface pins rxtip[x] and rxring[x] active short haul analogue inputs txtip1[x], txtip2[x], txring1[x], txring2[x] tristated timing options not applicable jitter attenuation enabled, with output clock frequency referenced to tclk[n] diagnostics all diagnostic modes disabled all diagnostic modes disabled 12.2 servicing interrupts the octliu will assert intb to logic 0 when a condition that is configured to produce an interrupt occurs. to find which condition caused this interrupt to occur, the procedure outlined below should be followed: 1. read the bits of the master interrupt source registers (002h and 003h) to identify which octants and/or sbi interface blocks generated the interrupt. for example, a logic one read in the liu[2] bit of the master interrupt source #1 register indicates that octant #2 produced the interrupt. 2. read the bits of the second level line interface interrupt source registers to identify the block within the octant generating the interrupt. the interrupt source registers for octant #1 are at addresses 00ch and 00dh. the interrupt source registers for octant #2 are at addresses 08ch and 08dh. the interrupt source registers for octant #3 are at addresses 10ch and 10dh. the interrupt source registers for octant #4 are at addresses 18ch and 18dh. the interrupt source registers for octant #5 are at addresses 20ch and 20dh. the interrupt source registers for octant #6 are at addresses 28ch and 28dh. the interrupt source registers for octant #7 are at addresses 30ch and 30dh. the interrupt source registers for octant #8 are at addresses 38ch and 38dh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 173 3. read the third level interrupt source bits to identify the interrupt source. (these bits are contained within the registers for the various functional blocks.) 4. service the interrupt. 5. if the intb pin is still logic 0, then there are still interrupts to be serviced. otherwise, all interrupts have been serviced. wait for the next assertion of intb 12.3 using the performance monitoring features the pmon blocks are provided for performance monitoring purposes. the pmon blocks within each liu are used to monitor lcv events. an accumulation interval is initiated by writing to one of the pmon event counter register addresses or by writing to the line interface interrupt source / pmon update register. after initiating an accumulation interval, 3.5 recovered clock periods must be allowed to elapse to permit the pmon counter values to be properly transferred before the pmon registers may be read. 12.4 using the transmit line pulse generator the internal d/a pulse waveform template ram, accessible via the microprocessor bus, can be used to create up to 12 custom waveforms. the ram is accessed indirectly through the xlpg pulse waveform storage write address and xlpg pulse waveform storage data registers. the values written into the pulse waveform storage registers correspond to one of 127 quantized levels. 24 samples are output during every transmit clock cycle. the waveform being programmed is completely arbitrary and programming must be done properly in order to meet the various t1 and e1 template specifications. the scale[4:0] bits of line driver configuration register bits are used to obtain a proper output amplitude. it must also be noted that since samples from the 5 ui are added before driving the dac, it is possible to create arithmetic overflows. the xlpg detects overflows and saturates the resulting value to ?62 or +62 as appropriate. however, it is recommended that the pulse amplitude be programmed such that overflows are avoided. it is possible to verify if an overflow condition occurred by reading the ovrflw register bit after programming a new waveform and transmission of data. the following tables contain the waveform values to be programmed for different situations. table 20 to table 29 specify waveform values typically used for t1 long haul and short haul transmission. table 30 to table 36 specify waveform values for compliance to the at&t tr62411 accunet t1.5 pulse template. table 37 and table 38 specify waveform values for e1 transmission. the t1 and e1 waveforms shown in these tables (but not the tr62411 waveforms) are also stored in a rom within the octliu. the rom contents can be automatically loaded into the waveform template ram by setting the initram bit in xlpg control/status register. note that the programming of template values must observe the following sequencing rule: samples must be written in groups of 5 at a time, each group consisting of the 5 ui values corresponding to a particular waveform and sample number. for example, the following programming sequence fragment is legal:
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 174 : write data for waveform=0, sample=0, ui=0 write data for waveform=0, sample=0, ui=1 write data for waveform=0, sample=0, ui=2 write data for waveform=0, sample=0, ui=3 write data for waveform=0, sample=0, ui=4 write data for waveform=1, sample=12, ui=0 write data for waveform=1, sample=12, ui=1 write data for waveform=1, sample=12, ui=2 write data for waveform=1, sample=12, ui=3 write data for waveform=1, sample=12, ui=4 : whereas the following sequence fragment is illegal: : write data for waveform=0, sample=0, ui=0 write data for waveform=0, sample=1, ui=0 write data for waveform=0, sample=2, ui=0 write data for waveform=0, sample=3, ui=0 write data for waveform=0, sample=4, ui=0 write data for waveform=0, sample=5, ui=0 write data for waveform=0, sample=6, ui=0 write data for waveform=0, sample=7, ui=0 write data for waveform=0, sample=8, ui=0 write data for waveform=0, sample=9, ui=0 : this restriction is necessary because each group of five 7-bit samples is stored in a temporary holding register as it is written. the 5 samples are then transferred to the pulse template ram as a single 35-bit word when the 5 th sample (i.e. the sample whose ui[2:0] address field is set to 4) is written. prior to commencing normal operation, the highz bit of the octant?s xlpg line driver configuration register must be programmed to logic 0 to remove the high impedance state from the txtip1[x], txtip2[x], txring1[x] and txring2[x] transmit outputs.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 175 table 20 ? t1.102 transmit waveform values for t1 long haul (lbo 0 db) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10044000000 20844000000 31543000000 42843000000 53642000000 63a42000000 73a41000000 83841000000 93800000000 10 38 00 00 00 00 11 38 00 00 00 00 12 37 00 00 00 00 13 36 00 00 00 00 14 34 00 00 00 00 15 30 00 00 00 00 16 1b 00 00 00 00 17 00 00 00 00 00 18 4e 00 00 00 00 19 4c 00 00 00 00 20 49 00 00 00 00 21 47 00 00 00 00 22 47 00 00 00 00 23 46 00 00 00 00 24 46 00 00 00 00 note: scale[4:0] programmed to 0ah.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 176 table 21 ? t1.102 transmit waveform values for t1 long haul (lbo 7.5 db) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10010000000 2010e000000 3020c000000 4040a000000 50808000000 60c06000000 71004000000 81602000000 91a01000000 10 1e 00 00 00 00 11 22 00 00 00 00 12 26 00 00 00 00 13 2a 00 00 00 00 14 2b 00 00 00 00 15 2c 00 00 00 00 16 2d 00 00 00 00 17 2c 00 00 00 00 18 28 00 00 00 00 19 24 00 00 00 00 20 20 00 00 00 00 21 1c 00 00 00 00 22 18 00 00 00 00 23 14 00 00 00 00 24 12 00 00 00 00 note: scale[4:0] programmed to 06h.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 177 table 22 ? t1.102 transmit waveform values for t1 long haul (lbo 15 db) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10022070100 20020060100 3001e060100 4001d060100 5011b060100 6021a050000 70418050000 80616040000 90815040000 10 0a 14 04 00 00 11 0d 13 03 00 00 12 10 12 03 00 00 13 13 11 03 00 00 14 16 0f 02 00 00 15 18 0e 02 00 00 16 1a 0d 02 00 00 17 1d 0c 02 00 00 18 1f 0b 02 00 00 19 22 0a 02 00 00 20 23 0a 01 00 00 21 24 09 01 00 00 22 25 08 01 00 00 23 25 08 01 00 00 24 23 07 01 00 00 note: scale[4:0] programmed to 03h.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 178 table 23 ? t1.102 transmit waveform values for t1 long haul (lbo 22.5 db) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10031230a01 20033220901 30035210801 40036200801 500371e0700 600381d0600 701391c0600 802391b0500 903381a0500 10 04 38 19 05 00 11 05 37 18 04 00 12 08 36 17 04 00 13 0b 35 16 04 00 14 0e 33 15 03 00 15 12 31 13 03 00 16 16 2f 12 03 00 17 1a 2e 11 03 00 18 1e 2d 10 03 00 19 22 2b 0f 02 00 20 25 2a 0e 02 00 21 28 29 0d 02 00 22 2b 27 0d 02 00 23 2e 25 0b 02 00 24 30 24 0a 01 00 note: scale[4:0] programmed to 01h.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 179 table 24 ? t1.102 transmit waveform values for t1 short haul (0 ? 110 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10044000000 20a44000000 31a43000000 42843000000 53d42000000 63c42000000 73b41000000 83941000000 93900000000 10 38 00 00 00 00 11 38 00 00 00 00 12 37 00 00 00 00 13 36 00 00 00 00 14 34 00 00 00 00 15 30 00 00 00 00 16 1d 00 00 00 00 17 00 00 00 00 00 18 56 00 00 00 00 19 53 00 00 00 00 20 4f 00 00 00 00 21 4c 00 00 00 00 22 49 00 00 00 00 23 47 00 00 00 00 24 46 00 00 00 00 note: scale[4:0] programmed to 0ah.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 180 table 25 ? t1.102 transmit waveform values for t1 short haul (110 ? 220 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10045000000 20a44000000 31b43000000 42943000000 53342000000 63342000000 73041000000 82f41000000 92e00000000 10 2e 00 00 00 00 11 2d 00 00 00 00 12 2c 00 00 00 00 13 2c 00 00 00 00 14 29 00 00 00 00 15 26 00 00 00 00 16 00 00 00 00 00 17 54 00 00 00 00 18 51 00 00 00 00 19 4d 00 00 00 00 20 49 00 00 00 00 21 48 00 00 00 00 22 47 00 00 00 00 23 46 00 00 00 00 24 45 00 00 00 00 note: scale[4:0] programmed to 0dh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 181 table 26 ? t1.102 transmit waveform values for t1 short haul (220 ? 330 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10044000000 20a44000000 31e43000000 42d43000000 53642000000 63442000000 73041000000 82f41000000 92d00000000 10 2d 00 00 00 00 11 2c 00 00 00 00 12 2b 00 00 00 00 13 2a 00 00 00 00 14 29 00 00 00 00 15 26 00 00 00 00 16 00 00 00 00 00 17 58 00 00 00 00 18 54 00 00 00 00 19 4f 00 00 00 00 20 4a 00 00 00 00 21 49 00 00 00 00 22 47 00 00 00 00 23 47 00 00 00 00 24 46 00 00 00 00 note: scale[4:0] programmed to 0eh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 182 table 27 ? t1.102 transmit waveform values for t1 short haul (330 ? 440 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10044000000 20a44000000 32443000000 42c43000000 53642000000 63442000000 72f41000000 82d41000000 92c00000000 10 2c 00 00 00 00 11 2b 00 00 00 00 12 2a 00 00 00 00 13 29 00 00 00 00 14 28 00 00 00 00 15 1c 00 00 00 00 16 00 00 00 00 00 17 5a 00 00 00 00 18 54 00 00 00 00 19 4f 00 00 00 00 20 4a 00 00 00 00 21 49 00 00 00 00 22 47 00 00 00 00 23 47 00 00 00 00 24 46 00 00 00 00 note: scale[4:0] programmed to 0fh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 183 table 28 ? t1.102 transmit waveform values for t1 short haul (440 ? 550 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10044000000 20a44000000 32543000000 43743000000 53342000000 63142000000 72f41000000 82d41000000 92b00000000 10 2b 00 00 00 00 11 2a 00 00 00 00 12 2a 00 00 00 00 13 28 00 00 00 00 14 25 00 00 00 00 15 1a 00 00 00 00 16 00 00 00 00 00 17 5e 00 00 00 00 18 59 00 00 00 00 19 4f 00 00 00 00 20 4a 00 00 00 00 21 49 00 00 00 00 22 47 00 00 00 00 23 47 00 00 00 00 24 46 00 00 00 00 note: scale[4:0] programmed to 10h.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 184 table 29 ? t1.102 transmit waveform values for t1 short haul (550 ? 660 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10045000000 20845000000 33043000000 43b43000000 53b42000000 63142000000 73041000000 82f41000000 92e00000000 10 2d 00 00 00 00 11 2c 00 00 00 00 12 2b 00 00 00 00 13 2a 00 00 00 00 14 28 00 00 00 00 15 0c 00 00 00 00 16 00 00 00 00 00 17 68 00 00 00 00 18 5d 00 00 00 00 19 51 00 00 00 00 20 4b 00 00 00 00 21 4a 00 00 00 00 22 48 00 00 00 00 23 48 00 00 00 00 24 47 00 00 00 00 note: scale[4:0] programmed to 10h.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 185 table 30 ? tr62411 transmit waveform values for t1 long haul (lbo 0 db) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10000000000 20800000000 31500000000 42800000000 53600000000 63a00000000 73a00000000 83800000000 93800000000 10 38 00 00 00 00 11 38 00 00 00 00 12 37 00 00 00 00 13 36 00 00 00 00 14 34 00 00 00 00 15 30 00 00 00 00 16 1b 00 00 00 00 17 00 00 00 00 00 18 4e 00 00 00 00 19 4c 00 00 00 00 20 49 00 00 00 00 21 46 00 00 00 00 22 43 00 00 00 00 23 00 00 00 00 00 24 00 00 00 00 00 note: scale[4:0] programmed to 0ah.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 186 table 31 ? tr62411 transmit waveform values for t1 short haul (0 ? 110 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10000000000 20a00000000 31a00000000 42800000000 53d00000000 63c00000000 73b00000000 83900000000 93900000000 10 38 00 00 00 00 11 38 00 00 00 00 12 37 00 00 00 00 13 36 00 00 00 00 14 34 00 00 00 00 15 30 00 00 00 00 16 1d 00 00 00 00 17 00 00 00 00 00 18 4f 00 00 00 00 19 4c 00 00 00 00 20 49 00 00 00 00 21 46 00 00 00 00 22 43 00 00 00 00 23 00 00 00 00 00 24 00 00 00 00 00 note: scale[4:0] programmed to 0ah.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 187 table 32 ? tr62411 transmit waveform values for t1 short haul (110 ? 220 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10000000000 20a00000000 31b00000000 42900000000 53300000000 63300000000 73000000000 82f00000000 92e00000000 10 2e 00 00 00 00 11 2d 00 00 00 00 12 2c 00 00 00 00 13 2c 00 00 00 00 14 29 00 00 00 00 15 26 00 00 00 00 16 00 00 00 00 00 17 54 00 00 00 00 18 50 00 00 00 00 19 4c 00 00 00 00 20 48 00 00 00 00 21 45 00 00 00 00 22 42 00 00 00 00 23 00 00 00 00 00 24 00 00 00 00 00 note: scale[4:0] programmed to 0dh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 188 table 33 ? tr62411 transmit waveform values for t1 short haul (220 ? 330 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10000000000 20a00000000 31e00000000 42d00000000 53600000000 63400000000 73000000000 82f00000000 92d00000000 10 2d 00 00 00 00 11 2c 00 00 00 00 12 2b 00 00 00 00 13 2a 00 00 00 00 14 29 00 00 00 00 15 26 00 00 00 00 16 00 00 00 00 00 17 58 00 00 00 00 18 54 00 00 00 00 19 4f 00 00 00 00 20 4b 00 00 00 00 21 47 00 00 00 00 22 43 00 00 00 00 23 00 00 00 00 00 24 00 00 00 00 00 note: scale[4:0] programmed to 0eh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 189 table 34 ? tr62411 transmit waveform values for t1 short haul (330 ? 440 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10000000000 20a00000000 32400000000 42c00000000 53600000000 63400000000 72f00000000 82d00000000 92c00000000 10 2c 00 00 00 00 11 2b 00 00 00 00 12 2a 00 00 00 00 13 29 00 00 00 00 14 28 00 00 00 00 15 1c 00 00 00 00 16 00 00 00 00 00 17 5a 00 00 00 00 18 54 00 00 00 00 19 4f 00 00 00 00 20 4b 00 00 00 00 21 47 00 00 00 00 22 43 00 00 00 00 23 00 00 00 00 00 24 00 00 00 00 00 note: scale[4:0] programmed to 0fh.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 190 table 35 ? tr62411 transmit waveform values for t1 short haul (440 ? 550 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10000000000 20a00000000 32500000000 43700000000 53300000000 63100000000 72f00000000 82d00000000 92b00000000 10 2b 00 00 00 00 11 2a 00 00 00 00 12 2a 00 00 00 00 13 28 00 00 00 00 14 25 00 00 00 00 15 1a 00 00 00 00 16 00 00 00 00 00 17 5e 00 00 00 00 18 59 00 00 00 00 19 53 00 00 00 00 20 4e 00 00 00 00 21 49 00 00 00 00 22 44 00 00 00 00 23 00 00 00 00 00 24 00 00 00 00 00 note: scale[4:0] programmed to 10h.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 191 table 36 ? tr62411 transmit waveform values for t1 short haul (550 ? 660 ft.) sample number ui #0 ui #1 ui #2 ui #3 ui #4 10000000000 20800000000 33000000000 43b00000000 53b00000000 63100000000 73000000000 82f00000000 92e00000000 10 2d 00 00 00 00 11 2c 00 00 00 00 12 2b 00 00 00 00 13 2a 00 00 00 00 14 28 00 00 00 00 15 0c 00 00 00 00 16 00 00 00 00 00 17 68 00 00 00 00 18 5d 00 00 00 00 19 53 00 00 00 00 20 4d 00 00 00 00 21 49 00 00 00 00 22 44 00 00 00 00 23 00 00 00 00 00 24 00 00 00 00 00 note: scale[4:0] programmed to 10h.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 192 table 37 ? transmit waveform values for e1 120 ohm sample number ui #0 ui #1 ui #2 ui #3 ui #4 10000000000 20000000000 30a00000000 42600000000 53200000000 63200000000 73200000000 83200000000 93200000000 10 32 00 00 00 00 11 32 00 00 00 00 12 32 00 00 00 00 13 32 00 00 00 00 14 32 00 00 00 00 15 26 00 00 00 00 16 0a 00 00 00 00 17 00 00 00 00 00 18 00 00 00 00 00 19 00 00 00 00 00 20 00 00 00 00 00 21 00 00 00 00 00 22 00 00 00 00 00 23 00 00 00 00 00 24 00 00 00 00 00 note: scale[4:0] programmed to 0ah.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 193 table 38 ? transmit waveform values for e1 75 ohm sample number ui #0 ui #1 ui #2 ui #3 ui #4 10000000000 20000000000 30a00000000 42800000000 53400000000 63400000000 73400000000 83400000000 93400000000 10 34 00 00 00 00 11 34 00 00 00 00 12 34 00 00 00 00 13 34 00 00 00 00 14 34 00 00 00 00 15 2d 00 00 00 00 16 0a 00 00 00 00 17 00 00 00 00 00 18 00 00 00 00 00 19 00 00 00 00 00 20 00 00 00 00 00 21 00 00 00 00 00 22 00 00 00 00 00 23 00 00 00 00 00 24 00 00 00 00 00 note: scale[4:0] programmed to 0ch.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 194 12.5 using the line receiver the line receiver must be properly initialized for correct operation. several register bits must be programmed and the equalizer ram table must be initialized according to the appropriate table below. the rlps equalizer ram content is programmed by the rlps equalization indirect data registers for each address location. the address location is given by the octant?s rlps equalization indirect address register. a read or write request is done by setting the rwb bit in the octant?s rlps equalization read/writeb select register. note that several registers are not their default values. the eq_en bit of the rlps equalizer configuration register must be set to logic 1. the cutoff[1:0] bits of the rlps voltage thresholds #2 register must be programmed to 3h (11b) for t1 mode or 0h (00b) for e1 mode. table 39 summarizes the values the rlps registers are to contain. table 39 ? rlps register programming register data value bin hex rlps configuration and status xx000xx1 01h rlps alos detection/ clearance threshold x000x000 00h rlps alos detection period 00000001 01h rlps alos clearance period 00000001 01h rlps equalization indirect address 00000000 00h rlps equalization ram read/writeb select 1xxxxxxx 80h rlps equalizer loop status and control 00000000 00h rlps equalizer configuration 00x01011 0bh rlps equalization indirect data[31:24] * * rlps equalization indirect data[23:16] * * rlps equalization indirect data[15:8] * * rlps equalization indirect data[7:0] * * rlps voltage thresholds #1 xx101110 2eh rlps voltage thresholds #2 (t1 mode) (e1 mode) 11xxx011 00xxx011 c3h 03h since the line receiver supports both e1 and t1 standards over either short haul or long haul cables, the line receiver has two normal modes of operation, as selected by the e1/t1b bit of the global configuration register. access to the equalizer ram is provided by means of indirect access registers a typical programming sequence follows. this programming sequence is repeated for each of the 256 equalizer ram addresses.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 195 write rlps indirect data register <31 ? 24 bits of data> write rlps indirect data register <23 ? 16 bits of data> write rlps indirect data register <1 5 ? 8 bits of data> write rlps indirect data register < 7 ? 0 bits of data> action rlps equalisation read/writeb select register write rlps equalisation indirect address register

pause table 40 ? rlps equalizer ram table (t1 mode) ram address content (msb..lsb) ram address content (msb..lsb) 00d 03061c3bh 128d 766b38bbh 01d 03061c3bh 129d 766b38bbh 02d 03061c3bh 130d 766b38bbh 03d 03061c3bh 131d 7e6b38bbh 04d 03061c3bh 132d 7e7338bbh 05d 03062c3bh 133d 7e73393bh 06d 03062c3bh 134d 7e733d3bh 07d 03062c3bh 135d 7e7b3d3bh 08d 03062c3bh 136d 7e7b3d3bh 09d 03062c3bh 137d 867b3d3bh 10d 030e2c3bh 138d 867b4d3bh 11d 030e2c3bh 139d 867b4d3bh 12d 030e2c3bh 140d 867b4d3bh 13d 03162c3bh 141d 867b5d3bh 14d 03162c3bh 142d 867b5d3bh 15d 03162c3bh 143d 8e7b5d3bh 16d 03162c3bh 144d 8e7b6d3bh 17d 03163c3bh 145d 8e7b6d3bh 18d 03163c3bh 146d 8e7b6d3bh 19d 03163c3bh 147d 8e7b7d3bh 20d 03163c3bh 148d 8e7b7d3bh 21d 03163c3bh 149d 967b7d3bh 22d 03163c3bh 150d 967b7d3bh 23d 031e3c3bh 151d 967b7d3bh 24d 031c3c3bh 152d 967b793bh 25d 031c3c3bh 153d 967b793bh
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 196 ram address content (msb..lsb) ram address content (msb..lsb) 26d 031c3c3bh 154d 967b793bh 27d 031c3c3bh 155d 9e7b793bh 28d 031c3c3bh 156d 9e7b793bh 29d 03243c3bh 157d 9e7b793bh 30d 03244c3bh 158d 9e83793bh 31d 03244c3bh 159d 9d83793bh 32d 03244c3bh 160d 9d83793bh 33d 03244c3bh 161d 9d83793bh 34d 03244c3bh 162d a583793bh 35d 032c4c3bh 163d a583893bh 36d 032e4c3bh 164d a583893bh 37d 032e5c3bh 165d a583893bh 38d 032e6c3bh 166d a583993bh 39d 032e6c3bh 167d a583993bh 40d 032e6c3bh 168d ad83993bh 41d 032e7c3bh 169d ad8b993bh 42d 032e7c3bh 170d ad8ba93bh 43d 032e7c3bh 171d ad89a93bh 44d 072e8c3bh 172d ad89a93bh 45d 072e8c3bh 173d ad89a93bh 46d 0f2e8c3bh 174d b589a93bh 47d 0f2e8c3bh 175d b589a93bh 48d 0f368c3bh 176d b589b93bh 49d 0f368c3bh 177d b589b53bh 50d 0f368c3bh 178d b589b53bh 51d 0f368c3bh 179d b589b53bh 52d 17368c3bh 180d bd89b53bh 53d 17369c3bh 181d bd89b53bh 54d 17369c3bh 182d bd91b53bh 55d 17369c3bh 183d bd91b53bh 56d 1736ac3bh 184d bd91b53bh 57d 1736ac3bh 185d bd91b53bh 58d 1f3eac3bh 186d c591b53bh 59d 1f3e9c3bh 187d c591c53bh 60d 1f3e9c3bh 188d c591c53bh 61d 1f469c3bh 189d c591c53bh 62d 1e469c3bh 190d c591d53bh 63d 1e469c3bh 191d c591d53bh 64d 26469c3bh 192d cd91d53bh 65d 2646ac3bh 193d cd99d53bh 66d 2646ac3bh 194d cc99d53bh 67d 2646ac3bh 195d cc99d4bbh 68d 2646bc3bh 196d cca1d4bbh
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 197 ram address content (msb..lsb) ram address content (msb..lsb) 69d 2646bc3bh 197d cca1d4bbh 70d 2e46bc3bh 198d d4a1d4bbh 71d 2e46bc3bh 199d d4a1d4bbh 72d 2e4ebc3bh 200d d4a1d53bh 73d 2e4ecc3bh 201d d4a1d13bh 74d 2e4ecc3bh 202d d4a3d13bh 75d 2e4ecc3bh 203d d4a3d13bh 76d 364ecc3bh 204d dca3d13bh 77d 364ecc3bh 205d dca3d13bh 78d 3656cc3bh 206d dcabd13bh 79d 3656dc3bh 207d dca9d13bh 80d 3656dc3bh 208d dca9d13bh 81d 3656dc3bh 209d dca9d13bh 82d 3e56dc3bh 210d e4a9d13bh 83d 3e56dc3bh 211d e4a9d1bbh 84d 3e56ec3bh 212d e4b1d1bbh 85d 3e54ec3bh 213d e4b1d1bbh 86d 3e54ec3bh 214d e4b1c1bbh 87d 3e54ec3bh 215d e4b1c1bbh 88d 4654ec3bh 216d ecb1c1bbh 89d 4654ec3bh 217d ecb1c1bbh 90d 465cec3bh 218d ecb1d1bbh 91d 465cec3bh 219d ecb1d1bbh 92d 465cec3bh 220d ecb1d1bbh 93d 465cec3bh 221d ecb1d1bbh 94d 4e5cec3bh 222d f4b1d1bbh 95d 4e5cec3bh 223d f4b1d1bbh 96d 4e5cfc3bh 224d f4b1d23bh 97d 4e5efc3bh 225d f4b9d23bh 98d 4e5ef83bh 226d f4b9c23bh 99d 4e5ef83bh 227d f4b9c23bh 100d 4e5ef83bh 228d f4b9c23bh 101d 565ef83bh 229d fcb9c23bh 102d 565f083bh 230d fcb9d23bh 103d 565f083bh 231d fcb9d23bh 104d 565f083bh 232d fcb9d23bh 105d 565f183bh 233d fcb9e23bh 106d 565f183bh 234d fcb9e23bh 107d 5e5f183bh 235d fcb9e23bh 108d 5e5f183bh 236d fcb9e23bh 109d 5e5f283bh 237d fcb9e2bbh 110d 5e67283bh 238d fcb9d2bbh 111d 5e67283bh 239d fcb9d2bbh
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 198 ram address content (msb..lsb) ram address content (msb..lsb) 112d 5e67283bh 240d fcb9d2bbh 113d 6667283bh 241d fcb9d2bbh 114d 6665283bh 242d fcb9d2bbh 115d 6665283bh 243d fcb9e2bbh 116d 6665283bh 244d fcb9e2bbh 117d 6663283bh 245d fcb9e2bbh 118d 6663283bh 246d fcb9e2bbh 119d 6e63283bh 247d fcb9e2bbh 120d 6e6b283bh 248d fcb9e2bbh 121d 6e6b28bbh 249d fcb9e2bbh 122d 6e6b2cbbh 250d fcb9e2bbh 123d 6e732cbbh 251d fcb9e2bbh 124d 6e732cbbh 252d fcb9f2bbh 125d 76732cbbh 253d fcb9f2bbh 126d 767328bbh 254d fcb9f2bbh 127d 767338bbh 255d fcb9f2bbh table 41 ? rlps equalizer ram table (e1 mode) ram address content (msb..lsb) ram address content (msb..lsb) 00d 03062c3bh 128d 8a80f93bh 01d 03062c3bh 129d 8a80f9bbh 02d 03062c3bh 130d 8a80f9bbh 03d 03062c3bh 131d 9280f9bbh 04d 030e2c3bh 132d 928109bbh 05d 030e2c3bh 133d 918109bbh 06d 03162c3bh 134d 918119bbh 07d 03162c3bh 135d 918119bbh 08d 03162c3bh 136d 998129bbh 09d 03163c3bh 137d 998125bbh 10d 031e3c3bh 138d 998135bbh 11d 031e3c3bh 139d 998135bbh 12d 031e3c3bh 140d 998131bbh 13d 031e3c3bh 141d a18131bbh 14d 031e3c3bh 142d a18931bbh 15d 031e4c3bh 143d a18931bbh 16d 031e4c3bh 144d a18931bbh 17d 031e4c3bh 145d a19131bbh 18d 031e4c3bh 146d a19131bbh 19d 031e4c3bh 147d a99131bbh 20d 03264c3bh 148d a99131bbh 21d 03264c3bh 149d a991323bh 22d 032e4c3bh 150d a991323bh 23d 032e4c3bh 151d a991323bh
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 199 ram address content (msb..lsb) ram address content (msb..lsb) 24d 032e4c3bh 152d b191323bh 25d 032e4c3bh 153d b191323bh 26d 032e5c3bh 154d b199323bh 27d 032e5c3bh 155d b199323bh 28d 032e5c3bh 156d b199323bh 29d 032e5c3bh 157d b999323bh 30d 032e5c3bh 158d b999323bh 31d 03365c3bh 159d b999423bh 32d 03366c3bh 160d b9a1423bh 33d 03366c3bh 161d b9a1423bh 34d 03366c3bh 162d b9a1423bh 35d 03366c3bh 163d c1a1423bh 36d 03366c3bh 164d c1a1523bh 37d 03367c3bh 165d c1a1523bh 38d 03367c3bh 166d c1a1623bh 39d 03367c3bh 167d c1a1623bh 40d 0b367c3bh 168d c9a1623bh 41d 0b3e7c3bh 169d c9a1623bh 42d 0b3e8c3bh 170d c9a1723bh 43d 0b3e8c3bh 171d c9a172bbh 44d 0b3e8c3bh 172d c9a172bbh 45d 133e8c3bh 173d d1a172bbh 46d 13468c3bh 174d d1a972bbh 47d 13469c3bh 175d d1a972bbh 48d 13469c3bh 176d d1a972bbh 49d 13469c3bh 177d d1b172bbh 50d 13469c3bh 178d d1b172bbh 51d 1b469c3bh 179d d9b172bbh 52d 1b4e9c3bh 180d d9b172bbh 53d 1b4eac3bh 181d d9b972bbh 54d 1b4eac3bh 182d d9b972bbh 55d 1b4eac3bh 183d d9b972bbh 56d 234eac3bh 184d e1b982bbh 57d 2346ac3bh 185d e1bb82bbh 58d 2346acbbh 186d e0bb82bbh 59d 2346acbbh 187d e0bb92bbh 60d 2346acbbh 188d e0bb92bbh 61d 2b46acbbh 189d e8bb92bbh 62d 2b4eacbbh 190d e8bb92bbh 63d 2b4ebcbbh 191d e8bba2bbh 64d 2b4ebcbbh 192d e8c3a2bbh 65d 2b56bcbbh 193d e8c3a2bbh 66d 2b56bcbbh 194d e8c3a2bbh
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 200 ram address content (msb..lsb) ram address content (msb..lsb) 67d 3356bcbbh 195d f0c3a2bbh 68d 3356bcbbh 196d f0c3a2bbh 69d 3356ccbbh 197d f0cba2bbh 70d 3356ccbbh 198d f0cba2bbh 71d 3356ccbbh 199d f0cba2bbh 72d 3b56ccbbh 200d f8cba2bbh 73d 3b5eccbbh 201d f8c3a2bbh 74d 3b5edcbbh 202d f8c3a33bh 75d 3b5edcbbh 203d f8c3a33bh 76d 3b5edcbbh 204d f8c3a33bh 77d 435edcbbh 205d f8c3a33bh 78d 435edcbbh 206d f8c3a33bh 79d 4366dcbbh 207d f8cba33bh 80d 4364dcbbh 208d f8c9a33bh 81d 4364dcbbh 209d f8c9a33bh 82d 4364dcbbh 210d f8c9a33bh 83d 4b64dcbbh 211d f8c9a33bh 84d 4b6cdcbbh 212d f8c9a73bh 85d 4b6cecbbh 213d f8c9a7bbh 86d 4b6cecbbh 214d f8c9b7bbh 87d 4b6cecbbh 215d f8c9b7bbh 88d 536cecbbh 216d f8c9b7bbh 89d 536ce8bbh 217d f8c9bbbbh 90d 536cf8bbh 218d f8d1bbbbh 91d 536cf83bh 219d f8d1bbbbh 92d 536cf83bh 220d f8d1bbbbh 93d 5b6cf83bh 221d f8d1bbbbh 94d 5b6cf83bh 222d f8d1bbbbh 95d 5b6cf8bbh 223d f8d1cbbbh 96d 5b64f8bbh 224d f8d1cbbbh 97d 5b64f8bbh 225d f8d1cbbbh 98d 5b64f8bbh 226d f8d1cbbbh 99d 6364f8bbh 227d f8d1cbbbh 100d 636cf8bbh 228d f8d9cbbbh 101d 626cf8bbh 229d f8d9cbbbh 102d 6274f8bbh 230d f8e1cbbbh 103d 6274f8bbh 231d f8e1cbbbh 104d 6a74f8bbh 232d f8e1cbbbh 105d 6a74f8bbh 233d f8e1cbbbh 106d 6a74f93bh 234d f8e1c7bbh 107d 6a74f93bh 235d f8d9c7bbh 108d 6a74f93bh 236d f8d9d7bbh 109d 7274f93bh 237d f8d9d7bbh
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 201 ram address content (msb..lsb) ram address content (msb..lsb) 110d 7274f93bh 238d f8d9d7bbh 111d 7274f93bh 239d f8d9e7bbh 112d 7272f93bh 240d f8d9e3bbh 113d 7272f93bh 241d f8d9e3bbh 114d 7272f93bh 242d f8d9e3bbh 115d 7a72f93bh 243d f8d9e3bbh 116d 7a70f93bh 244d f8d9e3bbh 117d 7a70e93bh 245d f8d9f3bbh 118d 7a78e93bh 246d f8d9f3bbh 119d 7a78e93bh 247d f8d9f3bbh 120d 8278e93bh 248d f8d9f3bbh 121d 8278e93bh 249d f8d9f3bbh 122d 8278e8bbh 250d f8d9f3bbh 123d 8278e8bbh 251d f8d9f3bbh 124d 8278e8bbh 252d f8d9f3bbh 125d 8a78e8bbh 253d f8d9f3bbh 126d 8a78e93bh 254d f8d9f3bbh 127d 8a78f93bh 255d f8d9f3bbh table 42 ? rlps equalizer ram table (monitor mode) tbd 12.6 using the prbs generator and detector prbs patterns may be generated and detected in either the transmit or receive directions, as configured by the tx_gen, rx_gen and tx_det bits of the line interface prbs position registers. 12.7 loopback modes the octliu provides two loopback modes to aid in network and system diagnostics. the network (line) loopback can be initiated at any time via the p interface, but is usually initiated once an inband loopback activate code is detected. the system diagnostic digital loopback can be initiated at any time by the system via the p interface to check the path of system data through the liu. 12.7.1 line loopback when line loopback (linelb) is initiated by setting the linelb bit in the line interface diagnostics register to logic 1, the liu is configured to internally connect the recovered data to the transmit jitter attenuator, tjat. the data sent to the tjat is the recovered data from the output of the cdrc block. note that when line loopback is enabled, the contents of the tjat reference clock divisor and output clock divisor registers should be programmed to 2fh in t1
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 202 mode / ffh in e1 mode to correctly attenuate the jitter on the receive clock. conceptually, the data flow through a single octant of the octliu in this loopback mode is illustrated in figure 18. figure 18 ? line loopback xibc xpde rjat lcode ib cd tjat pdvd cdrc xlpg rlps txtip[x] txring[x] rxtip[x] rxring[x] tdp[n] tdn[n] tclk[n] rdp[n] rdn/rlcv[n] rclk[n] line loopback 12.7.2 diagnostic digital loopback when diagnostic digital loopback (ddlb) mode is initiated by setting the ddlb bit in the line interface diagnostics register to logic 1, the octliu octant is configured to internally direct the output of the tjat to the inputs of the receiver section. the dual-rail rz outputs of the tjat are directed to the dual-rail inputs of the cdrc. conceptually, the data flow through a single octant of the octliu in this loopback condition is illustrated in figure 19. figure 19 ? diagnostic digital loopback diagnostic loopback xibc xpde lcode tjat cdrc xlpg rlps txtip[x] txring[x] rxtip[x] rxring[x] tdp[n] tdn[n] tclk[n] rdp[n] rdn/rlcv[n] rclk[n] rjat ib c d pdvd 12.8 jtag support the octliu supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms,
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 203 tdi and tdo used to control the tap controller and the boundary scan registers. the trstb input is the active-low reset signal used to reset the tap controller. tck is the test clock used to sample data on the tdi primary input and to output data on the tdo primary output. the tms primary input is used to direct the tap controller through its states. the basic boundary scan architecture is shown below. figure 20 ? boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable the boundary scan architecture consists of a tap controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single-bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 204 the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register placed in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi, and forced onto all digital outputs. 12.8.1 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described below.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 205 figure 21 ? tap controller finite state machine test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 a ll transitions dependent on input tms 0 0 0 0 0 1 test-logic-reset the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 206 synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instruction register is set to the idcode instruction. run-test-idle the run/test/idle state is used to execute tests. capture-dr the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr the update data register state is used to load a test register?s parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register?s parallel output latches are used to control the device?s outputs. the parallel output latches are updated on the falling edge of tck. capture-ir the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-ir the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 207 boundary scan instructions the following is a description of the standard instructions. each instruction selects a serial test data register path between input, tdi and output, tdo. bypass the bypass instruction shifts data from input, tdi to output, tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is placed between input, tdi and output, tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. idcode the identification instruction is used to connect the identification register between tdi and tdo. the device?s identification code can then be shifted out using the shift-dr state. stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out of the output, tdo, using the shift-dr state. boundary scan cells in the following diagrams, clock-dr is equal to tck when the current controller state is shift- dr or capture-dr, and unchanging otherwise. the multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the boundary scan register table in the jtag test port section 11.2.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 208 figure 22 ? input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2 figure 23 ? output cell (out_cell) or enable cell (enable) extest d c d c g1 g2 12 mux g1 1 1 mux output or enable from system logic scan chain in scan chain out output or enable shift-dr clock-dr update-dr 12 12 12 idoode i.d. code bit
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 209 figure 24 ? bidirectional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit figure 25 ? layout of output enable and bidirectional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 210 13 functional timing 13.1 sbi bus interface timing figure 26 ? sbi bus functional timing c1 v3 v3 v3 ds0#4. v5 ds0#9. refclk c1fp data[7:0] pl v5 dp ??? ??? ??? ??? ??? ??? figure 26 illustrates the operation of the sbi bus, using a negative justification on the second to last v3 octet as an example. the justification is indicated by asserting pl high during the v3 octet. the timing diagram also shows the location of one of the tributaries by asserting v5 high during the v5 octet. note ? the sbi add and drop busses operate in an identical manner. signal names on the add bus have an a prepended to the names shown in figure 26 (e.g, ac1fp, adata[7:0], etc.) and those on the drop bus have an d prepended to them (e.g, dc1fp, ddata[7:0], etc.)
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 211 13.2 line code violation insertion figure 27 ? b8zs line code violation insertion tclk tdp txtip txring continuous zeros 000 0 vv bb b8zs signature pattern b b v v 000 0 b b 0 v 000 0 tclk tdp txtip txring 000 0 vv bb b8zs signature pattern lcvins = 1 causes omission of first bipolar violation pulse. continuous zeros the effect of setting the lcvins bit of the line interface diagnostics register is shown in figure 27. txtip[x] and txring[x] have been shown as square nrz pulses for illustrative purposes. setting lcvins to a logic 1 generates one line code violation and 3 bit errors by causing the omission of the first line code violation pulse when a string of 8 consecutive zeros occurs in the unipolar data stream tdp. to generate another line code violation, the lcvins bit must be reset to logic 0 and then set to logic 1 again.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 212 figure 28 ? hdb3 line code violation insertion tclk tdp txtip txring continuous zeros 00 0v 10 0v 10 0v 1 tclk tdp txtip txring continuous zeros 000 v 100v v 00 0 1 lcvins = 1 causes omission of bipolar pulse and violation of same polarity as previous violation. the effect of setting the lcvins bit of the line interface diagnostics register is shown in figure 28. txtip[x] and txring[x] have been shown as square nrz pulses for illustrative purposes. setting lcvins to a logic 1 generates one line code violation by causing the omission of a bipolar pulse and hence a bipolar violation pulse of the same polarity as the previous bipolar violation pulse when a string of 4 consecutive zeros occurs in the unipolar data stream tdp. to generate another line code violation, the lcvins bit must be reset to logic 0 and then set to logic 1 again.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 213 figure 29 ? ami line code violation insertion tclk tdp txtip txring tclk tdp txtip txring v lcvins = 1 causes a bipolar violation the effect of setting the lcvins bit of the line interface diagnostics register is shown in figure 29. txtip[x] and txring[x] have been shown as square nrz pulses for illustrative purposes. setting lcvins to a logic 1 generates one line code violation by causing the next pulse to be of the same polarity as the previous pulse. subsequent pulses will be of alternate polarity. to generate another line code violation, the lcvins bit must be reset to logic 0 and then set to logic 1 again. 13.3 alarm interface figure 30 ? los alarm serial output los8 xclk los_l1 los los1 los2 los3 los4 los5 los6 los7 los8 los1 figure 30 shows the operation of the alarm interface. the los status of the 8 liu octants is output continuously in a serial format with a marker signal los_l1 to indicate the presence of the los status for liu #1.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 214 14 absolute maximum ratings maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. table 43 ? absolute maximum ratings case temperature under bias -40c to +85c storage temperature -40c to +125c supply voltage v ddall33 1 -0.3v to +4.6v supply voltage v dd1v8 -0.3v to +3.6v voltage on any pin -0.3v to v ddall33 + 0.3v static discharge voltage 1000v latch-up current 100ma dc input current 20ma lead temperature +230c junction temperature +150c not withstanding the values in the above table 3.3v power supplies must always be at a voltage greater than or equal to the 1.8v power supplies. 1 the octliu 3.3 volt digital and analogue power pins are collectively referred to as v ddall33 .
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 215 15 d.c. characteristics t a = -40c to +85c, v ddall33 = 3.3v 5%, v dd1v8 = 1.8v 5% (typical conditions: t a = 25c, v ddall33 = 3.3v, v dd1v8 = 1.8v) table 44 ? d.c. characteristics symbol parameter min typ max units conditions vdd3v3, tavd1, tavd2, tavd3, cavd, ravd1, ravd2, qavd power supply 3.135 3.3 3.465 volts note 5. vdd1v8 power supply 1.71 1.8 1.89 volts note 5. vil input low voltage 0.8 volts guaranteed input low voltage vih input high voltage 2.0 volts guaranteed input high voltage vol output or bidirectional low voltage 0.1 0.4 volts vdd = min, iol = -6ma for los, los_l1, tdo and serial prom interface outputs; -8ma for others. notes 3, 5 voh output or bidirectional high voltage 2.4 2.7 volts vdd = min, ioh = 6ma for los, los_l1, tdo and serial prom interface outputs; 8ma for others. notes 3,5 vt+ reset input high voltage 2.0 1.6 volts applies to ttl schmidt-triggered inputs (rstb, trstb) only. note 5. vt- reset input low voltage 1.1 0.8 volts applies to ttl schmidt-triggered inputs (rstb, trstb) only. note 5. vth reset input hysteresis voltage 0.5 volts applies to ttl schmidt-triggered inputs (rstb, trstb) only. note 5. iilpu input low current +20 +83 +200 a vil = gnd. notes 1, 3, 5 iihpu input high current -10 0 +10 a vih = vdd. notes 1, 3, 5 iilpd input low current -10 0 +10 a vil = gnd. notes 4, 3, 5 iihpd input high current -200 -83 -20 a vih = vdd. notes 4, 3, 5 iil input low current -10 0 +10 a vil = gnd. notes 2, 3, 5 iih input high current -10 0 +10 a vih = vdd. notes 2, 3, 5 cin input capacitance 5pf excluding package, package typically 2 pf. note 5. cout output capacitance 5 pf excluding package, package typically 2 pf. note 5.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 216 symbol parameter min typ max units conditions cio bidirectional capacitance 5pf excluding package, package typically 2 pf. note 5. iddop 3v3 3.3v operating current 400 ma digital output pads loaded wih max capacitance. transmission of pattern containing 50% ones. iddop 1v8 1.8v operating current 150 ma notes on d.c. characteristics: 1. input pin or bi-directional pin with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up or pull-down resistor 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. input pin or bi-directional pin with internal pull-down resistor. 5. typical values are given as a design aid. this product is not tested to the typical values given in the datasheet.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 217 16 microprocessor interface timing characteristics (t a = -40c to +85c, v ddall33 = 3.3v 5%, v dd1v8 = 1.8v 5%) table 45 ? microprocessor interface read access symbol parameter min max units tsar address to valid read set-up time 10 ns thar address to valid read hold time 5 ns tsalr address to latch set-up time 10 ns thalr address to latch hold time 10 ns tvl valid latch pulse width 20 ns tslr latch to read set-up 0 ns thlr latch to read hold 5 ns tprd valid read to valid data propagation delay 70 ns tzrd valid read negated to output tri-state 20 ns tzinth valid read negated to output tri-state 50 ns
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 218 figure 31 ? microprocessor interface read timing intb tz inth (csb+rdb) valid data d[7:0] tp rd tz rd ts ar th ar valid address a [10:0] a le ts alr tv l ts lr th alr th lr notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. in non-multiplexed address/data bus architectures, ale should be held high so parameters tsalr, thalr, tvl, and tslr are not applicable. 5. parameter thar is not applicable if address latching is used.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 219 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. table 46 ? microprocessor interface write access symbol parameter min max units tsaw address to valid write set-up time 10 ns tsdw data to valid write set-up time 20 ns tsalw address to latch set-up time 10 ns thalw address to latch hold time 10 ns tvl valid latch pulse width 5 ns tslw latch to write set-up 0 ns thlw latch to write hold 5 ns thdw data to valid write hold time 5 ns thaw address to valid write hold time 5 ns tvwr valid write pulse width 40 ns
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 220 figure 32 ? microprocessor interface write timing th dw valid data d[7:0] tv wr ts aw th aw ts dw (csb+wrb) a [9:0] valid address a le tv l ts alw ts lw th alw th lw notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. in non-multiplexed address/data bus architectures, ale should be held high so parameters tsalw, thalw, tvl, tslw and thlw are not applicable. 3. parameter thaw is not applicable if address latching is used. 4. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 5. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 221 17 octliu timing characteristics 17.1 rstb timing (figure 33) (t a = -40c to +85c v ddall33 = 3.3v 5%, v dd1v8 = 1.8v 5%) table 47 ? rtsb timing symbol description min max units tv rstb rstb pulse width 100 ns figure 33 ? rstb timing rstb tv rstb 17.2 xclk input timing (figure 34) table 48 ? xclk input timing symbol description min max units t xclk xclk frequency (1.544 mhz or 2.048 mhz 100ppm) 1.544 ? 100ppm 2.048 +100ppm mhz tl xclk xclk low pulse width (note 1) 160 ns th xclk xclk high pulse width (note 1) 160 ns figure 34 ? xclk input timing xclk t l t h t xclk xclk xclk
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 222 17.3 transmit serial interface (figure 35) (t a = -40c to +85c, v ddall33 = 3.3v 5%, v dd1v8 = 1.8v 5%) table 49 ? transmit serial interface symbol description min max units tclk[8:1] frequency (1.544mhz 200ppm or 2.048mhz 200 ppm) 1.544 ? 200ppm 2.048 +200ppm mhz tclk[8:1] jitter -50 50 ns tclk[8:1] duty cycle 35 65 % ts td tdp[n], tdn[n] to tclk[n] set-up time 20 ns th td tdp[n], tdn[n] to tclk[n] hold time 20 ns figure 35 ? transmit serial interface timing diagram tclk[n] valid ts td th td tclk[n] ts td th td valid inputs samped on rising edge tdp[n] tdn[n] tdp[n] tdn[n] inputs samped on falling edge
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 223 17.4 receive serial interface (figure 36) (t a = -40c to +85c v ddall33 = 3.3v 5%, v dd1v8 = 1.8v 5%) table 50 ? receive serial interface symbol description min max units tp rd rclk[n] to rdp[n], rdn/rlcv[n] propagation delay -20 50 ns figure 36 ? receive serial interface timing diagram valid tp rd rclk[n] valid tp rd rdp[n] rdn/rlcv[n] output on rising edge rclk[n] rdp[n] rdn/rlcv[n] output on falling edge
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 224 17.5 sbi interface (figure 37 to figure 39) (t a = -40c to +85c v ddall33 = 3.3v 5%, v dd1v8 = 1.8v 5%) table 51 ? clocks and sbi frame pulse symbol description min max units refclk frequency 19.44 ? 50ppm 19.44 +50ppm mhz refclk duty cycle 40 60 % ts c1fp ac1fp, dc1fp set-up time to refclk 4 ns th c1fp ac1fp, dc1fp hold time to refclk 0 ns t p c1fpout refclk to c1fpout valid 1 20 ns figure 37 ? sbi frame pulse timing refclk c1fpout tp c1fpout ac1fp dc1fp ts c1fp th c1fp
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 225 table 52 ? sbi add bus symbol description min max units ts sbiadd all sbi add bus inputs set-up time to refclk 4ns th sbiadd all sbi add bus inputs hold time to refclk 0ns figure 38 ? sbi add bus timing refclk ts sbiadd th sbiadd a data[7:0] a dp, apl a v5 table 53 ? sbi drop bus symbol description min max units t p dactive refclk to dactive valid 2 15 ns t p sbidrop refclk to all sbi drop bus outputs (except dactive) valid 220ns t z sbidrop refclk to all sbi drop bus outputs (except dactive) tristate 220ns
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 226 figure 39 ? sbi drop bus timing refclk ddata[7:0] ddp, dpl, dv5 tp sbidrop tz sbidrop ddata[7:0] ddp, dpl, dv5 dactive tp dactive
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 227 17.6 serial prom (spi) interface (figure 40) (t a = -40c to +85c v ddall33 = 3.3v 5%, v dd1v8 = 1.8v 5%) table 54 ? spi interface symbol description min max units srclk frequency xclk frequency 4 srcclk frequency xclk frequency 4 ts spi spi input set-up time to srclk, srrclk 50 ns th spi spi input set-up time to srclk, srrclk 50 ns t p spi srclk, srrclk to spi output prop. time -50 50 ns figure 40 ? spi interface timing srclk sren (master) srdi sren (slave) srdo ts spi th spi tp spi srcclk srcen srcdo tp spi
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 228 17.7 alarm interface (figure 41) (t a = -40c to +85c v ddall33 = 3.3v 5%, v dd1v8 = 1.8v 5%) table 55 ? alarm interface symbol description min max units t p los xclk to los, los_l1 output prop. time -50 50 ns figure 41 ? alarm interface timing xclk los los_l1 tp los 17.8 ingress clk/data interface (figure 42) table 56 ? ingress clk/data interface symbol description min max units iclk_in frequency (1.544mhz 200ppm or 2.048mhz 200 ppm) 1.544 ? 200ppm 2.048 +200ppm mhz iclk_in duty cycle 35 65 % ts ingress idata[8:1], ifp_in set-up time 20 ns th ingress idata[8:1], ifp_in hold time 20 ns tp ingress iclk_out to ifp_out propagation delay -20 50 ns
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 229 figure 42 ? ingress clk/data interface timing diagram iclk_in ts ingress th ingress idata[8:1] ifp_in iclk_out ifp_out tp ingress 17.9 egress clk/data interface (figure 43) table 57 ? engress clk/data interface symbol description min max units tp egress eclk to edata[8:1], efp propagation delay -20 50 ns figure 43 ? egress clk/data interface timing diagram eclk edata[8:1] efp tp egress
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 230 17.10 jtag port interface (figure 44) (t a = -40c to +85c v ddall33 = 3.3v 5%, v dd1v8 = 1.8v 5%) table 58 ? jtag port interface symbol description min max units tck frequency 1 mhz tck duty cycle 40 60 % ts tms tms set-up time to tck 50 ns th tms tms hold time to tck 50 ns ts tdi tdi set-up time to tck 50 ns th tdi tdi hold time to tck 50 ns tp tdo tck low to tdo valid 2 50 ns tv trstb trstb pulse width 100 ns
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 231 figure 44 ? jtag port interface timing ts tms th tms tms tck ts tdi th tdi tdi tp tdo tdo tck trstb tv trstb notes on octliu timing: 1. high pulse width is measured from the 1.4 volt points of the rise and fall ramps. low pulse width is measured from the 1.4 volt points of the fall and rise ramps. 2. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 3. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 4. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 5. maximum output propagation delays are measured with a 100 pf load on the sbi drop bus outputs (except dactive) and a 50 pf load on dactive and all other outputs. minimum output propagation delays are measured with a 0 pf load on the outputs.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 232 18 ordering and thermal information table 59 ? ordering information part no. description PM4318-BI 288-pin tape super ball grid array (tsbga) table 60 ? octliu theta jc part no. case temperature theta jc PM4318-BI -40c to +85c 1.0 c/w table 61 ? octliu junction temperature PM4318-BI maximum junction temperature for long term reliability 110 c table 62 ? octliu theta ja vs. airflow forced air (linear feet per minute) part no. case temperature theta j-a at 2.5 watts conv 100 200 300 400 500 dense board 1 32.8 30.1 28.3 27.2 26.7 26.5 PM4318-BI -40 c to 85 c jedec board 2 13.7 12.0 10.8 10.0 9.4 9.0 1. ? dense board is defined as a 3s3p board and consists of a 3x3 array of PM4318-BI devices located as close to each other as board design rules allow. all PM4318-BI devices are assumed to be dissipating maximum power. theta j-a listed is for the device in the middle of the array. 2. ? jedec board theta j-a is the measured value for a single thermal device in the same package on a 2s2p board following eia/jesd 51-3.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 233 19 mechanical information e d1,m a b c d e f g h j k l m n p r t u v w y aa ab 1 3 5 7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 22 bottom view a 1 ball corner b m m eee f f f c c a b e a s s e1,n a d b a top view a1 ball indicator a1 ball pad corner e aaa c 2x aaa c 2x seating plane bbb c c ddd c a1 a a2 side view 0.075 min d a-a section view ccc c notes: 1) all dimensions in millimeter. 2) dimension aaa denotes package body profile. 3) dimension bbb denotes parallel. 4) dimension ccc denotes flatness. 5) dimension ddd denotes coplanarity. 6) diameter of solder mask opening is 0.550 mm (smd). 6.
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 234 notes
preliminary pm4318 octliu datasheet pmc- 2001578 issue 3 octal e1/t1/j1 line interface device none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in t his document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the inform ation, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-inf ringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 2001 pmc-sierra, inc. pmc-2001578 (p3) issue date: april 2001 pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 604 .415.6000 contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com

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