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- i - typical applications features description e mbedding the wireless future.. ewm-900-fdtc low cost 902-928mhz full duple x a udio/data transceive r ? automated meter reading ? wireless handsets ? on-site paging ? asset tracking ? wireless alarm and security systems ? long range rfid ? automated resource management ? low cost ? 56 channels ? 3v operation ? small size: 1.22? x 0.82? ? no external parts are required ? simple serial programming interface ? rssi the ewm-900-fdtc is ideal for unlicensed voice and data applications. the transceiver module requires no external rf components except for the antenna. it is designed to make fcc and etsi approvals easy. the transceiver operates in full duplex. it can transmit and receive data and/or voice simultaneously. the receiver section employs a direct-conversion, zero if architecture, eliminating image frequency interference. the manufacturing- friendly dip style package and low-cost make the ewm-900-fdtc suitable for high volume applications.
- ii - document control created by steve montgomery 10/30/02 engineering review marketing review approved - engineering approved - marketing revision history revision author date description 1.0 sjm 10/30/01 document created 1.1 sjm 11/18/02 module pin-out diagram and table corrected 1.2 gwh 01/22/03 updated. 1.3 trm 11/26/03 fixed erroneous frequency table headers 1.4 gwh 2/10/04 updated to reflect rev d hardware.
- ii - table of contents typical app lications ............................................................................................ i featur es................................................................................................................ i descripti on ........................................................................................................... i document c ontrol............................................................................................... ii revision hi story.................................................................................................. ii table of figures ................................................................................................. iii pin out di agram.................................................................................................. 1 pin descrip tion.................................................................................................... 1 mechanical drawing ........................................................................................... 2 absolute maxi mum rati ngs ............................................................................... 2 detailed electrical specificat ions...................................................................... 2 notes:................................................................................................................... 3 circuit descr iption.............................................................................................. 5 theory of op eration............................................................................................ 5 configurat ion ...................................................................................................... 6 reference frequency c ontrol regi ster .............................................................6 applications information.................................................................................. 11 power su pply ..................................................................................................11 ground ............................................................................................................11 transmitter star t-up time ...............................................................................11 transmitter channe l-change ti me .................................................................11 transmitter audio/data input require ments ...................................................11 receiver star t-up time...................................................................................12 receiver channe l-change ti me .....................................................................12 receiver audi o out put ....................................................................................12 receiver data output......................................................................................12 rssi ................................................................................................................12 ordering info rmation ........................................................................................ 12
- iii - table of figures figure 1, modul e pin diagram................................................................................................... ...... 1 table 1, ewm-900-fdtc m odule pin desc ription.......................................................................... 1 figure 2, mechanical draw ing of ewm- 900-fdtc ......................................................................... 2 table 2, absolute maximum ratings.............................................................................................. .2 table 3, detailed electr ical specifications .................................................................................... .. 3 figure 3, block di agram of module .............................................................................................. ... 4 figure 4, serial progr amming wave forms. ..................................................................................... 6 table 4, reference fr equency register ......................................................................................... 6 table 5, register address bits ................................................................................................. ....... 6 table 6, receiv e vco re gister .................................................................................................. .... 7 table 7, transmit vco register ................................................................................................. .... 7 table 8, mode c ontrol register................................................................................................. ...... 8 table 9, receive/transmit channel progra mming table ............................................................... 9 figure 5, evaluation boar d schematic diagram ........................................................................... 10 table 10, orderi ng information................................................................................................. ..... 12
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 1 revision 1.2 - 2/11/2004 pin out diagram figure 1, module pin diagram pin description pin no. pin name description 1 gnd transceiver ground. connect to ground plane. 2 ant 50 ohm antenna input. 3 gnd transceiver ground. connect to ground plane. 4 gnd transceiver ground. connect to ground plane. 5 gnd transceiver ground. connect to ground plane. 6 gnd transceiver ground. connect to ground plane. 7 audio receive audio output. 8 nc no connection. 9 gnd transceiver ground. connect to ground plane. 10 clk serial programming interface clock. 11 dat serial programming interface data. 12 le serial programming interface latch enable. 13 rssi receive signal strength indicator. 14 rxd receive data output. 15 txd/audin transmit data/audio input. 16 vcc power supply. vcc should be bypassed with a .01uf ceramic capacitor and filtered with a 4.7uf tantalum capacitor. noise on the power supply will degrade re ceiver sensitivity. table 1, ewm-900-fdtc module pin description
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 2 revision 1.2 - 2/11/2004 mechanical drawing figure 2, mechanical drawing of ewm-900-fdtc absolute maximum ratings parameter min max units power supply & all input pins -0.3 +12 vdc soldering temp (10 sec) 350 c storage temperature -50 150 c operating temperature 0 70 c table 2, absolute maximum ratings detailed electrical specifications parameter (general) min typ. max units notes operating voltage 2.7 3.0 3.3 volts dc sleep current 5 ua rx current 35 ma tx current 26 ma parameter (receiver) min typ. max units notes audio sensitivity -109 dbm note 1 data sensitivity -100 dbm note 2 strong signal sinad 44 db note 3 input ip3 -1 dbm input p1db -18 dbm adjacent channel rejection 60 db tx carrier suppression 45 db lo feedthrough -65 dbm
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 3 revision 1.2 - 2/11/2004 audio output level 600 mv p-p data high voltage vcc-0.7 vcc volts dc data low voltage 0 0.7 volts dc rssi voltage range 0.1 2.1 volts dc rssi gain -32 mv/db rssi dynamic range 65 db parameter (transmitter) min typ. max units notes output power 0 dbm note 4 2 nd harmonic power -50 dbm note 4 3 rd harmonic power -60 dbm note 4 4 th harmonic power -70 dbm note 4 modulation bandwidth 0.3 10 khz data input high voltage vcc-0.7 vcc volts dc data input low voltage 0 0.7 volts dc peak deviation 25 khz pk table 3, detailed electr ical specifications notes: 1) 12db sinad, 1khz modulati on tone, 25khz frequency deviation. 2) 19.2kbit/second, 10 -5 ber, 25khz p-p deviation. 3) ?85dbm input level, 1khz tone, 25khz p-p deviation. 4) 50 ohm load.
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 4 revision 1.2 - 2/11/2004 figure 3, block diagram of module
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 5 revision 1.2 - 2/11/2004 circuit description the ewm-900-fdtc is a complete, fully integr ated fm/fsk transceiver module capable of full- duplex transmission and reception of voice and data. the transceiver operates on one of 56 channels in the 902-928mhz unlicensed band. no external rf components (except for the antenna) are required. the transceiver is configured via a 3-wire seri al programming interface comprised of le, dat, and clk. parameters that can be set using th is interface include transmit channel, receive channel, transmit enable, and receive enable. the unique zero-if receiver architecture allows for a simple, low-cost solution that does not exhibit the image frequency interference probl ems of traditional super-het designs. theory of operation a block diagram of the ewm-900-fdtc transceiver is shown in figure 3. the antenna input pin is connected directly to t he saw duplexer. the purpose of the duplexer is to separate the receive and transmit frequency bands, effectively combining them while isolating the transmit and receive circuitry. table 9 show s the frequency plan for -bs (base station) and - hs (handset) versions of the module. it should be noted that -bs modules can only talk to -hs modules and visa-versa because of the complimentary frequency plan. the receive port of the duplexer is connected to a low noise-amplifier. the purpose of the amplifier is to compensate for the signal loss th rough the duplexer and to improve the noise figure of the receiver. after the lna, the incoming carrier is directly converted to baseband (zero-if) using a pair of quadrature mixers. special dc offset correction ci rcuitry is employed to ensure proper operation at zero-if. after the mixers, the receive chain is split into a quadrature pair (i-chain and q-chain). following the quadrature mixers, a pair of variable gain amplifiers and low-pass-filters are used to amplify and filter the low-level input signal. bec ause the receiver uses a zero-if architecture, these filters can be realized on-chip using only resistors and capacitors, reducing the size and cost of the transceiver. the gain of the quadrature down-conversion mixers and variable-gain amplifiers is automatically controlled by an inter nal agc circuit. this is done to maintain linearity in the receive chain. the rssi circuit derives the rssi voltage from the q receive chain. demodulation is achieved by up-converting t he baseband to 140khz and digitizing the resultant frequency spectrum. a s pecial p/d circuit is used to demodulate the carrier and generate an analog waveform using a 9-bit d/a converter. in st rong signal conditions, this will result in a 44db sinad. the analog output is low-pass filtered to remove if noise. the demodulated output of the receiver is availabl e at two pins on the module. in data mode, pin 14 (rxd) should be used. in audio mode, pin 7 should be used. pin 14 is the unfiltered output. the transceiver includes on-board frequency synthes izers for the transmitter and the receiver. these are programmed through the serial progr amming interface discussed later in this document. the transmitter synthesizer includes a m odulation input that can be driven with digital or analog information. there is a 150hz high-pass filter on this input. therefore, dc voltage levels cannot be sent. the output of the transmitter synthesizer is connected to a power amplifier that boosts the out put power to +3dbm typical. after the losses through the duplexer, the output tr ansmit power is 0dbm typical.
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 6 revision 1.2 - 2/11/2004 configuration the transceiver is configured by programming four registers via a three-wire serial interface comprised of clk (pin 10), dat (pin 11), and le (pin 12). when le is high, bits are shifted in from dat on each rising edge of clk. the most significant bit of the most significant byte is shifted in first. bits 0 and 1 of byte 0 determine which register is programmed. figure 4, serial programming waveforms. reference frequency control register the value programmed into this register deter mines the reference frequency for the transceiver. for proper operation, the reference frequency must be set to 50khz. the programming word is: binary: 00000000 01000011 11000000 hex: 0x0043c0 bit position 7 6 5 4 3 2 1 0 byte 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 2 table 4, reference frequency register bits 0 and 1 of byte 0 of all register programming words are the register select bits, as described in the following table. the reference fr equency should be fixed at 50khz and should not be changed. table 5, register address bits bit 1 bit 0 register 0 0 reference frequency control 0 1 rx vco control 1 0 tx vco control 1 1 mode control each register is either 22 or 23 bits. for consistency?s sake, 24 bits should be shifted into the dat pin to successfully program a register. when le transitions high, the incoming bits are stored in a shift register until le transitions low. on the falling edge of the transition, the c ontents of the shift register are transferred to the appropriate control register.
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 7 revision 1.2 - 2/11/2004 bit position 7 6 5 4 3 2 1 0 byte a count [2:0] f register [2:0] register sel [1:0] a 2 a 1 a 0 f 2 f 1 f 0 0 1 0 m count [5:0] a count [4:3] m 5 m 4 m 3 m 2 m 1 m 0 a 4 a 3 1 pad trim [1:0] m count [9:6] 0 0 t 1 t 0 m 9 m 8 m 7 m 6 2 table 6, receive vco register the receive vco control register determines t he operating channel of the receiver. the receive frequency is determined by the values of the a, f, and m counters. the trim bits are used to adjust the tuning range of the receive vco. the trim value is determined at the factory and is provided with each module. it is clearly marked on t he top of the module in indelible ink on either the module?s pcb or, on newer modules, indicat ed on the product barcode sticker. the number is two digits. the second digit repres ents the rx vco trim value. the actual receive frequency can be calculated using the following formula: f=50e3 * (32 * m) + a +(f/8) example: calculate the a, m, and f values for a base station (bs) receive frequency of 926 mhz. m=578 a=24 f=0 for this example, assuming a trim value of 2, the programming word will be: binary: 00101001 00001011 00000001 hex: 0x290b01 table 9 lists the receive frequency and register va lues for each of the 56 receive channels. the table lists these values for both the - bs and -hs versions of the transceiver. bit position 7 6 5 4 3 2 1 0 byte a count [2:0] f register [2:0] register sel [1:0] a 2 a 1 a 0 f 2 f 1 f 0 1 0 0 m count [5:0] a count [4:3] m 5 m 4 m 3 m 2 m 1 m 0 a 4 a 3 1 pad trim [2:0] m count [9:6] 0 t 2 t 1 t 0 m 9 m 8 m 7 m 6 2 table 7, transmit vco register
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 8 revision 1.2 - 2/11/2004 the transmit vco control register determines the operating channel of the transmitter. the receive frequency is determined by the va lues of the m, a, and f counters. note that the tx register has thr ee trim bits, where the rx register has only two. the trim bits are used to adjust the tuning range of the transmit vco. the trim value is determined at the factory and is provided with each module. it is clearly ma rked on the top of the module in indelible ink. the number is two digits. the first digit represent s the tx vco trim value. the actual transmit frequency can be calculated using same formula as for the receive register. see the receive register description for more information on calculating the m, a, and f values. table 9 lists the m, a, and f values for each channel. use this table to quickly determine the values for programming. bit position 7 6 5 4 3 2 1 0 byte 0 0 1 txe rxe 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 dat* 2 table 8, mode control register the mode control register determines the operating modes of the transceiver. with the register, the designer can turn on and off the transmitte r and operating channel of the transmitter. the receive frequency is determined by the va lues of the m, a, and f counters. note that the tx register has thr ee trim bits, where the rx register has only two. the trim bits are used to receiver sections of the transceiver. rxe determines the state of the receiver. when the bit is set to 1, the receiver is on. when the bit is set to 0 the bit is off. txe determines the state of the transmitter. when t he bit set to 1, the transmitter is on. when the bit is set to 0, the bit is off. the transceiver is placed in power-down mode by turning both the transmitter and receiver off. in this mode, the transceiver will draw <5ua. the on-board crystal oscillator is automatically enabled when either the transmitter or receiver is enabled. dat determines the operating mode of the transmitte r/receiver. when this bit is set to 1, the internal data-slicer is enabled. this allows data reception. when the dat bit is set to 0, then internal data-slicer is disabled for audio reception.
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 9 revision 1.2 - 2/11/2004 rx: ewm-900-fdtc-bs tx: EWM-900-FDTC-HS rx: EWM-900-FDTC-HS tx: ewm-900-fdtc-bs channel frequency m a f frequency m a f 0 902.250 563 29 0 924.850 578 1 0 1 902.300 563 30 0 924.900 578 2 0 2 902.350 563 31 0 924.950 578 3 0 3 902.400 564 0 0 925.000 578 4 0 4 902.450 564 1 0 925.050 578 5 0 5 902.500 564 2 0 925.100 578 6 0 6 902.550 564 3 0 925.150 578 7 0 7 902.600 564 4 0 925.200 578 8 0 8 902.650 564 5 0 925.250 578 9 0 9 902.700 564 6 0 925.300 578 10 0 10 902.750 564 7 0 925.250 578 11 0 11 902.800 564 8 0 925.400 578 12 0 12 902.850 564 9 0 925.450 578 13 0 13 902.900 564 10 0 925.500 578 14 0 14 902.950 564 11 0 925.550 578 15 0 15 903.000 564 12 0 925.600 578 16 0 16 903.050 564 13 0 925.650 578 17 0 17 903.100 564 14 0 925.700 578 18 0 18 903.150 564 15 0 925.750 578 19 0 19 903.200 564 16 0 925.800 578 20 0 20 903.250 564 17 0 925.850 578 21 0 21 903.300 564 18 0 925.900 578 22 0 22 903.350 564 19 0 925.950 578 23 0 23 903.400 564 20 0 926.000 578 24 0 24 903.450 564 21 0 926.050 578 25 0 25 903.500 564 22 0 926.100 578 26 0 26 903.550 564 23 0 926.150 578 27 0 27 903.600 564 24 0 926.200 578 28 0 28 903.650 564 25 0 926.250 578 29 0 29 903.700 564 26 0 926.300 578 30 0 30 903.750 564 27 0 926.350 578 31 0 31 903.800 564 28 0 926.400 579 0 0 32 903.850 564 29 0 926.450 579 1 0 33 903.900 564 30 0 926.500 579 2 0 34 903.950 564 31 0 926.550 579 3 0 35 904.000 565 0 0 926.600 579 4 0 36 904.050 565 1 0 926.650 579 5 0 37 904.100 565 2 0 926.700 579 6 0 38 904.150 565 3 0 926.750 579 7 0 39 904.200 565 4 0 926.800 579 8 0 40 904.250 565 5 0 926.850 579 9 0 41 904.300 565 6 0 926.900 579 10 0 42 904.350 565 7 0 926.950 579 11 0 43 904.400 565 8 0 927.000 579 12 0 44 904.450 565 9 0 927.050 579 13 0 45 904.500 565 10 0 927.100 579 14 0 46 904.550 565 11 0 927.150 579 15 0 47 904.600 565 12 0 927.200 579 16 0 48 904.650 565 13 0 927.250 579 17 0 49 904.700 565 14 0 927.300 579 18 0 50 904.750 565 15 0 927.350 579 19 0 51 904.800 565 16 0 927.400 579 20 0 52 904.850 565 17 0 927.450 579 21 0 53 904.900 565 18 0 927.500 579 22 0 54 904.950 565 19 0 927.550 579 23 0 55 905.000 565 20 0 927.600 579 24 0 table 9, receive/transmi t channel programming table
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 10 revision 1.2 - 2/11/2004 figure 5, evaluation b oard schematic diagram
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 11 revision 1.2 - 2/11/2004 applications information figure 5 shows the schematic diagram of our eval uation board. all of the transceiver parameters in the specification sheet were determined on this board. power supply the transceiver is designed to operate from a 3v dc power supply. power is provided to the transceiver on pin 16. this power supply shoul d be noise-free. noise on the power supply will degrade the receiver sensitivit y, thereby decreasing range. ground it is important to have a good ground system for any wireless design. the ground plane serves as a base reference for the operation of rf circui try. all filters are referenced to ground. all oscillators are referenced to ground. if the ground system design is bad, rf circuitry may not function correctly. the results may be r educed performance or spurious emissions. as a rule of thumb, it is best to use a solid fill ground plane to connect all of the ground pins of the transceiver. transmitter start-up time the start-up time for the transmitter is determi ned mainly by the loop bandwidth of the pll loop filter. when the transmitter is enabled by setting the txe bit in the mode register to a 1, it can take up to 20msec for the transmitter to be on-channel and ready to transmit information. transmitter channel-change time the channel change time for the transmitter is the time it takes for the transmitter to be locked onto the new channel after programming the tx c hannel register. for a 1mhz jump, the channel change time is 11msec. for a 100khz ju mp, the channel change time is 7 msec. transmitter audio/data input requirements the txd/audin pin is connected to the trans mit vco. voltage changes on this pin will frequency modulate the vco. the input impedance of this pin will vary from module to module as required to set the proper frequency deviation. therefore, the pin must be driven by a low impedance source. if the driving circuit is digital, it must have a push-pull outpu t. if the driving circuit is analog, the signal should be buffered by an operational amplifier. a 3v p-p signal present at this pin will result in a +/-25khz frequency deviation. there is a 150hz high-pass response on this pin due to the tx pll loop filter. therefore, the transmitter is not capable of transmitting dc volt age levels. the bandwidth of the signal used to modulate the transmitter should be between 300h z and 15khz. for data applications, the baud rate should be between 9600 bps and 19.2kbps.
ewm-900-fdtc full duplex voice/ data transceiver data sheet ewm-900-fdtc data sheet page 12 revision 1.2 - 2/11/2004 receiver start-up time like the transmitter, the receiver start-up time is determined by the loop bandwidth of the pll loop filter. when the receiver is enabled by setting t he rxe bit in the mode register to a 1, it can take up to 20msec for the receiver to be on-channel and ready to receive information. receiver channel-change time the channel change time for the receiver is the time it takes for the receiver to be locked onto the new channel after programming the rx channel register. for a 1mhz jump, the channel change time is 7msec. for a 100khz jump, the channel change time is 5 msec. receiver audio output (audio mode only) the receiver audio output is the analog signal direct ly from the fm demodulator. it is filtered by a 3rd order lpf with a cu t-off frequency of 15khz. the audio signal is 600mv typically. the receiver sensitivity can be increased for audio applications by using an external lpf with a 4khz cutoff frequency. without this filter, the audio sensitivity is - 109dbm for a 12db sinad. with this filter, the sensitivity should improve by 3-6db. receiver data output (data mode only) the receiver data output is the digital signal from the bit-slicer. it repr esents the binary data used to modulate the transmitter in data applications. the data output is rail-to-rail and is compatible with cmos and ttl signal levels. rssi the rssi pin indicates the received signal str ength of the incoming carrier via a dc voltage. the rssi dynamic range is 65db. howeve r, the lna extends this dynamic. the rssi will indicate from -112 to -62dbm. the voltage range is 0.1 to 2.1 v with 0.1v representing -62dbm. note: the rssi is not a calibrated value. t he actual signal range, dynamic range, and voltage will vary from part to part. the lna should be turned off by bringing lnaen low whenever the input signal level is above -70dbm. ordering information product order code ewm-900-fdtc-bs 100-900-01a EWM-900-FDTC-HS 100-900-02a table 10, ordering information

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