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advance data sheet february 1997 4 features n compliant with iso 8802.3 - 1993, ieee * 802.3u - 1995, and ieee 802.3x - 1995 standards for media access control: ?data transmission and reception rates of 10 mbits/s at a clock speed of 2.5 mhz or 100 mbits/s at a clock speed of 25 mhz. ?state machines for implementing the mii inter- face support standards-based connectivity to a variety of physical layer devices (phys). ?transmits or receives at full- or half-duplex. ?supports ?w control. ?supports both level 1 and level 2 vlan frame recognition. n extensive network management signals are pro- vided. n transmit and receive functions can be asynchro- nously reset with no clocks present. n supports full internal scan test methodology. n designed using verilog ? hdl. n suitable for lucent technologies 0.5 m m and 0.35 m m cmos technology (3 v or 5 v operation). n a kit part and evaluation board is planned for eval- uating the macrocell: ?the kit part provides a cpu interface for regis- tered access to con?uration and status signals, management counters, and the mii manage- ment interface. ?all con?uration and status signals also go to pins to facilitate prototyping asic logic around the macrocell. n companion macrocells planned: ?10 mbits/s and 100 mbits/s transceivers. ?autonegotiation. ?content addressable memory (cam). * ieee is a registered trademark of the institute of electrical and electronics engineers, inc. ? verilog is a registered trademark of cadence design systems, inc. description the DNCM01 is an 802.3u - 1993 compliant macro- cell capable of both 10 mbits/s and 100 mbits/s data operation. the mac interfaces with a transceiver through a media independent interface (mii). the transmit and receive clocks are 2.5 mhz or 25 mhz, depending on which speed the phy is running. the DNCM01 supports half-duplex and full-duplex opera- tion. the DNCM01 is capable of transmitting and receiving mac control frames, including the pause opcode. the DNCM01 allows full-duplex ?w control using the pause opcode. the DNCM01 supports both level 1 and level 2 vlan tagging. the DNCM01 is able to increase the maximum legal byte count when frames are transmitted or received with level 1 or level 2 vlan tags. all transmit and receive functions can be asynchronously reset with no clocks present. the DNCM01 can be used with full internal scan test methodology to ease test devel- opment time and increase fault coverage. this data sheet also describes the kit part for evalua- tion of the DNCM01 macrocell. the kit part has a cpu interface providing access to registers that control transmit con?uration and report transmit status and receive status. the kit part con?uration signals are the logic or of the con?uration pins and con?uration register bits. the kit part status signals are available as both register bits and output pins. figure 1 shows the DNCM01 block diagram. DNCM01 10/100 ethernet mac asic macrocell note: advisories are issued as needed to update product information. when using this data sheet for design purposes, please contact your lucent technologies microelectronics group account manager to obtain the latest advisory on this product.
2 lucent technologies inc. DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 description (continued) figure 1. DNCM01 (shown in dotted lines) and DNCM01 kit part block diagram test logic registers event counter data address tx control tx data rx data rx control transmit DNCM01 macrocell DNCM01 kit part tx data rx data rx control & status tx control & status tx control tx status mii port flow control receive rx control rx status tx data rx data tx data rx data duplex pause mdio mdc 5-5113 (f)
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 3 4 signal information table 1. mii signal descriptions (16 signals) signal type description col i collision (active-high). used to indicate a collision between two stations. assumed to be active a minimum of two tx_clk cycles. col is only sampled during half-duplex transmit operations when txe is active, and during the ?st 64 bit times of interpacket gap time after any (normal or aborted) transmission if isqe is active. crs i carrier sense. asynchronously asserted by the physical layer when traf? is detected on the medium. rx_clk i receive clock. 2.5 mhz or 25 mhz receive clock. rx_clk is sourced by the physical layer device. rxd[3:0] i receive data. 4-bit nibble containing received data. rxd is valid on the rising edge of rx_clk. rx_dv i receive data valid. used to indicate that the data nibble on rxd has been decoded. rx_err i receive error. rx_err will be asserted by the phy when it has detected an error with the frame currently being received that the DNCM01 may not be able to detect. tx_clk i transmit clock. 2.5 mhz or 25 mhz 50% duty cycle, continuously running. tx_clk clocks all transmitter and timer logic. tx_clk is sourced by the phy. txd[3:0] o transmit data. 4-bit nibble with data to be transmitted. txd is driven on the rising edge of tx_clk. tx_err o transmit error. the DNCM01 does not implement this function at this time. tx_en o transmit enable. indicates that a transmission is in progress. table 2. kit part cpu interface signal descriptions (29 signals) signal type description mdc o management data clock. 2.5 mhz (maximum) clock to exchange management data with a device on mdio. mdio i/o management data. bidirectional management data for external device. rst i reset (active-high). assumed to be asynchronous. used to reset state machines, counters, and critical logic in the cpu interface. cpustrb i cpu strobe (active-low). during a write, this signal indicates that the data on cpudb[7:0] bus is valid and can be latched into the mac. during a read, this signal indicates that the mac should drive cpudb[7:0]. cpuad[2:0] and cpur/w are sampled on the falling edge of cpustrb. cpur/w i cpu read/write. indicates which direction the cpu data bus is in for the current register or counter access. this signal should be driven high when reading a register/ counter and low when writing a register. cpurdy o cpu ready (active-low). this signal indicates that the mac has latched data dur- ing a write cycle and has placed valid data onto the bus during a read cycle. an external 1 k w pull-up resistor is required. cpudb[15:0] i cpu data bus. this data bus is used by the cpu to write and read registers and to read counters inside the DNCM01. cpuad[4:0] i cpu address bus. the address bus is used by the cpu to indicate which register/ counter is being read or written. hclk i host clock. clock for the DNCM01, supplied by the host. selpll i select pll. selects the divisor of the host clock for the mdc clock of the mii inter- face. high?igh-speed hclk, mdc = hclk/32 low?ow-speed hclk, mdc = hclk/16
4 lucent technologies inc. DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 signal information (continued) table 3. tx control signal descriptions (31 signals) signal type description txrst i transmit reset (active-high). assumed to be asynchronous. used to reset state machines and critical logic in the transmitter. invcrc i invert crc (active-high). used to invert the polarity of the 32-bit crc polynomial. the normal crc is inverted prior to transmission. if invcrc is high, the normal crc is re- inverted prior to sending, forcing a crc error. apndcrc i append crc (active-high) . used to control if a 32-bit crc polynomial is appended to the end of transmitted packet. if high, the crc is appended. retry[1:0] i retry. used to control the total number of attempts (initial + retries after collision) the mac makes to transmit a packet. the total attempts follow the table below: retry1 retry0 attempts 00 16 01 8 10 4 11 1 bsel i backoff select (active-high). used to control whether the binary backoff algorithm is used during collision handling. if bsel is high, the backoff algorithm is not used. the transmitter jams for 32 tx_clk cycles and attempts to retransmit after 96 bit times (nor- mal ifg). if low, the transmitter follows the normal binary backoff algorithm following a collision. defer i defer (active-high). used to force the transmitter to abort a transmission attempt if it has deferred for more than 24,288 tx_clk cycles. deferring starts when the transmitter is ready to transmit, but is prevented from doing so because crs is active. defer time is not cumulative. if the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of backoff, the deferral timer resets to 0 and restarts. if defer is low, the transmitter defers inde?itely. mfdup i mac full duplex (active-high). used to control half- or full-duplex operation. when mfdup is low, the col input is monitored and the binary backoff algorithm is employed if collisions occur during transmission. when mfdup is low and crs is asserted while the macs own packet is being transmitted, the receiver is not enabled since the received packet is the macs own transmitted packet. when mfdup is high, all packets are received regardless of the status of txe. txreq i transmit request (active-high). used to request a packet transmission. txreq is a handshake signal and should be held high until txack is activated by the transmitter. txreq should not be activated until txeop is returned by the transmitter. txabort i transmit abort (active-high). used to stop a transmission ungracefully. the transmit- ter immediately terminates a transmission if this input is set. txabort should be held high for two or more tx_clk cycles. when a packet is aborted during preamble, the pre- amble is completed and the apndcrc and invcrc inputs are followed. if txabort is activated during transmission, transmission immediately stops, and the apndcrc and invcrc inputs are followed.
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 5 4 signal information (continued) table 3. tx control signal descriptions (31 signals) (continued) signal type description txack o transmit acknowledge (active-high). used in conjunction with txreq as a hand- shake. when txack goes high in response to txreq, txreq can be deactivated. txinprog o transmit in progress (active-high). this output is set high if the mac is currently transmitting preamble, data, or crc. txinprog will not be active if the transmitter is deferring in collision backoff. txeod i transmit end of data (active-high). used to end a transmit operation normally. txeod should activate one clock after the dma receives a txld from the transmitter. the transmitter loads and transmits that byte, and then transmits crc according to the status of apndcrc and invcrc. txsop o transmit start of packet. active for 1 bit time at the start of preamble. valid on the positive edge of tx_clk. txdin[7:0] i transmit data in. txdb is loaded into the transmit shift register on the falling edge of the txld input. the lsb is transmitted ?st. txld o transmit load data (active-high). used to tell that the mac transmitter requires a byte of data for transmission. txdb[7:0] is strobed into the transmit shift register on the falling edge of txld. valid on the positive edge of tx_clk. txeop o transmit end of packet (active-high). used to indicate the end of transmit operation. the operation may end because of successful transmission, excessive collisions, excess deferral or an txabort command. txeop is active for 1 tx_clk cycle. transmit statistics, except for sqe, should be latched on the falling edge of txeop. valid on positive edge of tx_clk. sqe should be latched on the falling edge of txsop of the following frame. cntrl i send control frame. used to indicate that the current frame is a control frame. the destination will be the reserved multicast address. the control opcode and pause time data will be sent to txdb[7:0] and the transmit control signals will be valid. this signal may be deactivated after cntrlack. cntrlack o control acknowledge (active-high). used in conjunction with cntrl as a hand- shake. when cntrlack goes high in response to cntrl, cntrl may be deacti- vated. isqe i ignore sqe test. used to ignore the sqe signal from the phy during the ?st 64 bit times of interframe gap. if high, the sqe error ?g will not be set. fcsop o flow control start of packet (active-high). activates for 1 txc at the start of trans- mission of a ?w control frame, synchronous with txc. fceop o flow control end of packet (active-high). activates for 1 txc at the end of trans- mission of a ?w control frame, synchronous with txc. transmit statistics can be strobed using fceop as a strobe. pream[1:0] i preamble. used to control the number of preamble bits that will be transmitted before the start of frame delimiter. pream1 pream0 preamble 0 0 56 bits 0 1 48 bits 1 0 40 bits 1 1 8 bits
6 lucent technologies inc. DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 signal information (continued) table 4. rx control signal descriptions (13 signals) signal type description rxbyte[7:0] o receive byte (active-high). an 8-bit latch that holds a byte of receive data. valid on positive edge of rx_clk. rxrst i receive reset (active-high). assumed to be asynchronous. used to reset state machines and critical logic in the receiver. valid on positive edge of rx_clk. rxsop o receive start-of-packet (active-high). indicates that the receiver has detected that crs is high and that rx_clk is being generated. receive statistics are reset on the falling edge of rxsop. valid on the positive edge of rx_clk. rxsfd o receive start-of-frame delimiter (active-high). indicates that a start-of-frame delimiter has been detected in a received packet (10101011). valid on positive edge of rx_clk. rxeop o receive end-of-packet (active-high). indicates that crs has gone inactive and that receive statistics are valid for reading. valid on positive edge of rx_clk. rxbvld o receive byte valid (active-high). active for 1 bit time after a new receive byte has been loaded into the rxbyte[7:0] latch. valid on positive edge of rx_clk. table 5. tx status signal descriptions (19 signals) signal type description txbyte o transmit byte. indicates that a complete byte of data or crc has been transmit- ted. txbyte is valid for 1 tx_clk bit time immediately after the last bit of a byte was transmitted. valid on the positive edge of tx_clk. exdef o excessive deferral (active-high). indicates transmission ended because of waiting for more than 24,288 bit times for the medium to become not busy. valid on the positive edge of tx_clk. def o deferral (active-high). indicates that a transmission deferred for 1 bit time to 24,288 bit times during transmission. valid on the positive edge of tx_clk. scol o single collision (active-high). indicates that there was one collision during transmission of the previous packet. valid on the positive edge of tx_clk. mcol o multiple collisions (active-high). indicates that there was more than one colli- sion during the transmission of the previous packet. valid on the positive edge of tx_clk. cerr o collision error (active-high). indicates that the previous transmission was stopped because of excessive collisions as allowed by the retry[1:0] inputs. scol and mcol are also valid if cerr is active. valid on the positive edge of tx_clk. coldet o collision detected (active-high). indicates that a collision has been detected. this signal is active from the time of a collision until the completion of the 32-bit jam sequence. the col signal is monitored only when the transmitter is actively transmitting data. valid on the positive edge of tx_clk.
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 7 4 signal information (continued) table 5. tx status signal descriptions (19 signals) (continued) signal type description lcrs o loss of carrier (active-high). indicates that the crs input was inactive for one or more bit times while the transmitter is active and in half duplex. valid on the positive edge of tx_clk. aborted o transmission aborted (active-high). indicates that a transmission has been aborted before completion. valid on the positive edge of tx_clk. late o late collision (active-high). indicates that a collision occurred more than 512 bit times from the start of a transmission. the start of transmission is de?ed as the transmission of the ?st bit of preamble. valid on the positive edge of tx_clk. tcntrl o mac control frame transmitted. indicates that the last packet sent was a mac control frame. valid on the positive edge of tx_clk. tpause o pause frame transmitted. indicates that the last mac control frame sent was a pause frame. valid on the positive edge of tx_clk. sqefail o sqe test failed (active-high). indicates that a col signal was not detected during the ?st 6.4 m s of interframe gap following a transmit attempt. sqe is inac- tive if the isqe input is high. valid on the positive edge of tx_clk. sqevalid o sqe valid. this signal goes active 6.4 m s after the end of transmission to indicate to the dma that the sqefail signal contains valid information. pauseactive o pause active (active-high). active while the transmitter is blocked from trans- mitting after the reception of a pause command. this output is synchronous with txc. tx_vlan2 o two-level vlan frame. when this signal is set, the current transmission is tagged with a vlan2 id. the thirteenth and fourteenth bytes at the frame are compared to the two-level vlan tag register. this signal is set if there is a non- zero match. tx_vlan1 o one-level vlan frame. when this signal is set, the current transmission is tagged with a vlan1 id. the thirteenth and fourteenth bytes at the frame are compared to the one-level vlan tag register. this signal is set if there is a non- zero match. txbroad o transmit broadcast (active-high). active from txeop (fceop) to txsop (fcsop) of the following frame, synchronous with txc. txeop can be used to strobe txbroad. txbroad is active if the transmitted frame has a destination address of all 1s. txmult o transmit multicast (active-high). active from txeop (fceop) to txsop (fcsop) of the following frame, synchronous with txc. txeop can be used to strobe txmult. txmult is active if the transmitted frame has a destination address with the ?st transmitted address bit a 1 and at least one of the following 47 address bits a 0.
8 lucent technologies inc. DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 signal information (continued) table 6. rx status signal descriptions (35 signals) signal type description ifg o short ifg (active-high). indicates that the interframe gap prior to the start of the packet was less than 76 bit times. valid on the positive edge of rx_clk. rxjab o receive jabber error (active-high). indicates that receive packet length was greater than 1518 bytes, and the packet had a bad crc or fae. valid on the pos- itive edge of rx_clk. fae o frame alignment error (active-high). indicates a packet was received with a frame alignment error. an fae occurs when the resultant remainder from the divi- sion between the number of bits in a frame and eight is nonzero (nonintegral number of octets), the crc is invalid, and the octet counters are greater than or equal to 64 and less than or equal to 1518. valid on the positive edge of rx_clk. dribble bits have no effect. crc o crc error (active-high). indicates a packet was received with a bit count hav- ing a mod 8 remainder equal to 0, and that packet had an incorrect crc. valid on the positive edge of rx_clk. runt o runt packet (active-high). indicates a packet was received with a byte count (including crc) <64, and the packet had a good crc. valid on the positive edge of rx_clk. frag o fragment (active-high). indicates a packet was received with a byte count (including crc) <64, and the packet had a bad crc or fae. valid on the positive edge of rx_clk. long o frame long error (active-high). indicates that the received packets length was greater than 1518 bytes, and the packet had good crc. valid on the positive edge of rx_clk. phys o received physical address (active-high). indicates that the ?st bit of the received packet was 0, and that at least 6 bytes of data were received. valid on the positive edge of rx_clk. mult o received multicast address. indicates that the ?st bit of the received packet was 1, all address bits were not 1, and that at least 6 bytes of data were received. valid on the positive edge of rx_clk. broad o received broadcast address. indicates that all 48 address bits of a received frame are 1. valid on the positive edge of rx_clk. nulpkt o null packet . indicates that crs and rx_clk were active for some time and that no sfd sequence was detected. valid on the positive edge of rx_clk. rxcount[15:0] o received byte counter . a 16-bit counter that indicates the number of full bytes received in the current packet. this counter freezes at ffff bytes. this counter clears on read. rcntrl o mac control frame received. indicates that the last packet received was a valid mac control frame. valid on the positive edge of rx_clk. runsup o unsupported opcode received. indicates that the last mac control frame received had an unsupported opcode. valid on the positive edge of rx_clk. rpause o pause frames received. indicates that the last control frame received has a multicast address, length/type ?ld, and opcode for the pause operation. valid on the positive edge of rx_clk. rx_vlan2 o two-level vlan frame. when this signal is set, the current reception is tagged with a vlan2 id. the 13th and 14th bytes at the frame are compared to the two- level vlan tag register. this signal is set if there is a nonzero match.
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 9 4 signal information (continued) table 6. rx status signal descriptions (35 signals) (continued ) signal type description rx_vlan1 o one-level vlan frame. when this signal is set, the current reception is tagged with a vlan1 id. the 13th and 14th bytes at the frame are compared to the one- level vlan tag register. this signal is set if there is a nonzero match. epause o early pause (active-high). a frame with the control multicast address, the con- trol type/length ?ld, and the pause opcode was received. this output is valid prior to eop. ecntrl o early control . active from the 18th byte of an incoming control frame until rxsop of the following frame, synchronous with rxc. rxerout o receive error output (active-high). active from rxeop of an incoming frame to rxsop of the next frame, synchronous with rxc. rxeop can be used to strobe rxerout. rxerout will activate if the rx_err input from the mii acti- vates for 1 or more clocks while rx_dv is high. table 7. control frame con?uration signal descriptions (101 signals) signal type description cfd0[15:0] i control frame destination address 0. these signals represent the ?st 16 bits of the 48-bit reserved multicast address for control frames. cfd1[15:0] i control frame destination address 1. these signals represent the second 16 bits of the 48-bit reserved multicast address for control frames. cfd2[15:0] i control frame destination address 2. these signals represent the third 16 bits of the 48-bit reserved multicast address for control frames. cft i control frame type . the assigned 2-octet length/type ?ld of a mac control frame. cfo i control frame opcode . the 2-octet mac control opcode ?ld indicating the mac control function. cftv1 i vlan type 1 type field . the assigned 2-octet length/type ?ld of a vlan type 1 packet. cftv2 i vlan type 2 type field . the assigned 2-octet length/type ?ld of a vlan type 2 packet. cfs0[15:0] i control frame source address 0. these signals represent the ?st 16 bits of the 48-bit source address for control frames. cfs1[15:0] i control frame source address 1. these signals represent the second 16 bits of the 48-bit source address for control frames. cfs2[15:0] i control frame source address 2 . these signals represent the third 16 bits of the 48-bit source address for control frames. cfdata i control frame data . two octets provided for the data ?ld inside the control frame.
10 DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 signal information (continued) table 8. test signal descriptions (2 signals) signal type description tstmode i test mode. used to modify the terminal count of transmit counters to speed up testing. when tstmode is high, the counters are modi?d as follows: counter normal count modi?d count 51.2 m s timer 512 3 defer timer 24288 242 rstrndm i reset random binary backoff algorithm. used to reset the random backoff timer. netlist order inputs, outputs:txrst, rxrst, tx_clk, hclk, col, mfdup, retry, bsel, pream, isqe, defer, txreq, txeod, txabort, apndcrc, invcrc, tstmode, rstrndm, txdin, cntrl, cfd0, cfd1, cfd2, cft, cfo, cftv1, cftv2, cfs0, cfs1, cfs2, cfdata, txack, txin- prog, txld, txeop, late, exdef, def, coldet, scol, mcol, cerr, lcrs, sqefail, sqevalid, txbyte, txsop, aborted, txd, tx_en, tx_err, rx_clk, crs, rx_dv, rx_err, rxd, rxcount, rxsop, rxsfd, rxeop, rxbvld, rxjab, fae, crc, runt, frag, long, phys, mult, broad, ifg, nulpkt, rxbyte, cntrlack, rcntrl, runsup, rpause, pauseac- tive, fcsop, fceop, txmult, txbroad, epause, rxerout, tx_vlan1, tx_vlan2, rx_vlan1, rx_vlan2, tcntrl, tpause, ecntrl functional description transmitter the transmitter in the DNCM01 is made up of a state machine, a preamble-jam counter block, a transmit counters block, a 32-bit crc generator, a 15-bit deferral time-out counter, and a transmit serializer. frame transmission a transmit operation is initiated by the host activating txreq. when txreq is recognized, the DNCM01 responds by activating txack. after txreq, the transmitter holds txack active until txreq is dropped; until the transmitter successfully sends the packet; or until transmit is aborted because of exces- sive collisions, excessive deferral, or host-initiated abort. transmission begins when the intergap timer has expired. if the timer has reached 9.6 m s (0.96 m s at 100 mbits/s) prior to txreq, packet transmission begins immediately. if txreq is given before 6.4 m s (0.64 m s at 100 mbits/s) of intergap and the DNCM01 was the station transmitting, the new packet begins transmission at 9.6 m s (0.96 m s at 100 mbits/s) regard- less of crs. if the timer is greater than 6.4 m s (0.64 m s at 100 mbits/s) and crs is high, the transmission defers until crs is deasserted, at which time, the 9.6 m s (0.96 m s at 100 mbits/s) timer activates, and transmission starts after time-out. transmitter operation is controlled by a state machine modeled after the one shown in appendix b of the 1993 version of iso 8802.3 standard. immediately prior to starting preamble, the DNCM01 sends a 1 tx_clk signal, txsop, to the host. another DNCM01 output, txinprog, is valid while the DNCM01 is actively transmitting.
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 11 4 functional description (continued) preamble is programmable by pream[1:0] to be 32, 40, 48, or 56 bits, and an 8-bit sfd (10101011) is appended after preamble. the DNCM01 has no address registers, so source and destination addresses must be included in the byte stream sent by the host. the DNCM01 does not provide automatic frame padding for frames less than 64 bytes. at the end of preamble, the DNCM01 sends one tx_clk signal, txld, to the host. the DNCM01 strobes in the byte to be transmitted on the falling edge of txld. after the ?st txld, subsequent requests are sent every two tx_clk cycles. after the last byte is sent by the host, the host signi?s the end of data by activating txeod for one tx_clk. after transmitting the last byte, the DNCM01 appends the crc to the data stream if the crc input to the DNCM01 is high. the crc can also be sent inverted if desired (to force a bad crc) by setting the invcrc input high. after completing transmission, the DNCM01 sends a txeop signal to the host. all transmit statistics (scol, mcol, cerr, aborted, exdef, etc.) except sqe can be latched on the falling edge of txeop. during transmission, the DNCM01 activates txbyte for one tx_clk for each byte it sends. for an n byte packet, the DNCM01 sends n + 4 txbyte signals if crc was appended. after successful transmission, the DNCM01 monitors the col input for an sqe test signal if the isqe input is low. col is monitored for the ?st 64 bits of intergap time. if sqe test is not observed, the sqe output is set to 1 and held until the next txsop signal. a control output sqefail is valid from 6.4 m s (0.64 m s at 100 mbits/s) until txsop of the next packet, and sqe is valid when sqefail is high. if another txreq is sent before 6.4 m s (0.64 m s at 100 mbits/s) of intergap time, the mac attempts to transmit the new packet regardless of crs. crs normally does not activate during this time if all stations are observing proper protocol, so this should be an infrequent event. collision retransmission the DNCM01 handles collision situations in accor- dance with iso 8802.3. the retry[1:0] inputs select 1, 4, 8, or 16 attempts to transmit, with retry[1:0] = 00 giving the standard 16 attempts. the standard backoff algorithm is used. the DNCM01 has a 12-bit pseudorandom shift register counter which free runs. the counter can be frozen for periods of time by driving the rstrndm input high. this signal can be driven by a decoded chip enable or some other unique signal to increase the randomness of a group of 10/100 base-t macs. when a collision is sensed, a 32-bit jam pattern (1111 . . .) is transmitted. after the jam pattern completes, n bits of the counter (n depends on the collision number) is dumped into a 10-bit counter which in turn decrements by the turnover of the 51.2 m s (5.12 m s at 100 mbits/s) timer. backoff lasts until the 10-bit counter reaches 0. transmission is retried if the 9.6 m s (0.96 m s at 100 mbits/s) timer has expired or is deferred until crs deactivates and the 9.6 m s (0.96 m s at 100 mbits/s) timer expires. if a deferral lasts longer than 24,288 bit times, the DNCM01 aborts transmis- sion if the defer input is set high. this also applies to a deferral at the start of regular transmission. deferral is not cumulative; it restarts from 0 each time a deferral state is entered. if a packet cannot be transmitted after making the selected number of attempts, the transmit is aborted and the cerr output is activated. if a colli- sion occurs during preamble, the preamble-sfd sequence is completed prior to jamming. the coldet output indicates the presence of a colli- sion situation to the host. if a late collision (after 512 bit times, including preamble and sfd) occurs, the late output is set high. the mac does not abort after a late collision is detected. this must be done by the host. if the DNCM01 detects a collision while transmitting, it always sends a jam pattern prior to deactivating txe regardless of the status of txabort, txeod, or the status of the collision counter. the host should always reset its transmit stack if the coldet output goes high to ensure complete packet transmission. the bsel input can be used to override the backoff timer if desired. if bsel is 1 and a collision is detected, the DNCM01 jams and retransmits when the 9.6 m s (0.96 m s at 100 mbits/s) ifg has expired. if the mfdup is high (full-duplex mode), the DNCM01 ignores the collision signal. receiver the DNCM01 receiver consists of a state machine, crc generator, 64 kbyte counter, and deserializer. when the DNCM01 detects a low-to-high transition of crs, and rx_clk is operating, it sends an rxsop signal to the host. the ?st 10 bits of preamble sensed are ignored. after the ?st 10 bits of preamble, an sfd sequence (10101011) causes an rxsfd signal to be sent. after rxsfd, the receiver buffers each byte of received data. after assembling the byte, one rx_clk time rxbvld signal is sent to the host. the host has two rx_clk times to read the byte from the rxbyte register. when crs falls, the receiver monitors the
12 lucent technologies inc. DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 functional description (continued) result of crc calculated on the last full byte. if crc falls on a byte boundary, the packet is either good or has a crc error. if crs falls on a nonbyte boundary, but the last full byte received had a good crc, it is a good packet with dribble bits. if crs falls on a nonbyte boundary and the crc was bad, it is a frame alignment error. the receiver informs the host of the end of the packet by activating the rxeop output for 1 rx_clk. other receive statistics include rxjab (packet with > 1518 bytes and a crc or fae), long (>1518 bytes with good crc), nul (crs high for an inde?ite time with no sfd), and others which are described in the signal list. receive statistics are valid from rxeop to the next rxsop. if the mfdup input is low (half duplex), the receiver ignores any packets that start while txe is high, to avoid buffering ones own transmitted packet. in order to prevent glitches on crs during a collision situation from affecting the receiver, the receiver ignores high-to- low transitions of crs if a packet reception is in progress and the col signal is present. if mfdup is high (full duplex), the receiver ignores the col signal. the DNCM01 does not have any physical address registers or multicast address registers, nor does it have any multicast address group detection logic. it does have three outputs phys, mult, and broad, one of which activates after 6 bytes of data have been received. phys means the ?st bit of data in the packet was 0, mult means the ?st bit was 1 and at least 1 of the next 47 was 0, and broad is a 48-bit address of all 1s. flow control the DNCM01 allows full-duplex control using the pause operation. the pause operation is used to inhibit data transmission of data frames for a speci?d period of time. a pause operation consists of the frame containing the globally assigned multicast address (in the address block: 01-80-c2-00-00-01 through 01-80-c2-00-00-0f), the pause opcode, and a parameter indicating the quanta of slot time (512 bit times) to inhibit data transmissions. the pause parameter may range from 0 to 65,535 slot times. a DNCM01 receiving a frame with the multicast address and pause opcode will inhibit data frame transmis- sions of the length of time indicated. if a pause request is received while a transmission is in progress, then pause will take effect after the transmission is complete. control frames are received and processed by the mac and are passed on. the signal epause can be used to prevent having a control frame passed up to upper layers. to send pause frames, the DNCM01 may transmit control frames. to transmit a control frame, assert the cntrl signal. hold the cntrl signal active until the DNCM01 responds by activating cntrlack. the DNCM01 will automatically begin the transmission of a control frame after the 96 bit time ifg expires. if the transmitter is in the process of transmitting a frame, the control frame will be transmitted when the normal transmit is complete and the ifg timer expires. the DNCM01 will assert the txinprog signal until the transmission of the control frame has completed. the DNCM01 may transmit control frames if it has been paused by another station. vlan support the DNCM01 recognizes transmit and receive frames that are tagged with either one-level or two-level vlan ids. the DNCM01 compares the thirteenth and four- teenth bytes of transmit and receive frames to the contents of both the one-level vlan tag register and the two-level vlan tag register. if a nonzero match is made, the DNCM01 identi?s the frame as either a one-level or two-level vlan frame, but not both. upon recognizing that a frame has a vlan tag, counter thresholds are adjusted to account for the extra bytes that the vlan tag adds to the frame. if the frame is a one-level vlan frame, the maximum length of a good packet is changed from 1518 bytes to 1522 bytes. if the frame is a two-level vlan frame, the maximum length of a good packet is changed from 1518 bytes to 1538 bytes. in both cases, status signals are set indi- cating which vlan frame occurred. timing the kit parts address and data bus should have 20 ns setup and 10 ns hold time in respect to the falling edge of the cpustrb signal. register writes are synchro- nized to the appropriate clock; this may delay cpurdy. cpustrb should be held for one hclk after cpurdy is deasserted. transmit input signals require 20 ns setup and 10 ns hold time. transmit output signals are valid after a maximum of 20 ns after the appropriate positive edge of txclk. during a transmission, txdata is strobed in on the falling edge of txld. txbyte will be valid for one txclk after a byte has been transmitted. transmit status signals are valid from txeop of the current packet until txsop of the next packet.
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 13 4 functional description (continued) receive input signals require 20 ns setup and 10 ns hold time. receive output signals are valid after a maximum of 20 ns after the appropriate positive edge of rxclk. receive status signals are valid from rxeop of the current packet until rxsop of the next packet. early pause will be valid after the sixteenth byte of a pause frame has been received. general information the DNCM01 is approximately 8500 gates without scan logic or the cpu interface of the kit part. it exists as a fully synthesizable verilog * hdl behavioral/state table description and can easily be modi?d for speci? customer requirements. DNCM01 kit part cpu interface a cpu interface (figure 2) is included in the DNCM01 kit part. this interface allows access to the registers and counters of the DNCM01 kit part. this interface also has a reset signal that will reset the state machines, counters, and critical logic in the cpu inter- face. registers and counters the DNCM01 kit part contains transmit con?uration, transmit status, and receive status registers. the transmit con?uration register provides access to internal signals that control the transmission options for the DNCM01 kit part. the transmit status and receive * verilog is a registered trademark of cadence design systems, inc. status registers provide access to output signals that describe the results of the last transmitted or received frame. the DNCM01 kit part contains control frame registers that hold the reserved multicast destination address, source address, reserved length/type ?ld, control opcode, and data. the DNCM01 will assemble a frame from the contents of the control frame registers. the DNCM01 kit part contains receive and collision counters. the receive counter is a 16-bit register that counts the number of valid bytes received in the current packet by the DNCM01 kit part. this counter freezes at 0xffff bytes. the receive counter clears on read. the collision counter is a 16-bit counter that reports the number of collisions on a transmit attempt. valid counts are 0 through 15. when the number of collisions is equal to the retry attempt value, retry[1:0], an exces- sive collision error occurs. the collision counter clears on read. flow control the DNCM01 kit part implements ?w control by receiving and sending pause (control) frames. the DNCM01 kit part contains the necessary registers and logic to automatically send control frames. these control frame registers hold the reserved multicast destination address, source address, reserved length/ type ?ld, control opcode, and data. the DNCM01 will automatically transmit a control frame when the cntrl signal is asserted. the DNCM01 kit part will assemble a frame from the contents of the control frame registers. the txinprog signal will be asserted while the transmission is in progress. the DNCM01 kit part handles the transfer of data from the control registers to the transmit data bus of the DNCM01.
14 lucent technologies inc. DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 DNCM01 kit part (continued) table 9. DNCM01 registers and counters table 10. mii address register cpu ad[4:0] register/counter read/write mii registers 00000 mii address register read/write 00001 mii data register read/write DNCM01 registers 00010 con?uration register read/write 00011 transmit status register read 00100 receive status register read 00101?0111 control frame destination address register read 01000?1010 control frame source address register read/write 01011 control frame length/type register read 01100 control frame opcode register read/write 01101 control frame data register read/write DNCM01 counters 01110 receive counter read 01111 collision counter read 10000 vlan1 type/length ?ld read/write 10001 vlan2 type/length ?ld read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 phy4 phy3 phy2 phy1 phy0 reg4 reg3 reg2 reg1 reg0 reserved write busy bit name description 15:11 phy[4:0] phy address. these bits tell which of the 32 possible phy devices are being accessed. 10:6 reg[4:0] mii register. these bits select the desired mii register in the selected phy device. 5:2 reserved. these bits are reserved and must be set to 0. 1 write mii write. setting this bit tells the phy that this will be a write operation using the mii data register. if this bit is not set, this will be a read operation, placing the data in the mii data register. 0 busy mii busy . this bit should read a logic 0 before writing to the mii address and mii data reg- isters. this bit must also be set to 0 during a write to the mii address register. during a mii register access, this bit will then be set to signify that a read or write is in progress. the mii data register should be kept valid until this bit is cleared during a phy write operation. the mii data register is invalid until this bit is cleared by the mac during a phy read operation. the mii address register should not be written to until this bit is cleared.
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 15 4 DNCM01 kit part (continued) table 11. mii data register table 12. con?uration register 1514131211109876543210 data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 bit name description 15:0 data[15:0] mii data. 16-bit data value read from the phy after a mii read operation. 16-bit data value to be written to the phy before a mii write operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txrst rxrst mfdup reserved invcrc appcrc retry1 retry0 rstrndm bsel reserved isqe defer reserved bit name description 15 txrst transmit reset . setting this bit causes the reset of transmit state machines and counters. this bit is self-clearing. 14 rxrst receive reset . setting this bit causes the reset of receive state machines and counters. this bit is self-clearing. 13 mfdup full duplex . this bit sets either half- or full-duplex operation. when mfdup is high, the col input is ignored during packet transmission and monitored during intergap delay for the presence of sqe, if the isqe signal is not active. when mfdup is high, all packets are received regardless of the status of txe. 12 reserved . this bit is reserved and must be set to 0. 11 invcrc invert crc . this bit inverts the polarity of the 32-bit crc polynomial. the normal crc is inverted prior to transmission. if invcrc is high, the normal crc is reinverted prior to sending, forcing a crc error. 10 apndcrc append crc . when this bit is set, a 32-bit crc polynomial is appended to the end of a transmitted packet. 9, 8 retry[1:0] retry attempt select . these bits set the total number of attempts (initial and retries after collision) the mac makes to transmit a packet. the total attempts follow the table below: retry1 retry0 attempts 0016 01 8 104 111 7 rstrndm reset random binary backoff algorithm . set and then clear this bit to reset the random binary backoff algorithm. this is a test feature. 6 bsel backoff select . when this bit is set, the backoff algorithm is not used. after a collision occurs during transmission, the transmitter jams for 32 tx_clk cycles and attempts to re- transmit after 9.6 m s (0.96 m s at 100 mbits/s) of intergap time. if low, the transmitter follows the normal binary backoff algorithm following a collision. 5:3 reserved . these bits are reserved and must be set to 0. 2 isqe ignore sqe test. used to ignore the sqe signal from the phy during the ?st 6.4 m s at 10 mbits/s of interframe gap. if high, the sqe error ?g will not be set. 1 defer abort after max deferral . when defer is set, the transmitter aborts a transmission attempt if it has deferred for more than 24,233 tx_clk cycles. deferring starts when the transmitter is ready to transmit, but is prevented from doing so because crs is active. defer time is not cumulative. if the transmitter defers for 10,000 bit times, then transmits and collides, backs off, and then has to defer again after completion of backoff, the deferral timer resets to 0 and restarts. if defer is low, the transmitter defers inde?itely. 0 reserved reserved . this bit is reserved and must be set to 0.
16 lucent technologies inc. DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 DNCM01 kit part (continued) table 13. control frame destination address register table 14. control frame source address register table 15. control frame length/type register table 16. control frame opcode register table 17. mac control parameters register bit name description 47:0 cdest control frame destination address . the 48-bit reserved multicast address register for control frames. bit name description 47:0 csource control frame source address . the 48-bit individual address register of the station sending the frame. bit name description 15:0 ctype control frame length/type . the assigned 2-octet length/type ?ld of a mac control frame. bit name description 15:0 copcode control frame opcode . the 2-octet mac control opcode ?ld indicating the mac con- trol function. bit name description 15:0 cparam mac control parameters . two octets are provided to hold mac control opcode-speci? parameters.
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 17 4 DNCM01 kit part (continued) table 18. transmit status register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved txmult txbroad tx_vlan2 tx_vlan1 late exdef def scol mcol cerr lcrs sqefail reserved aborted bit name description 15:14 reserved . these bits are reserved and must be set to 0. 13 txmult transmit multicast. txmult is active if the transmitted frame has a destination address with the ?st transmitted address bit a 1 and at least one of the following 47 address bits a 0. txbroad and txmult are mutually exclusive. valid on the positive edge of tx_clk. 12 txbroad transmit broadcast. txbroad is active if the transmitted frame has a destination address of all 1s. valid on the positive edge of tx_clk. 11 tx_vlan2 two-level vlan frame. when this bit is set, the current transmission is tagged with a vlan2 id. the thirteenth and fourteenth bytes at the frame are compared to the two-level vlan tag register. this bit is set if there is a nonzero match. 10 tx_vlan1 one-level vlan frame. when this bit is set, the current transmission is tagged with a vlan1 id. the thirteenth and fourteenth bytes at the frame are compared to the one- level vlan tag register. this bit is set if there is a nonzero match. 9late late collision . this bit is set when a collision occurred more than 512 bit times (64 bytes) from the start of a transmission. the start of the transmission is de?ed as the transmission of the ?st bit of preamble. 8 exdef excessive deferral . this bit is set if the transmission ended because of excessive defer- ral of over 24,288 bit times if the defer bit is selected in the transmit con?uration register. 7 def deferred . this bit is set if a transmission deferred for 1 to 24,288 bit times during trans- mission. 6 scol single collision . this bit is set if the frame being transmitted collided once and was then transmitted successfully. this bit is not set if the transmission is aborted due to excess collisions or there are multiple collisions. this bit is not valid if the mac is con?ured for full duplex. 5 mcol multiple collisions . this bit is set if the frame being transmitted collided more than once and was then transmitted successfully. this bit is not set if the transmission is aborted due to excess collisions or there is a single collision. this bit is not valid if the mac is con- ?ured for full duplex. 4 cerr collision error . this bit is set if the previous transmission was stopped because of excessive collisions as allowed by the retry[1:0] inputs. scol and mcol are also valid if cerr is active. 3 lcrs loss of carrier . this bit is set if the crs input was inactive for one or more bit times while the transmitter was active. 2 sqefail sqe test failed. indicates that a col signal was not detected during the ?st 6.4 m s of interframe gap following a transmit attempt. sqe is inactive if the isqe input is high. 1 reserved . these bits are reserved and must be set to 0. 0 aborted frame aborted . this bit is set if a transmission has aborted before completion.
18 lucent technologies inc. DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 DNCM01 kit part (continued) table 19. receive status register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ifg nulpkt reserved rx_vlan2 rx_vlan1 reserved rxjab fae crc runt frag long phys mult broad bit name description 15 ifg short ifg . this bit is set if the interframe gap prior to the start of the packet was less than 9.6 m s (0.96 m s at 100 mbits/s). 14 nulpkt null packet . this bit is set if crs and rx_clk were active for some time, but no sfd sequence was detected. 13 reserved . these bits are reserved and must be set to 0. 12 rx_vlan2 two-level vlan frame. when this bit is set, the current reception is tagged with a vlan2 id. the thirteenth and fourteenth bytes at the frame are compared to the two-level vlan tag register. this bit is set if there is a nonzero match. 11 rx_vlan1 one-level vlan frame. when this bit is set, the current reception is tagged with a vlan1 id. the thirteenth and fourteenth bytes at the frame are compared to the one-level vlan tag register. this bit is set if there is a nonzero match. 10:9 reserved . these bits are reserved and must be set to 0. 8 rxjab receive jabber error . this bit is set when the current frame is greater than 1518 bytes, and the packet has a bad crc or a fae. 7fae frame alignment error . this bit is set if the current frame being received has a frame alignment error. an fae occurs when the resultant remainder from the division between the number of bits in the frame and eight is nonzero (nonintegral number of octets), the fcs is invalid, and the octet counters are greater than or equal to 64 and less than or equal to 1518. 6 crc crc error . this bit is set if a packet was received with a bit count with a mod 8 remainder equal to 0, and that packet has an incorrect crc. 5 runt runt packet . this bit is set if a packet was received with a byte count (including crc) <64, and the packet had a good crc. 4 frag fragment . this bit is set if a packet was received with a byte count (including crc) <64, and the packet had a bad crc or a fae. 3 long frame long error . this bit is set if the received packets length was greater than 1518 bytes, and the packet had a good crc. 2phys received physical address . this bit is set if the ?st bit of the received packet was 0, and at least 6 bytes of data were received. 1 mult received multicast address . this bit is set if the ?st bit of the received packet was 1, all address bits were not 1, and at least 6 bytes of data were received. 0 broad received broadcast address . this bit is set if all 36 address bits were 1.
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 19 4 DNCM01 kit part (continued) application information DNCM01 demo board features n switchable base address n 16-bit mac register bus n 8-bit fifo bus n mii interface n hardware interrupt (based on rxeop, resettable by software) n eight board commands: ?transmit a single packet ?start continuous transmissions ?read receive fifo ?write transmit fifo ?clear transmit fifo ?reset ?clear interrupt ?send control frame table 20. counters counter description receive received bytes . 16-bit counter, indicates the number of full bytes received in the current packet. this counter freezes at ffff bytes. this counter clears on read. collision collisions detected . 5-bit counter, reports the number of collisions on a transmit attempt. valid counts are 0 through 15. when the number of collisions is equal to the retry attempt value, retry[1:0], an excessive collision error occurs and the jam pattern is transmitted. this counter clears on read or next transmission.
20 lucent technologies inc. DNCM01 advance data sheet 10/100 ethernet mac asic macrocell february 1997 4 application information (continued) figure 2. demo board tx fifo rx fifo control logic control logic control logic control logic set/clear interrupt transceiver host cpu bus tx/rx data interrupt address data txdata rxdata data address tx data tx control rx data rx control test logic registers event counter transmit DNCM01 macrocell DNCM01 kit part rx control & status tx control tx status mii port flow control receive rx control rx status txdata rxdata txdata rxdata duplex pause tx control & status 5-5114 (f)
advance data sheet DNCM01 february 1997 10/100 ethernet mac asic macrocell lucent technologies inc. 21 4 notes:
4 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ?1997 lucent technologies inc. all rights reserved printed in u.s.a. february 1997 ds97-045asic printed on recycled paper for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com u.s.a.: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singapore 118256 tel. (65) 778 8833 , fax (65) 777 7495 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (bracknell), france: (33) 1 41 45 77 00 (paris), sweden: (46) 8 600 7070 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 2 6601 1800 (milan), spain: (34) 1 807 1441 (madrid)

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