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1/21 L9347 june 2002 n quad low-side switch n 2 x 5a designed as conventional switch n 2 x 2.5a designed as switched current-regulator n low on-resistance 2 x 0.2 w , 2 x 0.35 w (typ.) n power so-36 - package with integrated cooling area n integrated free-wheeling and clamping z-diodes n output slope control n short circuit protection n selective overtemperature shutdown n open load detection n ground and supply loss detection n external clock control n recirculation control n regulator drift detection n regulator error control n regulator resolution 5ma n status monitoring n status push-pull stages n electrostatic discharge (esd) protection description the L9347 is an integrated quad low-side power switch to drive inductive loads like valves used in abs systems. two of the four channels are current regulators with current range from 250ma to 2.25a and an accuracy of 10%. all channels are protected against fail functions. they are monitored by a status output. figure 1. pin connection 36 n.c. 35 in3 st4 34 pgnd3 33 32 pgnd3 q3 31 q3 30 29 d3 d3 28 q2 27 26 q2 pgnd2 25 pgnd2 24 23 vs vdd 22 vcc 21 20 in2 st1 19 gnd 1 in4 2 3 st3 pgnd4 4 pgnd4 5 6 q4 q4 7 d4 8 9 d4 q1 10 q1 11 12 pgnd1 pgnd1 13 en 14 15 clk in1 16 st2 17 18 test 99at0060 powerso-36 bare die ordering numbers: L9347pd L9347die1 intelligent quad (2 x 5a/2 x 2.5a) low-side switch
L9347 2/21 figure 2. block diagram 99at0059 logic overload open load gnd-det. overtemperature channel 1 overtemperature channel 4 logic & da overload open load gnd-det. ipd ipd logic overload open load gnd-det. overtemperature channel 2 overtemperature channel 3 logic & da overload open load gnd-det. ipd ipd drift-det. vs vcc vdd q1 d4 q4 q2 d3 q3 gnd test st3 in3 st2 in2 st4 in4 st1 in1 clk en internal supply
3/21 L9347 pin description n pin function 1 gnd logic ground 2, 3 pgnd 3 power ground channel 3 4, 5 q 3 power output channel 3 6, 7 d 3 free-wheeling diode channel 3 8, 9 q 1 power output channel 1 10, 11 q 2 power output channel 2 12, 13 d 4 free-wheeling diode channel 4 14, 15 q 4 power output channel 4 16, 17 pgnd 4 power ground channel 4 18 nc not connected 19 vcc 5v supply 20 vdd 5v supply 21 st 4 status output channel 4 22 in 2 control input channel 2 23 in 4 control input channel 4 24 st 2 status output channel 2 25 en enable input for all four channels 26 test enable input for drift detection 27, 28 pgnd 2 power ground channel 2 29 vs supply voltage 30, 31 pgnd 1 power ground channel 1 32 st 1 status output channel 1 33 in 3 control input channel 3 34 in 1 control input channel 1 35 st 3 status output channel 3 36 clk clock input
L9347 4/21 absolute maximum ratings the absolute maximum ratings are the limiting values for this device. damage may occur if this device is sub- jected to conditions which are beyond these values. thermal data symbol parameter test conditions min typ max unit e q switch off energy for inductive loads 50 mj voltages v s supply voltage -0.3 40 v v cc , v dd supply voltage -0.3 6 v v q output voltage static 40 v v q output voltage during clamping t < 1ms 60 v v in , v en input voltage in1 to in4, en i i < |10|ma -1.5 6 v v clk input voltage clk -1.5 6 v v st output voltage status -0.3 6 v v d recirculation circuits d3, d4 40 v v drmax max. reverse breakdown voltage of free wheeling diodes d3, d4 55 v currents i q1/2 output current for q1 and q2 >5 internal limited a i q3/4 output current for q3 and q4 >3 internal limited a i q1/2 , i pgnd1/2 output current at reversal supply for q1 and q2 -4 a i q3/4 , i pgnd3/4 output current at reversal supply for q3 and q4 -2 a i st output current status pin -5 5 ma esd protection esd electrostatical discharging mil883c 2kv esd output pins (qx, dx) vs. common gnd (pgnd1-4 + gnd) 4kv symbol parameter test conditions min typ max unit t j junction temperature t j -40 150 c t jc junction temperature during clamping (life time) s t = 30min s t = 15min 175 190 c t stg storage temperature t stg -55 150 c t th overtemperature shutdown threshold (1) (1) this parameter will not be tested but assured by design. 175 200 c t hy overtemperature shutdown hysteresis (1) 10 c r thjc thermal resistance junction to case r thjc 2 k/w
5/21 L9347 operating range . symbol parameter test conditions min. typ. max. unit v s supply voltage 4.8 18 v v cc , v dd supply voltage 4.5 5.5 v dv s /dt supply voltage transient time -1 1 v/ m s v q output voltage static -0.3 40 v v q output voltage induced by inductive switching voltage will be limited by internal z-diode clamping 60 v v st output voltage status -0.3 6 v i st output current status -1 1 ma t j junction temperature -40 150 c t jc junction temperature during clamping s = 30min s = 15min 175 190 c electrical characteristcs : (vs = 4.8 to 18v; t j = -40 to 150c unless otherwise specified) symbol parameter test condition min. typ. max. unit power supply i son supply current v s 18v (outputs on) 5ma i soff quiescent current v s 18v (outputs off) 5ma i cc supply current vcc (analog supply) vcc =5v 5 ma i dd supply current vdd (digital supply) vdd =5v f clk =0hz 5 ua i dd supply current vdd (digital supply) vdd =5v f clk =250khz 5 ma general diagnostic functions v qu open load voltage v s 3 6.5v (outputs off) 0.3 0.33 0.36 x v q v thgnd signal-gnd-loss threshold vcc= 5v 0.1 1 v v thpgl power-gnd-loss threshold vcc= 5v 1.5 2.5 3.5 v f clk,min clock frequency error 10 100 khz dc clke_l ow clock duty cycle error detection low f clk = 250 khz 33,3 45 % dc clke_ high clock duty cycle error detection high f clk = 250 khz 55 66,6 % vs loss supply detection vcc = vdd = 5v 2 4.5 v additional diagnostic functions channel 1 and channel 2 (non regulated channels) i qu1,2 open-load current channel 1, 2 v s 3 6.5v 50 140 ma i qo1,2 over-load current channel 1, 2 v s 3 6.5v 57.59 a
L9347 6/21 additional diagnostic functions channel 3 and channel 4 (regulated channels) dc out output duty cycle range filtered with 10ms 10 90 % i qo3,4 overload current channel 3,4 v s 3 6.5v 2.5 5 8 a v rerr recirculation error shutdown threshold (open d3/d4) iout > 50ma 45 50 60 v pwm dou t output pwm ratio during drift comparison v in3 = v in4 = pwm in v test = h -14.3 +14.3 % digital inputs (in1 to in4, ena, clk, test). the valid pwm-ratio for in3/in4 is 10% to 90% v il input low voltage -0.3 1 v v ih input high voltage 2 6 v v ihy input voltage hysteresis (1) 20 500 mv i i input pull down current v in = 5v, v s 3 6.5v 82040 m a digital outputs (st1 to st4) v stl status output voltage in low state (2) i st 40 m a 0 0.4 v v sth status output voltage in high state 2) i st 3 -40 m a 2.5 3.45 v i st 3 -120 m a 23.45v r diagl r out + r dson in low state 0.3 0.64 1.5 k w r diagh r out + r dson in high state 1.5 3.2 7.0 k w power outputs (q1 to q4) r dson1,2 static drain-source on-resistance q1 and q2 (non-reg. channels) i q = 1a; v s 3 9.5v t j = 25c t j = 125c (3) t j = 150c (4) 0.2 0.5 0.5 w w w r dson3,4 static drain-source on-resistance q3 and q4 (reg. channels) i q = 1a; v s 3 9.5v t j = 25c t j = 125c 3) t j = 150c 4) 0.35 0.75 0.75 w w w v f_250ma forward voltage of free wheeling path d3, d4 @250ma i d3/4 = -250ma 0.5 1.5 v v f_2.25a forward voltage of free wheeling path d3, d4 @2.25a i d3/4 = -2.25a 2.0 4.5 v r sens sense resistor = (v f_2.25a- v f_250ma )/ 2a 1 w electrical characteristcs : (continued) (vs = 4.8 to 18v; t j = -40 to 150c unless otherwise specified) symbol parameter test condition min. typ. max. unit
7/21 L9347 v z z-diode clamping voltage i q 3 100ma 45 60 v i pd output pull down current v en = h, v in = l 10 150 m a i qlk output leakage current v en = l; v q = 20v 5 m a timing t on output on delay time i q = 1a 0520 m s t off output off delay time channel i q = 1a 01030 m s t offreg output off delay time regulator (5) 528 m s t r output rise time i q = 1a 0.5 1.5 8 m s t f output fall time i q = 1a 0.5 1.5 8 m s t sf short error detection filter time f clk = 250khz dc = 50% (5) 48 m s t lf long error detection filter time f clk = 250khz dc = 50% (5) 16 32 m s t scp short circuit switch-off delay time (5) 430 m s t d status delay time (5) 896 1024 us t re regulation error status delay time (5) (reg. channels only) 10 ms t dreg output off status delay time (5) (reg. channels only 528 m s reg. current accuracy (reg. channels only) i q3/q4 minimum current dc = 10% 200 250 300 ma i q3/q4 maximum current dc = 90% 2 2.25 2.5 a i reg max. regulation deviation @ dc 10% - 90% 250ma < i q3/q4 < 400ma 400ma i q3/q4 800ma 800ma < i q3/q4 < 2.25a 10 6 10 % % % d i q3/q4 min. quant. step 5 ma frequencies clk frequency crystal-controlled 250 khz input pwm frequency (reg. channels only) 2 khz (1) this parameter will not be tested but assured by design (2) short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "low" (3) measured chip, bond wires not included (4) measured on power so-36 devices (5) digital filtered with external clock, only functional test electrical characteristcs : (continued) (vs = 4.8 to 18v; t j = -40 to 150c unless otherwise specified) symbol parameter test condition min. typ. max. unit
L9347 8/21 1.0 functional description 1.1 overview the L9347 is designed to drive inductive loads (relays, electromagnetic valves) in low side configuration. inte- grated active zener-clamp (for channel1 and 2) or free wheeling diodes (for channel 3 and 4) allow the recircu- lation of the inductive loads. all four channels are monitored with a status output. all wiring to the loads and supply pins of the device are controlled. the device is self-protected against short circuit at the outputs and over- temperature. for each channel one independent push-pull status output is used for a parallel diagnostic func- tion. channel 3 and 4 work as current regulator. a pwm signal on the input defines the target output current. the output current is controlled through the output pwm of the power stage. the regulator limits of 10% or 90% are detected and monitored with the status signal. the current is measured during recirculation phase of the load. a test mode compares the differences between the two regulators. this drift test compares the output pwm of the regulators. by this feature a drift of the load during lifetime can be detected. 1.2 input circuits the input, clk, test and enable inputs, are active high, consist of schmidt triggers with hysteresis. all inputs are connected to pull-down current sources. 1.3 output stages (not regulated) channel 1 and 2 the two power outputs (5a) consist of dmos-power transistors with open drain output. the output stages are protected against short circuit. via integrated zener-clamp-diodes the overvoltage of the inductive loads due to recirculation are clamped to typ. 52v for fast shut off of the valves. parallel to the dmos transistors there are internal pull-down current sources. they are provided to assure an open load condition in the off-state. with en=low this current source is switched off, but the open load comparator is still active. 1.4 current-regulator-stages channel 3 and 4 the current-regulator channels are designed to drive inductive loads. the target value of the current is given by the duty cycle (dc) of the 2khz pwm input signal. the following figure shows the relation between the input pwm and the output current and the specified accuracy . figure 3. input pwm to output current range 10 90 250 2250 output current [ma] input pwm[%] 400 curre n t preci s ion 800 10% +- 6% +-10%
9/21 L9347 the on period of the input signal is measured with a 1mhz clock, synchronized with the external 250khz clock. for requested precision of the output current the ratio between the frequencies of the input signal and the ex- ternal 250khz clock has to be fixed according to the graph shown in fig. figure 4. current accuracy according to the input and clock frequency ratio the theoretical error is zero for f clk / f in = 125. if the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. for a clock frequency lower than 100khz the clock control will also disable the regulator. for high precision appli- cations the clock frequency and the input frequency have to be correlated. the output current is measured during the recirculation of the load. the current sense resistor is in series to the free wheeling diode. if this recirculation path is interrupted the regulator stops immediately and the status output remains low for the rest of the input cycle. the output period is 64 times the clock period. with a clock frequency of 250khz the output pwm frequency is 3.9khz. the output pwm is synchronized with the first negative edge of the input signal. after that the output and the input are asynchronous. the first period is used to measure the current. this means the first turn-on of the power is 256 m s after the first negative edge of the input signal. as regulator a digital pi-regulator with the transfer function for: ki: and kp: 0.96 for a sampling time of 256us is realised. to speed up the current settling time the regulator output is locked to 90% output pwm untill the target current value is reached. this happens alsowhen the target current value changes and the output pwm reaches 90% during the regulation. the status output gets low if the target current value is not reached within the regulation error delay time of t re =10ms. the output pwm is than out of the regulation range from 10% to 90%. 1.5 protective circuits the outputs are protected against current overload, overtemperature, and power-gnd-loss. the external clock is monitored by a clock watchdog. this clock watchdog detects a minimal frequency f clk,min and wrong clock duty cycles. the allowed clock duty cycle range is 45% to 55%. the current-regulator stages are protected -10% 5.6% 112.5 132 125 f clk / f in 0% current accuracy regulator switched off 0.126 z1 C -------------- -
L9347 10/21 against recirculation errors, when d3 or d4 is not connected. all these error conditions shut off the power stage and invert the status output information. 1.6 error detection the status outputs indicate the switching state under normal conditions (status low = off; status high = on). if an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. all ex- ternal errors, for example open load, are filtered internally. the following table shows the detected errors, the filter times and the detection mode (on/off). en&in=low means that at least one between enable and input is low. for the inputs in=low means also no input pwm. for the regulator input period longer than t dreg and for the standard channel input period longer thant d . a detected error is stored in an error register. the reset of this register is made with a timer t d . with this ap- proach all errors are present at the status output at least for the time t d . all protection functions like short circuit of the output, overtemperature, clock failure or power-gnd-loss in on condition are stored into an internal fail register. the output is then shut off. the register must be reset with a low signal at the input. a low signal means that the input is low for a time longer than t d or t dreg for the re- ulated channel, otherwise it is interpreted as a pwm input signal and the register is left in set mode. signal-gnd-loss and vs-loss are detected in the active on mode, but they do not set the fail register. this type of error is only delayed with the standard timer t lf function. open load is detected for all four channels in on- and off-state. open load in off condition detects the voltage on the output pin. if this voltage is below 0.33 * vs the error reg- ister is set and delayed with t d . a sink current stage pull the output down to ground, with en high. with en low the output is floating in case of openload and the detection is not assured. in the on state the load current is monitored by the non-regulated channels. if it drops below the specified threshold value i qu an open load is detected and the error register is set and delayed with t d . a regulated channel detects the open load in the on state with the current regulator error detection. if the output pwm reaches 90% for a time longer than t re than an error occurs. this could happen when no load is connected, the resistivity of the load is too high or the supply voltage too low. the same error is shown if the regulator is not able to reduce the current in the load in the time t re , so the output pwm falls below 10%. a clock failure (clock loss) is detected when the frequency becomes lower than f clk,min . all status outputs are on state en &in = high off state en &in = low filter time reset done by short circuit of the load xt sf en & in = low for t d or t dreg open load (under voltage detection) xt lf timer t d open load (under current detection) xt sf timer t d overtemperature xt sf en & in = low for t d or t dreg power-gnd-loss xxt lf in on: en & in = low for t d or t dreg in off: timer t d signal-gnd-loss xxt lf timer t d supply-vs-loss xxt lf timer t d clock control x x no in on: en & in = low for t d or t dreg in off: timer t d output voltage clamp active x (regulated channels) no in on: en & in = low for t d or t dreg in off: timer t d
11/21 L9347 set on error and all power outputs are shut off. the status signals remain in their state until the clock signal is present again. a clock failure during power on of vcc is detected only on the regulated channels. the status outputs of the channel 1 and 2 are low in this case. 1.7 drift detection (regulated channels only) the drift detection is used to compare the two regulated channels during regulation. this drift test compares the output pwm of the regulators. the resistivity of the load influences the output pwm. the approximated for- mula for the output current below shows the dependency of the load resistor to the output pwm. in this formula the energy reduction during the recirculation is not taken into account. the real output pwm is higher. the test- mode is enabled with in,en and test high. with an identical 2khz pwm-signal connected to the in-inputs the output pwm must be in a range of +-14.3%. if the difference between the two on-times is more than 14.3% of the expected value an error is detected and monitored by the status outputs, in the same way as described above, but a drift error will not be registered and also not delayed with t d as other errors a 7bit output-pwm-register is used for the comparison. the register with the lower value is subtracted from the higher one. this result is multiplied by four and compared with the higher value. 1.8 other test modes the test pin is also used to test the regulated channels in the production. with a special sequence on this pin the power stages of the regulated channels can be controlled direct from the input. no status feedback of the regulated channels is given. the status output is clocked by the regulator logic. the output sequence is a indi- cation of a proper logic functionality. the following table shows the functionality of this special test mode for more details about the test condition four see timing diagram. en in test out status note 1 x x x x disable test mode 1 1 1 on 1 drift mode 0 x off test pattern test condition one 0 x off test pattern test condition two 0 x off test pattern test condition three 0 0 off test pattern test condition four 0 1 on test pattern test condition four iout vbat rl ron + ---------------------------- pwm = drift definition: drift = pwm(1+e) - pwm (1-e) = 2pwm e drift * 4 < pwm (1+e) with e >14.3% a drift is detected e.. not correlated error of the channels %pwm ... corresponding ideal output pwm to a given input pwm
L9347 12/21 diagnostic table the status follows the input signal in normal operating conditions. if any error is detected the status is inverted. operating condition test input test enable input ena control input non-reg./reg. in power output/ current reg. q status output st normal function l l l l l l h h l h/pwm l h/pwm off off off on l l l h open load or short to ground l l l l l l h h l h/pwm l h/pwm off off off on x x h l overload or short to supply latched overload reset latch reset latch l l l l h h h C> l h h/pwm h/pwm x h/pwm C> l off off off off l l l l overtemperature latched overtemperature reset latch reset latch l l l l h h h C> l h h/pwm h/pwm x h/pwm C> l off off off off l l l l recirculation error (reg.chn.) latched error reset latch reset latch l l l l h h h C> l h pwm pwm x pwm C> l off off off off l l l l clock failure (clock loss) (1) (1) during power on sequence only detected on channel 3 and 4 (see description). l l l l l l h h l h/pwm l h/pwm off off off off h h h l drift (2) failure no failure (2) this input combination is also used for an internal chip-test and must not be used. h h h h l l h h l h/pwm h/pwm h/pwm off off on on x x l h
13/21 L9347 2.0 timing diagrams 2.1 non regulated channels figure 5. output slope, resistive load figure 6. overload switch-off delay 99at0061 t v i v ih v il t v q t on t f v s t off t r 15% v s 85% v s 00rs0001 t i q i qo i qu t v st t d t scp t sf
L9347 14/21 figure 7. normal condition, resistive load, pulsed input signal figure 8. current overload 99at0063 v in v q i q i qu t d v st t d 99at0064 v in v q i q i qo v st t d t d reset fail register set fail register
15/21 L9347 figure 9. diagnostic status output at different open load current conditions 99at0065 v in v q i qu v st t d i q t d under current condition followed by normal operation 99at0066 v in v q i q i qu v st t d t d open load condition in the case of pulsed input signal followed by normal operation
L9347 16/21 figure 10. pulsed open load conditions (regulated and non-regulated channels) 2.2 regulated channels (timing diagrams of diagnostic with 2khz pwm input signal) figure 11. normal condition, inductive load 99at0067 v in v q 0.33 x v s v st t d i q t lf t lf 99at0068 v in v q i q t dreg v st 500 m s target current 256 m s 256 m s
17/21 L9347 figure 12. current overload figure 13. recirculation error 99at0069 v in v q i q v st i qo set fail registor reset fail register t dreg 500 m s t sf 99at0070 v in v q i q v st target current set fail register reset fail register t dreg 500 m s
L9347 18/21 figure 14. current regulation error (e.g. as a result of voltage reduction) figure 15. overtemperature 99at0071 v in v st 500 m s t re target current pwm ratio = 90% v q i q 99at0072 v in v st 500 m s target current v q t dreg reset fail register overtemperature condition set fail register i q
19/21 L9347 figure 16. 99at0073 v test v in3/4 v q3/4 test mode 4 v en low
L9347 20/21 dim. mm inch min. typ. max. min. typ. max. a 3.60 0.141 a1 0.10 0.30 0.004 0.012 a2 3.30 0.130 a3 0 0.10 0 0.004 b 0.22 0.38 0.008 0.015 c 0.23 0.32 0.009 0.012 d (1) 15.80 16.00 0.622 0.630 d1 9.40 9.80 0.370 0.385 e 13.90 14.50 0.547 0.570 e 0.65 0.0256 e3 11.05 0.435 e1 (1) 10.90 11.10 0.429 0.437 e2 2.90 0.114 e3 5.80 6.20 0.228 0.244 e4 2.90 3.20 0.114 0.126 g 0 0.10 0 0.004 h 15.50 15.90 0.610 0.626 h 1.10 0.043 l 0.80 1.10 0.031 0.043 n10 (max.) s8 (max.) (1): "d" and "e1" do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - critical dimensions are "a3", "e" and "g". powerso36 e a2 a e a1 pso36mec detail a d 118 19 36 e1 e2 h x 45? detail a lead slug a3 s gage plane 0.35 l detail b detail b (coplanarity) gc - c - seating plane e3 c n n ? m 0.12 ab b b a h e3 d1 bottom view outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 21/21 L9347

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