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1 ? fn8109.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. x28hc64 64k, 8k x 8-bit 5 volt, byte alterable eeprom the x28hc64 is an 8k x 8 eeprom, fabricated with intersil?s proprietary, high perform ance, floating gate cmos technology. like all intersil programmable nonvolatile memories, the x28hc64 is a 5v only device. it features the jedec approved pinout for byte-wide memories, compatible with industry standard rams. the x28hc64 supports a 64-byte page write operation, effectively providing a 32s/byt e write cycle, and enabling the entire memory to be typically written in 0.25 seconds. the x28hc64 also features data polling and toggle bit polling, two methods providing early end of write detection. in addition, the x28hc64 includes a user-optional software data protection mode that further enhances inte rsil?s hardware write protect capability. intersil eeproms are designed and tested for applications requiring extended endurance. i nherent data retention is greater than 100 years. features ? 70ns access time ? simple byte and page write - single 5v supply - no external high voltages or v pp control circuits - self-timed - no erase before write - no complex programming algorithms - no overerase problem ? low power cmos - 40ma active current max. ? 200a standby current max. ? fast write cycle times - 64-byte page write operation - byte or page write cycle: 2ms typical - complete memory rewrite: 0.25 sec. typical - effective byte write cycle time: 32s typical ? software data protection ? end of write detection - data polling - toggle bit ? high reliability - endurance: 100000 cycles - data retention: 100 years ? jedec approved byte-wide pin out ? pb-free available (rohs compliant) pinouts x28hc64 (28 ld pdip, soic) top view x28hc64 (32 ld plcc) top view nc a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we nc a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 x28hc64 a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 8 a 9 a 11 nc oe a 10 ce i/o 7 i/o 6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a 7 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 (top view) a 12 nc v cc we nc x28hc64 nc nc data sheet august 28, 2009
2 fn8109.2 august 28, 2009 ordering information part number part marking temperature range (c) access time (ns) package pkg. dwg. # x28hc64j-70* x28hc64j-70 rr 0 to +70 70 32 ld plcc n32.45x55 x28hc64jiz-70* (note 1) x28hc64ji-70 zrr -40 to +85 32 ld plcc (pb-free) n32.45x55 x28hc64jz-70* (note 1) x28hc64j-70 zrr 0 to +70 32 ld plcc (pb-free) n32.45x55 x28hc64siz-70 x28hc64si-70 rr -40 to +85 28 ld soic (300 mil) m28.3 x28hc64sz-70 (note 1) x28hc64s-70 rrz 0 to +70 28 ld soic (300 mil) (pb-free) m28.3 x28hc64j-90* x28hc64j-90 rr 0 to +70 90 32 ld plcc n32.45x55 x28hc64ji-90** x28hc64ji-90 rr -40 to +85 32 ld plcc n32.45x55 x28hc64jiz-90* (note 1) x28hc64ji-90 zrr -40 to +85 32 ld plcc (pb-free) n32.45x55 x28hc64p-90 x28hc64p-90 rr 0 to +70 28 ld pdip e28.6 x28hc64pi-90 x28hc64pi-90 rr -40 to +85 28 ld pdip e28.6 x28hc64piz-90 (notes 1, 2) x28hc64pi-90 rrz -40 to +85 28 ld pdip (pb-free) e28.6 x28hc64pz-90 (notes 1, 2) x28hc64p-90 rrz 0 to +70 28 ld pdip (pb-free) e28.6 x28hc64j-12* x28hc64j-12 rr 0 to +70 120 32 ld plcc n32.45x55 x28hc64ji-12* x28hc64ji-12 rr -40 to +85 32 ld plcc n32.45x55 x28hc64jiz-12* (note 1) x28hc64ji-12 z rr -40 to +85 32 ld plcc (pb-free) n32.45x55 x28hc64jz-12* (note 1) x28hc64j-12 rrz 0 to +70 32 ld plcc (pb-free) n32.45x55 x28hc64p-12 x28hc64p-12 rr 0 to +70 28 ld pdip e28.6 x28hc64pi-12 x28hc64pi-12 rr -40 to +85 28 ld pdip e28.6 x28hc64piz-12 (notes 1, 2) x28hc64pi-12 rrz -40 to +85 28 ld pdip (pb-free) e28.6 x28hc64pz-12 (notes 1, 2) x28hc64p-12 rrz 0 to +70 28 ld pdip (pb-free) e28.6 x28hc64s-12* , ** x28hc64s-12 rr 0 to +70 28 ld soic (300 mil) m28.3 x28hc64si-12* x28hc64si-12 rr -40 to +85 28 ld soic (300 mil) m28.3 X28HC64SIZ-12* (note 1) x28hc64si-12 rrz -40 to +85 28 ld soic (300 mil) (pb-free) m28.3 x28hc64sz-12 (note 1) x28hc64s-12 rrz 0 to +70 28 ld soic (300 mil) (pb-free) m28.3 *add ?t1? suffix for tape and reel. please refer to tb347 for details on reel specifications. ***add ?t2? suffix for tape and reel. please refer to tb347 for details on reel specifications. notes: 1. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. 2. pb-free pdips can be used for through hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. x28hc64
3 fn8109.2 august 28, 2009 pin descriptions addresses (a 0 -a 12 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable (ce ) the chip enable input must be low to enable all read/write operations. when ce is high, power consumption is reduced. output enable (oe ) the output enable input contro ls the data output buffers and is used to initiate read operations. data in/data out (i/o 0 -i/o 7 ) data is written to or read from the x28hc64 through the i/o pins. write enable (we ) the write enable input controls the writing of data to the x28hc64. block diagram device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this two line control architecture eliminates bus contention in a system environm ent. the data bus will be in a high impedance state when either oe or ce is high. write write operations are initiated when both ce and we are low and oe is high. the x28hc64 supports both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs first. a byte write operation, once initiated, will automatically continue to completion, typically within 2ms. page write operation the page write feature of the x28hc64 allows the entire memory to be written in 0.25 seconds. page write allows two to sixty-four bytes of data to be consecutively written to the x28hc64 prior to the commencement of the internal programming cycle. the host can fetch data from another device within the system dur ing a page write operation (change the source address) , but the page address (a 6 through a 12 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following t he initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner. each successive byte load cycle, started by the we high to low transition, must begin within 100s of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100s, the internal automatic programming cycle will commence. there is no page write window limitation. effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. write operation status bits the x28hc64 provides the user two write operation status bits. these can be used to optimize a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. table 1. pin names symbol description a 0 -a 12 address inputs i/o 0 -i/o 7 data input/output we write enable ce chip enable oe output enable v cc +5v v ss ground nc no connect x buffers latches and decoder i/o buffers and latches y buffers latches decoder control logic and timing 65,536-bit eeprom array i/o 0 ?i/o 7 data inputs/outputs ce oe v cc v ss a 0 ?a 12 we address inputs and 5 tb dp 43210 i/o reserved toggle bit data polling figure 1. status bit assignment x28hc64
4 fn8109.2 august 28, 2009 data polling (i/o 7 ) the x28hc64 features data polling as a method to indicate to the host system that the byte write or page write cycle has completed. data polling allows a simple bit test operation to determine the status of the x 28hc64, eliminating additional interrupt inputs or external hardware. during the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on i/o 7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). once the programming cycle is complete, i/o 7 will reflect true data. toggle bit (i/o 6 ) the x28hc64 also provides another method for determining when the internal wr ite cycle is complete. during the internal programming cycle i/o 6 will toggle from high to low and low to high on subsequent attempts to read the device. when the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. data polling i/o 7 data polling can effectively reduce the time for writing to the x28hc64. the timing diagram in figure 2 illustrates the sequence of events on the bus. the software flow diagram in figure 3 illustrates one method of implementing the routine. ce oe we i/o 7 x28hc64 ready last write high z v ol v ih a 0 ?a 12 an an an an an an v oh an figure 2. data polling bus sequence write data save last data and address read last address io 7 compare? no yes writes complete? no yes ready figure 3. data polling software flow x28hc64
5 fn8109.2 august 28, 2009 the toggle bit i/o 6 the toggle bit can eliminate the chore of saving and fetching the last address and data in order to implement data polling. this can be especially helpful in an array comprised of multiple x28hc64 memories that is frequently updated. toggle bit polling can also provide a method for status checking in multiprocessor applications. the timing diagram in figure 4 illustrates the sequence of events on the bus. the software flow diagram in figure 5 illustrates a method for polling the toggle bit. hardware data protection the x28hc64 provides two hard ware features that protect nonvolatile data from inadvertent writes. ? default v cc sense?all write functions are inhibited when v cc is 3v typically. ? write inhibit?holding either oe low, we high, or ce high will prevent an inadvert ent write cycle during power- up and power-down, maintaining data integrity. software data protection the x28hc64 offers a software controlled data protection feature. the x28hc64 is shipped fr om intersil with the software data protection not enabled; that is, the device will be in the standard operating mode. in this mode data should be protected during power-up/-down o perations through the use of external circuits. the host would then have open read and write access of the device once v cc was stable. the x28hc64 can be automatica lly protected during power- up and power-down without the need for external circuits by employing the software data prot ection feature. the internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. this circuit is nonvolatile and will remain set for the life of the device, unless the reset command is issued. once the software protection is enabled, the x28hc64 is also protected from inadvertent and accidental writes in the powered-up state. that is, the software algorithm must be issued prior to writing additional data to the device. software algorithm selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. refer to figure 6 and 7 for the sequence. the three-byte sequence opens the page write window, enabling the host to write from one to sixty-four bytes of data. once the page load cycle has been completed, the device will aut omatically be returned to the data protected state. ce oe we x28hc64 last write i/o 6 high z * * v oh v ol ready * beginning and ending state of i/o 6 will vary. figure 4. toggle bit bus sequence compare no yes ok? compare accum with addr n load accum from addr n last write ready yes figure 5. toggle bit software flow x28hc64
6 fn8109.2 august 28, 2009 software data protection regardless of whether the device has previously been protected or not, once the soft ware data protection algorithm is used, the x28hc64 will automatically disable further writes unless another command is issued to deactivate it. if no further commands are issued the x28hc64 will be write protected during power-down and after any subsequent power-up. note: once initiated, the sequence of write operations should not be interrupted. ce we (v cc ) write protected v cc 0v data addr aaa 1555 55 0aaa a0 1555 t blc max writes ok byte or page t wc figure 6. timing sequence?byte or page write write last write data xx to any write data a0 to address 1555 write data 55 to address 0aaa write data aa to address 1555 after t wc re-enters data protected state byte to last address address optional byte/page load operation byte/page load enabled figure 7. write sequence for software data protection x28hc64
7 fn8109.2 august 28, 2009 resetting software data protection in the event the user wants to deactivate the software data protection feature for testing or reprogramming in an eeprom programmer, the following six step algorithm will reset the internal protection circuit. after t wc , the x28hc64 will be in standard operating mode. note: once initiated, the sequence of write operations should not be interrupted. ce we standard operating mode v cc data addr aaa 1555 55 0aaa 80 1555 t wc aa 1555 55 0aaa 20 1555 figure 8. reset software data protection timing sequence write data 55 to address 0aaa write data 55 to address 0aaa write data 80 to address 1555 write data aa address 1555 write data 20 to address 1555 write data aa to address 1555 figure 9. software sequence to deactivate software x28hc64
8 fn8109.2 august 28, 2009 system considerations because the x28hc64 is frequently used in large memory arrays, it is provided with a tw o-line control architecture for both read and write operations . proper usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where multiple i/o pins share the same bus. to gain the most benefit, it is recommended that ce be decoded from the address bus, and be used as the primary device selection input. both oe and we would then be common among all devices in the array. for a read operation, this assures that al l deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. because the x28hc64 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. enabling ce will cause transient current spikes. the magnitude of these spikes is dependent on the output capacitive loading of the i/os. therefore, the larger the array sharing a common bus, the larger the transient spikes. the voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. as a minimum, it is recommended that a 0.1f high frequency ceramic capacitor be used between v cc and v ss at each device. depending on the size of the array, the value of the capacitor may have to be larger. in addition, it is recommended th at a 4.7f electrolytic bulk capacitor be placed between v cc and v ss for each eight devices employed in the array. this bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the pc board traces. figure 10. normalized i cc (rd) by temperature over frequency data protection figure 11. normalized i cc (rd) @ 25% over the v cc range and frequency 1.4 1.2 0.8 0.4 0.6 0.2 1.0 0m 10m 20m - 55c + 25c frequency (hz) + 125c 5.5v cc i cc rd normalized (ma) 4.5v cc 5.0v cc 5.5v cc 1.4 1.2 0.8 0.4 0.6 0.2 1.0 0m 10m 20m frequency (hz) i cc rd normalized (ma) x28hc64
9 fn8109.2 august 28, 2009 absolute maximum rati ngs thermal information temperature under bias x28hc64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +85c x28hc64i. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on any pin with respect to v ss . . . . . . . . . . . . . . -1v to +7v dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. recommended operating conditions commercial temperature range. . . . . . . . . . . . . . . . . 0c to +70c industrial temperature range . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage range x28hc64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 10% caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. dc electrical specifications over recommended operating conditions, unless otherwis e specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperatur e limits established by characterization and are not production tested. parameter symbol test conditions min typ (note 3) max unit v cc current (active) (ttl inputs) i cc ce = oe = v il , we = v ih , all i/o?s = open, address inputs = ttl levels @ f = 10 mhz 15 40 ma v cc current (standby) (ttl inputs) i sb1 ce = v ih , oe = v il all i/o?s = open, other inputs = v ih 12ma v cc current (standby) (cmos inputs) i sb2 ce = v cc - 0.3v, oe = gnd, all i/o?s = open, other inputs = v cc - 0.3v 100 200 a input leakage current i li v in = v ss to v cc 10 a output leakage current i lo v out = v ss to v cc , ce = v ih 10 a input low voltage (note 4) v ll -1 0.8 v input high voltage (note 4) v ih 2v cc + 1 v output low voltage v ol i ol = 5ma 0.4 v output high voltage v oh i oh = -5ma 2.4 v notes: 3. typical values are for t a = +25c and nominal supply voltage 4. v il min. and v ih max. are for reference only and are not tested. endurance and data retention parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits establ ished by characterization and are not production tested. parameter min max unit minimum endurance 100,000 cycles data retention 100 years x28hc64
10 fn8109.2 august 28, 2009 equivalent ac load circuits symbol table power-up timing parameters with min and/or max limits are 100% tested at +25c, unless otherwise spec ified. temperature limits established by characterizati on and are not production tested. parameter symbol typ (note 3) unit power-up to read operation (note 5) t pur 100 s power-up to write operation (note 5) t puw 5ms capacitance t a = +25c, f = 1mhz, v cc = 5v parameter symbol test conditions max unit input/output capacitance (note 5) c i/o v i/o = 0v 10 pf input capacitance (note 5) c in v in = 0v 6 pf note: 5. this parameter is periodically sampled and not 100% tested. table 2. ac conditions of test input pulse levels 0v to 3v input rise and fall times 5ns input and output timing levels 1.5v table 3. mode selection ce oe we mode i/o power l l h read d out active lhl write d in active h x x standby and write inhibit high z standby x l x write inhibit ? ? x x h write inhibit ? ? 5v 1.92k 30pf output 1.37k waveform inputs outputs must be steady will be steady ma y change from lo w to high will change from lo w to high ma y change from high to lo w will change from high to lo w don?t care: changes allowed changing: state not known n/a center line is high impedance x28hc64
11 fn8109.2 august 28, 2009 ac electrical specifications read cycle read cycle limits over the recommended operating conditions unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temper ature limits established by characterization and are not production tested. parameter symbol x28hc64-70 x28hc64-90 x28hc64-12 unit -55c to +125c -55c to +125c -55c to +125c min max min max min max read cycle time t rc 70 90 120 ns chip enable access time t ce 70 90 120 ns address access time t aa 70 90 120 ns output enable access time t oe 35 40 50 ns ce low to active output (note 6) t lz 000 ns oe low to active output (note 6) t olz 000 ns ce high to high z output (note 6) t hz 30 30 30 ns oe high to high z output (note 6) t ohz 30 30 30 ns output hold from address change t oh 000ns note: 6. t lz min., t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. t ce t rc address ce oe we data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z data valid x28hc64
12 fn8109.2 august 28, 2009 we controlled write cycle write cycle limits parameters with min and/or max limits are 100% tested at +25c, unless otherwise spec ified. temperature limits established by characterizati on and are not production tested. parameter symbol min typ (note 3) max unit write cycle time (note 7) t wc 25ms address setup time t as 0ns address hold time t ah 50 ns write setup time t cs 0ns write hold time t ch 0ns ce pulse width t cw 50 ns oe high setup time t oes 0ns oe high hold time t oeh 0ns we pulse width t wp 50 ns we high recovery (note 8) t wph 50 ns data valid (note 8) t dv 1s data setup t ds 50 ns data hold t dh 0ns delay to next write (note 8) t dw 10 s byte load cycle t blc 0.15 100 s notes: 7. t wc is the minimum cycle time to be allow ed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. 8. t wph and t dw are periodically sampled and not 100% tested. address t as t wc t ah t oes t ds t dh t oeh ce we oe data in data out high z t cs t ch t wp t dv data valid x28hc64
13 fn8109.2 august 28, 2009 ce controlled write cycle page write cycle notes: 9. between successive byte writes within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively performing a polling operation. 10. the timings shown above are unique to page write operations. i ndividual byte load operations within the page write must conf orm to either the ce or we controlled write cycle timing. address t as t oeh t wc t ah t oes t cs t ds t dh t ch ce we oe data in data out high z data valid t cw t dv we oe last byte byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce address i/o *for each successive write within the page write operation, a 6 ?a 12 should be the same or writes to an unknown address could occur. (note 10) (note 9) x28hc64
14 fn8109.2 august 28, 2009 data polling timing diagram (note 11) toggle bit timing diagram (note 11) note: 11. polling operations are by defin ition read cycles and are therefor e subject to read cycle timings. address a n d in = x d out = x t wc t oeh t oes a n a n ce we oe i/o 7 t dw d out = x ce oe we i/o* 6 t oes t dw t wc t oeh high z * * * i/o 6 beginning and ending state will vary, depending upon actual t wc . x28hc64
15 fn8109.2 august 28, 2009 x28hc64 plastic leaded chip carrier packages (plcc) a1 a seating plane 0.015 (0.38) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 pin (1) c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.050 (1.27) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l ne nd identifier (0.12) m ds - b s as 0.042 (1.07) 0.048 (1.22) 0.005 n32.45x55 (jedec ms-016ae issue a) 32 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.125 0.140 3.18 3.55 - a1 0.060 0.095 1.53 2.41 - d 0.485 0.495 12.32 12.57 - d1 0.447 0.453 11.36 11.50 3 d2 0.188 0.223 4.78 5.66 4, 5 e 0.585 0.595 14.86 15.11 - e1 0.547 0.553 13.90 14.04 3 e2 0.238 0.273 6.05 6.93 4, 5 n28 286 nd 7 7 7 ne 9 9 7 rev. 0 7/98 notes: 1. controlling dimension: inch . converted millimeter dimen- sions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. al- lowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are mea- sured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. 7. nd denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. ne denotes the num- ber of leads on the two long sides of the package. -c-
16 fn8109.2 august 28, 2009 x28hc64 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 12/93
17 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8109.2 august 28, 2009 x28hc64 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-011-ab issue b) 28 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 1 12/00

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