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nanoamp solutions, inc. 1982 zanker road, san jose, ca 95112 ph: 408-573-8878, fax: 408-573-8877 www.nanoamp.com n16t1618c2(d1/a1)a stock no. 23183 - 04 4/03 1 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information 16mb ultra-low power asynchronous cmos psram 1m x 16 bit overview the n16t1618c2(d1/a1)a is an integrated memory device containing a 16 mbit pseudo static random access memory using a self-refresh dram array organized as 1,048,576 words by 16 bits. it is designed to be compatible in operation and interface to standard 6t srams. the device is designed for low standby and operating current and includes a power-down feature to automatically enter standby mode. the device is available in a 2 ce (chip enable) version and two zz (deep sleep) versions. the zz version includes several power saving modes: a deep sleep mode where data is not retained in the array and partial array refresh mode where data is retained in a portion of the array. both these modes reduce standby current drain. the vfbga package has separate power rails, vccq and vssq for the i/o to be run from a separate power supply from the device core. features ? dual voltage for optimum performance v ccq and v ssq for separate i/o power rails vcc - 1.65v to 2.2 v vccq - 1.65v to 3.6v ? fast cycle times t acc < 85 ns ? very low standby current i sb < 40a @ 1.8v ? very low operating current icc < 25ma ? memory expansion with ce and oe ? automatic power down mode ? 48-pin vfbga, wafers available pin configuration product family part number feature package type operating temperature power supply speed standby current (i sb ), max operating current (icc), max N16T1618C2Az 2 ce 48 - bga -30 o c to +85 o c 1.65v - 2.2v 85ns @ 1.65v 40 a @ 1.8v 3 ma @ 1mhz n16t1618d1az deep sleep disabled n16t1618a1az deep sleep active 123456 a lb oe a 0 a 1 a 2 ce2/ zz b i/o 8 ub a 3 a 4 ce1 i/o 0 c i/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 d v ssq i/o 11 a 17 a 7 i/o 3 v cc e v ccq i/o 12 dnu a 16 i/o 4 v ss f i/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 g i/o 15 a 19 a 12 a 13 we i/o 7 h a 18 a 8 a 9 a 10 a 11 nc 48 pin bga (top) 6 x 8 mm pin descriptions pin name pin function a 0 -a 19 address inputs we write enable input ce1 chip enable input ce2 chip enable input (only for ce2 device) zz deep sleep input (only for a1 or d1 deep sleep device) oe output enable input lb lower byte enable input ub upper byte enable input i/o 0 -i/o 15 data inputs/outputs v cc power v ss ground v ccq power i/o pin only v ssq ground i/o pin only dnu do not use (or connect to v ss )
stock no. 23183 - 04 4/03 2 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information functional block diagram functional description ce1 ce2 1 we oe ub /lb zz 2 i/o 3 mode power h x x x x h high z standby 4 standby x l x x x h high z standby 4 standby xxxxhh high z standby 4 standby lhl x 5 l 3 h data in write 5 active -> standby 6 lhhl l 3 h data out read active -> standby 6 lhhh l 3 h high z active standby 6 1.) only on the two-ce option device. 2. only on the one-ce option device with sleep mode. 3. when ub and lb are in select mode (low), i/o 0 - i/o 15 are affected as shown. when lb only is in the select mode only i/o 0 - io 7 are affected as shown. when ub is in the select mode only i/o 8 - i/o 15 are affected as shown. if both ub and lb are in the deselect mode (high), the chip is in a standby mode regardless of the state of ce1 or ce2. 4. when the device is in stan dby mode, control inputs (we , oe , ub , and lb ), address inputs and data input/outputs are internally isolated from any external in fluence and disabled from exerti ng any influence externally. 5. when we is invoked, the oe input is internally disabled and has no effect on the circuit. 6. the device will consume active power in this mode whenever addresses are changed. data inputs are internally isolated from a ny external influence. capacitance 1 1. these parameters are verified in device characterization and are not 100% tested item symbol test condition min max unit input capacitance c in v in = 0v, f = 1 mhz, t a = 25 o c 8pf i/o capacitance c i/o v in = 0v, f = 1 mhz, t a = 25 o c 8pf control logic decode logic address inputs a 0 - a 19 ce1 we oe input/ output mux and buffers i/o 0 - i/o 7 ub lb i/o 8 - i/o 15 address ce2 1 1024k x 16 memory array zz 2
stock no. 23183 - 04 4/03 3 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information absolute maximum ratings 1 1. stresses greater than those listed above may cause permanent dam age to the device. this is a stress rating only and functiona l operation of the device at these or any other conditions above those indicated in the operating section of this specification i s not implied. exposure to absolute maximum rating cond itions for extended periods may affect reliability. item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc +0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 4.0 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 o c operating temperature t a -30 to +85 o c soldering temperature and time t solder 240 o c, 10sec(lead only) o c operating characteristics (ove r specified temperature range) item symbol comments min. typ 1 1. typical values are measured at vcc=vcc typ., t a =25c and not 100% tested. max. unit supply voltage v cc n16t1618 1.65 1.8 2.2 v supply voltage for i/o v ccq 1.65 3.6 v input high voltage v ih 1.4 vcc v input low voltage v il ?0.3 0.4 v output high voltage v oh i oh = -0.2ma 0.8v ccq v output low voltage v ol i ol = 0.2ma 0.2 v input leakage current i li v in = 0 to v cc 0.5 a output leakage current i lo oe = v ih or chip disabled 0.5 a read/write operating supply current @ 1 s cycle time 2 2. this parameter is specified with the outputs disabled to avoi d external loading effects. the user must add current required to drive output capacitance expected in the actual system. i cc1 v cc =v cc max, v in =v ih / v il chip enabled, i out = 0 4ma read/write operating supply current @ 70 ns cycle time 2 i cc2 v cc =v cc max, v in =v ih / v il chip enabled, i out = 0 25 ma standby current 3 3. this device assumes a standby m ode if the chip is disabled (ce1 high or ce2 low). in order to achieve low standby current all inputs must be within 0.2 volts of either vcc or vss. i sb1 v in = v cc or 0v chip disabled t a = 30 o c tbd a i sb2 t a = 85 o c, v cc = 1.8v 40 a t a = 85 o c, v cc = 2.0v 70 a t a = 85 o c, v cc = 2.2v 100 a
stock no. 23183 - 04 4/03 4 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information output load circuit timing test conditions item input pulse level 0.1v cc to 0.9 v cc input rise and fall time 5ns input timing reference levels 0.5 v cc output timing reference levels 0.5 v ccq operating temperature -30 o c to +85 o c v ccq 50 pf i/o 14.5k 14.5k output load
stock no. 23183 - 04 4/03 5 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information timings item symbol min. max. unit read cycle read cycle time t rc 85 ns address access time t aa 85 ns chip enable to valid output t co 85 ns output enable to valid output t oe 15 ns byte select to valid output t lb , t ub 85 ns chip enable to low-z output t lz 10 ns output enable to low-z output t olz 5ns byte select to low-z output t lbz , t ubz 10 ns chip disable to high-z output t hz 020ns output disable to high-z output t ohz 020ns byte select disable to high-z output t lbhz , t ubhz 020ns output hold from address change t oh 5ns write cycle write cycle time t wc 85 ns chip enable to end of write t cw 85 ns address valid to end of write t aw 85 ns byte select to end of write t lbw , t ubw 85 ns write pulse width t wp 65 30000 ns write recovery time t wr 0ns write to high-z output t whz 20 ns address setup time t as 0ns data to write time overlap t dw 25 ns data hold from write time t dh 0 ns end write to low-z output t ow 5ns all cycle address skew t sk 10 ns
stock no. 23183 - 04 4/03 6 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information timing of read cycle (ce1 = oe = v il , we = ce2 = v ih ) timing waveform of read cycle (we =v ih ) address data out t rc t aa t oh data valid previous data valid t sk address lb , ub oe data valid t rc t aa t co t hz t ohz t lbhz, t ubhz t olz t oe t lz high-z data out t lb, t ub t lblz, t ublz ce1 ce2 t sk
stock no. 23183 - 04 4/03 7 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information timing waveform of write cycle (we control) timing waveform of write cycle (ce1 control, ce2 = high) address data in ce1 ce2 lb , ub data valid t wc t aw t cw t wr t whz t dh high-z we data out high-z t ow t as t wp t dw t lbw , t ubw t sk t sk t sk address we data valid t wc t aw t cw t wr t dh lb , ub data in high-z t as t wp t dw t lbw , t ubw data out t whz ce1
stock no. 23183 - 04 4/03 8 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information timing waveform of write cycle (ub , lb control, ce2 = high) address we data valid t wc t aw t cw t wr t dh lb , ub data in high-z t as t wp t dw t lbw , t ubw data out t whz ce1 address we data valid t wc t aw t cw t wr t dh lb data in 0-7 high-z t as t wp t dw t lbw data out t whz ce1 ub high ub , lb can be swapped and only da ta-in 8-15 will be written
stock no. 23183 - 04 4/03 9 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information power savings modes in the n16t1618d1(a1)a devices there are several power savings modes. the three modes are: ? reduced memory size ? partial array refresh ? deep sleep mode all three modes are available only on the d1 and a1 devices which have a single ce and a zz (deep sleep mode) input pin. the operation of the power saving modes is controlled by setting the variable address register (var). this var is shown in the following ?v ariable address register? figure and is used to enable/disable the various low power modes. the var is set by using th e timings defined in the figure titled ?variable address register (var) update timings?. the regi ster must be set in less then 1us after zz is enabled low. 1) reduced memory size (rms) in this mode of operation, the 16mb psram can be operated as a 4mb, 8mb or a 12mb device. the mode and array size are determined by the settings in the va register. the va register is set according to the fol- lowing timings and the bit settings in the table ?add ress patterns for rms?. the rms mode is enabled at the time of zz transitioning high and the mode remains ac tive until the register is up dated. to return to the full 16mb address space, the va register must be re set using the previously defined procedures. while operating in the rms mode, the unselected portion of the array may not be used. the high order address, a19, is internally ignored within the psram and must be at a logic level to addressing the selected portion of the array. 2) partial array refresh (par) in this mode of operation, the internal refresh operat ion can be restricted to a 4mb, 8mb or 12mb portion of the array. the mode and array partition to be refreshed are determined by the settings in the va register. the va register is set according to the following timings and the bit settings in the table ?address patterns for par?. in this mode, when zz is active low, only the portion of the array that is set in the register is refreshed. the operating mode is only available during standby time (zz low) and once zz is returned high, the device resumes full array re fresh. all future par cycles will use the contents of the va register that has been previously set. to change the address space of the par mode, the va register must be reset using the previously defined procedures. the two device versions (d1 and a1) only differ in that they have different default settings for the va regis- ter. in the first version (a1), the default state for the zz enable/disable register (register a4) will be ?deep sleep enabled? where zz low will initiate a deep sleep mode after 1us. this device is referred to as deep sleep active, or dsa device. in the second version (d1), the default state for the zz enable/disable regis- ter (register a4) will be ?deep sleep disabled? such that zz low will not initiate a deep sleep mode but rather put the device into par mode after 1us. this dev ice is referred to as deep sleep inactive, or dsi device. to enter deep sleep in the d1 or dsa device the a4 register must first be programmed. in either device, once the sram enters deep sleep mode, the var contents are destroyed and the default register settings are reset. 3) deep sleep mode in this mode of operation, the internal refresh is turn ed off and all data integrity of the array is lost. deep sleep is entered by bringing zz low with the a4 register programmed to ?deep sleep enabled?. the device will remain in this mode as long as zz remains low.
stock no. 23183 - 04 4/03 10 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information variable address register (var) variable address register (var) update timings 1) applies only for setting the register for rms mode. deep sleep mode - entry/exit timings reserved for future zz enable/disabl e 0 = deep sleep enabled (default for dsa device) 1 = deep sleep disabled (default for dsi device) array mode for zz 0 = par mode (default) 1 = rms mode array half 0 = bottom array (default) 1 = top array array section 1 1 = 1/4 array 1 0 = 1/2 array 0 1 = 3/4 array 0 0 = full array (default) preferably set to all 0 a19 - a5 a0 a1 a2 a3 a4 a0-a4 zz t wc t lbw, ubw lb , ub t as ce we t zzwe t aw t wp t wr t cdzz t zzh 1 zz lb , ub t zzmin t cdzz t r ce or
stock no. 23183 - 04 4/03 11 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information var update and deep sleep timings item symbol min max unit par and rms zz low to we low t zzwe 1000 ns chip (ce , ub /lb ) deselect to zz low t cdzz 0ns zz low after we high t zzh 1 20 ns deep sleep mode t zzmin 10 us deep sleep recovery t r 200 us 1) applies only for setting the register for rms mode. address patterns for par (a3 = 0, a4 = 1) a2 a1 a0 active section address space size density 011 one-quarter of die00 000h - 3ffffh 256kb x 16 4mb 010 one-half of die 00 000h - 7ffffh 512kb x 16 8mb 001three-quarters of die00 000h - bffffh 768kb x 16 12mb 111one-quarter of diec 0000h - ffffh 256kb x 16 4mb 110one-half of die 80 000h - fffffh 512kb x 16 8mb 101three-quarters of die40 000h - fffffh 768kb x 16 12mb address patterns for rms (a3 = 1, a4 = 1) a2 a1 a0 active section address space a19 a18 size density 011 one-quarter of die 00 000h - 3ffffh 0 0 256kb x 16 4mb 010 one-half of die 00 000h - 7ffffh 0 x 512kb x 16 8mb 001 three-quarters of die 00 000h - bffffh 0 0 768kb x 16 12mb 01 10 000full die 000 00h - fffffh x x 1mb x 16 16mb 111one-quarter of diec 0000h - ffffh 1 1 256kb x 16 4mb 110one-half of die 800 00h - fffffh 1 x 512kb x 16 8mb 101three-quarters of die400 00h - fffffh 1 1 768kb x 16 12mb 10 01 100full die 000 00h - fffffh x x 1mb x 16 16mb
stock no. 23183 - 04 4/03 12 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information low power icc characteristi cs for n16t1618c2(d1/a1)a item symbol test array partition typ max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85 o c 1/4 array 35 ua 1/2 array 40 3/4 array 55 rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85 o c 4mb device 35 ua 8mb device 40 12mb device 55 deep sleep current i zz v in = v cc or 0v, chip in zz mode, t a = 85 o c 10 ua
stock no. 23183 - 04 4/03 13 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information ball grid array packag dimensions (mm) de e = 0.75 ball matrix type sd se j k 60.10 80.10 0.375 0.375 1.125 1.375 full side view top view bottom view e d a1 ball pad corner (3) 0.900.10 0.230.05 0.15 0.08 z z 1. 0.300.05 dia. 1. dimension is measured at the maximum solder ball diameter. parallel to primary z. 2. primary datum z and seating plane are defined by the spherical crowns of the solder balls. 3. a1 ball pad corner i.d. to be marked by ink. 2. seating plane - z sd se e k typ j typ e a1 ball pad corner
stock no. 23183 - 04 4/03 14 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n16t1618c2(d1/a1)a advance information ordering information ? 2002, 2003 nanoamp solutions, inc. all rights reserved. nanoamp solutions, inc. ("nanoamp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. nanoamp does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. nanoamp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does nanoamp ass ume any liability arising out of the application or use of any product or circuit described herein. nanoamp does not authorize use of its products as critical components in any application in which the failure of the nanoamp product may be expected to result in significant injury or de ath, including life support systems and critical medical instrumen t. revision history revision date change description 01 10/01/02 released new 1.8v only datasheet 02 november 2002 updated for standby and active current specs 03 january 2003 clarified tcp requirement 04 april 2003 removed tcp requirement n16t1618 xx az- 85 i note: add -t&r following th e part number for tape and reel. orders will be considered in tray if not noted. c2 = 2 ce device d1 = zz w/ deep sleep bit disabled a1 = zz w/ deep sleep bit active ce / zz options

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