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? 1999 burr-brown corporation pds-1501a printed in u.s.a. june, 1999 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 dac7612 dual, 12-bit serial input digital-to-analog converter description the dac7612 is a dual, 12-bit digital-to-analog con- verter (dac) with guaranteed 12-bit monotonicity performance over the industrial temperature range. it requires a single +5v supply and contains an input shift register, latch, 2.435v reference, a dual dac, and high speed rail-to-rail output amplifiers. for a full- scale step, each output will settle to 1 lsb within 7 m s while only consuming 3.7mw. the synchronous serial interface is compatible with a wide variety of dsps and microcontrollers. clock (clk), serial data in (sdi), chip select (cs) and load dacs (loaddacs) comprise the serial inter- face. the dac7612 is available in an 8-lead soic package and is fully specified over the industrial temperature range of C40 c to +85 c. features l low power: 3.7mw l fast settling: 7 m s to 1 lsb l 1mv lsb with 4.095v full-scale range l complete with reference l 12-bit linearity and monotonicity over industrial temp range l 3-wire interface: up to 20mhz clock l small package: 8-lead soic applications l process control l data acquisition systems l closed-loop servo-control l pc peripherals l portable instrumentation dac7612 12-bit dac a dac register a 14-bit serial shift register 12 12 dac register b ref 12 12 loaddacs cs clk sdi v dd gnd v outa dac7612 12-bit dac b v outb sbas106
2 dac7612 specifications at t a = C40 c to +85 c, and v dd = +5v, unless otherwise noted. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. dac7612u dac7612ub parameter conditions min typ max min typ max units resolution 12 [ bits accuracy relative accuracy (1) C2 1/2 +2 C1 1/4 +1 lsb differential nonlinearity guaranteed monotonic C1 1/2 +1 C1 1/4 +1 lsb zero-scale error code 000 h C1 +1 +3 [[[ lsb zero scale match code 000 h 1/2 1/2 2 lsb full-scale voltage code fff h 4.079 4.095 4.111 4.087 4.095 4.103 v full-scale match code fff h 1/2 1/2 2 lsb analog output output current code 800 h 5 7 [[ ma load regulation r load 3 402 w , code 800 h 13 [[ lsb capacitive load no oscillation 500 [ pf short-circuit current 15 [ ma short-circuit duration gnd or v dd indefinite [ digital input data format serial [ data coding straight binary [ logic family cmos [ logic levels v ih 0.7 ? v dd [ v v il 0.3 ? v dd [ v i ih 10 [ m a i il 10 [ m a dynamic performance settling time (2) (t s ) to 1 lsb of final value 7 [ m s dac glitch 2.5 [ nv-s digital feedthrough 0.5 [ nv-s power supply v dd +4.75 +5.0 +5.25 [[[ v i dd v ih = 5v, v il = 0v, no load, at code 000 h 0.75 1.5 [[ ma power dissipation v ih = 5v, v il = 0v, no load 3.5 7.5 [[ mw power supply sensitivity d v dd = 5% 0.0025 0.002 [[ %/% temperature range specified performance C40 +85 [[ c [ same specification as for dac7612u. notes: (1) this term is sometimes referred to as linearity error or integral nonlinearity (inl). (2) specification does not app ly to negative-going transitions where the final output voltage will be within 3 lsbs of ground. in this region, settling time may be double the value indicated.
3 dac7612 pin configuration top view so-8 v dd to gnd .......................................................................... C0.3v to 6v digital inputs to gnd .............................................. C0.3v to v dd + 0.3v v out to gnd ........................................................... C0.3v to v dd + 0.3v power dissipation ........................................................................ 325mw thermal resistance, q ja ........................................................... 150 c/w maximum junction temperature .................................................. +150 c operating temperature range ...................................... C40 c to +85 c storage temperature range ....................................... C65 c to +150 c lead temperature (soldering, 10s) .............................................. +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. absolute maximum ratings (1) pin descriptions pin label description 1 sdi serial data input. data is clocked into the internal serial register on the rising edge of clk. 2 clk synchronous clock for the serial data input. 3 loaddacs loads the internal dac registers. all dac registers are transparent latches and are transparent when loaddacs is low (regardless of the state of cs or clk). 4 cs chip select. active low. 5v outb dac b output voltage 6 gnd ground 7v dd positive power supply 8v outa dac a output voltage electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information minimum relative differential specification package accuracy nonlinearity temperature drawing ordering transport product (lsb) (lsb) range package number (1) number (2) media dac7612u 2 1 C40 c to +85 c so-8 182 dac7612u rails "" " " "" dac7612u/2k5 tape and reel dac7612ub 1 1 C40 c to +85 c so-8 182 dac7612ub rails "" " " "" dac7612ub/2k5 tape and reel notes: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. (2 ) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 devices per reel). ordering 2500 pieces of dac7612u/2k5 will get a single 2500-piece tape and reel. for detailed tape and reel mechanical information, refer to appendix b of burr-brown ic data book. 1 2 3 4 8 7 6 5 sdi clk loaddacs cs v outa v dd gnd v outb dac7612u
4 dac7612 equivalent input logic serial shift register dac b register dac a register dac switches data dac switches 12 12 12 12 esd protection diodes to v dd and gnd loaddacs sdi cs clk
5 dac7612 timing diagrams logic truth table timing specifications t a = C40 c to +85 c and v dd = +5v. symbol description min typ max units t ch clock width high 30 ns t cl clock width low 30 ns t ldw load pulse width 20 ns t ds data setup 15 ns t dh data hold 15 ns t ld1 load setup 15 ns t ld2 load hold 10 ns t css select 30 ns t csh deselect 20 ns note: all input control signals are specified with t r = t f = 5ns (10% to 90% of +5v) and timed from a voltage level of 2.5v. these parameters are guaranteed by design and are not subject to production testing. sdi clk t cl t ch t dh t ds serial shift dac dac a1 a0 clk cs loaddacs register register a register b x x x h h no change no change no change xx - l h shifts one bit no change no change lxxh (1) l no change loads serial loads serial data word data word h l x h l no change loads serial no change data word h h x h l no change no change loads serial data word - positive logic transition; x = dont care. note: (1) a high value is suggested in order to avoid to false clock from advancing the shift register and changing the dac voltage. b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data input table a1 (msb) (lsb) sdi clk cs loaddacs a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t css t ld1 t ld2 t csh loaddacs fs zs v out t ldw t s 1 lsb error band
6 dac7612 typical performance curves at t a = +25 , and v dd = 5v, unless otherwise specified. 5.0 4.8 4.6 4.4 4.2 4.0 minimum supply voltage vs load v dd minimum (v) output load current (ma) 0.01 0.1 1 10 5 4 3 2 1 0 output swing vs load output voltage (v) load resistance ( w ) 10 100 1k 10k 100k r l tied to v dd data = 000 h r l tied to gnd data = fff h 70 60 50 40 30 20 10 0 power supply rejection vs frequency psr (db) frequency (hz) 10 100 1k 10k 100k 1m data = fff h v dd = 5v 200mv ac time (2ms/div) code = fff h , bw = 1mhz broadband noise noise voltage (500 m v/div) 1k 100 10 1 0.1 0.01 pull-down voltage vs output sink current delta v out (mv) current (ma) 0.001 0.01 0.1 1 10 100 +85 c data = 000 h ?0 c +25 c 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 supply current vs logic input voltage supply current (ma) logic voltage (v) 01 2345
7 dac7612 rise time detail v out (1mv/div) time (10 s/div) loaddacs c l = 100pf r l = no load typical performance curves (cont) at t a = +25 , and v dd = 5v, unless otherwise specified. 20 15 10 5 0 ? ?0 ?5 ?0 short-circuit current vs output voltage output current (ma) output voltage (v) 01 4 23 56 positive current limit data = 800 h output tied to i source negative current limit midscale glitch performance v out (5mv/div) time (500ns/div) 7ff h to 800 h loaddacs midscale glitch performance v out (5mv/div) time (500ns/div) 800 h to 7ff h loaddacs large-signal settling time v out (1v/div) time (20 s/div) c l = 100pf r l = no load loaddacs 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 supply current vs temperature supply current (ma) temperature ( c) ?0 ?0 ?0 10 30 50 70 90 110 130 v logic = 3.5v data = fff h no load v dd = 4.75v at worst-case digital inputs. v dd = 5.25v v dd = 5.0v
8 dac7612 typical performance curves (cont) at t a = +25 , and v dd = 5v, unless otherwise specified. 10.000 1.000 0.100 0.010 output voltage noise vs frequency noise ( v/ ? hz) frequency (hz) 10 100 1k 10k 100k data = fff h 5 4 3 2 1 0 ? ? ? ? ? long-term drift accelerated by burn-in output voltage change at fs (mv) hours of operation at +150 c 0 168 336 504 672 840 1008 max avg min 4.111 4.103 4.095 4.087 4.079 full-scale voltage vs temperature full-scale output (v) temperature ( c) ?0 ?5 10 35 60 85 avg + 3 s avg ?3 s avg 35 30 25 20 15 10 5 0 ?2 ?0 ? ? ? ? 0 2 8 4 6 10 12 t.u.e = s (inl + z se + fse) sample size = 200 units t a = +25 c number of units total unadjusted error histogram fall time detail v out (1mv/div) time (10 s/div) c l = 100pf r l = no load loaddacs 3 2 1 0 ? zero-scale voltage vs temperature zero-scale output (mv) temperature ( c) ?0 ?5 10 35 60 85 avg ?3 s avg avg + 3 s
9 dac7612 typical performance curves (cont) at t a = +25 , and v dd = 5v, unless otherwise specified. 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 linearity error vs digital code (dac a at +85 c) linearity error (lsbs) code 0 512 1024 1536 2048 2560 3072 3584 4096 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 linearity error vs digital code (dac b at +85 c) linearity error (lsbs) code 0 512 1024 1536 2048 2560 3072 3584 4096 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 linearity error vs digital code (dac a at +25 c) linearity error (lsbs) code 0 512 1024 1536 2048 2560 3072 3584 4096 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 linearity error vs digital code (dac b at +25 c) linearity error (lsbs) code 0 512 1024 1536 2048 2560 3072 3584 4096 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 linearity error vs digital code (dac a at ?0 c) linearity error (lsbs) code 0 512 1024 1536 2048 2560 3072 3584 4096 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 linearity error vs digital code (dac b at ?0 c) linearity error (lsbs) code 0 512 1024 1536 2048 2560 3072 3584 4096
10 dac7612 next 12 bits are the code (msb-first) sent to the dac. the data format is straight binary and is loaded msb-first into the shift registers after loading the address bits. table i shows the relationship between input code and output voltage. the digital data into the dac7612 is double-buffered. this means that new data can be entered into the chosen dac without disturbing the old data and the analog output of the converter. at some point after the data has been entered into the serial shift register, this data can be transferred into the dac registers. this transfer is accomplished with a high to low transition of the loaddacs pin. the loaddacs pin makes the dac registers transparent. if new data is shifted into the shift register while loaddacs is low, the dac output voltages will change as each new bit is entered. to prevent this, loaddacs must be returned high prior to shifting in new serial data. digital-to-analog converter the internal dac section is a 12-bit voltage output device that swings between ground and the internal ref- erence voltage. the dac is realized by a laser-trimmed r-2r ladder network which is switched by n-channel mosfets. each dac output is internally connected to a rail-to-rail output operational amplifier. output amplifier a precision, low-power amplifier buffers the output of each dac section and provides additional gain to achieve a 0v to 4.095v range. each amplifier has low offset voltage, low operation the dac7612 is a dual, 12-bit digital-to-analog converter (dac) complete with a serial-to-parallel shift register, dac registers, laser-trimmed 12-bit dacs, on-board reference, and rail-to-rail output amplifiers. figure 1 shows the basic operation of the dac7612. interface figure 1 shows the basic connection between a microcontroller and the dac7612. the interface consists of a serial clock (clk), serial data (sdi), and a load dac signal (loaddacs). in addition, a chip select (cs) input is available to enable serial communication when there are multiple serial devices. loading either dac a or dac b is done by shifting 14 serial bits in via the sdi input. the first 2 bits represent the address of the dac to be updated and the dac7612 full-scale range = 4.095v least significant bit = 1mv digital input code analog output straight offsetbinary (v) description fff h +4.095 full scale 801 h +2.049 midscale + 1 lsb 800 h +2.048 midscale 7ff h +2.047 midscale C 1 lsb 000 h 0 zero scale table i. digital input code and corresponding ideal analog output. figure 1. basic operation of the dac7612. 1 2 3 4 8 7 6 5 sdi clk loaddacs cs v outa v dd gnd v outb dac7612u serial data serial clock load dacs chip select 0.1 f 0v to +4.095v 0v to +4.095v 10 f +
11 dac7612 noise, and a set gain of 1.682v/v (4.095/2.435). see figure 2 for an equivalent circuit schematic of the analog portion of the dac7612. the output amplifier has a 7 m s typical settling time to 1 lsb of the final value. note that there are differences in the settling time for negative-going signals versus positive- going signals. the rail-to-rail output stage of the amplifier provides the full- scale range of 0v to 4.095v while operating on a supply voltage as low as 4.75v. in addition to its ability to drive resistive loads, the amplifier will remain stable while driving capacitive loads of up to 500pf. see figure 3 for an equivalent circuit schematic of the amplifiers output driver and the typical performance curves section for more information regarding settling time, load driving capability, and output noise. power supply a bicmos process and careful design of the bipolar and cmos sections of the dac7612 result in a very low power device. bipolar transistors are used where tight matching and low noise are needed to achieve analog accuracy, and cmos transistors are used for logic, switching functions and for other low power stages. if power consumption is critical, it is important to keep the logic levels on the digital inputs (sdi, clk, cs, loaddacs) as close as possible to either v dd or ground. this will keep the cmos inputs (see supply current vs logic input voltages in the typical performance curves) from shunting current between v dd and ground. the dac7612 power supply should be bypassed as shown in figure 1. the bypass capacitors should be placed as close to the device as possible, with the 0.1 m f capacitor taking priority in this regard. the power supply rejection vs frequency graph in the typical performance curves sec- tion shows the psrr performance of the dac7612. this should be taken into account when using switching power supplies or dc/dc converters. in addition to offering guaranteed performance with v dd in the 4.75v to 5.25v range, the dac7612 will operate with reduced performance down to 4.5v. operation between 4.5v and 4.75v will result in longer settling time, reduced performance, and current sourcing capability. consult the v dd vs load current graph in the typical performance curves section for more information. figure 2. simplified schematic of analog portion. figure 3. simplified driver section of output amplifier. n-channel p-channel v dd v out gnd 2r 2r 2r r 2r 2r r r 1 r r 2 output amplifier r-2r dac bandgap reference 2.435v typical of dac a or dac b buffer
12 dac7612 figure 4. suggested power and ground connections for a dac7612 sharing a +5v supply with a digital system. applications power and grounding the dac7612 can be used in a wide variety of situations from low power, battery operated systems to large-scale industrial process control systems. in addition, some appli- cations require better performance than others, or are par- ticularly sensitive to one or two specific parameters. this diversity makes it difficult to define definite rules to follow concerning the power supply, bypassing, and grounding. the following discussion must be considered in relation to the desired performance and needs of the particular system. a precision analog component requires careful layout, ad- equate bypassing, and a clean, well-regulated power supply. as the dac7612 is a single-supply, +5v component, it will often be used in conjunction with digital logic, microcontrollers, microprocessors, and digital signal proces- sors. the more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good performance. because the dac7612 has a single ground pin, all return currents, including digital and analog return currents, must flow through this pin. the gnd pin is also the ground reference point for the internal bandgap reference. ideally, gnd would be connected directly to an analog ground plane. this plane would be separate from the ground con- nection for the digital components until they are connected at the power entry point of the system (see figure 4). the power applied to v dd should be well regulated and low- noise. switching power supplies and dc/dc converters will often have high-frequency glitches or spikes riding on the output voltage. in addition, digital components can create similar high frequency spikes as their internal logic switches states. this noise can easily couple into the dac output voltage through various paths between v dd and v out . as with the gnd connection, v dd should be connected to a +5v power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. in addition, the 10 m f and 0.1 m f capaci- tors shown in figure 4 are strongly recommended and should be installed as close to v dd and ground as possible. in some situations, additional bypassing may be required such as a 100 m f electrolytic capacitor or even a pi filter made up of inductors and capacitorsall designed to essen- tially lowpass filter the +5v supply, removing the high frequency noise (see figure 4). + +5v gnd 100 f digital circuits +5v gnd +5v power supply other analog components v dd gnd dac7612 + 10 f 0.1 f optional
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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