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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? xr17l154 3.3v pci bus quad uart october 2002 rev. 1.0.0 general description the xr17l154 1 (l154) is a quad pci bus universal asynchronous receiver and transmitter (uart) with same package and pin-out as the exar xr17c158 octal uart. the device is designed to meet todays 32-bit pci bus and high bandwidth requirement in communication systems. the global interrupt source register provides a complete interrupt status indication for all 4 channels to speed up interrupt parsing. each uart is independently controlled and has its own 16c550 compatible 5g register set, transmit and receive fifos of 64 bytes, fully programmable transmit and receive fifo trigger levels, transmit and receive fifo level counters, automatic hardware flow control with programmable hysteresis, automatic software (xon/xoff) flow control, irda (infrared data association) encoder/ decoder, 8 multi-purpose definable inputs/outputs, and a 16-bit general purpose timer/counter. n ote : 1 covered by u.s. patents #5,649,122, #5,832,205 applications remote access servers ethernet network to serial ports network management factory automation and process control point-of-sale systems multi-port rs-232/rs-422/rs-485 cards features high performance quad uart pci bus 2.2 target interface compliance 3.3 volt pci bus compliant up to 33 mhz clock 5 volt tolerant serial inputs 32-bit pci bus interface with eeprom interface a global interrupt source register for all 4 uarts data transfer in byte, word and double-word data read/write burst operation each uart is independently controlled with: 16c550 compatible 5g (fifth gen) register set 64-byte transmit and receive fifos transmit and receive fifo level counters automatic rts/cts or dtr/dsr flow control automatic xon/xoff software flow control automatic rs485 half-duplex control output with selectable turn-around delay (0 to 15 bit-times) infrared (irda 1.0) data encoder/decoder programmable data rate with prescaler up to 4 mbps serial data rate at 8x eight multi-purpose inputs/outputs general purpose 16-bit timer/counter sleep mode with automatic wake-up same package and pin-out as xr17c158 and xr17c154 uarts (20x20x1.4mm 144-tqfp) f igure 1. b lock d iagram tmrck device configuration registers xtal1 xtal2 crystal osc/buffer uart channel 0 tx0, rx0, dtr0#, dsr0#, rts0#, cts0#, cd0#, ri0# pci local bus interface clk (33mhz) rst# ad[31:0] c/be[3:0]# par frame# irdy# trdy# devsel# stop# idsel perr# serr# inta# configuration space registers . mpio0- mpio7 multi-purpose inputs/outputs tx3, rx3, dtr3#, dsr3#, rts3#, cts3#, cd3#, ri3# uart channel 3 uart channel 2 uart channel 1 16-bit timer/counter eeck eedi eedo eecs eeprom interface 64 byte tx fifo 64 byte rx fifo brg ir endec tx & rx uart regs 3.3v vcc gnd *5v tolerance for non-pci inputs enir
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 2 f igure 2. p in o ut of the d evice ordering information p art n umber p ackage o perating t emperature r ange xr17l154cv 144-tqfp 0c to +70c xr17l154iv 144-tqfp -40c to +85c gnd mpio5 gnd tmrck enir 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 mpio0 mpio1 vcc gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ad24 cbe3 idsel vi/o gnd ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 cbe2 frame# irdy# trdy# devsel# vi/o stop# perr# serr# par cbe1 ad15 ad14 ad13 ad12 ad11 gnd vcc mpio7 mpio6 mpio4 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 eecs eedi eeck eedo vcc test# xtal1 xtal2 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 31 32 33 34 ad10 ad9 ad8 vi/o 35 36 gnd cbe0 mpio2 78 77 76 75 74 73 mpio3 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 vi/o 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 ad26 ad27 ad28 ad29 ad30 ad31 vi/o gnd clk rst# 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 inta# ad25 nc nc nc nc nc nc nc nc rx0 cts0# dsr0# cd0# ri0# rts0# dtr0# tx0 rx1 cts1# tx1 dtr1# rts1# ri1# cd1# dsr1# nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc rx2 cts2# tx2 dtr2# rts2# ri2# cd2# dsr2# rx3 cts3# dsr3# cd3# ri3# rts3# dtr3# tx3 nc nc nc nc nc nc nc nc xr17l154 144-tqfp
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 3 pin descriptions n ame p in #t ype d escription pci local bus interface rst# 134 i bus reset input (active low). it resets the pci local bus configuration space registers, device configuration registers and uart channel registers to the default condition, see ta b l e 1 8 . clk 135 i bus clock input of up to 33mhz at 3.3v. ad31-ad0 138-144, 1, 6-13 26-33 37-44 io address data lines [31:0] (bidirectional). frame# 15 i bus transaction cycle frame (active low). it indicates the beginning and dura- tion of an access. c/be3# - c/be0# 2,14,25,36 i bus command/byte enable [3:0] (active low). this line is multiplexed for bus command during the address phase and byte enable during the data phase. irdy# 16 i initiator ready (active low). during a write, it indicates valid data is present on data bus. during a read, it indicates the master is ready to accept data. trdy# 17 o target ready (active low). stop# 21 o target request to stop current transaction (active low). 5 idsel 3 i initialization device select (active high). devsel# 18 o device select to the xr17l154 (active low). inta# 133 od device interrupt from xr17l154 (open drain, active low). par 24 io parity is even across ad[31:0] and c/be[3:0]# (bidirectional, active high). perr# 22 o parity error indicator to host (active low). optional in bus target application. serr# 23 od system error indicator to host (open drain, active low). optional in bus target application. modem or serial i/o interface tx0 125 o uart channel 0 transmit data or infrared transmit data. rx0 132 i uart channel 0 receive data or infrared receive data. normal rxd input idles at logic 1 condition. the infrared pulses can be inverted internally prior the decoder by fctr[4]. rts0# 127 o uart channel 0 request to send or general purpose output (active low). cts0# 131 i uart channel 0 clear to send or general purpose input (active low). dtr0# 126 o uart channel 0 data terminal ready or general purpose output (active low). dsr0# 130 i uart channel 0 data set ready or general purpose input (active low). cd0# 129 i uart channel 0 carrier detect or general purpose input (active low). ri0# 128 i uart channel 0 ring indicator or general purpose input (active low). tx1 106 o uart channel 1 transmit data or infrared transmit data.
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 4 rx1 99 i uart channel 1 receive data or infrared receive data. normal rxd input idles at logic 1 condition. the infrared pulses can be inverted internally prior the decoder by fctr[4]. rts1# 104 o uart channel 1 request to send or general purpose output (active low). cts1# 100 i uart channel 1 clear to send or general purpose input (active low). dtr1# 105 o uart channel 1 data terminal ready or general purpose output (active low). dsr1# 101 i uart channel 1 data set ready or general purpose input (active low). cd1# 102 i uart channel 1 carrier detect or general purpose input (active low). ri1# 103 i uart channel 1 ring indicator or general purpose input (active low). tx2 88 o uart channel 2 transmit data or infrared transmit data. rx2 81 i uart channel 2 receive data or infrared receive data. normal rxd input idles at logic 1 condition. the infrared pulses can be inverted internally prior the decoder by fctr[4]. rts2# 86 o uart channel 2 request to send or general purpose output (active low). cts2# 82 i uart channel 2 clear to send or general purpose input (active low). dtr2# 87 o uart channel 2 data terminal ready or general purpose output (active low). dsr2# 83 i uart channel 2 data set ready or general purpose input (active low). cd2# 84 i uart channel 2 carrier detect or general purpose input (active low). ri2# 85 i uart channel 2 ring indicator or general purpose input (active low). tx3 62 o uart channel 3 transmit data or infrared transmit data. rx3 55 i uart channel 3 receive data or infrared receive data. normal rxd input idles at logic 1 condition. the infrared pulses can be inverted internally prior the decoder by fctr[4]. rts3# 60 o uart channel 3 request to send or general purpose output (active low). cts3# 56 i uart channel 3 clear to send or general purpose input (active low).d. dtr3# 61 o uart channel 3 data terminal ready or general purpose output (active low). dsr3# 57 i uart channel 3 data set ready or general purpose input (active low). cd3# 58 i uart channel 3 carrier detect or general purpose input (active low). ri3# 59 i uart channel 3 ring indicator or general purpose input (active low). ancillary signals mpio0 108 i/o multi-purpose input/output 0. the function of this pin is defined thru the con- figuration register mpiosel, mpiolvl, mpioinv, mpio3t and mpioint mpio1 107 i/o multi-purpose input/output 1. the function of this pin is defined thru the con- figuration register mpiosel, mpiolvl, mpioinv, mpio3t and mpioint. mpio2 74 i/o multi-purpose input/output 2. the function of this pin is defined thru the con- figuration register mpiosel, mpiolvl, mpioinv, mpio3t and mpioint. pin descriptions n ame p in #t ype d escription
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 5 n ote : pin type: i=input, o=output, io= input/output, od=output open drain. mpio3 73 i/o multi-purpose input/output 3. the function of this pin is defined thru the con- figuration register mpiosel, mpiolvl, mpioinv, mpio3t and mpioint. mpio4 68 i/o multi-purpose input/output 4. the function of this pin is defined thru the con- figuration register mpiosel, mpiolvl, mpioinv, mpio3t and mpioint. mpio5 67 i/o multi-purpose input/output 5. the function of this pin is defined thru the con- figuration register mpiosel, mpiolvl, mpioinv, mpio3t and mpioint. mpio6 66 i/o multi-purpose input/output 6. the function of this pin is defined thru the con- figuration register mpiosel, mpiolvl, mpioinv, mpio3t and mpioint. mpio7 65 i/o multi-purpose input/output 7. the function of this pin is defined thru the con- figuration register mpiosel, mpiolvl, mpioinv, mpio3t and mpioint. eeck 116 o serial clock to eeprom. pin has a weak internal pull-down resistor and requires an external 10k resistor to operate correctly with the eeprom. an internal clock of clk divide by 256 is used for reading the vendor and sub- vendor id and model number during power up or reset. however, it can be manually clocked thru the configuration register regb. eecs 115 o chip select to a eeprom device like 93c46. it is manually selectable thru the configuration register regb. requires a pull-up 4.7k w resistor for external sensing of eeprom during power up. see dan112 for further details. eedi 114 o write data to eeprom device. it is manually accessible thru the configura- tion register regb. the l154 auto-configuration register interface logic uses the 16-bit format. eedo 113 i read data from eeprom device. it is manually accessible thru the configu- ration register regb. xtal1 110 i crystal or external clock input of up to 33mhz for 2mbps at 3.3v. caution: this input is not 5v tolerant. xtal2 109 o crystal or buffered clock output. tmrck 69 i 16-bit timer/counter external clock input. enir 70 i infrared mode enable (active high). start up all 4 uarts in infrared mode upon power up or reset. test# 111 i factory test. connect to vcc for normal operation. vcc 64, 90, 112 pwr 5v or 3.3v power supply for the core logic. vi/o 4, 19, 34, 45, 137 pwr pci bus i/o power supply. 3.3v only (pci 2.2 compliance). gnd 5,20,35,46,63, 89,136 pwr power supply common, ground. nc 47-54, 71, 72, 75-80, 91-98, 117-124 no connection. these pins are reserved and used by the octal pci uart xr17c158. pin descriptions n ame p in #t ype d escription
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 6 functional description the xr17l154 (l154) integrates the functions of 4 enhanced 16550 uarts with the pci local bus interface and a non-volatile memory interface for pci buss plug-and-play auto-configuration, a 16-bit timer/counter, 8 multi-purpose inputs/outputs, and an on-chip oscillator. the pci local bus is a synchronous timing bus where all bus transactions are associated to the bus clock of up to 33 mhz. the l154 supports 32-bit wide read and write data transfer operations including data burst mode through the pci local bus interface. read and write data operations maybe in byte, word or double-word (dword) format. the data transfer rate in a dword operation is 4 times faster than the single byte operation with 8-bit isa bus. a single 32-bit interrupt status register provides interrupts status for all 4 uarts, timer/counter, multipurpose inputs/outputs, and a special sleep wake up indicator. there are three sets of register in the device. first, the pci local bus configuration registers for pci auto configuration. a set of device configuration registers for overall control, 32-bit wide transmit and receive data transfer, and monitoring of the 4 uart channels. lastly, each uart channel has its own 16550 uart compatible configuration register set for individual channel control, status, and byte wide data transfer. each uart has the improved fifth generation (5g) register set, 64-byte fifos, automatic rts/cts or dtr/ dsr hardware flow control with hysteresis control, automatic xon/xoff and special character software flow control, programmable transmit and receive fifo trigger level, fifo level counters, infrared encoder and decoder (irda ver 1.0), programmable baud rate generator with a prescaler of 1x or 4x, and data rate up to 2 mbps. the xr17l154 bus timing and drive capability meets the pci local bus specification revision 2.2 for 3.3v 33 mhz operation over the temperature range. the xr17l154 is available in the same thin 144-pin tqfp (20x20x1.4mm) package and pin-out as the xr17c154 and xr17c158 in commercial and industrial temperature ranges. pci l ocal b us i nterface this is the host interface and it meets the pci local bus specification revision 2.2. the pci local bus operations are synchronous meaning each transaction is associated to the bus clock. the xr17l154 can operate with the bus clock of up to a 33 mhz. data transfers operation can be formatted in 8-bit, 16-bit, 24-bit or 32-bit wide. with 32-bit data operations, it pushes the data transfer rate on the bus up to 132 mbyte/sec. this increases the overall systems communication performance up to 16 times better than the 8-bit isa bus. see pci local bus specification revision 2.2 for bus operation details. pci l ocal b us c onfiguration s pace r egisters a set of pci local bus configuration space register is provided. these registers provide the pci local bus operating system with the cards vendor id, device id, sub-vendor id, product model number, and resources and capabilities. the pci local bus operating system collects this data from all the cards on the bus during the auto configuration phase that follows immediately after a power up or system reset/reboot. after it has sorted out all devices on the bus, it defines and download the operating conditions to the cards. one of the definitions is the base address loaded into the base address register (bar) where the card will be operating in the pci local bus memory space. eeprom i nterface an external 93c46 eeprom is only used to store the vendors id and model number, and the sub-vendors id and product model number. this information is only used with the plug-and-play auto configuration of the pci local bus. these data provide automatic hardware installation onto the pci bus. the eeprom interface consists of 4 signals, eedi, eedo, eecs, and eeck. the eeprom is not needed when auto configuration is not required in the application. however, if your design requires non-volatile memory for other purpose. it is possible to store and retrieve data on the eeprom through a special pci device configuration register. see application note dan112 for its programming details.
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 7 1.0 xr17l154 registers the xr17l154 uart has three different sets of registers as shown in figure 3 . the pci local bus configuration space registers are for plug-and-play auto-configuration when connecting the device to the pci bus. this auto-configuration feature makes installation very easy into a pci system and it is part of the pci local bus specification. the second register set is the device configuration registers that are accessible directly from the pci bus for programming general operating conditions of the device and monitoring the status of various functions. these registers are mapped into 2k of the pci bus memory address space. these functions include all 4 channel uarts interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification and revision. and lastly, each uart channel has its own set of 5g internal uart configuration registers for its own operation control and status reporting. all 4 sets of channel registers are embedded inside the device configuration registers space, which provides faster access. the following paragraphs describe all 3 sets of registers in detail. 1.1 pci local bus configuration space registers the pci local bus configuration space registers are responsible for setting up the devices operating environment in the pci local bus. the pre-defined operating parameters of the device are read by the pci bus plug-and-play auto-configuration manager in the operating system. after the pci bus has collected all data from every device/card on the bus, it defines and downloads the memory mapping information to each device/ card about their individual operation memory address location and conditions. the operating memory mapped address location is downloaded into the base address register (bar) register, 0x10. the plug-and-play auto configuration feature is only available when an external 93c46 eeprom is used. the eeprom contains the device vendor and sub-vendor data required by the auto-configuration setup. f igure 3. t he xr17l154 r egister s ets channel 0 int, mpio, timer, reg device configuration and uart[3:0] configuration registers are mapped on to the base address register (bar) in a 2k- byte of memory address space pci local bus target interface channel 0 channel 1 channel 2 channel 3 device configuration registers 4 channel interrupts, multipurpose i/os, 16-bit timer/counter, sleep, reset, dvid, drev uart[3:0] configuration registers 16550 compatible and exar enhanced registers pci local bus configuration space registers for plug- and-play auto configuration pciregs-1 vendor and sub-vendor id and product model number in external eeprom 0x0000 0x0200 0x0400 0x0600 0x0080 0x07ff 0x0100
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 8 t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress b its t ype d escription r eset v alue ( hex ) 0x00 31:16 rwr 1 device id (exar device id number or from eeprom) 0x0154 15:0 rwr 1 vendor id (exar id or from eeprom) specified by pcisig 0x13a8 0x04 31:28 ro status bits (error reporting bits) 0000 27 r-reset target abort. set whenever l154 terminates with a target abort. 0 26:25 ro devsel# timing. 00 24 ro unimplemented bus master error reporting bit 0 23 ro fast back to back transactions are supported 1 22:16 ro reserved status bits 000 0000 15:9,7, 5,4,3,2 ro command bits (reserved) 0x0000 8 wo serr# driver enable. logic 1=enable driver and 0=disable driver 0 6 wo parity error enable. logic 1=respond to parity error and 0=ignore 0 1 rwr command controls a devices response to mem space accesses: 0=disable mem space accesses, 1=enable mem space accesses 0 0 ro command controls a devices response to i/o space accesses: 0 = disable i/o space accesses 1 = enable i/o space accesses 0 0x08 31:8 ro class code (simple 550 communication controller). 0x070002 7:0 ro revision id (exar device revision number) 0x01 0x0c 31:24 ro bist (built-in self test) 0x00 23:16 ro header type (a single function device with one bar) 0x00 15:8 ro unimplemented latency timer (needed only for bus master) 0x00 7:0 ro unimplemented cache line size 0x00 0x10 31:11 rw memory base address register (bar) 0x00 10:0 ro claims a 2k address space for the memory mapped uarts 0xx000 0x14 31:0 ro unimplemented base address register (returns zeros) 0x00000000 0x18h 31:0 ro unimplemented base address register (returns zeros) 0x00000000 0x1c 31:0 ro unimplemented base address register (returns zeros) 0x00000000 0x20 31:0 ro unimplemented base address register (returns zeros) 0x00000000 0x24 31:0 ro unimplemented base address register (returns zeros) 0x00000000 0x28 31:0 ro reserved 0x00000000 0x2c 31:16 rwr 1 subsystem id (write from external eeprom by customer) 0x0000
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 9 1.2 device configuration register set the device configuration registers and a special way to access each of the uarts transmit and receive data fifos are accessible directly from the pci data bus. this provides easy programming of general operating parameters to the l154 uart and for monitoring the status of various functions. the registers occupy 2k of pci bus memory address space. these addresses are offset onto the basic memory address, a value loaded into the memory base address register (bar) in the pci local bus configuration register set. these registers control or report on all 4 channel uarts functions that include interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft- reset control, and device identification and revision, and others. the registers set is mapped into 4 address blocks where each uart channel occupies 512 bytes memory space for its own 16550 compatible configuration registers. the device configuration and control registers are embedded inside the uart channel zeros address space between 0x0080 to 0x0093. all these registers can be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the bus cycle. transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the registers address. every time a read or write operation is made to the transmit or receive register, its fifo data pointer is automatically bumped to the next sequential data location either in byte, word or dword. one special case applies to the receive data unloading when reading the receive data together with its lsr register content. the host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated error flags. 15:0 rwr 1 subsystem vendor id (write from external eeprom by cus- tomer) 0x0000 0x30 31:0 ro expansion rom base address (unimplemented) 0x00000000 0x34 31:0 ro reserved (returns zeros) 0x00000000 0x38 31:0 ro reserved (returns zeros) 0x00000000 0x3c 31:24 ro unimplemented maxlat 0x00 23:16 ro unimplemented mingnt 0x00 15:8 ro interrupt pin, use inta#. 0x01 7:0 rwr interrupt line. 0xxx n ote : rwr 1 =read/write from external eeprom. rwr=read/write from ad[31:0]. ro= read only. wo=write only. t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress b its t ype d escription r eset v alue ( hex )
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 10 t able 2: xr17l154 d evice c onfiguration r egisters o ffset a ddress m emory s pace r ead /w rite d ata w idth c omment 0x000 - 0x00f uart channel 0 regs ( ta b l e 1 0 & ta b l e 1 1 ) 8/16/24/32 first 8 regs are 16550 compatible 0x010 - 0x07f reserved 0x080 - 0x093 device config. registers ( ta b l e 3 ) 8/16/24/32 0x094 - 0x0ff reserved read/write 0x100 uart 0 C read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x100 uart 0 C write fifo write-only 8/16/24/32 64 bytes of tx fifo data 0x140 - 0x17f reserved 0x180 - 0x1ff uart 0 C read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr 0x200 - 0x20f uart channel 1 regs ( ta b l e 1 0 & ta b l e 1 1 ) 8/16//24/32 first 8 regs are 16550 compatible 0x210 - 0x2ff reserved read/write 0x300 uart 1 C read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x300 uart 1 C write fifo write-only 8/16/24/32 64 bytes of tx fifo data 0x340 - 0x37f reserved 0x380 - 0x3ff uart 1 C read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr 0x400 - 0x40f uart channel 2 regs ( ta b l e 1 0 & ta b l e 1 1 ) 8/16/24/32 first 8 regs are 16550 compatible 0x410 - 0x4ff reserved read/write 0x500 uart 2 C read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x500 uart 2 C write fifo write-only 8/16/24/32 64 bytes of tx fifo data 0x540 - 0x57f reserved 0x580 - 0x5ff uart 2 C read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr 0x600 - 0x60f uart channel 3 regs ( ta b l e 1 0 & ta b l e 1 1 ) 8/16/24/32 first 8 regs are 16550 compatible 0x610 - 0x6ff reserved read/write 0x700 uart 3 C read fifo read-only 8/16/24/32 64 bytes of rx fifo data 0x700 uart 3 C write fifo write-only 8/16/24/32 64 bytes of tx fifo data 0x740 - 0x77f reserved 0x780 - 0x7ff uart 3 C read fifo with errors read-only 16/32 64 bytes of rx fifo data + lsr
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 11 t able 3: d evice c onfiguration r egisters shown in byte alignment a ddress [a7:a0] r egister r ead /w rite c omment r eset s tate ox080 int0 [7:0] read-only interrupt [3:0], reserved [7:4] bits 7-0 = 0x00 ox081 int1 [15:8] read-only bits 7-0 = 0x00 ox082 int2 [23:16] read-only [3:0], reserved [7:4] bits 7-0 = 0x00 ox083 int3 [31:24] reserved [7:0] bits 7-0 = 0x00 ox084 timercntl read/write timer control bits 7-0 = 0x00 ox085 timer reserved bits 7-0 = 0x00 ox086 timerlsb read/write timer lsb bits 7-0 = 0x00 ox087 timermsb read/write timer msb bits 7-0 = 0x00 ox088 8xmode read/write bits 7-0 = 0x00 ox089 rega reserved bits 7-0 = 0x00 ox08a reset write-only self clear bits after executing reset [3:0] bits 7-0 = 0x00 ox08b sleep read/write sleep mode [3:0] bits 7-0 = 0x00 ox08c drev read-only device revision bits 7-0 = 0x01 ox08d dvid read-only device identification bits 7-0 = 0x24 ox08e regb read/write bits 7-0 = 0x00 ox08f mpioint read/write mpio interrupt mask bits 7-0 = 0x00 ox090 mpiolvl read/write mpio level control bits 7-0 = 0x00 ox091 mpio3t read/write mpio output control bits 7-0 = 0x00 ox092 mpioinv read/write mpio input polarity select bits 7-0 = 0x00 ox093 mpiosel read/write mpio select bits 7-0 = 0xff
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 12 1.2.1 the interrupt status register the xr17l154 has a 32-bit wide register [int0, int1, int2 and int3] to provide interrupt information and supports two interrupt schemes. the first scheme is a 4-bit indicator in int0 register representing the 4 channels with the first 4 bits representing each channel from 0 to 3. this permits the interrupt routine to quickly vector and serve that uart channel and determine the source(s) in each individual routines. int0 bit-0 represents the interrupt status for uart channel 0 when its transmitter, receiver, line status, or modem port status requires service. other bits in the int0 register provide indication for the other channels with bit-3 representing uart channel 4 respectively, bits 4 to 7 are reserved and remain at logic zero. the second scheme provides detail about the source of the interrupts for each uart channel. all the interrupts are encoded into a 3-bit code. this 3-bit code represents 7 interrupts corresponding to individual uarts transmitter, receiver, line status, modem port status. int1 and int2 registers provide the 12-bit interrupt status for all 4 channels. bits 8, 9 and 10 representing channel 0 and bits 17,18 and 19 representing channel 3 respectively. bits 20 to 31 are reserved and remain at logic zero. all 4 channel interrupts status are available with a single dword read operation. this feature allows the host quickly vectors and serves the interrupts, reducing service interval, hence, reduce host bandwidth requirement. all bits start up zero. a special interrupt condition is generated by the l154 upon awakening from sleep after all 4 channels were put to sleep mode earlier. figure 4 shows the 4-byte interrupt register and its make up. int0 [7:0] channel interrupt indicator each bit gives an indication of the channel that has requested for service. bit-0 represents channel 0 and bit-3 indicates channel 3. logic one indicates the channel n [3:0] has called for service. bits 4 to 7 are reserved and remain at logic zero the interrupt bit clears after reading the appropriate register of the interrupting channel register, see interrupt clearing section. t able 4: d evice c onfiguration r egisters shown in dword alignment a ddress r egister b yte 3 [31:24] b yte 2 [23:16] b yte 1 [15:8] b yte 0 [7:0] 0x080 - 083 interrupt (read-only) int3 int2 int1 int0 0x084-087 timer (read/write) timermsb timerlsb timer (reserved) timercntl 0x088-08b ancillary1 (read/write) sleep reset rega (reserved) 8xmode 0x08c-08f ancillary2 (read-only) mpioint regb dvid drev 0x090-093 mpio (read/write) mpiosel mpioinv mpio3t mpiolvl global interrupt register (dword) - [default 0x00-00-00-00] int3 [31:24] int2 [23:16] int1 [15:8] int0 [7:0] int0 register provides status for each channel int0 register individual uart channel interrupt status rsvd ch-3 ch-2 ch-1 ch-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd rsvd rsvd
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 13 registers int3, int2 and int1 [32:8] twenty four bit encoded interrupt indicator. each channels interrupt is encoded into 3 bits for receive, transmit, and status. bit [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. the 3 bit encoding and their priority order are shown below in ta b l e 5 . the timer and mpio interrupts are for the device and therefore they exist within channel 0 space and not in other channel interrupt. . f igure 4. t he g lobal i nterrupt r egister , int0, int1, int2 and int3 t able 5: uart c hannel [3:0] i nterrupt s ource e ncoding p riority b it [ n +2] b it [ n +1] b it [ n ] i nterrupt s ource ( s ) x000none 1 0 0 1 rxrdy and rx line status (logic or of lsr[4:1]) 2010rxrdy time-out 3 0 1 1 txrdy, thr or tsr (auto rs485 mode) empty 4 1 0 0 msr, rts/cts or dtr/dsr delta or xoff/xon det. or special char. detected 5 1 0 1 reserved. 6 1 1 0 mpio pin(s). available only within channel 0, reserved in other channels. 7 1 1 1 timer time-out. available only within channel 0, reserved in other channels. channel-3 channel-2 channel-1 channel-0 int2 register int1 register int3 register int0 register interrupt registers, int0, int1, int2 and int3 bit-0 bit-1 bit-2 bit-3 bit-7 bit-4 bit-5 bit-6 ch-3 ch-2 ch-1 ch-0 bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 14 1.2.2 general purpose 16-bit timer/counter [timermsb, timelsb, timer, timecntl] ( default 0 x xx-xx-00-00) a 16-bit down-count timer for general purpose timer or counter. its clock source may be selected from internal crystal oscillator or externally on pin tmrck. the timer can be set to be a single-shot for a one-time event or re-triggerable for continue interval. an interrupt may be generated in the int register when the timer times out. it is controlled through 4 configuration registers [timercntl, timer, timelsb, timermsb]. these registers provide start/stop and re-triggerable or one-shot operation. the time-out output of the timer can be set to generate an interrupt for system or event alarm. t able 6: uart c hannel [3:0] i nterrupt c learing : rxrdy is clear by reading data in the rx fifo until it falls below the trigger level. rxrdy time-out interrupt is cleared when the rx fifo becomes empty. rx line status interrupt clears after reading the lsr register. txrdy interrupt clears after reading isr register that is in the uart channel register set. modem status register interrupt clears after reading msr register that is in the uart channel register set. rts/cts or dtr/dsr delta interrupt clears after reading msr register that is in the uart channel register set. xoff/xon delta and special character detect interrupt clears after reading the isr register in the uart channel register set. timer time-out interrupt clears after reading the timercntl register that is in the device configuration register set. mpio interrupt clears after reading the mpiolvl register that is in the device configuration register set. f igure 5. t imer /c ounter circuit . t able 7: timer control r egisters timercntl [0] logic zero (default) disables timer-counter interrupt and logic one enables the interrupt, reading the timercntl clears the interrupt. timercnlt [1] logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter. timercntl [2] logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function. timercntl [3] logic zero (default) selects internal and logic one selects external clock to the timer/counter. timercntl [4] routes the timer-counter interrupt to mpio[0] if mpiosel[0]=0 for external event control. timercntl [7:5] reserved (defaults to zero) tmrck osc. clock timercntl [3] 16-bit timer/counter timercntl [2] re-trigger single-shot timercntl [1] start/stop timercntl [0] tim er interrupt, ch-0 int=7 time-out timer interrupt enable single/re-triggerable timermsb and timerlsb (16-bit value) 0 1 0 1 0 1 no interrupt clock select timercntl [4] 0 1 m pio [0] mpiolvl[0]
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 15 timer [15:8] - (default 0x00) reserved. timermsb [31:24] and timerlsb [23:16] timermsb and timerlsb form a 16-bit value. the least-significant bit of the timer is being bit [0] of the timerlsb with most-significant-bit being bit [7] in timermsb. notice that these registers do not hold the current counter value when read. reading the timercntl register will clear its interrupt. default value is zero (timer disabled) upon powerup and reset. 1.2.3 8xmode [7:0] - (default 0x00) each bit selects 8x or 16x sampling rate for that uart channel, bit-0 is channel 0. logic 0 (default) selects normal 16x sampling with logic one selects 8x sampling rate. transmit and receive data rates will double by selecting 8x. 1.2.4 rega [15:8] - (default 0x00) reserved. 1.2.5 reset [23:16] - (default 0x00) the 8-bit reset register [reset] provides the software with the ability to reset the uart(s) when there is a need. each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. all registers in that channel will be reset to the default condition, see table 18 for details. bit-0 =1 resets uart channel 0 with bit- 3=1 resets channel 3.. timercntl register rsvd rsvd rsvd mpio[0] control clock select single/ re-trigger start/ stop int enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 timermsb register bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 timerlsb register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 16-bit timer/counter programmable registers rsvd rsvd rsvd rsvd ch-3 ch-2 ch-1 ch-0 8xmode register individual uart channel 8x clock mode enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd rsvd rsvd rsvd ch-3 ch-2 ch-1 ch-0 reset register individual uart channel reset enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 16 1.2.6 sleep [31:24] - (default 0x00) the first four bits of the sleep register enables each uart channel separately to enter sleep mode. the upper bits 4 to 7 are reserved. sleep mode reduces power consumption when the system needs to put the uart(s) to idle. the uart enters sleep mode when there is no interrupt pending. when all 4 uarts are put to sleep, the on-chip oscillator shuts off to further conserve power. in this case, the quad uart is awaken by any of the uart channel on from a receive data byte or a change on the serial port. the uart is ready after 32 crystal clocks to ensure full functionality. also, a special interrupt is generated with an indication of no pending interrupt. logic 0 (default) is disable and logic 1 is enable to sleep mode. 1.2.7 device identification and revision there are 2 internal registers that provide device identification and revision, dvid and drev registers. the 8- bit content in the dvid register provides device identification. a return value of 0x24 from this register indicates the device is an xr17l154 or an xr17c154. the drev register returns an 8-bit value of 0x01 for revision a with 0x02 equals to revision b and so forth. this information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes. dvid [15:8] - (default 0x24) device identification for the type of uart. the upper nibble indicates it is a xr17cxxx series with lower nibble indicating the number of channels. examples: xr17c158 = 0x28 xr17l154 or xr17l154 = 0x24 xr17c152 or xr17l152 = 0x22 drev [7:0] - (default (0x01) revision number of the xr17l154. a 0x01 represents "revision-a" with 0x02 for rev-b and so forth. regb [23:16] - (default 0x00) regb register provides a control for simultaneous write to all 4 uarts configuration register or individually. this is very useful for device initialization in the power up and reset routines. also, the register provides a facility to interface to the non-volatile memory device such as a 93c46 eeprom. in embedded applications, the user can use this facility to store proprietary data. 1.2.8 rgeb register regb[16] (read/write) logic 0 (default) write to each uart configuration registers individually. logic 1 enables simultaneous write to all 4 uarts configuration register. regb[19:17] reserved regb[20] (write-only) control the eeck, clock, output (pin 116) on the eeprom interface. regb[21] (write-only) control the eecs, chips select, output (pin 115) to the eeprom device. regb[22] (write-only) eedi (pin 114) data input. write data to the eeprom device. regb[23] (read-only) eedo (pin 113) data output. read data from the eeprom device. sleep register individual uart channel sleep enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd ch-3 ch-2 ch-1 ch-0 rsvd rsvd rsvd
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 17 1.2.9 multi-purpose inputs and outputs the l154 provides 8 multi-purpose inputs/outputs [mpio7:0] for general use. each pin can be programmed to be an input or output function. the input logic state can be set for normal or inverted level, and optionally set to generate an interrupt. the outputs can be set to be normal logic 1 or 0 state, or tri-state. their functions and definitions are programmed through 5 registers: mpioint, mpiolvl, mpio3t, mpioinv and mpiosel. if all 8 pins are set for inputs, all 8 interrupts would be ored together. the ored interrupt is reported in the channel 0 uart interrupt status, see interrupt status register. the pins may also be programmed to be outputs and to the tri-state condition for signal sharing. 1.2.10 mpio register bit 7 represents mpio7 pin and bit 0 represents mpio0 pin. there are 5 registers that select, control and monitor the 8 multipurpose inputs and outputs pins. figure 6 shows the internal circuitry. f igure 6. m ultipurpose input / output internal circuit mpio pin [7:0] m pio lvl [7:0] read input level m pio int [7:0] rising edge detection int or and and 1 0 m pio sel [7:0] (select input=1, o utput=0 ) m pio 3t [7:0] (3-state enable =1) m pio lvl [7:0] (output level) m pio inv [7:0] (input inversion enable =1) mpiockt
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 18 mpioint [7:0] - (default 0x00) enable multipurpose input pin interrupt. if the pin is selected by mpiosel as input then bit-0 enables input pin 0 for interrupt, and bit-7 enables input pin 7. no interrupt is enable if the pin is selected to be an output. the interrupt is edge sensing and determined by mpioinv and mpiolvl registers. the mpio interrupt clears after a read to register mpiolvl. the combination of mpiolvl and mpioinv determines the interrupt being active low or active high, its level trigger. logic 0 (default) disables the pins interrupt and logic 1 enables it. mpiolvl [7:0] - (default 0x00) output pin level control and input level status. the status of the input pin(s) is read on this register and output pins are controlled on this register. a logic 0 (default) sets the output to low and a logic 1 sets the output pin to high. the mpio interrupt will clear upon reading this register. mpio3t [7:0] - (default 0x00) output pin tri-state control. a logic 0 (default) sets the output to active level per register mpiobit settling, a logic 1 sets the output pin to tri-state. mpioinv [7:0] - (default 0x00) input inversion control. a logic 0 (default) does not invert the input pin logic. a logic 1 inverts the input logic level. mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 m pioint register m ultipurpose input/output interrupt enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpiolvl re g ister multipurpose output level control bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 m pio3t re g ister multipurpose output 3-state enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 m pioinv register multipurpose input signal inversion enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 19 mpiosel [7:0] - (default 0xff) multipurpose input/output pin select. this register defines the functions of the pins. a logic 1 (default) defines the pin for input and a logic "0" for output. 2.0 crystal oscillator / buffer the l154 includes an on-chip oscillator (xtal1 and xtal2). the crystal oscillator provides the system clock to the baud rate generators (brg) in each of the 4 uarts, the 16-bit general purpose timer/counter and internal logics. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. caution: the xtal1 input is not 5v tolerant. see programmable baud rate generator in the uart section for programming details. the on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant with 10-22 pf capacitance load, 100ppm) connected externally between the xtal1 and xtal2 pins (see figure 7 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal 8 baud rate generators for standard or custom rates. typically, the oscillator connections are shown in figure 7 . for further reading on oscillator circuit please see application note dan108 on exars web site. 3.0 transmit and receive data there are two methods to load transmit data and unload receive data from each uart channel. first, there is a transmit data register and receive data register for each uart channel in the device configuration register set to ease programming. these registers support 8, 16 , 24 and 32 bits wide format. in the 32-bit format, it increases the data transfer rate on the pci bus. additionally, a special register location provides receive data byte with its associated error flags. this is a 16-bit or 32-bit read operation where the line status register (lsr) content in the uart channel register is paired along with the data byte. this operation further facilitates data unloading with the error flags without having to read the lsr register separately. furthermore, the xr17l154 supports pci burst mode for read/write operation of up to 64 bytes of data. the second method is through each uart channels transmit holding register (thr) and receive holding register (rhr). the thr and rhr registers are 16550 compatible so their access is limited to 8-bit format. the software driver must separately read the lsr content for the associated error flags before reading the data byte. f igure 7. t ypical oscillator connections mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpiosel re g ister multipurpose input/output selection bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 c1 22-47pf c2 22-47pf 14.7456 mhz xtal1 xtal2 r=300k to 400k
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 20 3.1 fifo data loading and unloading through the device configuration registers in 32-bit format. the transmit and receive data registers are defined for channel 0 to channel 3 with each channel having its own address as shown in ta b l e 2 for faster loading and unloading. the following paragraphs illustrate the receive and transmit data registers in more detail. each channel normal receive data fifo address for channels 0 to 3 are at 0x0100, 0x0300, 0x0500 and 0x0700. each channel normal transmit data fifo address for channel 0 to 3 are at 0x0100, 0x0300, 0x0500 and 0x0700. each channel special receive fifo data address for channel 0 to 3 are at 0x0180 0x380, 0x0580 and 0x0780. the status and data bytes must be read in 16 or 32 bits format to maintain data integrity. r ead rx fifo, with n o e rrors b yte 3 b yte 2b yte 1b yte 0 read n+0 to n+3 fifo data n+3 fifo data n+2 fifo data n+1 fifo data n+0 read n+4 to n+7 fifo data n+7 fifo data n+6 fifo data n+5 fifo data n+4 etc. w rite tx fifo b yte 3 b yte 2b yte 1b yte 0 write n+0 to n+3 fifo data n+3 fifo data n+2 fifo data n+1 fifo data n+0 write n+4 to n+7 fifo data n+7 fifo data n+6 fifo data n+5 fifo data n+4 etc. pci bus data b it-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 receive data b yte n+3 receive data b yte n+2 receive data b yte n+1 receive data b yte n+0 pci bus data b it-0 channel 0 to 3 receivedata in 32-bit alignment through the configuration register address 0x0100, 0x0300, 0x0500 and 0x0700 pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 transmit data byte n+3 transmit data byte n+2 transmit data byte n+1 transmit data byte n+0 pci bus data bit-0 channel 0 to 3 transmit data in 32-bit alignment through the configuration register address 0x0100, 0x0300, 0x0500 and 0x0700
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 21 3.2 fifo data loading and unloading through the uart channel registers, thr and rhr in 8-bit format. the thr and rhr register address for channel 0 to channel 3 is shown in ta b l e 8 below. the thr and rhr for each channel 0 to 3 are located sequentially at address 0x0000, 0x0200, 0x0400 and 0x0600. transmit data byte is loaded to the thr when writing to that address and receive data is unloaded from the rhr register when reading that address. both thr and rhr registers are 16c550 compatible in 8-bit format, so each bus operation can only write or read in bytes. 4.0 uart there are 4 uarts [channels 3:0] in the l154. each has its own 64-byte of transmit and receive fifo, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel data rate setting. eight additional registers per uart were added for the exar enhanced features. r ead rx fifo, with lsr e rrors b yte 3 b yte 2b yte 1b yte 0 read n+0 to n+1 fifo data n+1 lsr n+1 fifo data n+0 lsr n+0 read n+2 to n+3 fifo data n+3 lsr n+3 fifo data n+2 lsr n+2 etc t able 8: t ransmit and r eceive d ata r egister in b yte format , 16c550 compatible pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 receive data byte n+1 line status register n+1 receive data byte n+0 line status register n+0 pci bus data bit-0 channel 0 to 3 receive data with line status register in a 32-bit alignment through the configuration register address 0x0180, 0x0380, 0x0580 and 0x0780 thr and rhr address locations for ch0 to ch3 (16c550 compatible) ch0 0x000 write thr ch0 0x000 read rhr ch1 0x200 write thr ch1 0x200 read rhr ch2 0x400 write thr ch2 0x400 read rhr ch3 0x600 write thr ch3 0x600 read rhr 784thrrhr1 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 22 4.1 programmable baud rate generator each uart has its own baud rate generator (brg) with a prescaler for the transmitter and receiver. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the output of the prescaler clocks to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16x or 8x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll and dlm registers) defaults to a random value upon power up. therefore, the brg must be programmed during initialization to the operating data rate. programming the baud rate generator registers dlm and dll provides the capability for selecting the operating data rate. ta b l e 9 shows the standard data rates available with a 14.7456 mhz crystal or external clock at 16x clock rate. at 8x sampling rate, these data rates would double. when using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s). f igure 8. b aud r ate g enerator divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16), with 8xmode [3:0] is 0 divisor (decimal) = (xtal1 clock frequency / prescaler / (serial data rate x 8), with 8xmode [3:0] is 1 xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x or 8x sampling rate clock to transmitter and receiver to other channels baud rate generator logic
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 23 4.2 automatic hardware (rts/cts or dtr/dsr) flow control operation automatic rts/dtr and cts/dsr flow control, also known as hardware flow control, is used to prevent data overrun to the local receiver fifo and remote receiver fifo. the rts#/dtr# output pin is used to request remote unit to suspend/restart data transmission while the cts#/dsr# input pin is monitored to suspend/ restart local transmitter. the auto rts/dtr and auto cts/dsr flow control features are individually selected to fit specific application requirement and enabled through efr bit-6 and 7 and mcr bit-2 for either rts/cts or dtr/dsr control signals. the auto rts/dtr function must be started by asserting rts/dtr# output pin (mcr bit-0 or 1 to logic 1 after it is enabled. figure 9 below explains how it works. two interrupts associated with rts/dtr and cts/dsr flow control have been added to give indication when rts/dtr# pin or cts/dsr# pin is de-asserted during operation. the rts/dtr and cts/dsr interrupts must be first enabled by efr bit-4, and then enabled individually by ier bit-6 and 7, and chosen with mcr bit-2. automatic hardware flow control is selected by setting bits 6 (rts) and 7 (cts) of the efr register to logic 1. if cts# pin transitions from logic 0 to logic 1 indicting a flow control request, isr bit-5 will be set to logic 1, (if enabled via ier bit 6-7), and the uart will suspend tx transmissions as soon as the stop bit of the character in process is shifted out. transmission is resumed after the cts# input returns to logic 0, indicating more data may be sent. t able 9: t ypical data rates with a 14.7456 mh z crystal or external clock at 16x s ampling o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 24 f igure 9. a uto rts/dtr and cts/dsr f low c ontrol o peration the local uart (uarta) starts data transfer by asserting -rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to send data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger level, uarta activates its rxa data ready interrupt (5) and con- tinues to receive and put data into its fifo. if interrupt service latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper threshold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. uartb stops or finishes sending the data bits in its trans- mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 25 4.3 infrared mode each uart in the l154 includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the input pin enir conveniently activates all 4 uart channels to start up in the infrared mode. this global control pin enables the mcr bit-6 function in every uart channel register. after power up or a reset, the software can overwrite mcr bit-6 if so desired. enir and mcr bit-6 also disable its receiver while the transmitter is sending data. this prevents the echoed data from going to the receiver. the global activation enir pin prevents the infrared emitter from turning on and drawing large amount of current while the system is starting up. when the infrared feature is enabled, the transmit data outputs, tx[3:0], would idle at logic zero level. likewise, the rx[3:0] inputs assume an idle level of logic zero. the infrared encoder sends out a 3/16 of a bit wide pulse for each 0 bit in the transmit data stream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 10 below. the infrared decoder receives the input pulse from the infrared sensing diode on rx pin. each time it senses a light pulse, it returns a logic zero to the data bit stream. the rx input signal may be inverted prior delivered to the input of the decoder. this option supports active low instead of normal active high pulse from some infrared modules on the market. f igure 10. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 26 4.4 internal loopback each uart channel provides an internal loopback capability for system diagnostic. the internal loopback mode is enabled by setting mcr register bit-4 to logic 1. all regular uart functions operate normally. figure 11 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. 4.5 uart channel configuration registers and address decoding. the 4 sets of uart configuration registers are decoded using address lines a9 to a11 as shown below: f igure 11. i nternal l oop b ack a11 a10 a9 uart c hannel s election 000 0 001 1 010 2 011 3 tx [3:0] rx [3:0] modem / general purpose control logic internal bus lines and control signals rts# [3:0] mc r bit-4=1 vcc vcc vcc trans mit shif t register rec eiv e shif t register cts# [3:0] dtr# [3:0] dsr# [3:0] ri# [3:0] cd# [3:0] op1# op2# rts# cts# dtr# dsr# ri# cd#
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 27 address lines a0 to a3 select the 16 registers in each channel. the first 8 registers are 16550 compatible with the exar enhanced feature registers located on next 8 addresses locations. addresses 0x080 to 0x093 comprise the device configuration registers and they reside in channel 0s space. . t able 10: uart channel configuration registers. a ddress r egister r ead /w rite c omments a3 a2 a1 a0 16550 c ompatible 0 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 0 dll - div latch low read/write lcr[7] = 1 0 0 0 1 dlm - div latch high read/write lcr[7] = 1 0 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only 0 0 1 1 lcr - line control register read/write 0 1 0 0 mcr - modem control register read/write 0 1 0 1 lsr - line status register reserved read-only write-only 0 1 1 0 msr - modem status register - auto rs485 delay read-only write-only 0 1 1 1 spr - scratch pad reg read/write e nhanced r egister 1 0 0 0 fctr read/write 1 0 0 1 efr - enhanced function register read/write 1 0 1 0 txcnt - transmit fifo level counter txtrg - transmit fifo trigger level read-only write-only 1 0 1 1 rxcnt - receive fifo level counter rxtrg - receive fifo trigger level read-only write-only 1 1 0 0 xoff-1 - xoff character 1 xchar write-only read-only xon,xoff rcvd. flags 1 1 0 1 xoff-2 - xoff character 2 reserved write-only read-only 1 1 1 0 xon-1 - xon character 1 reserved write-only read-only 1 1 1 1 xon-2 - xon character 2 reserved write-only read-only
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 28 t able 11: uart channel configuration registers description. s haded bits are enabled by efr b it -4. a ddress a3-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 0 0 0 0 rhr r bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 0 thr w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 0 dll r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 0 0 0 1 dlm r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 0 0 0 1 ier r/w 0/ 0/ 0/ 0 modem status int. enable rx line status int. enable tx empty int. enable rx data int. enable cts/ dsr# int. enable rts/ dtr# int. enable xon/xoff/ sp. char. int. enable 0 0 1 0 isr r fifos enable fifos enable 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 delta- flow cntl xoff/spe- cial char 0 0 1 0 fcr w rx fifo trigger r x f i f o trigger 0/ 0/ dma mode tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 0 1 1 lcr r/w divisor enable set tx break set parity even par- ity parity enable stop bits word length bit-1 word length bit-0 0 1 0 0 mcr r/w 0/ 0/ 0/ internal lopback enable (op2) 1 (op1) 1 rts# pin control dtr# pin control brg prescaler ir enable xonany rts/dtr flow sel 0 1 0 1 lsr r/w rx fifo e rror tsr empty thr empty rx break rx fram- ing error rx parity error rx over- run rx data ready 0 1 1 0 msr r cd ri dsr cts delta cd# delta ri# delta dsr# delta cts# msr w rs485 dly-3 rs485 dly-2 rs485 dly-1 rs485 dly- 0 reserved reserved reserved reserved 0 1 1 1 spr r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 user data 1 0 0 0 fctr r/w trg ta b l e bit-1 trg ta b l e bit-0 auto rs485 enable invert ir rx input rts/dtr hyst bit-3 rts/dtr hyst bit-2 rts/dtr hyst bit-1 rts/dtr hyst bit-0 1 0 0 1 efr r/w auto cts/ dsr enable auto rts/ dtr enable special char select enable ier [7:5], isr [5:4], fcr[5:4], mcr[7:5,2] msr[7:4] software flow cntl bit-3 software flow cntl bit-2 software flow cntl bit-1 software flow cntl bit-0 1 0 1 0 txcnt r bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 0 txtrg w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 1 rxcnt r bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 1 rxtrg w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 29 n ote : mcr bits 2 and 3 (op1 and op2 outputs) are not available in the xr17l154. they are present for 16c550 compatibility during internal loopback, see figure 11 . 4.6 transmitter the transmitter section comprises of a 64 bytes of fifo, a byte-wide transmit holding register (thr) and an 8-bit transmit shift register (tsr). thr receives a data byte from the host (non-fifo mode) or a data byte from the fifo when the fifo is enabled by fcr bit-0. tsr shifts out every data bit with the 16x or 8x internal clock. a bit time is 16 or 8 clock periods. the transmitter sends the start bit followed by the number of data bits, inserts the proper parity bit if enable, and adds the stop bit(s). the status of the thr and tsr are reported in the line status register (lsr bit-5 and bit-6). 4.6.1 transmit holding register (thr) the transmit holding register is an 8-bit register providing a data interface to the host processor. the host writes transmit data byte to the thr to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-significant-bit (bit-0) becomes first data bit to go out. the thr is also the input register to the transmit fifo of 64 bytes when fifo operation is enabled by fcr bit-0. a thr empty interrupt can be generated when it is enabled in ier bit-1. 4.6.2 transmitter operation in non-fifo the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes completely empty. 1 1 0 0 xchar r 0 0 0 0 0 0 xon det. indicator xoff det. indicator self-clear after read 1 1 0 0 xoff1 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 1 xoff2 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 0 xon1 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 1 xon2 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 f igure 12. t ransmitter o peration in non -fifo m ode t able 11: uart channel configuration registers description. s haded bits are enabled by efr b it -4. a ddress a3-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment transmit h olding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x clock (8xm ode register)
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 30 4.6.3 transmitter operation in fifo the host may fill the transmit fifo with up to 64 bytes of transmit data. the thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can generate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed trigger level (see txtrg register). the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes completely empty. furthermore, with the rs485 half-duplex direction control enabled (fctr bit-5=1) the source of the transmit empty interrupt changes to tsr empty instead of thr empty. this is to ensure the rts# output is not changed until the last stop bit of the last character is shifted out. 4.6.4 auto rs485 operation the auto rs485 half-duplex direction control changes the behavior of the transmitter when enabled by fctr bit-5. it de-asserts rts# or dtr# after a specified delay indicated in msr[7:4] following the last stop bit of the last character that has been transmitted. this helps in turning around the transceiver to receive the remote stations response. the delay optimizes the time needed for the last transmission to reach the farthest station on a long cable network before switching off the line driver. this delay prevents undesirable line signal disturbance that causes signal degradation. it also changes the transmitter empty interrupt to tsr empty instead of thr empty. 4.7 receiver the receiver section contains an 8-bit receive shift register (rsr) and receive holding register (rhr). the rsr uses the 16x or 8x clock for timing. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x or 8x clock rate. after 8 or 4 clocks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits 1- 4 and an lsr interrupt is generated immediately if ier bit-2 is enabled. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay until it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach the receive fifo trigger level. this time-out delay is 4 word lengths as defined by lcr[1:0] plus 12 bits time. the rhr interrupt is enabled by ier bit-0. f igure 13. t ransmiitter o peration in fifo and f low c ontrol m ode transm it data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below programmed trigger level (txtrg) and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo (64-byte) txfifo1 16x or 8x clock (8xmode register) auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg.
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 31 4.7.1 receiver operation in non-fifo mode 4.7.2 receiver operation with fifo 4.8 registers receive holding register (rhr) the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register (rsr). it provides the receive data interface to the host processor. the host reads the receive data byte on this register whenever a data byte is transferred from the rsr. rhr also part of the receive fifo of 64 bytes by 11-bit wide, 4 extra bits are for the error tags to be in lsr register. when the fifo is enabled by fcr bit-0, it acts as the first-out register of the fifo as new data are put over the first-in register. the receive fifo pointer is bumped after the rhr register is read. also, the error tags associated with the data byte are immediately updated onto the line status register (lsr) bits 1-4. f igure 14. r eceiver o peration in non -fifo m ode f igure 15. r eceiver o peration in fifo and f low c ontrol m ode receive data shift register (rsr) receive d a ta b yte and e rrors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo 16x or 8x clock (8xm ode register) receive data characters d a ta b it validation e rror flags in lsr bits 4:1 receive data shift register (rsr) rxfifo1 16x or 8x sampling clock (8xmode reg.) error flags (64-sets) error tags in lsr bits 4:1 64 bytes by 11- bit wide fifo receive data characters fifo trigger=48 example: - fifo trigger level set at 48 bytes - rts/dtr hyasteresis set at +/-8 chars. data fills to 56 data falls to 40 data bit validation receive data fifo (64-byte) receive data receive data byte and errors rhr interrupt (isr bit-2) is programmed at fifo trigger level (rxtrg). fifo is enable by fcr bit-0=1 rts#/dtr# de-asserts when data fills above the trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-2. rts#/dtr# re-asserts when data falls below the trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-2.
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 32 baud rate generator divisors (dll and dlm) the baud rate generator (brg) is a 16-bit counter that generates the data rate for the transmitter and receiver. the rate is programmed through registers dll and dlm which are only accessible when lcr bit-7 is set to logic 1. see programmable baud rate generator section for more detail. interrupt enable register (ier) the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are reported in the interrupt status register (isr) register and also encoded in int (int0-int3) register in the device configuration registers. ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = logic 1) and receive interrupts (ier bit-0 = logic 1) are enabled, the rhr interrupts (see isr bits 3 and 4) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; resetting ier bits 0-3 enables the l154 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit 1-4 provides the type of receive data errors encountered for the data byte in rhr, if any. c. lsr bit-5 indicates thr is empty. d. lsr bit-6 indicates when both the transmit fifo and tsr are empty. e. lsr bit-7 indicates the ored function of errors in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. logic 0 = disable the receive data ready interrupt (default). logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this interrupt is associated with bit-5 in the lsr register. an interrupt is issued whenever the thr becomes empty (non-fifo mode) or when data in the fifo falls below the programmed trigger level in the 64-byte fifo mode. logic 0 = disable transmit holding register empty interrupt (default). logic 1 = enable transmit holding register empty interrupt. ier[2]: receive line status interrupt enable any of the lsr register bits 1,2,3 or 4 becomes active will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. logic 0 = disable the receiver line status interrupt (default). logic 1 = enable the receiver line status interrupt.
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 33 ier[3]: modem status interrupt enable logic 0 = disable the modem status register interrupt (default). logic 1 = enable the modem status register interrupt. ier[4]: reserved . ier[5]: xoff interrupt enable (requires efr bit-4=1) logic 0 = disable the software flow control, receive xoff interrupt. (default) logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details. ier[6]: rts# output interrupt enable (requires efr bit-4=1) logic 0 = disable the rts# interrupt. (default). logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# output pin makes a transition. ier[7]: cts# input interrupt enable (requires efr bit-4=1) logic 0 = disable the cts# interrupt. (default). logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# input pin makes a transition. interrupt status register (isr) the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current highest pending interrupt level to be serviced, others queue up for next service. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, ta b l e 1 2 , shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. interrupt generation: lsr is by any of the lsr bits 1, 2, 3 and 4. rxrdy is by rx trigger level. rxrdy time-out is by the a 4-char plus 12 bits delay timer if data doesnt reach fifo trigger level. txrdy is by lsr bit-5 in the non-fifo mode, tx trigger level setting in the fifo mode (or bit-6 in auto rs485 control). msr is by any of the msr bits, 0, 1, 2 and 3. receive xon / xoff/special character is by detection of a xon, xoff or special character. cts#/dsr# is by a change of state on the input pin with auto flow control enabled, efr bit-7, and depending on selection on mcr bit-2. rts#/dtr# is when its receiver changes the state of the output pin during auto rts/dtr flow control enabled by efr bit-6 and selection of mcr bit-2. interrupt clearing: lsr interrupt is cleared by a read to the lsr register. rxrdy interrupt is cleared by reading data until fifo falls below the trigger level. rxrdy time-out interrupt is cleared by emptying the rx fifo. txrdy interrupt is cleared by a read to the isr register. msr interrupt is cleared by a read to the msr register. xon, xoff or special character interrupt is cleared by a read to isr register.
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 34 rts#/dtr# output status change interrupt is cleared by a read to the isr register. cts#/dsr# input status change interrupt is cleared by a read to the msr register. ] isr[0]: interrupt status logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (see interrupt source ta b l e 1 2 ). isr[5:4]: interrupt status these bits are enabled when efr bit-4 is set to a logic 1. isr bit-4 indicates that the receiver detected a data match of the xon or xoff character(s). note that once set to a logic 1, the isr bit-4 will stay a logic 1 until a xon character is received. isr bit-5 indicates that cts#/dsr# or rts#/dtr# has changed state. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disabled. they are set to a logic 1 when the fifos are enabled. fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable logic 0 = disable the transmit and receive fifo (default). logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is active. logic 0 = no receive fifo reset (default). logic 1 = reset the receive fifo pointers and fifo level counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. t able 12: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of the interrupt + l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 0 1 0 0 rxrdy (received data ready) 3 0 0 1 1 0 0 rxrdy (receive data time-out) 4 0 0 0 0 1 0 txrdy (transmitter holding register empty) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xon/xoff or special character) 7 1 0 0 0 0 0 cts#/dsr#, rts#/dtr# change of state x 0 0 0 0 0 1 none (default)
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 35 fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is active. logic 0 = no transmit fifo reset (default). logic 1 = reset the transmit fifo pointers and fifo level counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select this bit has no effect since txrdy and rxrdy pins are not available in this device. it is provided for legacy software. logic 0 = set dma to mode 0. (default) logic 1 = set dma to mode 1. fcr[5:4]: transmit fifo trigger select (logic 0 = default, tx trigger level = one) the fctr bits 6-7 are associated with these 2 bits by selecting one of the four tables. the 4 user selectable trigger levels in 4 tables are supported for compatibility reasons. these 2 bits set the trigger level for the transmit fifo interrupt. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. ta b l e 1 3 below shows the selections. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) the fctr bits 6-7 are associated with these 2 bits. these 2 bits are used to set the trigger level for the receiver fifo interrupt. ta b l e 1 3 shows the complete selections.
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 36 line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. t able 13: t ransmit and r eceive fifo t rigger l evel s election fctr b it -7 fctr b it -6 fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel c ompatibility 00 0 0 1 1 0 1 0 1 00 1 (default) 4 8 14 1 (default) table-a. 16c550, 16c2550, 16c2552, 16c554, 16c580 compatible. 01 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 28 16 8 24 30 table-b. 16c650a compatible. 10 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 table-c. 16c654 compatible. 1 1xxxxprogrammable via rxtrg register programmable via txtrg reg- ister table-d. 16c850, 16c2850, 16c2852, 16c854, 16c864, 16c872 compatible. bit-1 bit-0 w ord length 0 0 5 (default) 01 6 10 7 11 8
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 37 lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bit in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the parity bit is a simple way used in communications for data integrity check. see ta b l e 1 4 for parity selection summary below. logic 0 = no parity. logic 1 = a parity bit is generated during the transmission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted character. the receiver must be programmed to check the same format (default). logic 1 = even parity is generated by forcing an even the number of logic 1s in the transmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit-5 selects the forced parity format. lcr bit-5 = logic 0, parity is not forced (default). lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable when enabled the break control bit it causes a break condition to be transmitted (the tx output is forced to a space, logic 0, state). this condition remains until disabled by setting lcr bit-6 to a logic 0. logic 0 = no tx break condition. (default) logic 1 = forces the transmitter output (tx) to a space, logic 0, for alerting the remote receiver of a line break condition. bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 15 1-1/2 1 6,7,8 2 t able 14: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 011 even parity 1 0 1 force parity to mark, 1 1 1 1 forced parity to space, 0
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 38 lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. logic 0 = data registers are selected. (default) logic 1 = divisor latch registers are selected. modem control register (mcr) the mcr register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. mcr[0]: dtr# pins the dtr# pin may be used for automatic hardware flow control enabled by efr bit-6 and mcr bit-2=1. if the modem interface is not used, this output may be used for general purpose. logic 0 = force dtr# output to a logic 1 (default). logic 1 = force dtr# output to a logic 0. mcr[1]: rts# pins the rts# pin may be used for automatic hardware flow control by enabled by efr bit-6 and mcr bit-2=0. if the modem interface is not used, this output may be used for general purpose. logic 0 = force rts# output to a logic 1 (default). logic 1 = force rts# output to a logic 0. mcr[2]: dtr# or rts# for auto flow control the op1 output is not available in the xr17l152. it is present for 16c550 compatibility during internal loopback. see figure 11 . logic zero is default. dtr# or rts# auto hardware flow control select. this bit is in effect only when auto rts/dtr is enabled by efr bit-6. logic 0 = uses rts#/cts# pins for auto hardware flow control. logic 1 = uses dtr#/dsr# pin is used for auto hardware flow control. mcr[3]: (op2) the op2 output is not available in the xr17l154. it is present for 16c550 compatibility during internal loopback. see figure 11 . logic zero is default. mcr[4]: internal loopback enable logic 0 = disable loopback mode (default). logic 1 = enable local loopback mode, see loopback section and figure 11 . mcr[5]: xon-any enable logic 0 = disable xon-any function (for 16c550 compatibility) (default). logic 1 = enable xon-any function. in this mode any rx character received will enable xon, resume data transmission. mcr[6]: infrared encoder/decoder enable this bit overrides the enir pin selection. logic 0 = disable the infrared mode (default). logic 1 = enable infrared irda receive and transmit inputs/outputs. while in this mode, the tx/rx output/ input are routed to the infrared encoder/decoder. the data input and output levels will conform to the irda infrared interface requirement. as such, while in this mode the infrared tx output will be a logic 0 during idle data conditions. fctr bit-4 may be selected to invert the rx input signal level going to the decoder for infrared modules that provide rather an inverted output.
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 39 mcr[7]: clock prescaler select logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. line status register (lsr) this register provides the status of data transfers between the uart and the host. if ier bit-2 is enabled, an lsr interrupt is generated when a received data error occurs due to overrrun, parity or framing. if lsr[0] = logic 0, then lsr bits 1-4 are invalid. lsr[0]: receive data ready indicator logic 0 = no data in receive holding register or fifo (default). logic 1 = data has been received and is saved in the receive holding register or fifo. lsr[1]: receiver overrun error tag logic 0 = no overrun error (default). logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fifo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. automatic hardware (rts/cts) or software (xon/xoff) flow control should be considered if this condition persists. lsr[2]: receive data parity error tag logic 0 = no parity error (default). logic 1 = parity error. the receive character in rhr does not have correct parity information and is suspect. this error is associated with the character available for reading in rhr. lsr[3]: receive data framing error tag logic 0 = no framing error (default). logic 1 = framing error tag. the receive character did not have a valid stop bit(s). this error tag is associated with the character available for reading in rhr. lsr[4]: receive break tag logic 0 = no break condition (default). logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, mark or logic 1. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. this bit indicates that the transmitter is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the host when the thr interrupt enable is set. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. in the fifo mode this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. lsr[6]: transmit shift register empty flag this bit is the transmit shift register empty indicator. this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty.
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 40 lsr[7]: receive fifo data error flag logic 0 = no fifo error (default). logic 1 = an indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in the fifo. modem status register (msr) - read only this register provides the current state of the modem interface signals, or other peripheral device that the uart is connected. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used as general purpose inputs/outputs when they are not used with modem signals. msr[0]: delta cts# input flag logic 0 = no change on cts# input (default). logic 1 = the cts# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[1]: delta dsr# input flag logic 0 = no change on dsr# input (default). logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[2]: delta ri# input flag logic 0 = no change on ri# input (default). logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringing signal. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[3]: delta cd# input flag logic 0 = no change on cd# input (default). logic 1 = indicates that the cd# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7) and rts/cts flow control select (mcr bit-2). auto cts flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a logic 1 on the cts# pin will stop uart transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. normally msr bit-4 bit is the compliment of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# (active high, logical 1). this input may be used for auto dtr/dsr flow control function, see auto \hardware flow control section. normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status ri# (active high, logical 1). normally this bit is the compliment of the ri# input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used.
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 41 msr[7]: cd input status cd# (active high, logical 1). normally this bit is the compliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. modem status register (msr) - write only the upper four bits 4-7 of this register sets the delay in number of bits time for the auto rs485 turn around from transmit to receive. msr [7:4]: programmable rs485 turn-around delay when auto rs485 feature is enabled (fctr bit-5=1) and rts# output is connected to the enable input of a rs-485 transceiver. these 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last transmitted character. this delay controls when to change the state of rts# output. this delay is very useful in long-cable networks. ta b l e 1 5 shows the selection. the bits are enabled by efr bit-4. scratch pad register (spr) this is an 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. feature control register (fctr) this register controls the uart enhanced functions that are not available on st16c554 or st16c654. t able 15: a uto rs485 h alf - duplex d irection c ontrol d elay from t ransmit - to -r eceive msr[7] msr[6] msr[5] msr[4] d elay in d ata b it ( s ) t ime 0000 0 0001 1 0010 2 0011 3 0100 4 9101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 42 fctr [3:0] - auto rts/dtr flow control hysteresis select these bits select the auto rts/dtr flow control hysteresis and only valid when tx and rx trigger table-d is selected (fctr bit-6 and 7 are set to logic 1). the rts/dtr hysteresis is referenced to the rx fifo trigger level. after reset, these bits are set to logic 0 selecting the next fifo trigger level for hardware flow control. ta b l e 1 6 below shows the 16 selectable hysteresis levels. fctr[4]: infrared rx input logic select logic 0 = select rx input as active high encoded irda data, normal, (default). logic 1 = select rx input as active low encoded irda data, inverted. fctr[5]: auto rs485 enable auto rs485 half duplex control enable/disable. logic 0 = standard st16c550 mode. transmitter generates an interrupt when transmit holding register (thr) becomes empty. transmit shift register (tsr) may still be shifting data bit out. logic 1 = enable auto rs485 half duplex direction control. rts# output changes its logic level from 1 to 0 when finished sending the last stop bit of the last character out of the tsr register. it changes back to logic level 1 from 0 when a data byte is loaded into the thr or transmit fifo. the change to logic 1 occurs prior sending the start-bit. it also changes the transmitter interrupt from transmit holding to transmit shift register (tsr) empty. t able 16: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected fctr b it -3 fctr b it -2 fctr b it -1 fctr b it -0 rts/dtr h ysteresis ( characters ) 0000 0 0001 +/- 4 0010 +/- 6 0011 +/- 8 0100 +/- 8 0101 +/- 16 0110 +/- 24 0111 +/- 32 1100 +/- 12 1101 +/- 20 1110 +/- 28 1111 +/- 36 1000 +/- 40 1001 +/- 44 1010 +/- 48 1011 +/- 52
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 43 fctr[7:6]: tx and rx fifo trigger table select these 2 bits select the transmit and receive fifo trigger level table a, b, c or d. when table a, b, or c is selected the auto rts flow control trigger level is set to "next fifo trigger level" for compatibility to st16c550 and st16c650 series. rts/dtr# triggers on the next level of the rx fifo trigger level, in another word, one fifo level above and one fifo level below. see ta b l e 1 3 for complete selection with fcr bit 4-5 and fctr bit 6-7, i.e. if table c is used on the receiver with rx fifo trigger level set to 56 bytes, rts/dtr# output will de-asserts at 60 and re-asserts at 16. enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide single or dual consecutive character software flow control selection (see ta b l e 1 7 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select combinations of software flow control can be selected by programming these bits (see ta b l e 1 7 ). t able 17: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1/xoff1 0 1 x x transmit xon2/xoff2 1 1 x x transmit xon1 and xon2/xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1/xoff1 x x 0 1 receiver compares xon2/xoff2 1 0 1 1 transmit xon1/ xoff1, receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2/xoff2, receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2/xoff1 and xoff2, receiver compares xon1 and xon2/xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2/xoff1 and xoff2
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 44 efr[4]: enhanced function bits enable enhanced function control bit. this bit enables the functions in ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. logic 0 = modification disable/latch enhanced features. ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are set to a logic 0 to be compatible with st16c554 mode (default). logic 1 = enables the enhanced functions. when this bit is set to a logic 1 all enhanced features are enabled. efr[5]: special character detect enable logic 0 = special character detect disabled. (default) logic 1 = special character detect enabled. the uart compares each incoming receive character with data in xoff-2 register. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 corresponds with the lsb bit for the receive character. if flow control is set for comparing xon1, xoff1 (efr [1:0]=10) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]=01) then flow control works normally, but xoff2 will not go to the fifo, and will generate an xoff interrupt and a special character interrupt. efr[6]: auto rts or dtr flow control enable rts#/dtr# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts/dtr is selected, an interrupt will be generated when the receive fifo is filled to the programmed trigger level and rts/dtr# will de-assert to a logic 1 at the next upper trigger or selected hysteresis level. rts/dtr# will return to a logic 0 when fifo data falls below the next lower trigger or selected hysteresis level (see fctr bits 4-7). the rts# or dtr# output must be asserted (logic 0) before the auto rts/dtr can take effect. the selection for rts# or dtr# is through mcr bit-2. rts/dtr# pin will function as a general purpose output when hardware flow control is disabled. logic 0 = automatic rts/dtr flow control is disabled. (default) logic 1 = enable automatic rts/dtr flow control. efr[7]: auto cts flow control enable automatic cts or dsr flow control. logic 0 = automatic cts/dsr flow control is disabled. (default) logic 1 = enable automatic cts/dsr flow control. transmission stops when cts/dsr# pin de-asserts to logic 1. transmission resumes when cts/dsr# pin returns to a logic 0. the selection for cts# or dsr# is through mcr bit-2.
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 45 txcnt[7:0]: transmit fifo level counter, read-only transmit fifo level byte count from 0x00 (zero) to 0x40 (64). this 8-bit register gives an indication of the number of characters in the transmit fifo. the fifo level byte count register is read only. the user can take advantage of the fifo level byte counter for faster data loading to the transmit fifo, which reduces cpu bandwidth requirements. txtrg [7:0]: transmit fifo trigger level, write only an 8-bit value written to this register sets the tx fifo trigger level from 0x00 (zero) to 0x40 (64). the tx fifo trigger level generates an interrupt whenever the data level in the transmit fifo falls below this preset trigger level. rxcnt[7:0]: receive fifo level counter, read-only receive fifo level byte count from 0x00 (zero) to 0x40 (64). it gives an indication of the number of characters in the receive fifo. the fifo level byte count register is read only. the user can take advantage of the fifo level byte counter for faster data unloading from the receiver fifo, which reduces cpu bandwidth requirements. rxtrg[7:0]: receive fifo trigger level, write-only an 8-bit value written to this register, sets the rx fifo trigger level from 0x00 (zero) to 0x40 (64). the rx fifo trigger level generates an interrupt whenever the receive fifo level rises to this preset trigger level.
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 46 t able 18: uart[3:0] reset conditions registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs spr bits 7-0 = 0xff fctr bits 7-0 = 0x00 efr bits 7-0 = 0x00 txcnt bits 7-0 = 0x00 txtrg bits 7-0 = 0x00 rxcnt bits 7-0 = 0x00 rxtrg bits 7-0 = 0x00 xchar bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 i/o signals reset state tx[ch-3:0] logic 1 irtx[ch-3:0] logic 0 rts#[ch-3:0] logic 1 dtr#[ch-3:0] logic 1 eeck logic 0 eecs logic 0 eedi logic 0
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 47 electrical characteristics absolute maximum ratings power supply range 4 volts voltage at any pin -0.5 to 4v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw thermal resistance (20x20x1.0mm 144-tqfp) theta-ja = 42, theta-jc = 8 o c/w dc electrical characteristics for 3.3v signalling ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package), vcc = 3.3v +/-10% unless otherwise specified. s ymbol p arameter m in m ax u nits c ondition n otes v il input low voltage -0.5 0.3vcc v v ih input high voltage 0.5vcc vcc + 0.5 v for pci bus and exter- nal clock (xtal1) inputs for other inputs, v ih max = 6.0 v v ol output low voltage 0.4 v i ol = 4ma v oh output high voltage 0.9vcc v i oh = -0.5ma i il input low leakage cur- rent -10 m a i ih input high leakage cur- rent 10 m a i cl input clock leakage +/-10 m a c in input pin capacitance 10 pf c clk clk pin capacitance 12 pf c idsel idsel pin capacitance 8 pf i cc power supply current 2 ma pci clk and ext. clock=2mhz, all inputs are at vcc or gnd and all outputs are unloaded i sleep sleep current 20 m a all four uarts asleep. ad[31:0] at gnd, all inputs at vcc or gnd
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 48 ac electrical characteristics for 3.3v signaling ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package), vcc = 3.3v +/-10% unless otherwise specified. s ymbol p arameter m in m ax u nits n otes clk pci bus clock 33 mhz xtal1 xtal2 crystal oscillator 24 mhz on-chip osc. eclk external clock 33 mhz ext. clock on xtal1 i oh(ac) switching current high -12vcc ma 0 < vout 0.3vcc i ol(ac) switching current low 16vcc ma vcc > vout 3 0.6vcc i ch clamping current high 25+(vin-vcc-1)/0.015 ma vcc+4 > vin 3 vcc+1 i cl clamping current low -25+(vin+1)/0.015 ma -3 < vin -1 slew r output rise slew rate 1 4 v/ns 0.2vcc - 0.6vcc load slew f output fall slew rate 1 4 v/ns 0.6vcc - 0.2vcc load t cyc clk cycle time 30 ns t hi clk high time 11 ns t lo clk low time 11 ns clk slew rate 1 4 v/ns t va l clk to signal valid delay 2 11 ns t on float to active delay 2 ns t off active to float delay 28 ns t setup input setup time to clk - bused signals 7ns t hold input hold time from clk 0 ns t prst rst# active time after power stable 1ms t crst# rst# active time after clk stable 100 us rst# slew rate 50 mv/ns
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 49 f igure 16. pci b us c onfiguration s pace r egisters r ead and w rite operation clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 123 4 cfg-rd byte enable# pcicfg_rd host host host host host target target target data transfer address data clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 123 4 cfg-wr byte enable# pcicfg_wr host host host host host target target target data transfer address write data
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 50 f igure 17. d evice c onfiguration and uart r egisters r ead o peration for a b yte or dword clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 1 23 4 address bus cmd byte enable# = byte byte transfer pci_rd1 5 6 7 par perr# 8 note: perr# and serr are optional in a bus target application. even parity is on ad[31:0], c/be[3:0]#, and par data parity active host host host host host target host target target target data byte wait wait wait address parity serr# target targe t active data word byte enable# = dword dword transfer wait wait data parity active 91011
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 51 f igure 18. d evice c onfiguration registers , uart r egisters and t ransmit d ata b urst w rite o pera - tion clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 1 23 4 address bus cmd byte enable# = dword pci _ bwr 5 6 7 par perr# 8 note: perr# and serr are optional in a bus target application. even parity is on ad[31:0], c/be[3:0]#, and par host host host host host target host target target target address parity serr# target target active data parity active 910 data dword data dword dword transfer dword transfer dword transfer dword transfer dword transfer data parity data parity data parity data parity active active active active 11 data dword data dword data dword
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 52 f igure 19. d evice c onfiguration r egisters , uart r egisters and r eceive d ata b urst r ead o peration data clk frame# ad[31:0] c/be[3:0]# trdy# irdy# devsel# 1 13 ad bus cmd byte enable# = dw ord pci_brd par perr# 18 note: perr# and serr are optional in a bus target application. even parity is on ad[31:0], c/be[3:0]#, and par host host host host host target host target target target serr# target target dword transfer dword transfer dword transfer dword transfer 23 8 ad data data data data active active active active active data data data
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 53 f igure 20. pci b us c lock (dc to 33mh z ) 0.4vcc p-to-p (minimum) 0.6 vcc 0.2 vcc clk bused signal output delay tri-state output tvalid (2-11 ns) ton (2 ns min) toff (28 ns max) 11 ns (min) 1.44 ns (max) 1.44 ns (max) 11 ns (min) tsetup (7 ns min) thold (0 ns) bused signal input pci_clk inputs valid
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 54 f igure 21. t ransmit d ata i nterrupt at t rigger l evel f igure 22. r eceive d ata r eady i nterrupt at t rigger l evel stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx data next data start bit tx interrupt at transmit trigger level baud rate clock of 16x or 8x txnofifo-1 set at below trigger level clear at above trigger level stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx data input first byte that reaches the trigger level rx data ready interrupt at receive trigger level rxfifo1 de-asserted at below trigger level asserted at above trigger level
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 55 package dimensions
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 56 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2002 exar corporation datasheet october 2002. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history d ate r evision d escription august 2002 adv. rev. 1.0.0 advanced datasheet october 2002 rev. 1.0.0 release into production. updated dc and ac electrical characteristics.
xr17l154 ? ? ? ? 3.3v pci bus quad uart rev. 1.0.0 i table of contents general description .................................................................................................1 a pplications ............................................................................................................................... .................1 f eatures ............................................................................................................................... ......................1 f igure 1. b lock d iagram ............................................................................................................................... .............................. 1 f igure 2. p in o ut of the d evice ............................................................................................................................... ................... 2 ordering information ............................................................................................................................... ..2 pin descriptions ..........................................................................................................3 pci local bus interface........................................................................................................ .............3 modem or serial i/o interface .................................................................................................. ......3 ancillary signals.............................................................................................................. ...................4 functional description ...........................................................................................6 pci local bus interface ........................................................................................................ ....................................... 6 pci local bus configuration space registers ............................................................................................................ 6 eeprom interface ............................................................................................................... ....................................... 6 1.0 xr17l154 registers ...................................................................................................... ...................7 1.1 pci local bus configuration space registers ............................................................................ 7 f igure 3. t he xr17l154 r egister s ets ............................................................................................................................... ...... 7 t able 1: pci l ocal b us c onfiguration s pace r egisters ......................................................................................................... 8 1.2 device configuration register set ....................................................................................... ............ 9 t able 2: xr17l154 d evice c onfiguration r egisters ............................................................................................................. 10 t able 3: d evice c onfiguration r egisters shown in byte alignment ................................................................................... 11 1.2.1 the interrupt status register .......................................................................................... ........................... 12 t able 4: d evice c onfiguration r egisters shown in dword alignment ............................................................................... 12 f igure 4. t he g lobal i nterrupt r egister , int0, int1, int2 and int3 .................................................................................. 13 t able 5: uart c hannel [3:0] i nterrupt s ource e ncoding ..................................................................................................... 13 1.2.2 general purpose 16-bit timer/counter [timermsb, timelsb, timer, timecntl] (default 0xxx-xx- 00-00)......................................................................................................................... ..................................................... 14 t able 6: uart c hannel [3:0] i nterrupt c learing : .................................................................................................................. 14 f igure 5. t imer /c ounter circuit ............................................................................................................................... ................ 14 t able 7: timer control r egisters ............................................................................................................................... ....... 14 1.2.3 8xmode [7:0] - (default 0x00) .......................................................................................... ................................... 15 1.2.4 rega [15:8] - (default 0x00) ........................................................................................... ..................................... 15 1.2.5 reset [23:16] - (default 0x00)......................................................................................... .................................... 15 1.2.6 sleep [31:24] - (default 0x00)........................................................................................ .................................... 16 1.2.7 device identification and revision ..................................................................................... .......................... 16 1.2.8 rgeb register .......................................................................................................... ............................................. 16 1.2.9 multi-purpose inputs and outputs ....................................................................................... ....................... 17 1.2.10 mpio register ......................................................................................................... ............................................. 17 f igure 6. m ultipurpose input / output internal circuit ........................................................................................................... 17 2.0 crystal oscillator / buffer ............................................................................................. ......19 3.0 transmit and receive data ............................................................................................... ........19 f igure 7. t ypical oscillator connections ............................................................................................................................... 19 3.1 fifo data loading and unloading through the device configuration registers in 32-bit format. ....................................................................................................................... ................................. 20 3.2 fifo data loading and unloading through the uart channel registers, thr and rhr in 8-bit format. ................................................................................................................. ............................. 21 4.0 uart .................................................................................................................... ................................21 t able 8: t ransmit and r eceive d ata r egister in b yte format , 16c550 compatible ............................................................ 21 4.1 programmable baud rate generator ........................................................................................ ... 22 f igure 8. b aud r ate g enerator ............................................................................................................................... ................ 22 4.2 automatic hardware (rts/cts or dtr/dsr) flow control operation .............................. 23 t able 9: t ypical data rates with a 14.7456 mh z crystal or external clock at 16x s ampling .......................................... 23 f igure 9. a uto rts/dtr and cts/dsr f low c ontrol o peration ........................................................................................ 24 4.3 infrared mode ........................................................................................................... ............................... 25 f igure 10. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 25 4.4 internal loopback ....................................................................................................... .......................... 26 4.5 uart channel configuration registers and address decoding. ...................................... 26 f igure 11. i nternal l oop b ack ............................................................................................................................... .................. 26
? ? ? ? xr17l154 3.3v pci bus quad uart rev. 1.0.0 ii t able 10: uart channel configuration registers. .................................................................................... .............. 27 t able 11: uart channel configuration registers description. s haded bits are enabled by efr b it -4. ....... 28 4.6 transmitter ............................................................................................................. .................................. 29 4.6.1 transmit holding register (thr)........................................................................................ ........................... 29 4.6.2 transmitter operation in non-fifo...................................................................................... ........................ 29 f igure 12. t ransmitter o peration in non -fifo m ode ............................................................................................................ 29 4.6.3 transmitter operation in fifo .......................................................................................... ............................. 30 4.6.4 auto rs485 operation ................................................................................................... ..................................... 30 4.7 receiver ................................................................................................................ ...................................... 30 f igure 13. t ransmiitter o peration in fifo and f low c ontrol m ode ................................................................................... 30 4.7.1 receiver operation in non-fifo mode ................................................................................... ..................... 31 4.7.2 receiver operation with fifo........................................................................................... .............................. 31 4.8 registers ............................................................................................................... ..................................... 31 f igure 14. r eceiver o peration in non -fifo m ode .................................................................................................................. 31 f igure 15. r eceiver o peration in fifo and f low c ontrol m ode ......................................................................................... 31 t able 12: i nterrupt s ource and p riority l evel ..................................................................................................................... 34 t able 13: t ransmit and r eceive fifo t rigger l evel s election ............................................................................................ 36 t able 14: p arity selection ............................................................................................................................... ......................... 37 t able 15: a uto rs485 h alf - duplex d irection c ontrol d elay from t ransmit - to -r eceive ................................................. 41 t able 16: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected ................................................................ 42 t able 17: s oftware f low c ontrol f unctions ........................................................................................................................ 43 t able 18: uart[3:0] reset conditions............................................................................................... ................................ 46 electrical characteristics................................................................................ 47 absolute maximum ratings .................................................................................. 47 dc electrical characteristics for 3.3v signalling .................................................................. 47 ta=0o to 70oc (-40o to +85oc for industrial grade package), vcc = 3.3v +/-10% unless otherwise specified........ 47 ac electrical characteristics for 3.3v signaling ............................................................... 48 ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc = 3.3v +/-10% unless otherwise spec - ified . .............................................................................................................................. ............................ 48 f igure 16. pci b us c onfiguration s pace r egisters r ead and w rite operation ................................................................. 49 f igure 17. d evice c onfiguration and uart r egisters r ead o peration for a b yte or dword ...................................... 50 f igure 18. d evice c onfiguration registers , uart r egisters and t ransmit d ata b urst w rite o peration ..................... 51 f igure 19. d evice c onfiguration r egisters , uart r egisters and r eceive d ata b urst r ead o peration ........................ 52 f igure 20. pci b us c lock (dc to 33mh z ).............................................................................................................................. .. 53 f igure 21. t ransmit d ata i nterrupt at t rigger l evel ........................................................................................................... 54 f igure 22. r eceive d ata r eady i nterrupt at t rigger l evel ................................................................................................. 54 package dimensions ................................................................................................ 55 r evision h istory .............................................................................................................................. ....... 56 t able of c ontents ............................................................................................................ i

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