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d a t a sh eet product speci?cation supersedes data of 1997 sep 01 file under integrated circuits, ic01 2002 jan 14 integrated circuits saa6588 rds/rbds pre-processor
2002 jan 14 2 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 features integrated switched capacitor filters demodulation of the european radio data system (rds) or the usa radio broadcast data system (rbds) signal rds and rbds block detection error detection and correction fast block synchronization synchronization control (flywheel) mode control for rds/rbds processing different rds/rbds block information output modes (e.g. a-block output mode) fast i 2 c-bus interface multi-path detector signal quality detector with sensitivity adjustment pause detector with pause level and time adjustment alternatively oscillator frequency: n 4.332 mhz (n = 1 to 4) uart compatible with 17.328 mhz (n = 4) cmos device single supply voltage extended temperature range ( - 40 to +85 c). general description today most fm radio stations in europe and meanwhile also many fm/am radio broadcasting stations in the usa transmit the inaudible european rds (radio data system) or the usa rbds (radio broadcast data system) informations respectively. likewise nowadays receivers, most car radios and also some home and portable radios on the market include at least some of the rds features. the rds/rbds system offers a large range of applications by its many functions to be implemented. for car radios the most important are: program service (ps) name traffic program (tp) identification traffic announcement (ta) signal alternative frequency (af) list program identification (pi) enhanced other networks (eon) information. the rds/rbds pre-processor is a cmos device that integrates all rds/rbds relevant functions in one chip. the ic contains filtering and demodulation of the rds/rbds signal, symbol decoding, block synchronization, error detection, error correction and additional detectors for multi-path, signal quality and audio signal pauses. the pre-processed rds/rbds information is available via the i 2 c-bus. the rds/rbds pre-processor replaces a number of ics and peripheral components used nowadays in car radio concepts with rds or rbds features. the integration of the relevant rds/rbds data processing functions provides, in an economic manner, high performance of rds/rbds processing and reduces the real-time requirements for the main radio microcontroller considerably. in addition it simplifies the development of the rds specific software for the main controller of the radio set. compared with standard radio systems, rds/rbds controlled radio systems additionally require an rds/rbds demodulator with a 57 khz band-pass filter, information about the current reception situation (reception quality, multi-path disturbance etc.), and additional microcontroller power for rds/rbds data processing, decoding and radio control. the new rds/rbds pre-processor includes all these specific functions and meets all requirements of a high end rds/rbds radio. moreover the timing requirements of the set controller, regarding rds/rbds data processing are reduced due to the integration of decoder functions, so that the development of radio control software can be concentrated specifically on radio set features.
2002 jan 14 3 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 quick reference data ordering information symbol parameter conditions min. typ. max. unit v dda analog supply voltage 4.5 5.0 5.5 v v ddd digital supply voltage 4.5 5.0 5.5 v i dd(tot) total supply current - 14.0 - ma v i(mpx) rds input sensitivity at pin mpx 1 -- mv d g sq step size for signal quality input gain - 0.6 - db cr gsq control range for signal quality input gain - 18.6 - db t pon(min) minimum time for pause adjustable in 4 steps 20.2 - 161.7 ms f i(xtal) crystal input frequency n = 1 - 4.332 - mhz n=2 - 8.664 - mhz n=3 - 12.996 - mhz n=4 - 17.328 - mhz type number package name description version saa6588 dip20 plastic dual in-line package; 20 leads (300 mil) sot146-1 saa6588t so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1
2002 jan 14 4 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... block diagram handbook, full pagewidth mgk535 10 k w 10 k w 470 k w 57 khz 8th order band-pass pause detector multi-path detector clocked comparator signal quality detector rds/rdbs demodulator interface register power supply and reset test control c10 c9 100 nf davn data available pause output multi-path output 8 7 19 18 11 2 9 10 scout cin v ddd 560 pf oscillator and clock i 2 c-bus slave transceiver i 2 c-bus rds/rdbs decoder multiplex input audio inputs level input 4 4 saa6588 tcon mro 100 nf c6 100 nf c8 c11 c2 c3 20 14 13 16 r3 r2 2.2 nf 330 pf lvin v dda afin mpx c7 2.2 m f 0.47 m f 0.47 m f c1 3 1 osci 5 q1 n 4.332 mhz n = 1 to 4 osco 4 r1 c5 82 pf c4 47 pf 1 k w mad 12 v ssd 6 r4 v ref v ssa 17 15 5 + 5 v + 5 v pswn mpth sda scl fig.1 block diagram.
2002 jan 14 5 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 pinning symbol pin description mro 1 multi-path recti?er output mpth 2 multi-path detector output tcon 3 test control input pin osco 4 oscillator output osci 5 oscillator input v ssd 6 digital ground (0 v) v ddd 7 digital supply voltage (5 v) davn 8 data available output (active low) sda 9 i 2 c-bus serial data i/o scl 10 i 2 c-bus serial clock input pswn 11 pause switch output (active low) mad 12 slave address (lsb) input afin 13 audio signal input v dda 14 analog supply voltage (5 v) v ssa 15 analog ground (0 v) mpx 16 multiplex input signal v ref 17 reference voltage output scout 18 band-pass ?lter output cin 19 comparator input lvin 20 level input symbol pin description fig.2 pin configuration (dip20). handbook, halfpage mro mpth tcon osco osci v ssd v ddd sda scl lvin cin scout v ref v ssa v dda mpx afin mad 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 saa6588 mgk533 davn pswn fig.3 pin configuration (so20). handbook, halfpage mro mpth tcon osco osci v ssd v ddd sda scl lvin cin scout v ref v ssa v dda mpx afin mad 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 mgk534 davn pswn saa6588t
2002 jan 14 6 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 functional description general the following functions are performed by the saa6588: selection of the rds/rbds signal from the mpx input signal 57 khz carrier regeneration demodulation of the rds/rbds signal symbol decoding rds/rbds block detection error detection and correction of transmission errors fast block synchronization and synchronization control detection of multi-path distortion and audio signal pauses determination of the signal quality mode control of processing and rds/rbds data output via i 2 c-bus interface sensing of pause and multi-path, information via extra output pins. the block diagram of the rds/rbds pre-processor is shown in fig.1. for the application of the device only a few external components are required. the pre-processors functional blocks are described in the following sections. rds/rbds signal demodulation b and - pass filter the band-pass filter has a centre frequency of 57 khz. it selects the rds/rbds sub-band from the multiplex signal mpx and suppresses the audio signal components. the filter block contains an analog anti-aliasing filter at the input followed by an 8th order switched capacitor band-pass filter and a reconstruction filter at the output. c locked comparator the comparator digitizes the output signal from the 57 khz band-pass filter for further processing by the digital rds/rbds demodulator. to attain high sensitivity and to avoid phase distortion, the comparator input stage contains an automatic offset compensation. d emodulation the demodulator provides all functions of the saa6579 but has improved performance under weak signal conditions. the demodulator includes: 57 khz carrier regeneration from the two sidebands (costas loop) symbol integration over one rds clock period bi-phase symbol decoding differential decoding synchronization of rds/rbds output data with clock. the rds/rbds demodulator recovers and regenerates the continuously transmitted rds/rbds data stream out of the multiplex signal (mpx) and provides the internal signals clock (rdcl) and data (rdda) for further processing by the rds/rbds decoder block. rds/rbds data processing the rds/rbds data processing of the pre-processor handles the complete processing and decoding of the continuous serial rds/rbds demodulator output data stream. different data processing modes are software controllable by the external main controller via i 2 c-bus. processed rds/rbds data blocks, decoder status information and signal quality information are also available via the i 2 c-bus. rds/rbds decoder the rds/rbds decoder contains: rds/rbds block detection error detection and correction synchronization flywheel for synchronization hold bit slip correction data processing control rds/rbds data output.
2002 jan 14 7 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 rds/rbds block detection the rds/rbds block detection is always active. for a received sequence of 26 data bits, a valid block and its offset are identified via syndrome calculation. during synchronization search, the syndrome is calculated with every new received data bit (bit-by-bit) for a received 26-bit sequence. if the decoder is synchronized, syndrome calculation is activated only after 26 data bits for each new block received. under rbds reception situation, beside the rds block sequences with (a, b, c/c', d) offset also block sequences of 4 blocks with offset e may be received. if the decoder detects an e-block, this block is marked in the block identification number bl and is available via an i 2 c-bus request. in rbds processing mode the block is signed as valid e-block and in rds processing mode, where only rds blocks are expected, signed as invalid e-block (see table 13). this information can be used by the main controller to detect e-block sequences and identify rds or rbds transmitter stations. error detection and correction the rds/rbds error detection and correction recognizes and corrects potential transmission errors within a received block via parity-check in consideration of the offset word of the expected block. burst errors with a maximum length of 5 bits are corrected with this method. after synchronization has been found the error correction is always active, but cannot be carried out in every reception situation. during synchronization search, the error correction is disabled for detection of the first block and is enabled for processing of the second block depending on the pre-selected error correction mode for synchronization (mode synca to syncc, see table 4). the processed block data and the status of error correction are available for data request via the i 2 c-bus for the last two blocks. processed blocks are characterized as uncorrectable under the following conditions: during synchronization search, if the burst error is higher than allowed by the pre-selected correction mode. after synchronization has been found, if the burst error is higher than 5 bits or if errors are detected but error correction is not possible. synchronization the decoder is synchronized if two successive valid blocks in a valid sequence are detected by the block detection. for detection of the second block of this sequence, error correction is also enabled depending on the pre-selected correction mode (see table 4). only valid (correctable) blocks are accepted for synchronization (see also section error detection and correction). if synchronization is found, the synchronization status flag (sync) is set and available via an i 2 c-bus request. the synchronization is held until the flywheel (for synchronization hold) detects a loss of synchronization (see section flywheel for synchronization hold) or an external restart of synchronization is performed (see section data processing control). flywheel for synchronization hold for a fast detection of loss of synchronization the internal flywheel counter checks the number of uncorrectable blocks (error blocks). error blocks increment and valid blocks decrement the block error counter. the flywheel counter is only active if the decoder is synchronized. the synchronization is held until the flywheel counter detects an error block overflow (loss of synchronization). the maximum value for the error block counter is adjustable via the i 2 c-bus in a range of 0 to 63 (see table 6). the value 32 is set after reset and the values 0 and 63 have a special function. if the value 0 is programmed then no flywheel is active if the value 63 is programmed then the flywheel is endless and no new start of synchronization is effected automatically (synchronization hold). bit slip correction during poor reception situation phase shifts of one bit to the left or right ( 1 bit slip) between the rds/rbds clock and data may occur, depending on the lock conditions of the demodulators clock regeneration. if the decoder is synchronized and detects a bit slip, the synchronization is corrected by +1 or - 1 bit via block detection on the respectively shifted expected new block.
2002 jan 14 8 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 data processing control the pre-processor provides different operating modes selectable via the external i 2 c-bus. the data processing control performs the pre-selected operating modes and controls the requested output of the rds/rbds information. restart of synchronization mode: the restart synchronization (nwsy) control mode immediately terminates the actual synchronization and restarts a new synchronization search procedure. the nwsy flag is automatically reset after the restart of synchronization by the decoder. this mode is required for a fast new synchronization on the rds/rbds data from a new transmitter station if the tuning frequency is changed by the radio set. restart of synchronization search is furthermore automatically carried out if the internal flywheel signals a loss of synchronization (see section flywheel for synchronization hold). error correction control mode for synchronization: for error correction and identification of valid blocks during synchronization search, three different modes are selectable. (sym1, sym0, see table 4). rbds processing mode: the pre-processor is suitable for receivers intended for the european (rds) as well as for the usa (rbds) standard. if rbds mode is selected via the i 2 c-bus, the block detection and the error detection and correction are adjusted to rbds data processing. data available control mode: the pre-processor provides three different rds/rbds data output processing modes selectable via the data available control mode: (see also section rds/rbds data output and table 5). standard processing mode: if the decoder is synchronized and a new block is received (every 26 bits), the actual rds/rbds information of the last two blocks is available with every new received block. fast pi search mode: during synchronization search and if a new a-block is received, the actual rds/rbds information of this or the last two a-blocks respectively is available with every new received a-block. if the decoder is synchronized, the standard processing mode is valid. reduced data request processing mode: if the decoder is synchronized and two new blocks are received (every 52 bits), the actual rds/rbds information of the last two blocks is available with every two new received blocks. the rds/rbds pre-processor provides data output of the block identification, the rds/rbds information words and error detection and correction status of the last two blocks as well as signal quality indication and general decoder status information. in addition, the decoder controls also the data request from the external main controller. the pre-processor activates the data overflow status flag dofl (see section programming), if the decoder is synchronized and a new rds/rbds block is received before the previously processed block was completely transmitted via i 2 c-bus. after detection of data overflow the interface registers are not updated until reset of the data overflow flag by reading via the i 2 c-bus. rds/rbds data output the decoded rds/rbds block information and the current pre-processor status is available via the i 2 c-bus. for synchronization of data request between main controller and pre-processor the additional data available output signal is used. if the decoder has processed new information for the main controller the data available signal (davn) is activated (low) under the following conditions (see also table 5): during synchronization search in davb mode if a valid a-block has been detected. this mode can be used for fast search tuning (detection and comparison of the pi code contained in the a-block). during synchronization search in any dav mode, if two blocks in correct sequence have been detected (synchronization criterion). if the pre-processor is synchronized and in mode dava and davb a new block has been processed. this mode is the standard data processing mode, if the decoder is synchronized. if the pre-processor is synchronized and in davc mode two new blocks have been processed. if the pre-processor is synchronized and in any dav mode loss of synchronization is detected (flywheel counter overflow and resulting restart of synchronization). in any dav mode, if a reset condition caused by power-on or voltage-drop is detected.
2002 jan 14 9 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 the processed rds/rbds data are available for i 2 c-bus request for at least 20 ms after the davn signal was activated. the davn signal is always automatically deactivated (high) after 10 ms or almost after the main controller has read the rds/rbds data via i 2 c-bus (see fig.4). the decoder ignores new processed rds/rbds blocks if the davn signal is active or if data overflow occurs (see section data processing control). multi-path detector the multi-path detector takes its information from the unweighted level signal of the fm if amplifier, input lvin (see fig.1). the part of frequency components around 21 khz is selected by a band-pass filter and rectified by a full-wave rectifier. the capacitor at pin mro is the charge capacitor. in combination with internal current sources the time constants of the rectifier are defined. the analogous output voltage of the multi-path rectifier is buffered and available via pin mpth. signal quality detector the signal quality detector takes its information from the multiplex signal. disturbances caused by adjacent-channel reception, noise, or multi-path, generate high frequency components (noise) on the multiplex signal besides the audible distortion. the signal quality measurement is provided for fast testing alternative frequencies as well as for the tuned frequency. it is a short start/stop procedure. the measuring time is limited to 850 m s. to attain an average value over a longer time, multiple measurements are possible with integration by software processing. the noise is detected from the frequency spectrum above 90 khz. the noise voltage is selected by a 4th order high-pass filter. a full-wave rectifier, controlled by this noise voltage, charges an initially discharged capacitor (on chip). the time is measured until the voltage across the capacitor has reached a defined threshold value. then that time equivalent value is stored. the resolution of the signal quality measurement is 4 bits (16 steps). for operating the noise detector two modes are provided, the triggered mode and the continuous mode. the mode is defined by the bit sqcm (signal quality continuous measurement) as described in section programming. the triggered mode is provided for a fast signal quality test of e.g. an alternative frequency. after the alternative frequency has been tuned, the signal quality detector has to be started (triggered) by transmitting the bits sqcm = 0 and tsqd = 1 via the i 2 c-bus (see fig.5). this causes a single shot measurement immediately after the acknowledgement of this byte. the bit tsqd is internally reset during the measurement (tsqd = 0). the result of the measurement is stored and is available for reading out, as long as no new measurement is started again e.g. after tuning back to the previous frequency. the continuous mode minimizes the required i 2 c-bus activities for multiple measurements. after transmission of sqcm = 1 and tsqd = 1, the signal quality detector starts a new measurement as described above. but every time after finishing one measuring procedure the result is stored (overwrites the previous value within the i 2 c-bus buffer sqi3 to sqi0) and a new measurement starts automatically. if at any time the pre-processor is read out by his master, the last measured value will be transmitted. after transmitting the control information sqcm = 0 and tsqd = 0, the measurement activity will be stopped. a previously started but not yet finished measurement will be completed and this last result will also be available. the control bit combination sqcm = 1 and tsqd = 0 must not be used. it is reserved for later applications. at a maximum time of 850 m s after triggering or automatic restart of the signal quality detector, the result of the measurement (signal quality indication) is available and represented by the four bits sqi3 to sqi0, in a value range of 0 to 15 and is available via the i 2 c-bus (see section programming). the result 0 characterizes no or less noise/distortion and 15 high noise/distortion. tolerances of the signal quality detector as well as characteristics and tolerances of the fm if amplifier can be compensated by adjusting the sensitivity of the signal quality detector with the control bits sqs0 to sqs4. the sensitivity can be adjusted over a range of 18.6 db ( - 9.0 to +9.6 db) in steps of 0.6 db as given in table 10. pause detector the pause detector watches the audio modulation for pauses or very low levels. this function can be used for performing inaudible rds af-tests if the radio is in fm mode as well as for automatic music search (ams) if the radio is in cassette mode.
2002 jan 14 10 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 the input of the pause detector (afin) is low-ohmic and must be current driven (negative input of an operational amplifier). this has the following advantages: one (mpx) as well as two (left and right) af channel application is possible and requires only one pin unwanted crosstalk is avoided if two af channel application is chosen matching the input sensitivity is possible by external resistors. for combined application (rds and ams) variations of the switching threshold level as well as the minimum time for pause detection are possible via i 2 c-bus control. the level can be adjusted in four steps of 4 db by the control bits pl0 and pl1, see table 8 (for 1 channel: r=5k w ; for 2 channels: r = 10 k w). the corresponding values of fm deviation are calculated for stereo decoders with an output voltage of 270 mv at 22.5 khz deviation. the minimum time for detecting a pause can be adjusted by the control bits sosc, ptf0 and ptf1; see table 9. the minimum time for detecting no pause is fixed to 5 ms to avoid interruptions of a pause by a short pulse. the output signal of the pause detector is a digital switching signal (active low). it is directly available via the output pin pswn. a detected pause may initiate an af search if required (fm mode). oscillator and clock for good performance of the band-pass and demodulator stages, the pre-processor requires a crystal oscillator with a frequency of n 4.332 mhz. the pre-processor can be operated with one of four different oscillator frequencies (n = 1 to 4). the 17.328 mhz frequency (n = 4) is also uart interface compatible for 8051 based microcontrollers with a 9600 baud rate (frequency error = 4.5%), so that a radio set with microcontroller can run in this case with one crystal only. the pre-processor oscillator can drive the microcontroller or vice versa. according to the used oscillator frequency, the mode control bits ptf1, ptf0 and sosc have to be set via the i 2 c-bus after every reset, see section programming the clock generator circuitry generates hereof the internally used 4.332 mhz system clock and further derived timing signals. power supply and reset the pre-processor has separate power supply inputs for the digital and analog parts of the device. for the analog functions an additional reference voltage ( 1 2 v dda ) is internally generated and available via the output pin v ref . the i 2 c-bus interface requires a defined reset condition. the pre-processor generates a reset signal: after the supply voltage v ddd is switched on at a supply voltage drop if the oscillator frequency is lower than 400 hz. this internal reset initializes the i 2 c-bus interface registers as well as the i 2 c-bus slave control and releases the data line sda (sda = high) for input of control mode settings from the main controller. if the decoder detects a reset condition, the status information reset detected (rstd) is set and available via i 2 c-bus request. the rstd flag is deactivated after the decoder status register was read by the i 2 c-bus. this status information is important to signal the main controller about a voltage drop in the pre-processor ic. by default, the bits in the write registers (except bit sosc) are set to the values in table 11. if these values are the required values, no further initialization is necessary. programming i 2 c- bus slave transceiver for communication with the external main controller (master transceiver) the standard i 2 c-bus is used. the pre-processors i 2 c-bus interface acts as a slave transceiver with fast mode option, that allows a transfer bit rate up to 400 kbits/s but is also capable of operating at lower rates ( 100 kbits/s). the i 2 c-bus interface is connected to the external i 2 c-bus via the serial clock line scl and the serial data line sda. the clock line is supplied by the master and is only input for the slave transceiver. the data line is a serial 8-bit oriented bidirectional data transfer line, and acts as input for control mode settings from the main controller to the pre-processor, as output for requested rds/rbds data from the pre-processor to the main controller and acknowledge between pre-processor and main controller.
2002 jan 14 11 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 the transfer of requested data to the main controller is synchronized via the additional data available output signal davn to avoid loss of rds/rbds data. the davn signal is activated if the pre-processor has provided new data information for the main controller (see section rds/rbds data output) and can be used for the polling mode as well as for the interrupt mode of the main microcontroller. i 2 c- bus interface registers the i 2 c-bus interface is connected to other blocks of the pre-processor via internal registers (byte oriented). those can either be written by the pre-processor control and read by the main controller i 2 c-bus or vice versa. the device provides 3 input control registers to which may be written via the i 2 c-bus and 7 output registers which may be read via the i 2 c-bus. the decoder control updates the output registers after the detection of a new rds/rbds information block and reads the new mode control settings of the input control registers. both operations may occur in the same time slot, provided that the read operation is complete before a new rds/rbds data bit is processed by the demodulator. for the corresponding access the registers are addressed by two separate register pointers, write-enable and read-enable signals, which are activated either via the decoder control or via the i 2 c-bus interface control. during a read or write transmission from the i 2 c-bus the read/write pointer selects the register of the first byte for transmission and is auto-incremented by the i 2 c-bus control for the transfer of subsequent bytes. during a write transmission after reception of the device slave address and write bit, the mode control settings for the pre-processor have to be send in the protocol sequence as shown in table 1 and fig.5. during a read cycle after reception of the device slave address and read bit the requested rds/rbds data has to be received in the protocol sequence as given in table 2 and fig.7. table 1 input control registers table 2 output registers w rite transmission format table 3 description of initialization and mode control byte (byte 0 w ) data function byte 0 w initialization and mode control setting; see table 3 byte 1 w pause level and ?ywheel setting; see table 6 byte 2 w pause time/oscillator frequency and quality detector sensitivity setting; see table 7 data function byte 0 r decoder and data status information; see table 12 byte 1 r last processed block (high byte); see table 15 byte 2 r last processed block (low byte); see table 15 byte 3 r previously processed block (high byte); see table 15 byte 4 r previously processed block (low byte); see table 15 byte 5 r error status information; see table 15 byte 6 r signal quality indication; see table 15 bit name function 7 sqcm 0: triggered signal quality measurement 1: signal quality continuous measurement 6 tsqd 0: no determination of signal quality 1: trigger of signal quality detector measurement 5 nwsy 0: normal processing mode 1: restart of synchronization 4 sym1 selection of error correction mode for synchronization search; see table 4 3 sym0 2 rbds 0: rds processing mode 1: rbds processing mode 1 dac1 selection of data output protocol and indirectly control of data available output signal (davn); see table 5 0dac0
2002 jan 14 12 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 table 4 selection of error correction mode for synchronization search table 5 selection of data output protocol and davn signal table 6 description of pause level and ?ywheel setting bytes (byte1 w ) table 7 description of pause time/oscillator frequency and quality detector sensitivity setting (byte 2 w ) table 8 control bits pl0 and pl1 sym1 sym0 mode description 0 0 synca no error correction 0 1 syncb error correction of a burst error maximum 2 bits 1 0 syncc error correction of a burst error maximum 5 bits 1 1 syncd no error correction; no e-e block sequence allowed (for rbds mode, e-a or d-e block sequences are still allowed) dac1 dac0 mode function description 0 0 dava standard processing mode rds standard output mode; synchronization search: davn = high; synchronized: block information available and davn active after detection of a new block (every 26 bits) 0 1 davb fast pi search mode synchronization search: for fast pi search, block information available and davn active only if a correct a-block is detected; synchronized: same as standard dava mode 1 0 davc reduced data request processing mode synchronization search: davn inactive = high; synchronized: block information available and davn active only after detection of two new blocks (every 52 bits) 11 --- bit name function 7 pl1 level sensitivity for pause detection; see table 8 6 pl0 5 to 0 feb5 to feb0 maximum number of error blocks for synchronization hold ?ywheel (0 to 63) bit name function 7 ptf1 time criteria for pause (20 to 160 ms); see table 9 oscillator frequency: n 4.332 mhz (n = 1 to 4); see table 9 6 ptf0 5 sosc 0: set pause time criteria via pft1 and pft0 1: select oscillator frequency via pft1 and pft0 4 to 0 sqs4 to sqs0 adjustment of signal quality detector sensitivity ( - 9 to +9.6 db); see table 10 pl1 pl0 pause level (mv rms) below dolby level (db) fm deviation (khz) 0 0 11 30.2 1.0 0 1 17 26.2 1.6 1 0 27 22.2 2.5 1 1 43 18.2 4.0
2002 jan 14 13 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 table 9 control bits sosc, ptf0 and ptf1 table 10 control bits sqs0 to sqs4 sosc ptf1 ptf0 sosc = 0 sosc = 1 minimum time (ms) oscillator frequency (mhz) 0 0 0 20.2 4.332 (n = 1) 0 0 1 40.4 8.664 (n = 2) 0 1 0 80.8 12.996 (n = 3) 0 1 1 161.7 17.328 (n = 4) sqs correction (db) sqs4 sqs3 sqs2 sqs1 sqs0 hex 0000000 - 9.0 0000101 - 8.4 0001002 - 7.8 0001103 - 7.2 0010004 - 6.6 0010105 - 6.0 0011006 - 5.4 0011107 - 4.8 0100008 - 4.2 0100109 - 3.6 010100a - 3.0 010110b - 2.4 011000c - 1.8 011010d - 1.2 011100e - 0.6 011110f0 1000010 +0.6 1000111 +1.2 1001012 +1.8 1001113 +2.4 1010014 +3.0 1010115 +3.6 1011016 +4.2 1011117 +4.8 1100018 +5.4 1100119 +6.0 110101a +6.6 110111b +7.2 111001c +7.8 111011d +8.4 111101e +9.0 111111f +9.6
2002 jan 14 14 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 table 11 default values of the write register bits after reset r ead transmission format table 12 description of decoder and data status information byte (byte 0 r ) table 13 block identi?cation number (last detected block) table 14 processed error correction table 15 bytes 1 r to 6 r bit value comments sqcm 0 triggered signal quality measurement tsqd 0 no determination of signal quality nwsy 1 restart of synchronization sym1 and sym0 00 no error correction during synchronization rbds 0 rds processing mode pl1 and pl0 00 pause level 12 mv dac1 and dac0 00 dava mode rds standard output mode feb5 to feb0 100000 ?ywheel = 32 decimal ptf1 and ptf0 00 oscillator frequency = 4.332 mhz (sosc = 1); pause time = 20.2 ms (sosc = 0) sqs4 to sqs0 01111 gai n=0db byte bit name function 0 r 7 to 5 bl2 to bl0 block identi?cation number of last processed block; see table 13 4 sync 0: not synchronized 1: synchronized 3 dofl 0: no data over?ow 1: data over?ow detected 2 rstd 0: no reset detected 1: reset detected 1 elb1 error status of last processed block; see table 14 0 elb0 bl2/ bp2 bl1/ bp1 bl0/ bp0 block identification 0 0 0 block a 0 0 1 block b 0 1 0 block c 0 1 1 block d 1 0 0 block c 1 0 1 block e (rbds mode) 1 1 0 invalid block e (rds mode) 1 1 1 invalid block elb1/ epb1 elb0/ epb0 mode description 0 0 erda no errors detected 0 1 erdb burst error of maximum 2 bits corrected 1 0 erdc burst error of maximum 5 bits corrected 1 1 erdd uncorrectable block byte bit name function 1 r 7 to 0 m15 to m08 high byte of last processed block 2 r 7 to 0 m07 to m00 low byte of last processed block 3 r 7 to 0 pm15 to pm08 high byte of previously processed block 4 r 7 to 0 pm07 to pm00 low byte of previously processed block 5 r 7 to 2 bec5 to bec0 number of counted block errors (0 to 63) 1 epb1 error status of previously processed block; see table 14 0 epb0 6 r 7 to 5 bp2 to bp0 block identi?cation number of previous processed block; see table 13 4 - not used (unde?ned) 3 to 0 sqi3 to sqi0 signal quality indication (0 to 15)
2002 jan 14 15 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. without latching in the entire temperature range. 2. human body model (equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor). except pin 17: - 4000 v minimum and +2500 v maximum. 3. machine model (equivalent to discharging a 200 pf capacitor through a 0 w series resistor and 0.75 m h inductance). thermal characteristics symbol parameter conditions min. max. unit v dd supply voltage 0 6.5 v v n voltage at pins 1 to 5, 8 to 13, and 16 to 20 with respect to pins 6 and 15 - 0.5 v dd + 0.5 6.5 v v i(mpx)(p-p) input voltage at pin mpx (peak-to-peak value) note 1 - 6v i i input current pins 1 to 5, 8, 10 to 13 and 16 to 20 - 10 +10 ma pin 9 - 20 +20 ma i lu(prot) latch-up protection current in pulsed mode t amb = - 40 to +85 c with voltage limiting - 2 to +10 v - 100 +100 ma t amb =25 c with voltage limiting - 2 to +12 v - 200 +200 ma t amb = - 40 to +85 c without voltage limiting - 10 +10 ma t amb operating ambient temperature - 40 +85 c t stg storage temperature - 65 +150 c v es electrostatic handling note 2 - 4000 +4000 v note 3 - 250 +250 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air saa6588t (sot163-1) 85 k/w saa6588 (sot146-1) 62 k/w
2002 jan 14 16 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 characteristics digital part v dda =v ddd =5v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v ddd digital supply voltage 4.5 5.0 5.5 v i ddd digital supply current - 6.0 - ma p tot total power dissipation - 70 - mw inputs v il1 low-level input voltage at pins tcon, osci and mad -- 0.3v ddd v v il2 low-level input voltage at pins scl and sda v ddd = 4.5 to 5.0 v - 0.5 - +1.5 v v ddd = 5.0 to 5.5 v - 0.5 - +0.3v ddd v v ih1 high-level input voltage at pins tcon, osci and mad 0.7v ddd -- v v ih2 high-level input voltage at pins scl and sda v ddd = 4.5 to 5.5 v 3.0 - v ddd + 0.5 v ? i li ? input leakage current at pins tcon, scl and sda v mad =0tov ddd -- 10 m a i i(pu) input pull-up current at pin mad v mad =v il1 - 30 - 20 -m a v mad = 3.5 v -- 20 - 10 m a outputs v ol1 low-level output voltage at pins davn, pswn and osco i ol =2ma -- 0.4 v v ol2 low-level output voltage at pin sda i ol1 = 4.0 ma -- 0.4 v i ol2 = 6.0 ma -- 0.6 v v oh high-level output voltage at pins davn, pswn and osco i oh = - 2 ma 4.0 -- v crystal parameters f i(xtal) crystal input frequency n = 1 - 4.332 - mhz n=2 - 8.664 - mhz n=3 - 12.996 - mhz n=4 - 17.328 - mhz ?d f osc ? adjustment tolerance of oscillator frequency -- 30 ppm ?d f osc(t) ? temperature drift of oscillator frequency t amb = - 40 to +85 c -- 30 ppm c l load capacitance - 30 - pf r xtal crystal resonance resistance f osc 12.996 mhz -- 120 w f osc = 17.328 mhz -- 60 w
2002 jan 14 17 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 characteristics analog part v dda =v ddd =5v; t amb =25 c; measurements taken in fig.1; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dda analog supply voltage 4.5 5.0 5.5 v ? v dda - v ddd ? voltage difference between analog and digital supply - 0 0.5 v i dd(tot) total supply current - 14.0 - ma v ref reference voltage v dda = 5 v 2.25 2.5 2.75 v z o(vref) output impedance at pin v ref - 25 - k w mpx input (signal before the capacitor on pin mpx) v i(mpx)(rms) rds amplitude (rms value) d f= 1.2 khz rds signal; d f= 3.2 khz spurious signal 1 -- mv v i(max)(p-p) maximum input signal capability (peak-to-peak value) f=57 2 khz 200 -- mv f < 50 khz 1.4 -- v f < 15 khz 2.8 -- v f > 70 khz 3.5 -- v r i(mpx) input resistance f = 0 to 100 khz 33 -- k w 57 khz band-pass ?lter f c centre frequency t amb = - 40 to +85 c 56.5 57.0 57.5 khz b - 3db - 3 db bandwidth 2.5 3.0 3.5 khz g mpx signal gain f = 57 khz 17 20 23 db a sb stop band attenuation d f= 7 khz 31 -- db f < 45 khz 40 -- db f < 20 khz 50 -- db f > 70 khz 40 -- db r o(scout) output resistance at pin scout f = 57 khz - 30 60 w comparator input (pin cin) v i(min)(rms) minimum input level (rms value) f = 57 khz - 110mv r i input resistance 70 110 150 k w multi-path detector (pins lvin, mpth and mro) z i(lvin) input impedance at pin lvin f = 21 khz 24 30 36 k w v i(lvin) input voltage at pin lvin 1.0 2.5 4.0 v f c(mpd) centre frequency of the multi-path detector band-pass ?lter 20 21 22 khz b mpd bandwidth of the multi-path detector band-pass ?lter 3.6 4.0 4.4 khz a sb stop band attenuation f = 11 khz 16 -- db f = 31 khz 12 -- db t att(mro) attack time of the recti?er c6 = 100 nf; r4 = 470 k w- 6.4 - ms
2002 jan 14 18 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 t dec(mro) decay time of the recti?er c6 = 100 nf; r4 = 470 k w- 50 - ms g v(mpth) recti?er voltage gain; v lvin(rms) = 0.1 v; f lvin = 21 khz - 20 - db z o(mpth) output impedance at pin mpth 150 200 250 w v o(mpth) output voltage swing at pin mpth 0.5 - 3.5 v z l(mpth) load impedance at pin mpth with respect to ground 5 -- k w c l(mpth) load capacitance at pin mpth with respect to ground -- 20 pf signal quality detector (pin mpx) f co cut-off frequency 85 90 95 khz pbrr pass-band ripple rejection -- 1db a sb stop band attenuation f = 40 khz 30 -- db v step2-3(rms) input voltage (rms value) for transition of signal quality indication between step 2 and 3 (sqi = 0010 and 0011) sensitivit y=0db (sqs = 01111; see table 10); f = 100 khz - 85 - mv d g sq step size for signal quality input gain 0.4 0.6 0.8 db cr gsq control range for signal quality input gain 15.6 18.6 21.6 db t sqd measuring time after acknowledgement of the i 2 c-bus transceiver -- 850 m s pause detector (pins afin and pswn) z i(afin) input impedance f = 10 khz -- 10 w v i(afin) dc input voltage unloaded - v ref - v i th(rms) ac input current for threshold (rms value) pl1 = 1; pl0 = 1 3.1 4.4 6.2 m a th pause(step) step size for pause threshold 345db th pause(r) control range for pause threshold 10 12 14 db i i(offset) input offset current -- 0.4 m a t pon(min) minimum time for pause pt1 = 0; pt0 = 0 - 20.2 - ms pt1 = 0; pt0 = 1 - 40.4 - ms pt1 = 1; pt0 = 0 - 80.8 - ms pt1 = 1; pt0 = 1 - 161.7 - ms t poff(min) minimum time for no pause - 5 - ms d t time error (all values) -- 1.0 ms symbol parameter conditions min. typ. max. unit g v(mpth) 20 log v mpth(dc) v lvin(rms) -------------------------- =
2002 jan 14 19 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 i 2 c-bus protocol i 2 c-bus format in communication with the pre-processor two basic types of i 2 c-bus protocols are allowed (see tables 16 and 17). every transmission begins with a start condition s followed by the 7-bit slave address and the r/ w mode bit, all generated by the external master. the 6 higher bits of the pre-processors slave address are fixed to 001000. the least significant bit of the slave address can be set via the external input pin mad to enable a variation if the slave address is already occupied by another device of the radio set. data is transferred with the most significant bit (msb) first. each transmitted byte is followed by an acknowledge bit a (sda = low). every transmission is completed with a stop condition p generated by the master. during read or write transfer the master can abridge the data transfer by generation of a stop condition. in case of transmission errors during a write cycle, the pre-processor can indirectly stop the transfer by generating no acknowledge (sda = high) hereafter the master can send the stop condition. table 16 transmitting to the pre-processor (write transfer) notes 1. s = start condition. 2. slave address (depends on level at pin mad) = 0010000 or 0010001. 3. w = write mode. 4. a = acknowledge bit (sda = low). 5. subsequently data bytes 0 w ,1 w and 2 w . 6. p = stop condition. table 17 receiving from the pre-processor (read transfer) notes 1. s = start condition. 2. slave address (depends on level at pin mad) = 0010000 or 0010001. 3. r = read mode. 4. a = acknowledge bit (sda = low). six data-acknowledge sequences must occur before the data-not acknowledge sequence. 5. subsequently data bytes 0 r to 6 r . 6. a = no acknowledge (sda = high). 7. p = stop condition. s (1) slave address (2) w (3) a (4) data (5) a (4) data (5) a (4) data (5) a (4) p (6) s (1) slave address (2) r (3) a (4) data (5) a (4) data (5) a (6) p (7)
2002 jan 14 20 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 timing data table 18 data available signal (davn) notes 1. see fig.4a. 2. see fig.4b. symbol parameter typ. unit t dvl data valid to davn low 2.0 m s t tdav data valid period 21.9 ms t dv data valid 21.9 ms t davl data available signal is low 10.1 (1) ms depends on data request via i 2 c-bus (2) ms fig.4 data available signal (davn). handbook, full pagewidth mgk540 t dv t tdav t davl t dvl davn data handbook, full pagewidth mgk541 t dv t tdav t davl t dvl pre-processor addressed i 2 c-bus davn data a. no i 2 c-bus request during davn low-time (decoder is synchronized). b. davn low-time shortened by data-request via i 2 c-bus (decoder is synchronized).
2002 jan 14 21 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 programming and i 2 c-bus summary fig.5 rds pre-processor control commands: mode control and preset settings for the pre-processor. handbook, full pagewidth acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave mgk538 sqs1 sqs0 sqs2 sqs3 sqs4 sosc ptf0 ptf1 a p byte 2 w from master feb1 feb0 feb2 feb3 feb4 feb5 pl0 pl1 a byte 1 w from master dac1 dac0 rbds sym0 sym1 nwsy tsqd sqcm a byte 0 w from master mad 0 0 0 0 1 0 0 a s slave address + write-bit from master start condition from master stop condition from master fig.6 rds pre-processor control commands: abridged protocol, for example for immediate restart synchronization. handbook, full pagewidth mgk539 dac1 dac0 rbds sym0 sym1 1 tsqd sqcm a p byte 0 w from master mad 0 0 0 0 1 0 0 a s slave address + write-bit from master acknowledgement from slave acknowledgement from slave start condition from master stop condition from master
2002 jan 14 22 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 fig.7 data output protocol (rds data output). handbook, full pagewidth mgk537 sqi1 sqi0 sqi2 sqi3 not used bp0 bp1 bp2 a p byte 6 r from device epb1 epb0 bec0 bec1 bec2 bec3 bec4 bec5 a byte 5 r from device a lower byte of previous processed block from device a higher byte of previous processed block from device a lower byte of last processed block from device a higher byte of last processed block from device elb1 elb0 rstd dofl sync bl0 bl1 bl2 m09 m08 m10 m11 m12 m13 m14 m15 m01 m00 m02 m03 m04 m05 m06 m07 pm09 pm08 pm10 pm11 pm12 pm13 pm14 pm15 pm01 pm00 pm02 pm03 pm04 pm05 pm06 pm07 a byte 0 r from device mad 1 0 0 0 1 0 0 a s slave address + read-bit from master not acknowledged from master start condition from master stop condition from master
2002 jan 14 23 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... application diagram o k, full pagewidth mgk536 r5 270 w (1) (3) r3 10 w r6 270 w (1) (3) r7 470 w (1) 1 k w r10 470 k w c11 2.2 m f c16 82 pf c15 47 pf c17 100 nf q1 (4) (1) r8 r11 10 w 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 saa6588 1 k w r9 c6 47 m f c12 (1) c13 2.2 nf c10 330 pf c9 r4 470 w c14 100 nf mro mpth tcon osco osci v ssd v ddd davn sda scl lvin cin scout v ref mpx v ssa v dda afin mad c18 1 nf (1) c1 1.5 nf (1) c51 470 pf (1) c2 220 pf (1) (3) c4 1.5 nf (1) c3 220 pf (1) (3) r2 10 k w c8 470 nf r1 10 k w c7 470 nf (1) + 5 v s_sda s_scl s_pswn gnd gnd af1 af2 mux lvl s_mpth + 5 v s_davn 560 pf 100 nf pswn hc49/u l1 (1) (2) fig.8 application diagram. (1) components for suppression of electromagnetic emission (eme). (2) l1 = type emifil, part number blm21a102s (murata) or equivalent. (3) values for standard mode i 2 c-bus. necessary pull-up resistors of 1.8 k w are part of the i 2 c-bus interface. (4) q1: 4.332 mhz, 8.664 mhz, 12.996 mhz or 17.328 mhz.
2002 jan 14 24 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 package outlines unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot146-1 95-05-24 99-12-27 a min. a max. b z max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.0 4.2 0.51 3.2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.078 0.17 0.020 0.13 sc-603 ms-001 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 20 1 11 10 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
2002 jan 14 25 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.050 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 97-05-22 99-12-27
2002 jan 14 26 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 soldering introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. through-hole mount packages s oldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. m anual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. surface mount packages r eflow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. w ave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. m anual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 jan 14 27 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 suitability of ic packages for wave, re?ow and dipping soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is only suitable for lqfp, qfp and tqfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. mounting package soldering method wave reflow (1) dipping through-hole mount dbs, dip, hdip, sdip, sil suitable (2) - suitable surface mount bga, hbga, lfbga, sqfp, tfbga not suitable suitable - hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable (3) suitable - plcc (4) , so, soj suitable suitable - lqfp, qfp, tqfp not recommended (4)(5) suitable - ssop, tssop, vso not recommended (6) suitable -
2002 jan 14 28 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 jan 14 29 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2002 jan 14 30 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 notes
2002 jan 14 31 philips semiconductors product speci?cation rds/rbds pre-processor saa6588 notes
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753503/02/pp 32 date of release: 2002 jan 14 document order number: 9397 750 09197

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