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june 2009 rev. 1.0 MPC8569E-MDS-PB hw user guide freescale semiconductor MPC8569E-MDS-PB moduled development system processor board hw user guide version 1.0
table of contents general information hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor i table of contents list of figures v list of tables vii chapter 1 general information 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.2 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1.3 document terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.3.1 bit and byte definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.2 attributes legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 mpc8569e-mds processor board . . . . . . . . . . . . . . . . . . . .7 1.4.1 working environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2 board features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.5.1 mpc8569e processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.2 mpc8569e mds processor board bl ock diagram . . . . . . . . . . . . 10 1.6 pb component placement . . . . . . . . . . . . . . . . . . . . . . . . .10 1.7 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 chapter 2 hardware getting started 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 chapter 3 power supply 3.1 primary power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
table of contents functional description MPC8569E-MDS-PB hardware user guide, ver. 1.0 ii freescale semiconductor 3.2 pb power supply struct ure . . . . . . . . . . . . . . . . . . . . . . . . .18 3.3 power supply operation . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3.1 power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 power-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.3 over-current, voltage, and temperat ure protection . . . . . . . . . . 21 3.3.4 current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.5 auxiliary function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.4.1 core and pll voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.2 ddr voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.3 geth voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.4 power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 chapter 4 functional description 4.1 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.1.1 clock architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.2 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.3 clock-out para meters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.2.1 power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.2 hreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.3 sreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3 pb control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.3.1 pb control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.2 system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.3 reset configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.3.1 dip-switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.3.2 non-customer configuration signals . . . . . . . . . . . . . . . 33 4.4 jtag cop connection . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.4.1 jtag-cop header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.6 debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.7 post module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
table of contents board control status registers (bcsr) hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor iii 4.8 irsense module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 chapter 5 board control status registers (bcsr) 5.1 bcsr features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.2 bcsr functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.3 bcsr reprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.3.1 usb tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4 bcsr register tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.4.1 bcsr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.4.2 bcsr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.4.3 bcsr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4.4 bcsr3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4.5 bcsr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4.6 bcsr5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4.7 bcsr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4.8 bcsr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.9 bcsr8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.10 bcsr9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4.11 bcsr10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4.12 bcsr11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.4.13 bcsr12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.4.14 bcsr13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.4.15 bcsr14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4.16 bcsr15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4.17 bcsr16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.4.18 bcsr17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.4.19 bcsr18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 chapter 6 interfaces 6.1 ddr sdram interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.1.1 ddr interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.2 ddr power sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
table of contents memory maps MPC8569E-MDS-PB hardware user guide, ver. 1.0 iv freescale semiconductor 6.1.3 spd function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2 serdes interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.2.1 serdes clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2.2 serdes power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2.3 serdes interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2.4 uem expansion module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2.5 srio expansion modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.2.6 pex expansion modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3 elbc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.3.1 elbc interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4 i 2 c and sd card interfaces . . . . . . . . . . . . . . . . . . . . . . . . .59 6.4.1 i 2 c interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.2 sd card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.5 rs-232, spi flash, and usb interfaces . . . . . . . . . . . . . .61 6.5.1 rs-232 interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.5.2 spi flash interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.5.3 usb interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.6 pib interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6.6.1 pib interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.7 geth interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 6.7.1 rgmii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.7.2 reduced 10-bit interface (rtbi) . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.8 qe interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 6.8.1 communication ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.8.2 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.8.3 riser connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 chapter 7 memory maps 7.1 mpc8569e pb memory ma p . . . . . . . . . . . . . . . . . . . . . . . .73
list of figures general information hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor v list of figures chapter 1 general information figure 1.1: mpc8569e processor block diagram. . . . . . . . . . . . . . . . . . 9 figure 1.2: MPC8569E-MDS-PB block diagram. . . . . . . . . . . . . . . . . . 10 figure 1.3: preliminary pb component placement . . . . . . . . . . . . . . . . 10 chapter 2 hardware getting started chapter 3 power supply figure 3.1: power supply block diagram . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3.2: power-up voltage sequence . . . . . . . . . . . . . . . . . . . . . . . 20 figure 3.3: power supply power sequence . . . . . . . . . . . . . . . . . . . . . 22 chapter 4 functional description figure 4.1: pb clocking system block diagram . . . . . . . . . . . . . . . . . . 23 figure 4.2: mpc8569e clock subsystem block diagram . . . . . . . . . . . 24 figure 4.3: reset unit block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4.4: reset implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
list of figures board control status registers (bcsr) MPC8569E-MDS-PB hardware user guide, ver. 1.0 vi freescale semiconductor figure 4.5: pb control block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 4.6: post module interconnections . . . . . . . . . . . . . . . . . . . . . . 35 figure 4.7: irsense module interconnections. . . . . . . . . . . . . . . . . . . . 36 chapter 5 board control status registers (bcsr) chapter 6 interfaces figure 6.1: ddr interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 6.2: serdes interface block diagram . . . . . . . . . . . . . . . . . . . . . 53 figure 6.3: expansion modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 6.4: uem block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 6.5: hip card: mechanical scenario . . . . . . . . . . . . . . . . . . . . . 56 figure 6.6: pex add-in card: mechanical scenario . . . . . . . . . . . . . . . 57 figure 6.7: elbc interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 6.8: i 2 c and sd card interface block diagram . . . . . . . . . . . . . 59 figure 6.9: rs-232, spi, and usb interfaces . . . . . . . . . . . . . . . . . . . . 61 figure 6.10: qe and pib interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 6.11: qe interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 6.12: rgmii interface device signal mapping . . . . . . . . . . . . . . 66 figure 6.13: rtbi mode signal mapping. . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 7 memory maps
list of tables general information hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor vii list of tables chapter 1 general information table 1.1: related reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 1.2: definitions, acronyms, and abbreviations . . . . . . . . . . . . . . . 3 table 1.3: bit and byte terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 1.4: attributes legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 1.5: MPC8569E-MDS-PB working environment modes . . . . . . . . 7 table 1.6: MPC8569E-MDS-PB features list . . . . . . . . . . . . . . . . . . . . 8 table 1.7: mpc8569e mds processor board specifications . . . . . . . . 11 chapter 2 hardware getting started chapter 3 power supply table 3.1: power supply options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3.2: sceptre 5v external power supply. . . . . . . . . . . . . . . . . . . . 18 table 3.3: MPC8569E-MDS-PB power supply devices . . . . . . . . . . . . 18 table 3.4: power-on process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 4
list of tables board control status registers (bcsr) MPC8569E-MDS-PB hardware user guide, ver. 1.0 viii freescale semiconductor functional description table 4.1: mds clock distribution options . . . . . . . . . . . . . . . . . . . . . . 24 table 4.2: clock-out parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 4.3: clock signal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 4.4: ptp signals (1588 rtc external signals) . . . . . . . . . . . . . . 26 table 4.5: ?clock? dip-switch block . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4.6: ?ddr? dip-switch block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4.7: ?qe? dip-switch block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4.8: ?i/o? dip-switch block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4.9: ?boot? dip-switch block. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4.10: ?aux? dip-switch block . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4.11: non-customer configuration signals 1 . . . . . . . . . . . . . . . 33 table 4.12: non-customer configuration signals 2 . . . . . . . . . . . . . . . 33 table 4.13: jtag-cop header j13 pinout. . . . . . . . . . . . . . . . . . . . . . 33 table 4.14: interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 chapter 5 board control status registers (bcsr) table 5.1: functions controlled/monitored by bcsr . . . . . . . . . . . . . . 37 table 5.2: bcsr control register mnemonics . . . . . . . . . . . . . . . . . . . 38 table 5.3: bcsr0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.4: bcsr1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.5: bcsr2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.6: bcsr3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.7: bcsr4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5.8: bcsr5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5.9: bcsr6 register description . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 5.10: bcsr7 register description . . . . . . . . . . . . . . . . . . . . . . . . 43
list of tables interfaces hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor ix table 5.11: bcsr8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 5.12: bcsr9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 5.13: bcsr10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 5.14: bcsr11 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 5.15: bcsr12 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5.16: bcsr13 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5.17: bcsr14 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5.18: bcsr15 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5.19: bcsr16 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5.20: bcsr17 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5.21: bcsr18 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 chapter 6 interfaces table 6.1: ddr interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 6.2: ddr3 sodimm (204-pin) pin configurations . . . . . . . . . . . 52 table 6.3: serdes clocking solutions . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6.4: rapidio connector assignments . . . . . . . . . . . . . . . . . . . . . 56 table 6.5: pex x2 signal co nnector assignments . . . . . . . . . . . . . . . . 57 table 6.6: elbc interface features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 6.7: i 2 c interface components . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 6.8: rs-232 interface components . . . . . . . . . . . . . . . . . . . . . . . 61 table 6.9: mpc8569e uart features . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 6.10: rs-232 signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 6.11: spi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 6.12: usb interface components . . . . . . . . . . . . . . . . . . . . . . . . 63 table 6.13: usb signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 6.14: geth interface components . . . . . . . . . . . . . . . . . . . . . . . 66
list of tables memory maps MPC8569E-MDS-PB hardware user guide, ver. 1.0 x freescale semiconductor table 6.15: rgmii and phy signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 6.16: rtbi interface pin mapping . . . . . . . . . . . . . . . . . . . . . . . . 67 table 6.17: pq-mds-pib connector table color legend . . . . . . . . . . 68 table 6.18: qe functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 6.19: qe clock distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 chapter 7 memory maps table 7.1: MPC8569E-MDS-PB memory m ap (with nor flash as boot source) 73
general information introduction hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 1 chapter 1: general information 1.1 introduction the mpc8569e mds processor board (pb) is an application development system. the pb, used to verify the operation of the mpc8569e integrated communicati ons processor, provides a high level of system performance characterization. the MPC8569E-MDS-PB is used to demonstrate design- focused, electrical, circui t, and logical testing reflective of most customer appli cations. the pb enables the simulta neous operation and verification of interfaces and protocols found in specific market applications. the mpc8569e integrates an e500v2 processor core (based on power architecture? technology) with the system logic required for netw orking, telecommunications, and wirele ss infrastructure applications. the terms pex and pcie are in terchangeable. ho wever, as the module s are stamped ?pex?, the document uses this term. the mpc8569e is characterized by the following: ? high-performance e500v2 power architectur e core with 36-bit physical addressing ? 512 kb of level-2 cache ? hw and sw debug support ? 4 geth interfaces (max imum of two with sgmii) ? ieee 1588 v2 support ? two ddr3/2 sdram memory controllers ? enhanced local bus controller (elbc) ? high speed serial interface (hssi): two x1 (w ith message unit) and one x4 srio; x4/x2/x1 pex; two sgmii ? integrated security engi ne with xor acceleration ? programmable interrupt controller (pic) ?i 2 c buses: i2c1 & i2c2 ? 4-channel direct memory access (dma) controller ? debug port ? duart (with optional qe uart) ? full-speed usb 2.0 compatible interface ? quicc engine? block; four risc processors support eth, atm, pos, t1/e1, and associated inter-workings
MPC8569E-MDS-PB hardware user guide, ver. 1.0 2 freescale semiconductor general information related documentation ? secure digital card (sd) interface ? spi interface the mpc8569e is a member of the powerquicc? family of devices. these devices combine system-level support fo r industry-standard interfaces with proces sors that implement power architecture technology. the board support package (bsp) is built using th e linux operating system (os). developers using MPC8569E-MDS-PB onboard resources and debuggi ng devices can perform the following: ? upload and run code, ? set breakpoints, ? display memory and registers, ? connect proprietary hardware for incorporation into a target system that uses mpc8569e as a processor, and ? use the MPC8569E-MDS-PB as a de monstration tool, i.e., develope r application software can be programmed into the flash memo ry and run in exhibitions. a sw application developed for the mpc8569e proce ssor can run as a "bare bones" operation or with various input/output data streams, e.g., geth, pex, or sgmii connections. results can be analyzed using the codewarrior ? debugger or with other methods that directly analyze input/output data streams. 1.2 related documentation the MPC8569E-MDS-PB hardware getting started guid e is required reading. a media copy is included in the hw development kit. table 1 lists documents available in the freescale we bsite to those with nda agreement access; the website is found at http://www.freescale.com/ . table 1. related reading document description codewarrior? kit configuration guide complete hw setup. the kit configuration guide explains how to set up and use each sw component in the development kit. mpc8569e powerquicc? iii integrated processor hardware specifications mpc8569eec mpc8569e powerquicc? iii integrated processor reference manual mpc8569erm
general information document terminology hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 3 1.3 document terminology table 2 provides a comprehensive list of mp c8569e-mds-pb user guide terminology. table 2. definitions, acronyms, and abbreviations usage description addr address ads application development system bcsr board control and status register bvdd local bus volt direct current ccb platform clock cke ddr clock enable clkin clock input; in terchangeable with sysclk clkout clock output cntr isp control pld integrated sw programming cop common on-chip processor cpu central processing unit cs component side ddr double data rate dip dual-in-line package (switches) duart dual universal asynchronous receiver/transmitter e500 cpu core name ecc error detection and correction eeprom electrical erasable programmable memory elbc enhanced local bus controller en enable ep end point eth ethernet fcm nand flash control machine fsl freescale semiconductor geth gigabit ethernet (also gbe) gpcm general purpose chip-select machine host mpc8569e
MPC8569E-MDS-PB hardware user guide, ver. 1.0 4 freescale semiconductor general information document terminology hreset hard reset hw hardware i 2 c inter-integrated circuit mult i-master serial computer bus ide integrated development environment io input/output irsense service voltage drop testing jtag joint test access group (ieee? std. 1149.1?) led light-emitting diode lynx internal terminology; interchangeable with serdes lvdd quicc engine block ucc1-ucc4 voltage mck(e) ddr master clock mdic ddr memory driver impedance calibration memc memory controller mmc multi media card mpi metallized particle interconnect matrix nand flash memory nmi non-maskable interrupt nmvrst marvell phy reset signal nor flash memory pb mpc8569e-mds processor board pci peripheral components interconnect pcie pci express = pcie = pex pex pci express = pex = pcie phy physical layer pib platform i/o board pld programmable logic device pll phased lock loop post fa_and service failure analysis preset power-on-reset ps print side table 2. definitions, acronyms, and abbreviations usage description
general information document terminology hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 5 ps isp ps control pld integrated sw programming ptp precision time protocol qe quick engine rc root complex rcw reset configuration word reg cfg configuration register rgmii reduced general medi a independent interface rmii reduced media independent interface rom read only memory rtbi reduced 10-bit interface rtc real time clock sd secure digital card sdhc secure digital high capacity card serdes ? serializer/deserializer ? high speed serial communication lines; e.g., pex (pcie), srio, sgmii, etc. sgmii serial gigabit medi a independent interface shmoo graphical representation of selected test parameters in an electronic circuit. smii serial media independent interface sodimm mini dimm form factor sreset soft reset srio serial rapidio sw switch sysclk system clock; interchangeable with clkin tap e.g., usb or eth tap tdm time division multiplexing trig out signal trigger_out uart universal asynchronous receiver/transmitter ucc universal communication controller uem universal ethernet module table 2. definitions, acronyms, and abbreviations usage description
MPC8569E-MDS-PB hardware user guide, ver. 1.0 6 freescale semiconductor general information document terminology 1.3.1 bit and byte definitions 1.3.2 attributes legend upc universal programmable controller usb universal serial bus vvolt vdd common power supply terminals table 1-3. bit and byte terminology bit byte binary digit with a single binary value, 1 or 0. commonly used for measuring the amount of data transferred in one second between two telecommunication points. a unit of data, eight binary units long, that is used as a measure of computer processor storage and real and virtual memory. kbps = kbit kilobit per second (1 kbps = 1000 bits) kbyte = kb = kbyte 1 kilobyte = 1024 bytes mbps = mbit megabit per second (1 mbps = 1,000,000 bits) mbyte = mb = mbyte 1 megabyte = ~ 1,000,000 bytes gbps = gbit gigabit per second (1 gbps = ?billions of bits?) gbyte = gb = gbyte 1 gigabyte = ~ 1 billion bytes table 1-4. attributes legend attributes options signals driver rwq i ood read write quiesce input output open drain table 2. definitions, acronyms, and abbreviations usage description
general information mpc8569e-mds processor board hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 7 1.4 mpc8569e-mds processor board 1.4.1 working environment see the hardware getting star ted guide or kit configuration guide for hw preparations. table 1-5 features MPC8569E-MDS-PB wo rking environment modes, conf igurations, and power options. table 1-5. MPC8569E-MDS-PB working environment modes 1.4.2 board features the MPC8569E-MDS-PB supports an mpc8569e characterized by the following: ? runs at a maximum of 1.33 ghz ? 1.1v core voltage ? maximum quicc engine frequency of 667 mhz. the device package is a 783-pin, f lip-chip pbga of 29x29 mm pitch; its estimated power will not exceed 7w. mode optional expansion description standalone pex rc includes the noted modules: ? geth3 & 4 uem ? serdes lane e, f sriox1 or uem (sgmii mode) ? serdes lane a, b sriox1 ? serdes lane a, b pexx2 ? 1xddr3 sodimmx64 or 2xddr3x32 sodimm ? pb powered, via p2, by an external 5v power supply (included in kit). ? [option] pex ep powered, via p2 of pexx2, by an external 12v power supply. pib-combined mode mpc9569-mds-pb on pib includes the noted modules: ? geth3 & 4 uem ? serdes lane e, f sriox1 or uem (sgmii mode) ? serdes lane a, b sriox1 ? serdes lane a, b pexx2 ? 1xddr3 sodimmx64 or 2xddr3x32 sodimm ? pb powered from pib via bottom riser connectors. ? [option] pex ep powered, via p2 of pexx2, from an external 12v power supply.
MPC8569E-MDS-PB hardware user guide, ver. 1.0 8 freescale semiconductor general information mpc8569e-mds processor board table 1-6. MPC8569E-MDS-PB features list feature description ddr2/3 sdram ? one sodimmx64 of 1gb ? or, two sodimmx32 at 512mb each debug port ? access via dedicated 16-pin cop connector or a pci port elbc interface ? 32 mb (expandable) nor flash with 8-bit port size in a socket ? 32 mb nand flash with 8-bit port size in a socket ? address latch, mux, data, and control buffers ? cpld-mapped board control and status register (bcsr) high-speed risers ? connect to an add-on communication board pib or pci-pex adaptor. i 2 c buses: i2c1 & i2c2 ? i 2 c bus 1: 256 kb boot eeprom, real-time clock (rtc), dac for power shmoo, and sodimm spd eeprom ?i 2 c bus 2: 1 kb brd eeprom and uem optional control rtc ? on-board battery-powered sd ? connector serdes connectors ? high-speed ? connected to the following: ? two srio x1(with message unit) or one x4 interface ? pex (x4/x2/x1) ?two sgmii shmoo ? automatic testing cap abilities provide core voltage, and clock changing; clock is pib-controlled. spi flash ? 4 mbit transceiver: dual rs232 ? duart port with optional qe uart interconnection transceiver: usb serial ? low-speed 1.5 mbit ? full-speed 12 mbit
general information block diagrams hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 9 1.5 block diagrams 1.5.1 mpc8569e processor figure 1-1 illustrates the mpc8569e processor block diagram. figure 1-1. mpc8569e processor block diagram
MPC8569E-MDS-PB hardware user guide, ver. 1.0 10 freescale semiconductor general information pb component placement 1.5.2 mpc8569e mds proce ssor board block diagram figure 1-2 illustrates the MPC8569E-MDS-PB block diagram; its interfaces a nd functions are detailed in chapter 4, functional description. figure 1-2. MPC8569E-MDS-PB block diagram 1.6 pb component placement component placement, using a piggyback form-factor set-up, complies with the current pib-pb concept. use the existent pci/pex adaptor, 084-00331-2, to provide pex ep device functionality. figure 1-3. preliminary pb component placement i 2 c and rs-232, power supply ddr3/2 sdram interface serdes interface elbc interface mpc8569e qe and pib interface sd card device spi flash, and usb interface interfaces in socket pb control clocking and reset
general information specifications hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 11 1.7 specifications table 1-7 lists pb specifications. table 1-7. mpc8569e mds processor board specifications feature specification description process technology a soi ? 45-nm package b flip-chip pbga ? 783-pin ? 29x29 mm pitch power requirements standalone ? independent host, or as pex or agent (not in pc): 5v @ 8a external dc power supply. pib-combined mode ? pib-powered pc mode ? pc-supplied power power consumption core ? less t han 7 w at 800mhz at vdd=1.0v supply voltages core ? 1.0 v and 1.10 v pex and srio ? 1.0 v and 1.10v ethernet ? 3.3 or 2.5 v ? subject to protocol local bus ? 3.3 v ddr2 ? 1.8 v (conforms to jedec standard) ddr3 ? 1.5 v (conforms to jedec standard) processor mpc8569e ? internal clock runs at 1.33 ghz @ 1.1v core voltage ? maximum quicc engine frequency of 667 mhz memory ddr3/2 bus ? 1 gb space, 64-bit wide in one sodimm-204 ddr3, or 2x512kb, 32-bit wide on two sodimm-204 ddr3 ? data rate 800 mhz local bus buffered memory: nor flash on socket ? 32 mb space, 8-bit wide buffered memory: nand flash on socket ? 32 mb space, 8-bit wide bcsr on cpld ? 18-registers, 8-bit wide expansion ? four banks: 16-bit address bus and 16-bit data bus connected to riser connectors
MPC8569E-MDS-PB hardware user guide, ver. 1.0 12 freescale semiconductor general information specifications environmental conditions operating temperature ? 0 o c to 70 o c operating junction temp (tj) c ? 0 o c to 105 c storage temperature ? -25 o c to 85 o c relative humidity ? 5% to 90% (non-condensing) dimensions (witho ut heat-sink): per pci 64-bit add-in card form factor length ? 285 mm width ? 110 mm height ? 45 mm a relates to the processor, not the processor board. b same as above footnote. c same as above footnote. table 1-7. mpc8569e mds processor board specifications feature specification description
hardware getting started general hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 15 chapter 2: hardware getting started 2.1 general the MPC8569E-MDS-PB getting started guide explai ns and verifies pb basic operations in a step-by-step format. the getting st arted guide is required reading a nd is found in the hw development kit in cd-rom media format. switch, connector, push button, and le d settings are illustrated and de scribed in the getting started guide. instructions for connecting peripheral devices are also included. the mpc8569e mds processor board functions with an integrated developm ent environment (ide), such as freescale?s codewarrior ?. instructions for working with an ide are beyond the scope of this document.
MPC8569E-MDS-PB hardware user guide, ver. 1.0 16 freescale semiconductor hardware getting started general
power supply hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 17 chapter 3: power supply the MPC8569E-MDS-PB power supply provides all the voltages necessary for co rrect operation of the mpc8569e and all onboard peripherals. figure 3-1 illustrates the power supply block diagram. figure 3-1. power supply block diagram 5vdc in mpc8569e riser connectors l,ll,r,rr ddr3/2 ps 1.5v/1.8v core ps 0.9v- 1.25v 30a lpf lpf 5v from pib ddr block & sodimm?s vdd avdd?s scorevdd,xvdd a 3v3 ps 30a 2v5 ps 3a 1v0 ps 3a power sequencer & monitor pld altera ovdd,bvdd & board related geth phy?s geth phy?s pwr_on/off pwr failed pwr on 5vin dig.pot i2c1 voltage supervisor 1v8 ps 1.5a to lynx mux.(aux) & irsense module 5vin pwr_ok 5vin fan fan_on/off pwr_on3 pwr_on2 pwr_on1 pwr_on4 test 2v5 ps 3a uem?s lvdd1 lvdd2 pwr switch qe lvdd volt select pwr switch
MPC8569E-MDS-PB hardware user guide, ver. 1.0 18 freescale semiconductor power supply primary power supply 3.1 primary power supply table 3-1 outlines MPC8569E-MDS-PB pow er supply options while table 3-2 notes sceptre external power supply specifications. 3.2 pb power supply structure table 3-3 lists power supply devices. devices include vi sual indications and power sequence functions. table 3-1. power supply options set-up power description pb standalone 40w ? standard ce/ul-approved 40w primary power supply pb on pib 5v ? pib onboard power supply provides primary 5v voltage to the pb external power supply 5v dc input ? required by pb-mounted secondary power supplies ? sceptre ps-5080apl05 table 3-2. sceptre 5v external power supply power supply description external 5v standard ? vin = 100 - 250v ac ? fin frequency = 47 - 63hz ?iin < 1.5a ? output 40w max. = 5v dc out 5% @ 8a table 3-3. MPC8569E-MDS-PB power supply devices power supply device description texas instruments: pth05t210wad (u5) programmable power dc/dc module produces mpc8569e core/pll voltages: ?v dd = 0.9 -1.25v with step 2mv ? rated voltage = 1.2v ? iout <=30a texas instruments: pth05t210wad (u13) power dc/dc module produces 3v3 voltage for mpc8569e and general on-board components: ? ovdd, bvdd, etc. = 3.3v ? iout <=30a texas instruments: tps51116pwp (u75) synchronous dc/dc converter produces all required ddr3 sdram voltages: ?gv dd = 1.8/1.5v and iout <=10a ? vtt = 0.9/0.75v and iout <=3a ? vref = 0.9/0.75v and iout <=10ma
power supply power supply operation hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 19 3.3 power supply operation 3.3.1 power-on the primary power source provides 5v0 voltage when connect ed to an ac power outlet. the voltage powers onboard power supply pld control circuits (u84). power-on process steps are described in table 3-4 and illustrated in figure 3-2 . linear tech: ? lt1764-2.5 micrel: ? mic49300wr ? mic37139-1.8ys set linear regulators provide all necessary eth phys, uems, and corresponding mpc8569e voltages: ? 2.5v dc @3a ? 1.0v dc @3a ? 1.8v dc @1.5a texas instruments: tps2115 (u98, u109) two power switches select 2.5v or 3. 3v for mpc8569e lvdd1 and lvdd2 power inputs. maxim: max16006_tg+ (u80) octal voltage supervisor determ ines ?power-good? status of all onboard secondary supply voltages. altera: epm7064stc44-10n pld (u84) control circuits based on this power supply device provide: ? needed quantity of onboard secondary ps on/off signals. ? additional heat sink fan on/off signal. ? visual indication. ? power sequence functions. ? auxiliary test mode identifies non-functioning onboard power supplies. ? auxiliary test mode cancels ?power-good? signal monitoring. ? start/stop power-on condition watchdog. ? added time interval , between power-off and power-on cycles, that discharges bulk capacitors located on all secondary onboard power supplies outputs. table 3-4. power-on process step stage description 1 supplied voltage ? 5v0 2 auxiliary reset controller (u12) ? produces a reset signal that resets the pld 3 yellow led ?5vin? ? indicates power supply ready status ? no other voltages are present on the pb 4 on/off button ? push button 5 pld ? sends a ps_on signal to all onboard power supplies to produce all voltages ? see ta b l e 3 - 3 table 3-3. MPC8569E-MDS-PB power supply devices power supply device description
MPC8569E-MDS-PB hardware user guide, ver. 1.0 20 freescale semiconductor power supply power supply operation figure 3-2. power-up voltage sequence 6 transients ? completes all transients 7 octal voltage supervisor ? produces pwr_ok signal ? informs pld-mapped control circuits that all output voltages are in good condition 8 mpc8569e power rails ? must be applied in a gi ven sequence to ensure proper device operation ? all power supplies reach stable values within 18ms ? concurrently, pld-mapped watchdog circuits begin (t~20ms) monitoring the power-on condition ? power-up requirements are as follows: ?vdd ? avdd_ n ? bvdd ?lvdd n ?ovdd ? svdd ? xvdd ?gvdd 9 success ? each power supply?s ?power-good? signal stops the watchdog ? green ?pwr_on? led is illuminated failure ? watchdog sets the power-failed flip-flop (pld-mapped) ? indicated by the red ?pwr_failed? led ? resets power-on/off flip-flop (pld-mapped) that cancels the ps_on signal to the onboard power supplies; the latter are switched off repeat on switching ? only after reconnecting the external power supply to the ac outlet table 3-4. power-on process step stage description 2 4 6 8 10 12 14 16 18 20 22 ms 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v bvdd gvdd vdd 270 300 pwr_on hrst 2.5v_geth,2.5v_uem 1v_geth 1.8v
power supply voltage regulation hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 21 3.3.2 power-off power switches off when, ? pb is in power-on status (?pw r_on? led is illuminated), and ? on/off button is activated, as ? pld-mapped power-on/off flip-flop cancels ps_on signal to all on- board power supplies. 3.3.3 over-current, voltage, and temperature protection the external primary power supply and all onboard power supply regulators ha ve embedded, over-current, over-voltage, and over-te mperature protection. 3.3.4 current measurement allegro?s bidirectional 1.5 mohm hall-effect-based linear curr ent sensor (acs712elctr-20a-t) measures the amount of current consumed by the core. the allegro sensor is ch aracterized by the following: ? precision, low-offset, line ar, hall sensor circuit; ? sensor circuit with a c opper conduction path located near the die surface; ? applied current flows through the copper conduction path and genera tes a magnetic field that is sensed by the integrated hall ic and converted into a pr oportional voltage; and, ? measurement results represen ted by the following formula, icore(a)=[vout(mv)-2500] /100; tolerance <=10% 3.3.5 auxiliary function the optional auxiliary function is remote pb powe r-on/off functionality?wit h each ?short?, the pb toggles between power-on/off. activate the function as follows: ? connect j8 pins with any ?dry? contact-like relay; or, ? connect j8 pins (j8/1: gnd and j8/2: "+") with any npn or fet transistors. 3.4 voltage regulation 3.4.1 core and pll voltage simultaneously adjust v dd and av dd voltages, within the range of 0.9-1.25v, as follows: ? manually adjust the potentiometer (r5); this cha nge creates a new default value that is unaffected by power-on/off. ? software-related voltage ad justments, made via the i 2 c1-mapped digital potentiometer (u73), revert to the factory default (1.1v) following each power-on.
MPC8569E-MDS-PB hardware user guide, ver. 1.0 22 freescale semiconductor power supply voltage regulation 3.4.2 ddr voltage ddr sdram gv dd , termination (v tt ), and reference (v ref ) voltages are automatic ally set within the following limits: ? ddr3 default gv dd value is 1.5v. voltages are automatically set to appropriate values after power-on. 3.4.3 geth voltage each mpc8569e geth pin (lvdd1 and lvdd2) vol tage can be switched to 2.5v or 3.3v. ? onboard dip switches (sw6/7 and 6/8) control the ti t ps2115 (u98, u109) power switch. ? ti power switch (u109 or u98) selects the voltage. 3.4.4 power sequence figure 3-3 illustrates the power supply power sequence. figure 3-3. power supply power sequence ps_on on/off 5v0 pwr_in v dd , av dd gv dd , v tt bv dd, lv dd, ov dd watchdog pwr_ok , sv dd, xv dd pwr off <5ms wd interval ~20ms wd expired release wd start wd pwr on
functional description clocking hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 23 chapter 4: functional description 4.1 clocking 4.1.1 clock architecture figure 4-1 illustrates a detailed pb clocking system block diagram. figure 4-1. pb clocking system block diagram i2c control register m[0-8], n0-1 clock set m[0-8], n0-1, p_load clock synthesizer 25-450mhz mpc9229 clock oscillator 16mhz pib pecl to lvttl translator pecl mc100ept21dtg ext. generator clock buffer ics553milf optional mpc8569e sysclk rtcclk to cpld pb clock oscillator 66.67mhz socket 2 clk_sel crystal frequency synthesizer ics840s07i idt 25mhz cpld controlled: clk_sel, slew rate 125mhz ref.clk rj-45 10/100/1000-baset mii/gmii/rgmii /tbi/rtbi/sgmii phy 88e1111-b2- bab1c000 marvell x2 universal 10/100/1000-baset eth module mii/rmii/gmii/rgmii/tbi/ rtbi/smii/sgmii x2 tp ptp_ext clock clock oscillator 66.67mhz socket clk_src_sel ptp_clk optional pc28 ptp/1588 ext. signals pps1,2,3 alarm1,2 ext_trig1,2 sof_rx1357/2468 sof_tx1357/2468 ref_clk 50/125mhz ref.clk fanout buffer mpc9448 qaa qab, qb
MPC8569E-MDS-PB hardware user guide, ver. 1.0 24 freescale semiconductor functional description clocking figure 4-2 shows how the pb clocking system sends re quired clock signals to the mpc8569e clock subsystem. figure 4-2. mpc8569e clock subsystem block diagram table 4-1 describes two mds clock distribution opt ions, pb-on-pib and standalone modes. table 4-1. mds clock distribution options clock mode hardware description pb on pib idt mpc9229 (pib-assembled) 1. clock synthesizer supplies system cl ock to the pb within the 25 - 450 mhz range. 2. synthesizer output (differential pecl) clock is routed to an on-semi translator (u104). 3. clock output is converted to cm os and distributed to mpc8569e auxiliary inputs (sysclk and rtc) via an idt (u50) low skew, fan-out buffer with a maximum frequency of 200mhz. on-semi mc100ept21dtg differential lvpecl to lvttl translator (u104) idt ics553milf (u50)
functional description clocking hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 25 ? use an additional socketable clock oscill ator to provide ptp ieee1588 functionality. ? all corresponding 1588 rtc signals have service access via correspondi ng test points; see table 4-4 for all related ptp signals. ? use an external clock generator if j18 (c lk_src_sel) is set with pins 1-2 shortened. 4.1.2 clock control pib-assembled clock synthesizer programs its output through an 11-bit parallel interface. this pib-enabled function is achieved by setting dip-swit ches to a desired value or via the i2c2 bus. the pb-assembled geth frequency synthesizer is mode-programmed via a bc sr that is mapped onto the onboard cpld. 4.1.3 clock-out parameters the pib-assembled clock synthe sizer produces clock signals with a period jitter of < 25 ps; see table 4-2 . table 4-2. clock-out parameters the clock fanout buffer (u50) supplies clock signals to the mpc8569e. the clock signals have the following parameters: standalone mtron socketable clock oscillator (66.66-133.33 mhz) ? [option] use an external clock generator if the clk sel jumper is set to the appropriate position. ? measure the clock using the clock signal test point. ? idt frequency synthesizer supplies both onboard geth phys and the mpc8569e with reference clock signa ls of 125mhz with cycle-to-cycle jitter below +/-100ps. ? uem modules receive reference clocks (50/125mhz) from the same synthesizer via another fanout buffer (u103). external clock generator idt ics840s07i (u21) crystal-to-lvcmos/lvttl frequency synthesizer output frequency range (mhz) frequency step (mhz) 25 ? 56.25 0.125 50 ? 112.5 0.25 100 ? 225 0.5 200 ? 450 1.00 table 4-1. mds clock distribution options clock mode hardware description
MPC8569E-MDS-PB hardware user guide, ver. 1.0 26 freescale semiconductor functional description clocking table 4-3. clock signal parameters table 4-4 details ptp signals. table 4-4. ptp signals (1588 rtc external signals) output frequency parameters values output clock frequency range ? 0 ? 200 mhz clock skew ? < 50 ps cycle-to-cycle worst case jitter (def ined by clock oscillator) ? <110 ps output ? each output drives a 50 ohm series terminated transmission line output rise/fall time ? <0.7 ns geth clock synthesizer with output clo ck jitter ? (at any frequency) of <100ps signal name i/o timing description parallel port signal pins ptp_pps1 output transitions synchronously in phase & frequency with respect to ptp_ref_clk. ? pps output signal generated by configuring the tmr_fiper1 register. ? every time the fiper1 value expires, one rtc clock period pulse is generated. ce_pe24 ptp_pps2 output transitions synchronously in phase & frequency with respect to tp_ref_clk. ? pps output signal generated by configuring the tmr_fiper2 register. ? every time the fiper2 value expires, one rtc clock period pulse is generated. ce_pc23 ptp_pps3 output transitions synchronously in phase & frequency with respect to ptp_ref_clk. ? pps output signal generated by configuring the tmr_fiper3 register. ? every time the fiper3 value expires, one rtc clock period pulse is generated. ce_pb31 ptp_alarm1 output asynchronous signal ? alarm output trigger: set if the timer value reaches the tmr_alarm1 register value. ce_pe25 ptp_alarm2 output asynchronous signal ? alarm output trigger: set if the timer value reaches the tmr_alarm2 register value. ce_pb30 ptp_ref_clk output - ? divided output clock is generated by dividing the timer clock. ? tmr_prsc register is configured to the division factor. ce_pc29 ptp_ext_trig1 input asynchronous signal ? i nput trigger to capture time stamps. ? captured time stamp value is stored in tmr_etts1l/tmr_etts1h. ce_pe26
functional description reset hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 27 4.2 reset figure 4-3 illustrates a detailed pb reset unit bloc k diagram. the reset unit acts as follows: ? resets the mpc8569e and all pe riphery onboard components; and, ? provides power-on, hreset, and sreset signals in compliance with mpc8569e hardware specifications. ptp_ext_trig2 input asynchronous signal ? i nput trigger to capture time stamps. ? captured time stamp value is stored in tmr_etts2l/tmr_etts2h. ce_pb28 ptp_clk input - ? external oscillator rtc. ce_pc28 ptp_sof_rx1357 input transitions synchronously with respect to the rx serial clock. ? input trigger to capture time stamps for each frame received in one of ucc1/ucc3/ucc5/ucc7 instead of time stamping according to sfd detection. ? captured time stamp value is stored in tmr_uc1_rxts_l/tmr_uc1_rxts_h. ce_pb26 ptp_sof_tx1357 input transitions synchronously with respect to the tx serial clock. ? input trigger to capture time stamps for each frame transmitted by one of ucc1/ucc3/ucc5/ucc7 instead of time stamping according to sfd detection. ? captured time stamp value is stored in tmr_uc1_txts_l/tmr_uc1_txts_h. ce_pb27 ptp_sof_rx2468 input transitions synchronously with respect to the rx serial clock. ? input trigger to capture time stamps for each frame received in one of ucc2/ucc4/ucc6/ucc8 instead of time stamping according to sfd detection. ? captured time stamp value is stored in tmr_uc2_rxts_l/tmr_uc2_rxts_h. ce_pf13 ptp_sof_tx2468 input transitions synchronously with respect to the tx serial clock. ? input trigger to capture time stamps for each frame transmitted by one of ucc2/ucc4/ucc6/ucc8 instead of time stamping according to sfd detection. ? captured time stamp value is stored in tmr_uc2_txts_l/tmr_uc2_txts_h. ce_pf14 signal name i/o timing description parallel port signal pins
MPC8569E-MDS-PB hardware user guide, ver. 1.0 28 freescale semiconductor functional description reset figure 4-3. reset unit block diagram figure 4-4 illustrates the interconnection between hreset, sreset, and cop reset signals. figure 4-4. reset implementation hreset switch is included as a bsdl testing precaution. set to position a (clo sed) to avoid asserting trst during bsdl testing. when not testing bsdl then set the switch to position b. hrst srst reset controller ds1834a maxim 3v3 5v0 poreset cpld altera cop/jtag mpc8569e hreset sreset hreset_req cop_hrst, cop_srst, cop_trst pib_rst ddr_rst aux_rst or sys_clock or 3.3vrst 5vrst mpc8569e
functional description pb control hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 29 4.2.1 power-on power_on reset stages: 1. stabilizes 3.3v and 5v dc input voltages. 2. dallas/maxim ds1834a (u87) reset controller drives (low) the 3.3v rst and 5v rst output signals for approximately 350ms. 3. pll locking: system clock runs at 100khz wh ile the internal counter waits 16,384 clock cycles. 4.2.2 hreset hreset push button provides manual reset control by st arting a one-shot circuit (w ith debounce flip-flop) that sends a pulse to the altera cpld-ma pped reset controller. reset controller output is comb ined with mpc8569e hreset_req output and routed to mpc8569e hreset input. routed input acts in two manners: ? creates a power-on or hreset push button reset. ? stops reset when the mpc8569e is ready to operate (auto-cancelling). 4.2.3 sreset sreset unit implements a one-shot circuit (with de bounce flip-flop) that se nds a pulse to mpc8569e sreset input. tsrst 10ms is sufficient even if the system clock is as low as 100khz. sreset is asserted at the same time as hreset. however, sreset remains asserted for eight system clocks following negation of the hreset signal. 4.3 pb control mpc8569e provides numerous configurat ion options when reset configur ation signals ar e driven during device hreset. this pb functionality, as well as various other control functions, ar e provided with the elbc-mapped cpld. the mapping contains a softwa re accessible set of registers (b csr) and logic networks that actualize required auxilia ry functions like hreset and sreset generation, etc.
MPC8569E-MDS-PB hardware user guide, ver. 1.0 30 freescale semiconductor functional description pb control 4.3.1 pb control block diagram figure 4-5 is a detailed block diagram of the pb control system and debug signals. figure 4-5. pb control block diagram mpc8569e jtag cpld altera cop/jtag hrst ccb clock pll ratio e500 core pll ratio boot source la24-27, lbctl, lale, lgpl2, la16 ddr pll ratio ddr pll fbk. sel ddr sdram type sel ddr mode ddr speed qe pll config sdhc lvdd volt select. { { { i/o port selection serdes ref clock config rio id la18-21, irq_out, la17, dma0_dack, lgpl0 { rio system size boot rom location cpu boot config pb27-28, pc4, pd4,la23, lgpl3, lgpl5, dma1_dack { boot sequencer config host/agent config lcs0-2, pb26, hreset_req, pf14, pd0, pe26 { clock ddr qe i/o boot aux hrst+ asleep trig_out lwe0 lclk0 la22 pb31 srst reset controller ds1834a maxim 3v3 5v0 poreset hreset sreset tri tri tri tri tri tri riser connector r pib - jtag optional ovdd ?system version 0? ovdd ovdd ?abist run? ovdd ?60x debug mode? ovdd ?i2c test mode? ovdd ovdd ovdd ?global speed config? ovdd ?platform & qe test port mux select? ovdd ?synchronouse test mode? optional optional optional optional optional optional optional optional optional non-customer-visible configuration delay hreset_req clk_out thermo1.2,3 ckstp/in-out test_sel dma0... dma1... mcp/ude tp sw_controled led?s address data control elbc eth, tdm, uart?s, flash, elbc, aux. resets etc. control pe27- 29, lwe1, ckstp_out, lgpl1, dma_ddone1, pf13 lcs3-7, lclk1, lvdd_vsel0, lvdd_vsel1 ovdd optional ddr fix platform speed core speed elbc ecc pll fuse read fuse uart0_sout ?ddr1 debug config? dma_ddone0 ?ddr2 de bug config? irq_out hreset_ req ?system version 1? ?asleep? ?trig_out? pe24 pe25 ckstp_out ?eng use bit 0? ?eng use bit 1? ?spare0 rcw bits? tri tri tri tri tri tri tri tri tri tri tri optional tri ovdd optional tri ovdd ?reg_cfg? ?led1? ?led2? ?led3? dma2...
functional description pb control hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 31 4.3.2 system control at power-on it is necessary to configure the mpc8569e and define system interface parameters; e.g., serdes configuration, pll setting, etc. at reset the mpc8569e reads the status of the corresponding reset configuration pins. 4.3.3 reset configurations every mpc8569e reset configurati on pin is connected to a corres ponding tri-state buffer output; the latter provides, after a short delay, required se ttings to the mpc8569e and the basic periphery. every signal is set by a corres ponding dip-switch or sampled fro m a corresponding pre-programmed cpld register. alternative mpc8569e pin mode settings are listed in table 4-1 to table 4-6 . a number of auxiliary non-customer configuration signals with onboa rd optional pull-up/down resistors are available for assembly. table 4-7 and table 4-8 list alternativ e pin functions. 4.3.3.1 dip-switches 4.3.3.1.1 ?clock? dip-switches table 4-1. ?clock? dip-switch block 4.3.3.1.2 ?ddr? dip-switch block table 4-2. ?ddr? dip-switch block main function elbc la24 la25 la26 la27 lbctl lale lgpl2 la16 reset config setting ccb clock pll ratio e500 core pll ratios serdes ref clock config cfg_sys_pll[0] cfg_sys_pll[1] cfg_sys_pll[ 2] cfg_sys_pll[3] cfg_core_pll[0] cfg_cor e_pll[1] cfg_core_pll [2] cfg_srds_refclk main function qe elbc debug elbc dma qe pe27 pe28 pe29 lwe1 ckstp_out lgpl1 dma_ddone 1 pf13 reset config setting ddr complex clock pll ratio ddr pll feedback select ddr dram type ddr dram mode ddr speed ddr fix cfg_ddr_pll[0] cfg_ddr_pll[1] cfg_ddr_pll[2] cfg_ddr_pll_ fdbk_sel cfg_dram_type cfg_dram_ mode cfg_ddr_ speed cfg_ddr_fix_ dis
MPC8569E-MDS-PB hardware user guide, ver. 1.0 32 freescale semiconductor functional description pb control 4.3.3.1.3 ?qe? di p-switch block table 4-3. ?qe? dip-switch block 4.3.3.1.4 ?i/o? di p-switch block table 4-4. ?i/o? dip-switch block 4.3.3.1.5 ?boot? di p-switch block table 4-5. ?boot? dip-switch block 4.3.3.1.6 ?aux? dip-switch block table 4-6. ?aux? dip-switch block main function elbc elbc misc. lcs3 lcs4 lcs5 lcs6 lcs7 lclk 1 lvdd vsel0 lvdd vsel1 reset config setting qe multiplier sdhc_cd_ polarity quicc engine block ucc1-4 voltage select cfg_qe_pll[0] cfg_qe_pll[1] cfg_qe_pll[2] cfg_qe_pll[3] cfg_qe_pll[4] cfg_sdhc_cd_ pol_sel -- main function elbc mpic elbc dma elbc la18 la19 la20 la21 irq_out la17 dma0_ dack lgpl0 reset config setting i/o port selection rapidio device id rapidio system size cfg_io_port [0] cfg_io_port[1] cfg_io_port[2] cfg_io_port[3] cfg_device_ id5 cfg_device_ id6 cfg_device_ id7 cfg_rio_sys_ size main function qe elbc misc. pb27 pb28 pc4 pd4 la23 lgpl3 lgpl5 dma1_ dack reset config setting boot rom location cpu boot config boot sequencer configuration rcw source cfg_rom_loc[0] cfg_rom_loc[1] cfg_r om_loc[2] cfg_rom_loc[3] cfg_cpu_boot cpu_boot_seq [0] cpu_boot_seq [1] cfg_rcw_ source main function elbc qe misc. qe lcs0 lcs1 lcs2 pb26 hreset_req pf14 pd0 pe26 reset config setting host/agent configuration platform speed core speed elbc por ecc enabled pll fuse read fuse cfg_host_agt [0] cfg_host_agt [1] cfg_host_agt [2] cfg_plat_ speed cfg_core_ speed cfg_lb_por_ ecc_en cfg_pll_fuse_ ovrd_dis cfg_fuse_read _en
functional description jtag cop connection hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 33 4.3.3.2 non-customer configuration signals 4.3.3.2.1 non-customer c onfiguration signals 1 table 4-7. non-customer configuration signals 1 4.3.3.2.2 non-customer c onfiguration signals 2 table 4-8. non-customer configuration signals 2 4.4 jtag cop connection mpc8569e jtag connection capability is enabled via a direct connection to the j13 header connector. 4.4.1 jtag-cop header j13 jtag header connects between the mpc8569e and an external, comp atible jtag converter such as the codewarrior usb tap; this is the default converter. table 4-9 shows jtag dual-in-row header pin-outs. main function elbc misc. dma misc. lwe0 lclk0 la22 uart0_sout dma_ddone 0 asleep trig_out nirq_out reset config setting a a [optional] pull-up /down resistors 60x debug mode global speed configuration platform and qe test port mux select ddr1 debug config ddr2 debug config i2c test mode abist run system ver. number 0 cfg_60x_ debug cfg_global_ sfto cfg_test_port_ dis cfg_ddr1_ debug cfg_ddr2_ debug cfg_i2c_test cfg_abist_en cfg_svr0 main function misc. qe misc. qe hreset_req pe24 pe25 ckstp_out pb31 pb7 reset config setting a a [optional] pull-up/down resistors. system ver. number 1 eng use bit 0 eng use bit 1 spare0 rcw bits synchronous test mode enable global waitr enabled (debug mode) cfg_svr1 cfg_eng_use0 cfg_eng_use1 cfg_spare cfg_slave_ mode_dis cfg_global_ waitr table 4-9. jtag-cop header j13 pinout pin number 123 4 5 6 7 8 910111213 14 15 16 tdo nc tdi trst run/ stop 3.3v tck chkstp _in tms gnd srst gnd hrst hreset# _out chkstp _out gnd
MPC8569E-MDS-PB hardware user guide, ver. 1.0 34 freescale semiconductor functional description interrupts 4.5 interrupts the mpc8569e has seven external interrupts. see table 4-10 for interrupt connections 4.6 debugging chip debugging is done through the mpc8569e jtag port. dedicated mp c8569e pins are connected to specified test points to enable pb testing. see the tp grouping in figure 4-5 ; it is marked by a green circle. 4.7 post module the post module is operated via a serial shift register protocol. using a defined fa test/visibility mode, six module inputs and one module output are routed to io pins. this m ode is invoked by configuring ppar register bits to 01. the post module is powered by a dedicated suppl y pin (fa_vdd) and two dedicated analog pins (fa_analog_d and fa_analog_g.). fa post module operations are enabled using dedicate d mpc8569e pins connected to a set of pb jumper and test points; see figure 4-6 . the default customer mode has pins ? fa_vdd, fa_analog_d, and fa_analog_g ? connected to the gnd. table 4-10. interrupts name alternative functi on interrupt source note irq0 - ddr3 event, usb vcc pwr - irq1 - geth1 ucc1 irq2 - geth2 ucc2 irq3 - geth3, rtc ucc3 irq4 srcid3 geth4, pib ucc4 irq5 srcid4 pib - irq6 dval pib -
functional description post module hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 35 figure 4-6. post module interconnections mpc8569e jumper jumper jumper ?fa_cz_out? fa_vdd fa_analog_d fa_analog_g vdd tp i2c1_sda i2c1 bus 0r 50r (optional) ?fa_counter_sh_out_en? tp dma_dack_ b2_sd_cmd alternative function 0r ?fa_count_en? tp dma_ddone_ b2_sd_wp alternative function 0r ?fa_sh_en? tp dma_dreq_ b2_sd_dat0 alternative function 0r ?fa_sclk? tp dma_ddone_ b1_srcid2 alternative function 0r ?fa_sdi? tp dma_dack_ b1_srcid1 alternative function 0r ?fa_reset_b? tp dma_dreq_ b1_srcid0 alternative function 0r post inputs post output
MPC8569E-MDS-PB hardware user guide, ver. 1.0 36 freescale semiconductor functional description irsense module 4.8 irsense module the irsense module provides a digital indication of in ternal voltage (ir) drop; it is configured by a programming register (tbd). the module?s digital input/output is r outed to io pins in the defined fa test/visibility mode; the mode is invoked by configuring ppar register bits to 01. fa irsense module operation is enabled using dedi cated mpc8569e pins connected to the pb; see figure 4-7 . default customer mode: irds_vdd pin is connected to the gnd. figure 4-7. irsense module interconnections mpc8569e jumper irds_vdd 1.8v (on board ps) ?irs_out? tp iic2_scl 0r ?irs_sample_en2? tp uart_rts_b0 0r 1.8v 10k (optional) 0r
board control status registers (bcsr) bcsr features hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 37 chapter 5: board control status registers (bcsr) the cpld u86 incorporates bcsr s that are accessed th rough the elbc. the bcsr s use the cs1 region at addresses 0xf8000000-0xf8007fff. addr ess lines a[27:23] are decoded for bcsr register selection. 5.1 bcsr features bcsrs are characterized by the following features: ? implemented on an altera cpld device that provides register and logic functions for some MPC8569E-MDS-PB signals; ? 8-bit wide read/write register module; ? 32-register modules (maximum) control/m onitor various mpc8569e mds pb operations; ? maximum of 18 registers are accessible from the local bus; 5.2 bcsr functions bcsrs control/monitor the functions noted in table 5-1 . table 5-1. functions controlled/monitored by bcsr bcsr-controlled function description bcsrx status registers in the following state: ? board revision code (bcsr-rev, bcsr-subrev) board clocking configuration control ? onboard signal multiplexers ? serdes clock synthesizer ? geth phy reference clock source configuration settings ? processor poreset ? boot configuration settings enable/disable ? switch/bcsr boot configuration select on hrese t ? transceiver: dual rs232 ? transceivers: geth 1/2/3/4 ? transceiver: usb ? sd card functionality hardware configuration geth transc eivers (qe hw configurations). hw write protection flash and brd i 2 c eeprom. leds (3) providing sw signaling. push buttons hreset and s reset push buttons with debounce function.
MPC8569E-MDS-PB hardware user guide, ver. 1.0 38 freescale semiconductor board control status registers (bcsr) bcsr reprogramming bcsr bit status functions are noted in table 5-2 . table 5-2. bcsr control register mnemonics 5.3 bcsr reprogramming bcsrs are reprogrammable using usb tap. the following section explai ns bcsr reprogramming procedure. 5.3.1 usb tap follow the below steps to reprogram the bcsr using the usb tap. 1. turn off board power. 2. insert the interconnection head er into the 16-pin header fi rmware programming socket (u29, "cntr-isp"). 3. connect usb tap to the header. 4. turn on board power. 5. launch ccs by following the instructions noted below: bit status description ?1? high (active) function. ?0? low active function. r read-only. w write-only. r, w read and write. launch ccs ccs commands windows host machine ? launching ccs ? run the command \ccs\bin\ccs.exe ? add a ccs icon ( ) to the task bar. ? ? double-click the icon to open the command window. linux host machine ? launching ccs ? run the command: /ccs/bin/ccs ? command window automatically opens.
board control status registers (bcsr) bcsr register tables hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 39 6. follow the ccs commands noted below to load the program: 7. wait until bcsr completes reprogramming. 8. after the status light stops flas hing, only then disconnect the usb tap. 5.4 bcsr register tables 5.4.1 bcsr0 table 3. bcsr0 register 5.4.2 bcsr1 table 4. bcsr1 register ccs steps ccs commands initialize usb tap type (from the root directory) the following: ? ccs> delete all ? ccs> config cc utap move to bcsr directory type: ? ccs> cd ? ccs> ::svf::burn bcsr_top.svf program output ? "0: usb tap (jtag) (utap:01001762) loader software ver. {1.8}" ? "sending code to usb tap - please wait" bit config signals function default att [0:3] cfg_sys_pll[0:3] establishes clock ratio between sysclk and ccb. sw7[1:4] sampled at hreset. [ 1000 ] r,w [4:6] cfg_core_pll[0:2] sets ratio between e500 core pll clock and ccb. sw7[5:7] sampled at hreset [ 100 ] r,w [7] cfg_srds_refclk ? 0: serdes expects 125 mhz reference clock frequency. ? 1 (default): serdes expects 100 mhz reference clock frequency. sw7[8] sampled at hreset [ 1 ] r,w bit config signals function default att [0:2] cfg_ddr_clk_pll[0:2] configure ddr pll ratio. sw5[1:3] sampled at hreset. ? ddr2 [ 100 ] ? ddr3 [ 110 ] r,w [3] cfg_ddr_fb_sel ddr qe and platform pll feedback select ? 0: gclk-matched/long ddr, qe, and platform plls feedback path. ? 1 (default): local/short ddr pll feedback path. sw5[4] sampled at hreset [ 1 ] r,w
MPC8569E-MDS-PB hardware user guide, ver. 1.0 40 freescale semiconductor board control status registers (bcsr) bcsr register tables 5.4.3 bcsr2 table 5. bcsr2 register 5.4.4 bcsr3 table 6. bcsr3 register [4] cfg_ddr_type ddr dram type (ddr2 or ddr3) ? 0: ddr3 of 1.5v and low cke at reset. ? 1 (default): ddr2 of 1.8v and low cke at reset. sw5[5] sampled at hreset. ? ddr3 [ 0 ] ? ddr2 [ 1 ] r,w [5] cfg_ddr_mode ddr dram mode (1x64 or 2x32) ? 0: primary and secondary ddr is enabled (32-bit width data bus). ? 1 (default): primary ddr is enabled (64-bit width data bus) but secondary ddr is disabled. sw5[6] sampled at hreset [ 1 ] r,w [6] cfg_ddr_speed ddr speed configuration input configures internal logic for proper operation of the ddr. ? 0: ddr clock frequency < 500mhz. ? 1: ddr clock frequency is > or = 500mhz. sw5[7] sampled at hreset [ 0 ] r,w [7] ddr_fix ? 1: at reset, ddr disables both mck and mcke. ? 0: ddr disables mcke at reset; a few cycles later mck is disabled. sw5[8] sampled at hreset [ 1 ] r,w bit config signals function default att [0:4] cfg_qe_pll[0:4] ? a multiplier and divisor, applied to sysclk input, define the qe clock: ? qe clock=sysclk*(cfg qe pll[0:4]/cfg_qe_clk) sw6[1:5] sampled at hreset [ 01000 ] r,w [5] sdhc sdhc card detect polarity select ? 0: sdhc card-detect polarity is inverted. ? 1 (default): sdhc card-detect polarity isn?t inverted. sw6[6] sampled at hreset [ 1 ] r,w [6:7] cfg_lvdd_vsel[0:1] voltage select dedicated pins ? qe ucc1 and ucc3 voltage select ? qe ucc2 and ucc4 voltage select sw6[6:7] sampled at hreset [ 11 ] r,w bit config signals function default att [0:3] cfg_port_sel[0:3] io select configuration for serdes. sw8[1:4] sampled at hreset [ 0111 ] r,w [4:6] cfg_rio_id[5:7] rapi dio device id [5:7]. sw8[5:7] sampled at hreset [ 000 ] r,w
board control status registers (bcsr) bcsr register tables hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 41 5.4.5 bcsr4 table 7. bcsr4 register 5.4.6 bcsr5 table 8. bcsr5 register [7] cfg_rio_sys_size rapidio system size ? 0: large system size with a maximum of 65,536 devices. ? 1: small system size with a maximum of 256 devices. sw8[8] sampled at hreset [ 1 ] r,w bit config signals function default att [0:3] cfg_rom_loc[0:3] selects physical location of boot rom. sw9[1:4] sampled at hreset [ 1101 ] r,w [4] cfg_boot_cpu specifies boot configuration mode: ? 0: cpu boot hold-off mode; e500 core boots after configuration by an external master. ? 1 (default): e500 core boots without being configured by an external master. sw9[5] sampled at hreset [ 1 ] r,w [5:6] cfg_boot_seq[0:1] boot sequencer ? allows boot sequencer to load serial rom (on i 2 c1 port) configuration data before the host configures the mpc8569e. sw9[6:7] sampled at hreset [ 11 ] r,w [7] cfg_source reset configuration source bit lets users select rcw source. ? 0: rcw is read through i 2 c. ? 1: rcw is read through io pin sampling. sw9[8] sampled at hreset [ 1 ] r/w bit config signals function default att [0:2] cfg_host_agt[0:2] mpc8569e configured to act as a host or agent to another interface master (pex and srio). sw10[1:3] sampled at hreset [ 111 ] r,w [3] cfg_plat_speed platform speed configuration input configures internal logic for proper operation with ccb frequencies. ? 0: ccb frequency < 333 mhz ? 1: ccb frequency > or = 333 mhz. sw10[4] sampled at hreset [ 1 ]r,w [4] cfg_core_speed core speed configuration input configures internal logic for proper operation with core clock frequencies. ? 0: core clock frequency < or = to 1000mhz. ? 1: core clock frequency > 1000mhz. sw10[5] sampled at hreset [ 1 ]r,w bit config signals function default att
MPC8569E-MDS-PB hardware user guide, ver. 1.0 42 freescale semiconductor board control status registers (bcsr) bcsr register tables 5.4.7 bcsr6 table 9. bcsr6 register description [5] cfg_elbc_ecc por configuration input e nables elbc ecc checking on booted external local bus interface. ? 0: elbc ecc disabled after por. ? 1: elbc ecc enabled after por. sw10[5] sampled at hreset [ 0 ] r,w [6] cfg_fuse_ovr_dis ? 0: fuse pll override is enabled. ? 1: fuse pll override is disabled. sw10[6] sampled at hreset [ 1 ] r,w [7] cfg_fuse_read fuse read enable ? 0: fuse reads are disabled during reset sequence. ? 1 (default): fuse reads are enabled during reset sequence. sw10[7] sampled at hreset [ 1 ] r,w bit config signals function default att [0] upc1_en ? 1: enable upc1, atm, or pos ? 0: disable upc1 or enable tdm1a, tdm1b, tdm1e, tdm1f, tdm1g, tdm1h, tdm2a, tdm2c, tdm2d, tdm2e, rmii5, rmii7, rmii8, tdm2g, tdm2f, and rmii6 [1] r,w [1] rupc1pos_en ? 1: enable upc1pos ? 0: disable upc1pos or enable tdm2a and tdm1b [1] r,w [2] rupc1addr_en ? 1: enable upc1addr, atm, or pos ? 0: disable upc1addr (unsupported: smii8 and smii6) [1] r,w [3] rupc1dev2 ? 1: enable upc1dev2, atm, or pos ? 0: disable upc1dev2 or enable tdm2c and ucc3 [1] r,w [4] sd_card_1bit ? 1: enable sd serial mode and disable i 2 c2 ? 0: disable sd serial mode and enable i 2 c2 [0] r,w [5] sd_card_4bits ? 1: enable sd card nibble mode (sd_card_1bit should be ?1?) and disable duart0 and i 2 c2 bus ? 0: enable duart0 and disable sd card nibble mode [0] r,w [6] tdm2g ? upc1_en = 0(bcsr6[7], disable) ? if bit =1, tdm2g is enabled ? rmii7(bcsr6[7] should be = 0 [1] r,w [7] rmii7 ? upc1_en = 0((bcsr6[7], disable) ? if bit =1, rmii7 is enabled ? tdm2g(bcsr6[6] should be = 0) [1] r,w bit config signals function default att
board control status registers (bcsr) bcsr register tables hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 43 5.4.8 bcsr7 table 10. bcsr7 register description 5.4.9 bcsr8 table 11. bcsr8 register bit config signals function default att [0] ucc1_geth ? 1: enable ucc1_geth, rgmii, or rtbi ? 0: disable ucc1_geth or enable ucc1_rmii (rmii1) on pib [1] r,w [1] ucc1_rgmii ? 1: enable rgmii ? 0: disable rtbi and enable rmii on pib [1] r,w [2] ucc1_rtbi ? 1: enable rtbi ? 0: disable rgmii and enable rmii on pib [0] r,w [3] g1dis_125 ? 1: disable phy1 clock_out 125mhz ?0: enable [0] r,w [4] g1ena_xc ?1: enable ? 0: disable [0] r,w [5] ucc1/ucc2 gethrst ? 1: normal operation ? 0: reset (nmvrst) marvel ucc1 and ucc2 [1] r,w [6] brdwp ? brd (eeprom i 2 c memory): write protected for i 2 c flash ? 0: not protected [1] r,w [7] bootwp ? 1: not protected. ? boot write protected [0] r,w bit config signals function default att [0] ucc2_geth ? 1: enable ucc2_geth, rgmii, or rtbi ? 0: disable ucc2_geth or enable ucc2_rmii (rmii2) on pib [1] r,w [1] ucc2_rgmii ? 1: enable rgmii ? 0: disable rtbi and enable rmii on pib [1] r,w [2] ucc2_rtbi ? 1: enable rtbi ? 0: disable rgmii and enable rmii on pib [0] r,w [3] g2dis_125 ? 1: disable phy2 clock_out 125mhz ? 0: enable phy2 clock_out 125mhz [0] r,w [4] g2ena_xc ?1: enable ? 0: disable [0] r,w
MPC8569E-MDS-PB hardware user guide, ver. 1.0 44 freescale semiconductor board control status registers (bcsr) bcsr register tables 5.4.10 bcsr9 table 12. bcsr9 register [5] cs_nor ? 1: boot from nand_flash ? 0: boot from nor_flash [0] r,w [6] uem marvell phy reset ? 1: reset uem3 (ucc3) and uem4 (ucc4) ? 0: normal operation [0] r,w [7] ddrdrv_sel ? 1: memc1,2: mdic0,1=36.5ohm ? 0: memc1,2: mdic0,1=18ohm [1] r,w bit config signals function default att [0] ucc3_geth ? 1: enable ucc3_geth ? use uem module on pb for rgmii or rtbi. ? 0: disable ucc3_geth or enable (depending upon ucc3_rmii bit) ucc3_rmii (rmii3) on pib or tdm1c [1] r,w [1] ucc3_rgmii ? 1: enable rgmii on uem ? 0: disable rtbi on uem and enable rmii3 on pib [1] r,w [2] ucc3_rtbi ? 1: enable rtbi on uem ? 0: disable rgmii on uem and enable rmii3 on pib [0] r,w [3] ucc3_rmii ? if ucc3_geth = 0 ? then bit = 1 enables ucc3_rmii on pib ? then bit =0 enables tdm1c and upc1_dev2 ? if ucc3_geth = 1 ? then bit has no effect [0] r,w [4] rmii3__nsmii3 ? 1: enable rmii on pb (uem) ? 0: enable smii on pb (uem) ucc6 (smii unsupported) [1] r,w [5] r_smii3_nrmii3 ? 1: enable smii on pb (uem) ucc6 (smii unsupported) ? 0: enable rmii on pb (uem) [0] r,w [6] reserved reserved [1] r,w [7] nmvphy_micphy3 select uem-assembled marvell phy or micrel phy. ?1: micrel ? 0: marvel [0] r,w bit config signals function default att
board control status registers (bcsr) bcsr register tables hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 45 5.4.11 bcsr10 table 13. bcsr10 register bit config signals function default att [0] ucc4_geth ? 1: enable ucc4_geth use uem module on pb for rgmii or rtbi. ? 0: disable ucc4_geth or enable ucc4_rmii (rmii4) on pib or tdm1c [1] r,w [1] ucc4_rgmii ? 1: enable rgmii on uem ? 0: disable rtbi on uem and enable rmii3 on pib [1] r,w [2] ucc4_rtbi ? 1: enable rtbi on uem ? 0: disable rgmii on uem and enable rmii3 on pib [0] r,w [3] rmii4__nsmii4 ? 1: enable rmii on pb (uem) ? 0: enable smii on pb (uem) ucc8 (smii unsupported) [1] r,w [4] r_smii4_nrmii4 ? 0: enable rmii on pb (uem) ? 1: enable smii on pb (uem) ucc8 (smii unsupported) [0] r,w [5] nmvphy_micphy4 select uem assembled marvell phy or micrel phy. [0] r,w [6] rnmicrst ? 0: micrel phy reset on both ucc3- & ucc4-connected uems ? 1: normal operation [0] r,w [7] rmv_sel_freq_34 ? 1: marvell phy, ucc3 & ucc4 have 25mhz input on uem ? 0: marvell phy, ucc3 & ucc4 have 125mhz input on uem [0] r,w
MPC8569E-MDS-PB hardware user guide, ver. 1.0 46 freescale semiconductor board control status registers (bcsr) bcsr register tables 5.4.12 bcsr11 table 14. bcsr11 register bit config signals function default att [0] register_config ? 0: board configured through dip-switches ? 1: board configured through bcsr registers [0] r,w [1] led1 1: led on [0] r,w [2] led2 1: led on [0] r,w [3] led3 1: led on [0] r,w [4] r_slew0 select slew rate for geth input clock. [0] r,w [5] r_slew [1] r,w [6] ssc0 select serdes clock synthesiz er spread spectrum mode. [1] r,w [7] ssc1 [1] r,w slew rate slew0 slew1 (v/ns) 00 4 10 3 01 2 11 1 setting ssc0 ssc1 spread% 0 (on) 0 (on) center +/- 0.25 1 (off) 0 (on) down -0.5 0 (on) 1 (off) down -0.75 1 (off) 1 (off) no spread
board control status registers (bcsr) bcsr register tables hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 47 5.4.13 bcsr12 table 15. bcsr12 register 5.4.14 bcsr13 table 16. bcsr13 register bit config signals function default att [0] pcie_clkdis ? 1: enable pex clock ? 0: disable pex clock [1] r,w [1] trigin for internal use only (0) [z] r,w [2] rmii6 ? 1: enable rmii6 (on pib) and tdm2f a ? 0: disable rmii6 and enable atm or pos a i 2 c pca9555 address 26h should drive output register 1[0] to 1. [0] r,w [3] rmii8 ? 1: enable rmii8 (on pib) ? 0: disable rmii8 and enable tdm1h [0] r,w [4] tdm2d_2f_dis ? 1: for rmii6 on pib ? 0: for upc1 or tdm2d or tdm2f [0] r,w [5] rgeth_clksel ? 1: uem ref clk = 125mhz ? 0: uem ref clk = 50mhz [1] r,w [6] reset_pib ? 1: reset rmii phy, tdm framer, and/ or atm phy ? 0: normal operation for rmii phy, tdm framer, and/ or atm phy [0] r,w [7] isolate_gpio ? 1: for rmii6 and rmii7 operation ? 0: for upc1 operation [0] r,w bit config signals function default att [0:7] r_ps[0:7] intern al use only [1:1] r,w
MPC8569E-MDS-PB hardware user guide, ver. 1.0 48 freescale semiconductor board control status registers (bcsr) bcsr register tables 5.4.15 bcsr14 table 17. bcsr14 register 5.4.16 bcsr15 table 18. bcsr15 register bit config signals function default att [0:4] r_ps[8:12] internal use only [11111] r,w [5] tdm1g_en ? 1: tdm1g_en enabled ? 0: tdm1g_en disabled [0] r,w [6] presence 3 uem inserted into j15 ? 1: present ? 0: not present [x] r [7] presence 4 uem inserted into j5 ? 1: present ? 0: not present [x] r bit config signals function default att [0] g3ena_xc ? 1: enable ? 0: disable [0] r,w [1] g4ena_xc ? 1: enable ? 0: disable [0] r,w [2] g3dis_125 ? 1: disable phy3 clock_out 125mhz ? 0: enable phy3 clock_out 125mhz [0] r,w [3] g4dis_125 ? 1: disable phy4 clock_out 125mhx ? 0: enable [0] r,w [4] smii6 dis ? 1: disable smii6 and enable rmii6, tdm1c, upc1 dev2, and ucc3 ? 0: enable smii6 and tdm2d (smii unsupported) [1] r,w [5] smii8 dis ? 1: enable ucc8 rmii on pib and tdm1h and disable smii8. ? 0: enable smii8 (smii unsupported) [1] r,w [6] tdm1f ? 1: enable tdm1f ? 0: disable tdm1f [1] r,w [7] ruart1_nqeuart ? 1: enable qe_uart ? 0: enable uart1, tdm1d, and tdm2b [0] r,w
board control status registers (bcsr) bcsr register tables hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 49 5.4.17 bcsr16 table 19. bcsr16 register 5.4.18 bcsr17 table 20. bcsr17 register bit config signals function default att [0] poreset pwr_on reset/hreset ? 0: active [1] r,w [1] tsec0mst reserved [1] r,w [2] tsec1mst reserved [1] r,w [3] tsec2mst reserved [1] r,w [4] tsec3mst reserved [1] r,w [5] tsec4mst reserved [1] r,w [6] tdm1c_dev2 ? 1: enable upc1 device2 ? 0: disable upc1 device 2 or enable rmii3 on pib,tdm1c and tdm2c ? if bit = 0 then rmii3 is enabled ? dev2- rxen_b[2] ? tdm2c-tsync ?tdm1c [0] r,w [7] reserved - [0] r,w bit config signals function default att [0] rnusben ? 1: disable usb and enable tdm1b ? 0: enable usb [1] r,w [1] rnusblowspd ? 1: usb full-speed (12mb/s) ? 0: usb low-speed (1.5mb/s) [0] r,w [2] rnusbvcc ? 1: usb acts as device ? usb powered from an external host ? enables rmii6 and tdm1g ? 0: usb acts as host ? usb supplies power to external device [1] r,w [3] rusb_mode usb mode ?0: host ? 1: device [0] r,w
MPC8569E-MDS-PB hardware user guide, ver. 1.0 50 freescale semiconductor board control status registers (bcsr) bcsr register tables 5.4.19 bcsr18 table 21. bcsr18 register [4] rpresence_f uem inserted into j7 ? 1: present ? 0: not present [x] r [5] rpresence_e uem inserted into j16 ? 1: present ? 0: not present [x] r [6] rflash_rdy ?1: ready ?0: busy [x] r [7] flash_nwp ? 0: flash write protect ? 1: flash normal operation [0] r,w bit config signals function value att [0:3] rev ? bcsr revision ? four bit revision coding current version r,w [4:7] subrev ? bcsr sub revision ? four bit revision coding sub version r,w bit config signals function default att
interfaces ddr sdram interface hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 51 chapter 6: interfaces 6.1 ddr sdram interface figure 6-1 is a detailed block diagram of the ddr sdram interface. figure 6-1. ddr interface ddr1/0-31 ddr1/32-63 ddr2/0-31 ddr1/mdm/0-7 ddr2/mdm/4-7 ddr1/mdqs/0-3 ddr1/mdqs/4-7 ddr2/mdqs/0-3 ddr1/mba0-2 ddr1/ma0-15 ddr1/cntr. wr/ras/cas etc. ddr1/mck0-1 ddr2/mck/0-1 ddr2/mba0-2 ddr2/ma0-15 ddr2/cntr. wr/ras/cas etc. 2 nd low height slot j2 1 st high height slot j3 sodimm-204 ddr3 socket sodimm-204 ddr3 socket 1st option sodimm ddr3 x64 mpc8569e memc1 memc2 2nd option sodimm ddr3 x32 sodimm ddr3 x64 (used 32bit only)
MPC8569E-MDS-PB hardware user guide, ver. 1.0 52 freescale semiconductor interfaces ddr sdram interface 6.1.1 ddr interface overview the ddr interface is characterized by the following characteristics: table 6-1. ddr interface figure 6-2 lists pin configurations for the 204-pin ddr3 sodimm socket. table 6-2. ddr3 sodimm (204-pin) pin configurations ddr3 interface description features ? ready-for-operation. ? 204-pin standard sodimm sockets (2). ? supports a maximum of two unbuffered ddr3 sodimm modules. interface ? ensures spd functioning of ddr sodimms. ? enables correct ddr sodimm operations. ? maximum clock rate of 40 0 mhz (800 mbits for ddr3/2). ? ddr hssi-recommended layout guarantees performance. configuring mpc8569e ddr interface options: ? [default] ddr3 x64 sodimm: inserted into low-height j2 slot ? ddr3 x32 sodimm (2): inserted into high- and low-height slots respectively
interfaces serdes interface hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 53 6.1.2 ddr power sources vdd, vref, and vtt voltages power the mpc8569e and sodimm modules from a separate power supply. see section 3.2, ?pb power supply structure ?. the spd serial i 2 c eeprom is mounted on each ddr sodimm and powered from the onboard 3.3v power source. voltage values are automatically set according to the sodimm module: ddr3 @ 1.5v. a termination voltage is also provided. 6.1.3 spd function implement spd by connecting sodimm i 2 c signals to the mpc8569e?s i 2 c1 bus. 6.2 serdes interface figure 6-2 is a detailed serdes interface block diagram. figure 6-2. serdes interface block diagram oscillator 25mhz lynx a switch lynx b lynx e lynx f option 1 option 2,3 option 4,5 high speed riser connectors qth-030-01-ldak samtec pex x4 edge connector 2 2 2 2 2 sgmiix1 sgmiix1 sgmiix1 sgmiix1 2.5gbaud x2 pex 5 2.5gbaud x1 pex - 4 pex at 2.5gbaud x2 pex sgmii sgmii 3 pex at 2.5gbaud x1 pex - sgmii sgmii 2 srio at 2.5gbaud x1 srio1 sgmii sgmii 1 frequency information a b e f lanes 2.5gbaud x2 pex 5 2.5gbaud x1 pex - x1 srio1 x1 srio2 4 pex at 2.5gbaud x2 pex sgmii sgmii 3 pex at 2.5gbaud x1 pex - sgmii sgmii 2 srio at 2.5gbaud x1 srio1 x1 srio2 sgmii sgmii 1 frequency information a b e f lanes x1 srio2 x1 srio1 mpc8569e pi2pcie412-dzhe mux/demux switch pericom ics841202bk-245lf ics557g-06lf pex_root_complex_clk sgmii_clk sgmii_clk 1 1 clock mux 2:4 ics557g-06lf sd_tx_clk 2 2 2 2 2 clock mux 2:4 jitter 50ps 2 jitter 60ps pex x2 12 v pex x2 12 v srio x1 a 1 h 1 a 1 0 h 1 0 srio x1 a 1 h 1 a 1 0 h 1 0 srio x1 a 1 h 1 a 1 0 h 1 0 srio x1 a 1 h 1 a 1 0 h 1 0 j10 j17 j16 j7 u32 u46 u92 u49 u47 u82 u102 clock source 25/100/125/ 250 mhz option
MPC8569E-MDS-PB hardware user guide, ver. 1.0 54 freescale semiconductor interfaces serdes interface 6.2.1 serdes clocking the pb shown in figure 6-2 provides reference clocks to the mp c8569e serdes modul e and peripheral devices. table 6-3. serdes clocking solutions 6.2.2 serdes power mpc8569e serdes module power (avdd_srds, sc ore_vdd, and xvdd) is derived from a vdd core voltage source and supplied vi a recommended low-pass filters. 6.2.3 serdes interface overview the serdes interface is implemented as four independent, unidirectiona l, serdes lines providing three hssi|?srio, pex and sgmii. each serdes line connects to a predefined, hi gh-speed, onboard connector via a mux switch. if mpc8569e acts as a pex ep then th e mux switch redirects the serdes lines to the pex edge-connector (not populated). special expansion modules are used to create standard interfaces. all modules illustrated in figure 6-3 , aside from the uem, act as an electrical inte rconnection between onboard high-speed connectors and standard srio header and pex x2 rc slots. solution description idt clock source (ics841202bk-245lf) two idt solutions together provide the following: ? 25/100/125/250mhz reference clocks; ? pex-standard spread spectrum; ? total cycle-to-cycle jitter of less than or equal to 110ps; and, ? use of external pex rc reference clocks when onboard mpc8569e serves as a pex ep. idt clock mux ics557g-06lf ? when used, each high-speed connector defined for the srio interface receives a separate sd_tx_clk signal from the mpc8569e serdes module. idt clock mux (ics557g-06lf) idt high-speed differential line driver (ics83021amilf) ? provides sgmii-mode uem modules with a corresponding reference clock. ? required as uem-mounted marvell geth phy requires a lvttl single-ended reference clock.
interfaces serdes interface hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 55 figure 6-3. expansion modules 6.2.4 uem expansion module the uem acts as a piggyback board and, when mounted on the uem, its features include the following: ? phy supporting r/gmii, r/tb i, mii, and sgmii modes. ? phy supporting rmii and smii modes. ? magnetics. ? rj45 connector. ? auxiliary components that provide mpc8569e functionality: mac with 10/100/1000-baset mii/rmii/gmii/rgmii/tbi/rt bi/smii/sgmii interfaces. figure 6-4 is a detailed uem block-diagram. figure 6-4. uem block diagram srio x1 a1 h1 a10 h10 universal 10/100/1000-baset eth module mii/rmii/gmii/rgmii/tbi/rtbi/ smii/sgmii srio x1 module pex x2 module pex x2 12vdc 10/100- baset rmii/smii phy ksz8041ftl micrel 16-bit i2c-bus expander pca9555 nxp (optional) qth-30-01-d-em2 samtec i2c bus macphy_rst mvphy/micphy mii/gmii/rgmii/tbi/rtbi interface diff. data pairs rj-45 with transformer diff. data pairs sgmii interface rmii/smii interface diff. data pairs 10/100/1000-baset mii/gmii/rgmii /tbi/rtbi/sgmii phy 88e1111-b2- babi c000 marvell 50mhz(rmii)/125mhz(smii) dual spdt switch max4906f elb maxim freq_sel :4 25/125 mhz 100mhz(sgmii)/125mhz(all other) switch ts3l500ae ti mc74lcx74 on semi giga lan switch ts3l500ae ti sgmii mvphy/micphy mvphy_rst
MPC8569E-MDS-PB hardware user guide, ver. 1.0 56 freescale semiconductor interfaces serdes interface 6.2.5 srio expansion modules srio connectors are placed on srio x1 expansion modules to enable hip card or cable insertions. figure 6-5 illustrates a hip card connection mounted on the pb srio x1 module. srio connector pin assi gnments are defined in table 6-4 . figure 6-5. hip card: mechanical scenario table 6-4. rapidio connector assignments cola bbgc ddge f fgg hhg 1tx0 tx0 gnd unused unused gnd unused unused gnd gnd 2tx1 tx1 3tx2 tx2 4tx3 tx3 5tclk0tclk0 6 7 rx3 rx3 8 rx2 rx2 9 rx1 rx1 10 rx0 rx0 usb geth rj-45 geth rj-45 8569e in socket lane f lane e lane a lane b 8569-mds-pb sodimm ddr3/ddr2 x64 or 2xddr3/ddr2x32 isp cop nor flash nand flash 5vdc in hip card srio x1 a1 h1 a10 h10
interfaces serdes interface hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 57 6.2.6 pex expansion modules pex connectors are placed on pex x2 expansion module to inte rconnect with a standa rd pex add-in card. figure 6-6 shows a pex add-in card connection scenario. figure 6-6. pex add-in card: mechanical scenario table 6-5 lists pex x2 connector pin assignments. table 6-5. pex x2 signal connector assignments pin name pin name a11 perst b14 tx0 a13 refclk b15 tx0 a14 refclk b19 tx1 a16 rx0 b20 tx1 a17 rx0 - - a21 rx1 - - a22 rx1 - - usb geth rj-45 geth rj-45 8569e in socket lane f lane e lane a lane b 8569-mds-pb sodimm ddr3/ddr2 x64 or 2xddr3/ddr2x32 isp cop nor flash nand flash 5vdc in pex end point card 12vdc pex x2
MPC8569E-MDS-PB hardware user guide, ver. 1.0 58 freescale semiconductor interfaces elbc interface 6.3 elbc interface figure 6-7 shows principle inte rface connections on an elbc block diagram. figure 6-7. elbc interface 6.3.1 elbc interface overview the elbc port connects to a wide va riety of external memo ries, dsps, and asics. the gpcm, upm, and fcm state-machines can be programmed separa tely to access different types of devices. all state-machines can reside in the same system. every chip select signal can be config ured to allow a state-machine control of an associated chip interface: ? gpcm controls access to asynchronous devi ces using a simple handshake protocol. ? upm can be programmed to in terface with synchronous devices or custom asic interfaces. ? fcm or nand flash further extends interface options. onboard elbc interface features are noted in table 6-6 . mpc8569e nor flash nand flash address latch data buffer cpld address buffer riser connector r cop/jtag hrst/srst config switches hrst/srst config. signals jtag lad[0-15] la[16-27] control la[26-2] lad[0-15] lad[0-7] lad[0-7] lad[0-15] la[27-22] la[27-0] cs1 cs0/cs3 cs3/cs0 lsync_in lsync_out optional u119 u71 u65 u127 u118 u126 u67 u86 j13 sw5-sw10
interfaces i 2 c and sd card interfaces hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 59 table 6-6. elbc interface features 6.4 i 2 c and sd card interfaces figure 6-8 illustrates an i 2 c and sd card interface block diagram. figure 6-8. i 2 c and sd card interface block diagram features description nand flash ? samsung k9f5608u0d-pcb0 ? socketed, onboard memory ? 32mx8bit (32mb) flash device nor flash ? spansion s29gl256n11tfiv20 ? socketed, onboard memory ? 32mx8bit (32mb) flash device cpld-mapped bcsr ? controls selected pb functions. address latch ? for pib expansion purposes. address buffer ? for pib expansion purposes. data buffer ? for slow devices; e.g., cpld, nor flash, etc. boot ? selection capability. mpc8569e boot eeprom ddr spd eeprom (high slot) j3 core voltage pot rtc ddr spd eeprom (low slot) j2 addr. 50h addr. 51h addr. 52h addr. 2c addr. 68h i2c1 bus i2c2 bus i2c2/sd bus brd eeprom addr. 52h uem module?s i2c expander addr. 20h, 22h, 24h, 25h sd card batt. 3v riser connector ll riser connector r dat_0,cmd,wp clk,cd dat_1, dat_2, dat_3 sd bus tp ?dma2?? to uart0_mux sd card socket u88 u89 u73 u15 p3 u11
MPC8569E-MDS-PB hardware user guide, ver. 1.0 60 freescale semiconductor interfaces i 2 c and sd card interfaces 6.4.1 i 2 c interface overview the mpc8569e has two i 2 c controllers. these sync hronous, multi-master buses can be connected to additional devices for expa nsion and system development. non-m uxed and muxed buses can be connected to a pib board for extra functionality and expansion. figure 6-8 illustrates the below features: i 2 c1 (non-muxed) bus usage: ? load boot eeprom sequence. ? read ddr spd eeproms; they provide co rrect information for using ddr sodimm. ? vdd controlled via corresponding digital potentiometer. ? obtain rtc information for appl ication program synchronization. ? interconnect to pib for functional expansion. i 2 c2 (muxed) bus: ? used for onboard brd eeprom. enables storage of board-related information such as pcb and cpu revisions, history updates, etc. ? control i 2 c expanders are placed on the uems. ? sd card interface is an alternative i 2 c2 bus. software-related swit ches provides corresponding interconnections. the components noted in table 6-7 are utilized with the i 2 c interface: table 6-7. i 2 c interface components 6.4.2 sd card interface esdhc provides an interface betw een host system and sd/sdio/mmc/c e-ata cards. the sd card is specifically designed to meet the security, capacit y, performance, and e nvironmental requirements inherent in emerging audio and vi deo consumer electronic devices. feature description boot eeprom ? st: m24256-bwdw6tg ? 256kbit serial eeprom brd eeprom ? atmel: at24c01a-10tu-2. ? 1kb i2c eeprom core voltage pot ? analog device: ad5245brjz50-rl7 ?256-pos i 2 c compatible digi-pot rtc ? maxim: ds1374u-33+ ? real time clock mux switches ? ti: ts3l110rgyr ? mux 4line to 2x4lines
interfaces rs-232, spi flash, and usb interfaces hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 61 6.5 rs-232, spi flash, and usb interfaces figure 6-9 is a block diagram illustrating the rs-232, spi flash, and usb interfaces. figure 6-9. rs-232, spi, and usb interfaces 6.5.1 rs-232 interface overview the rs-232 interface provides an rs-232 standard interconnection between the following: mpc8569e duart module, qe-mapped universal asynchronous receiver/transmitter (uart), and an external host. table 6-8. rs-232 interface components the mpc8569e duart consists of two independent uarts; see table 6-9 for feature descriptions. feature description rs232 transceiver ? analog devices: adm561jrsz 4t5r ? rs232 transceiver 3v3 mux switches ? ti: ts3l110rgyr ? mux 4line to 2x4lines mpc8569e qe porte [27-30]/spi1 spi flash 4mb qe portf [3-8] usb 1.1 supporting usb2.0 (host/end point) qe portf [9-12] uart0 rs-232 phy uart0 uart1/ qe-uart qe-uart uart1 usb1.1 universal serial bus transceiver 90 ohm diff.imp. to sd bus dat_1, dat_2, dat_3 harness u14 u63 u122 u110 u4 j1 j21 riser connector ll qe porta [19,25]; portb [17,23]
MPC8569E-MDS-PB hardware user guide, ver. 1.0 62 freescale semiconductor interfaces rs-232, spi flash, and usb interfaces table 6-9. mpc8569e uart features table 6-10 lists rs-232 signals. features description uart0 ? defined pins. ? muxed with sd_dat[1...3] or dma3 dack, dreq, ddone signals. ? non-muxed rts signal. ? noted uart signals are routed to dual rs-232 phy and made rs-232 standard compliant. ? connect a pair of standard db9 connectors, via a complete harness, to create a physical interconnection. uart1 ? muxed with qe portf bit [9-12]. ? [option] reconnect and mux qe ucc uart (pa19 & 25 and pb17 & 23) with uart1signals to test functionality. ? [option] route signals to pib to provide atm, tdm, etc. functionality. full-duplex operation - sw-programmable baud generators ? divide input clock by 1 to (216 ? 1). ? generate a 16x clock for transmitter and receiver engines. modem control functions ? cts ?rts sw-selectable serial interface data format ? data length ?parity ? 1/1.5/2 stop bit ? baud rate error detection ? overrun ?parity ?framing table 6-10. rs-232 signals signal # port f bit# rs-232 signal alternative signal header j21 pin# db9 pin# 1 - ? uart0_sout (o) ? sd_dat1 1 uart0/2 2 - ? uart0_sin (i) ? sd_dat2 3 uart0/3 3 - ? uart0_cts_b (i) ? sd_dat3 2 uart0/7 4 - ? uart0_rts_b (o) - 4 uart0/8 59 ? uart1_sout ? qe uart sout (o) ? cfg. device id5 ?pa19 6uart1/2 612 ? uart1_sin ? qe uart sin (i) ?- ? pb17 8uart1/3
interfaces rs-232, spi flash, and usb interfaces hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 63 6.5.2 spi flash interface overview the spi management interface defines interconnections with all standard-confor ming peripheral devices. the 4 mbit, low voltage spi flash memory device (st m25p40vmn6tg) is inserted into the pb for test functionality. corres ponding signals are represen ted on port e bit[27-30]. table 6-11 lists spi signals. 6.5.3 usb interface overview the usb interface is characterized by the following: ? supports 12mbit/s full-speed and 1.5mbit/ s low-speed serial data transmission. ? defined to connect with any peripheral devi ce that conforms to the standard usb1.1. ? interface compatible with usb 2.0 protocol. table 6-12. usb interface components corresponding signals are repres ented on port f bit[3-8]. table 6-13 lists the usb signals. 710 ? uart1_cts_b ? qe uart cts (i) ? cfg. core speed ? pb23 7uart1/7 811 ? uart1_rts_b ? qe uart rts (o) ? cfg. dram type ?pa25 9uart1/8 9 - ? gnd - 5 uart0/5 10 - ? gnd - 10 uart1/5 table 6-11. spi signals signal # port e bit# spi si gnal alternative function 1 27 spi1_spimosi (io) cfg. ddr pll0 2 28 spi1_spimiso (io) cfg. ddr pll1 3 29 spi1_spiclk (o) cfg. ddr pll2 4 30 spi1_spisel_b (io) - feature description usb transceiver nxp: isp1105w mux switches idt: idt74cbtlv3257pgg quad, 2:1, mux/demux bus switch usb power switch micrel: mic2505-2ym table 6-10. rs-232 signals signal # port f bit# rs-232 signal alternative signal header j21 pin# db9 pin#
MPC8569E-MDS-PB hardware user guide, ver. 1.0 64 freescale semiconductor interfaces pib interface 6.6 pib interface 6.6.1 pib interface overview figure 6-10 illustrates the connection between the pb_mpc8569e_qe module and the pib. figure 6-10. qe and pib interface table 6-13. usb signals signal # port f bit# usb signal alternative function 1 3 usb_oe (o) - 2 4 usb_tp (o) - 3 5 usb_tn (o) - 4 6 usb_rp (i) - 5 7 usb_rxd (i) - 6 8 usb_rn (i) - mpc8569e octal10/100 baset mii/rmii phy marvell pmc0 pmc1 pmc cards: t1/e1/ds3,oc12 etc. pib riser connector l ucc1-4 riser connector ll ucc5-8 clock oscillator 33/66 mhz programmable clock oscillator ext.gen sys. clk pb
interfaces pib interface hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 65 figure 6-11 shows mpc8569e qe interconnections. figure 6-11. qe interconnections mpc8569e ucc1 riser connector ll rj-45 ucc2 riser connector ll rj-45 hi speed riser connectors qth-30-01-d-em2 samtec universal 10/100/1000-baset eth module mii/rmii/gmii/rgmii/tbi/rtbi/smii/sgmii ucc3 riser connector ll ucc6 hi speed riser connectors qth-30-01-d-em2 samtec universal 10/100/1000-baset eth module mii/rmii/gmii/rgmii/tbi/rtbi/smii/sgmii ucc4 riser connector ll ucc8 smii smii 10/100/1000-baset mii/gmii/rgmii /tbi/rtbi/sgmii phy 88e1111-b2- bab1c000 marvell 10/100/1000-baset mii/gmii/rgmii /tbi/rtbi/sgmii phy 88e1111-b2- bab1c000 marvell riser connectors l, ll other qe pins
MPC8569E-MDS-PB hardware user guide, ver. 1.0 66 freescale semiconductor interfaces geth interface 6.7 geth interface geth features are noted in table 6-14 . table 6-14. geth interface components 6.7.1 rgmii interface rgmii is the default interface at power-on a nd is recommended for the 1000/100/10base-t speed. ? rgmii interface supports rgmii- to-copper or rgmii-to-fiber c onnections at 1000base-t speed. ? select rgmii interface by setti ng 88e1111 hwcfg_mode [3-0] to 0b1011 or via bcsr control. ? if using 1000base-t speed then a mpc8569e 125 mhz input is ta ken from the phy. ? each phy drives its own 125 mhz clock to the appropriate ucc. ? mpc8569e rgmii interface transmits a 125mhz clock to the phy gtx_clk pin. ? use this option to achi eve 10, 100, or 1000base-t speed. figure 6-12 shows mpc8569e (with marvel 88e1111 de vice) and phy signal mapping to the rgmii interface. figure 6-12. rgmii interface device signal mapping the rgmii interface reduces (to 12) the numb er of pins between phy and mpc8569e. the rgmii-to-copper interface powers-up thr ough mdc and mdio pins or via bcsr. table 6-15 lists corresponding rgmii and phy signals. feature description geth phy (4) ? marvel 88e1111 ? connected to ucc1, ucc2, ucc3, and ucc4 ports. ? ucc3 and ucc4 are connected via the uem. ? configure phys via phy internal registers using mdc and mdio signals. geth port testing modes ? [def ault] rgmii for 10/100/1000-baset ? rtbi for 1000base-t ? rtbi for 10/100 mii rxd[3-0] rx_dv rx_clk txd[3-0] tx_en gtx_clk phy mpc8569e g-eth gtx_clk tx_ctl txd[3-0] rxc rx_ctl rxd[3-0] rgmii mode
interfaces geth interface hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 67 table 6-15. rgmii and phy signals 6.7.2 reduced 10-bit interface (rtbi) rtbi supports 1000base-t speed and reduces (to 12) the number of pins between phy and mpc8569e. 1. select the rtbi-to-copper interf ace: application software should make the selection via mdc and mdio pins. 2. select rtbi mode for any ucc( 1-4): use bcsr to set a mode c onfiguration that corresponds to the rtbi mode. table 6-16 lists rtbi interface pin mapping. table 6-16. rtbi interface pin mapping figure 6-13 shows mpc8569e and phy in rtbi mode signal mapping. figure 6-13. rtbi mode signal mapping rgmii signal name phy signal name gtx_clk gtx_clk tx_en tx_en txd[3-0] txd[3-0] rx_clk rx_clk rx_ctl rx_dv rxd[3-0] rxd[3-0] rtbi signal name phy signal name gtx_clk gtx_clk td4_td9 tx_en td [0-3] txd [3-0] rcx rxclk rd4_rd9 rx_dv rd [3-0] rxd [3-0] rxd[3-0] rx_dv rx_clk txd[3-0] tx_en gtx_clk phy mpc8569e g-eth gtx_clk td4_td9 td[3-0] rxc rd4_rd9 rd[3-0] rtbi mode
MPC8569E-MDS-PB hardware user guide, ver. 1.0 68 freescale semiconductor interfaces qe interface 6.8 qe interface 6.8.1 communication ports pb communication ports allow for a variety of qe evaluations though it isn?t possible to provide all qe-supported communication interface t ypes. the pb and pib, via rise r connectors on the board, provide the mpc8569e with convenient communi cation interface device connections. long layout traces between qe pins an d their expansion connectors are a voided as each board qe pin is automatically disconnected from the riser connector. pb and pib communication port interfaces: ? ucc1-ucc4 rgmii/rtbi ? upc1 atm 155 mhz with utopia 16-bits ? 16tdm 6.8.2 mode selection table 6-17 indicates the significance of the colors used in table 6-18, ?qe functions? . the table shows a selected number of application t ypes (as listed in the column he adings) and their related pins. it is possible to choose diff erent application types as long as pin blocks are maintained. table 6-17. pq-mds-pib connector table color legend clocks mii management qe_uart0 qe_uart1 rgmii rmii smii spi tdm1 tdm2 upc1 dev0 upc1 dev1 upc1 dev2 upc1 dev3 upc1 pos usb
interfaces qe interface hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 69 table 6-18. qe functions pq pin 16tdm, 2rgmii, 1rmii, usb 11tdm, 8rmii, usb 5tdm, 4rgmii, atm multidevice multiphy usb 5tdm, 2rgmii pos multidevice multiphy pa10 tdm1a- txd [ 0 ] tdm1a- txd [ 0 ] dev3-txen _ b [ 3 ] tdm1a- txd [ 0 ] pa5 tdm1a- rxd [ 0 ] tdm1a- rxd [ 0 ] dev3-txclav [ 3 ] tdm1a- rxd [ 0 ] pa11 tdm1a- rsync tdm1a- rsync dev3-rxclav [ 3 ] tdm1a- rsync pa28 dev2- txclav[2] pa3 rgmii-enet1_txd[3] rgmii-enet1_txd[3] rgmii-enet1_txd[3] pa2 rgmii-enet1_txd[2] rgmii-enet1_txd[2] rgmii-enet1_txd[2] pa8 rgmii-enet1_rxd[2] rgmii-enet1_rxd[2] rgmii-enet1_rxd[2] pa9 rgmii-enet1_rxd[3] rgmii-enet1_rxd[3] rgmii-enet1_rxd[3] pa12 rgmii-enet1_rx_dv rmii1- enet1_rx_dv rgmii-enet1_rx_dv rgmii-enet1_rx_dv pa4 rgmii-enet1_tx_en rmii1- enet1_tx_en rgmii-enet1_tx_en rgmii-enet1_tx_en pa1 rgmii-enet1_txd[1] rmii1- enet1_txd[1] rgmii-enet1_txd[1] rgmii-enet1_txd[1] pa0 rgmii-enet1_txd[0] rmii1- enet1_txd[0] rgmii-enet1_txd[0] rgmii-enet1_txd[0] pa7 rgmii-enet1_rxd[1] rmii1- enet1_rxd[1] rgmii-enet1_rxd[1] rgmii-enet1_rxd[1] pa6 rgmii-enet1_rxd[0] rmii1- enet1_rxd[0] rgmii-enet1_rxd[0] rgmii-enet1_rxd[0] pa13 tdm1a-tsync tdm1a-tsync pb11 dev3-rxen _ b [ 3 ] pb7 tdm2c-txd[0] tdm2c-txd[0] dev2-txen_b[2] tdm2c-txd[0] pb2 tdm2c-rxd[0] tdm2c-rxd[0] dev2-rxclav[2] tdm2c-rxd[0] pb8 tdm2c-rsync tdm2c-rsync tdm2c-rsync pb0 tdm2c-tsync tdm2c-tsync rgmii-enet3_txd[3] pa31 rgmii-enet3_txd[2] pb5 rgmii-enet3_rxd[2] pb6 rgmii-enet3_rxd[3] pb4 rmii3- enet3_rxd[1] rgmii-enet3_rxd[1] dev2- rxen_b[2] pa29 tdm1c- txd[0] rmii3- enet3_txd[0] rgmii-enet3_txd[0] pb3 tdm1c- rxd[0] rmii3- enet3_rxd[0] rgmii-enet3_rxd[0] pb9 tdm1c- tsync rmii3- enet3_rx_dv rgmii-enet3_rx_dv pb1 rmii3- enet3_tx_en rgmii-enet3_tx_en pa30 rmii3- enet3_txd[1] rgmii-enet3_txd[1] pb10 tdm1c-rsync tdm2c-tsync tdm2c-tsync pd1 rmii5- enet5_txd[1] rmii5- enet5_txd[1] txen_b[0] txen_b[0] pd7 rmii5- enet5_rxd[1] rmii5- enet5_rxd[1] txdata[11] txdata[11] pd0 rmii5- enet5_txd[0] rmii5- enet5_txd[0] txsoc txsoc pd6 rmii5- enet5_rxd[0] rmii5- enet5_rxd[0] txdata[12] txdata[12] pd4 rmii5- enet5_tx_en rmii5- enet5_tx_en txdata[14] txdata[14] pd12 rmii5- enet5_rx_dv rmii5- enet5_rx_dv txdata[15] txdata[15] pd13 rxdata[14] rxdata[14] pd9 txdata[9] txdata[9] pd8 txdata[10] txdata[10] pd2 txclav[0] txclav[0] pd11 tdm2e- rsync tdm2e- rsync txdata [ 7 ] txdata [ 7 ] pd10 tdm2e- txd [ 0 ] tdm2e- txd [ 0 ] txdata [ 8 ] txdata [ 8 ] pd5 tdm2e- rxd [ 0 ] tdm2e- rxd [ 0 ] txdata [ 13 ] txdata [ 13 ] pd3 tdm2e- tsync tdm2e- tsync rxdata [ 15 ] rxdata [ 15 ] pd31 tdm1 g - tsync tdm1 g - tsync rxdata [ 10 ] rxdata [ 10 ] pe1 tdm1 g - rxd [ 0 ] tdm1 g - rxd [ 0 ] rxdata [ 8 ] rxdata [ 8 ] pe6 tdm1 g - txd [ 0 ] tdm1 g - txd [ 0 ] txprt y txprt y pe7 tdm1 g - rsync tdm1 g - rsync rxprt y rxprt y pd30 rxdata[11] rxdata[11] pe4 rxen_b[0] rxen_b[0] pe5 rxclav[0] rxclav[0] pd29 rmii7- enet7_txd[1] rxdata[12] rxdata[12] pe3 rmii7- enet7_rxd[1] rxsoc rxsoc
MPC8569E-MDS-PB hardware user guide, ver. 1.0 70 freescale semiconductor interfaces qe interface pq pin 16tdm, 2rgmii, 1rmii, usb 11tdm, 8rmii, usb 5tdm, 4rgmii, atm multidevice multiphy usb 5tdm, 2rgmii pos multidevice multiphy pd 28 tdm2 g - txd [ 0 ] rmii7- enet7 _ txd [ 0 ] rxdata [ 13 ] rxdata [ 13 ] pe2 tdm2 g - rxd [ 0 ] rmii7- enet7 _ rxd [ 0 ] rxdata [ 7 ] rxdata [ 7 ] pe0 rmii7- enet7_tx_en rxdata[9] rxdata[9] pe8 tdm2 g - tsync rmii7- enet7 _ rx _ dv rxen _ b [ 1 ] rxen _ b [ 1 ] pe9 tdm2g- rsync txen_b[1] txen_b[1] pa19 tdm2b- rxd [ 0 ] tdm2b- rxd [ 0 ] qe _ uart _ txd pa24 tdm2b- txd [ 0 ] tdm2b- txd [ 0 ] tdm2b- txd [ 0 ] pa25 tdm2b- rsync tdm2b- rsync qe _ uart _ rts pa17 rgmii- enet2_txd[3] rgmii- enet2_txd[3] rgmii- enet2_txd[3] pa16 rgmii- enet2_txd[2] rgmii- enet2_txd[2] rgmii- enet2_txd[2] pa23 rgmii- enet2_rxd[3] rgmii- enet2_rxd[3] rgmii- enet2_rxd[3] pa22 rgmii- enet2_rxd[2] rgmii- enet2_rxd[2] rgmii- enet2_rxd[2] pa18 rgmii- enet2_tx_en rmii2- enet2_tx_en rgmii- enet2_tx_en rgmii- enet2_tx_en pa26 rgmii- enet2_rx_dv rmii2- enet2_rx_dv rgmii- enet2_rx_dv rgmii- enet2_rx_dv pa20 rgmii- enet2_rxd[0] rmii2- enet2_rxd[0] rgmii- enet2_rxd[0] rgmii- enet2_rxd[0] pa21 rgmii- enet2_rxd[1] rmii2- enet2_rxd[1] rgmii- enet2_rxd[1] rgmii- enet2_rxd[1] pa14 rgmii- enet2_txd[0] rmii2- enet2_txd[0] rgmii- enet2_txd[0] rgmii- enet2_txd[0] pa15 rgmii- enet2_txd[1] rmii2- enet2_txd[1] rgmii- enet2_txd[1] rgmii- enet2_txd[1] pa27 tdm2b- tsync tdm2b- tsync tdm2b- tsync tdm2b- tsync pb17 tdm1d- rxd [ 0 ] tdm1d- rxd [ 0 ] qe _ uart _ rxd pb22 tdm1d- txd[0] tdm1d- txd[0] tdm1d- txd[0] pb23 tdm1d- rsync tdm1d- rsync qe _ uart _ cts pb15 rgmii- enet4_txd[3] rgmii- enet4_txd[3] rgmii- enet4_txd[3] pb14 rgmii- enet4_txd[2] rgmii- enet4_txd[2] rgmii- enet4_txd[2] pb21 rgmii- enet4_rxd[3] rgmii- enet4_rxd[3] rgmii- enet4_rxd[3] pb20 rgmii- enet4_rxd[2] rgmii- enet4_rxd[2] rgmii- enet4_rxd[2] pb13 rgmii- enet4_txd[1] rmii4- enet4_txd[1] rgmii- enet4_txd[1] rgmii- enet4_txd[1] pb12 rgmii- enet4_txd[0] rmii4- enet4_txd[0] rgmii- enet4_txd[0] rgmii- enet4_txd[0] pb19 rgmii- enet4_rxd[1] rmii4- enet4_rxd[1] rgmii- enet4_rxd[1] rgmii- enet4_rxd[1] pb18 rgmii- enet4_rxd[0] rmii4- enet4_rxd[0] rgmii- enet4_rxd[0] rgmii- enet4_rxd[0] pb16 rgmii- enet4_tx_en rmii4- enet4_tx_en rgmii- enet4_tx_en rgmii- enet4_tx_en pb24 rgmii- enet4_rx_dv rmii4- enet4_rx_dv rgmii- enet4_rx_dv rgmii- enet4_rx_dv pb25 tdm1d- tsync tdm1d- tsync tdm1d- tsync pd 14 tdm2f- txd [ 0 ] rmii6- enet6 _ txd [ 0 ] txdata [ 6 ] txdata [ 6 ] pd 20 tdm2f- rxd [ 0 ] rmii6- enet6 _ rxd [ 0 ] txdata [ 2 ] txdata [ 2 ] pd 26 tdm2f- tsync rmii6- enet6 _ rx _ dv rxdata [ 4 ] rxdata [ 4 ] pd 27 tdm2f- rsync rxdata[5] rxdata[5] pd15 rmii6- enet6_txd[1] txdata[5] txdata[5] pd21 rmii6- enet6_rxd[1] txdata[3] txdata[3] pd 18 tdm2d- rxd [ 0 ] rmii6- enet6 _ tx _ en rxd ata [ 0 ] rxdata [ 0 ] pd 22 tdm2d- txd [ 0 ] rxdata [ 6 ] rxdata [ 6 ] pd 23 tdm2d- rsync txdata [ 1 ] txdata [ 1 ] pd 16 tdm2d- tsync rxdata [ 2 ] rxdata [ 2 ] pd17 tdm1f- tsync tdm1f- tsync rxd ata [ 1 ] rxdata [ 1 ] pd 19 tdm1f- rxd [ 0 ] tdm1f- rxd [ 0 ] rxdata [ 3 ] rxdata [ 3 ] pd 24 tdm1f- txd [ 0 ] tdm1f- txd [ 0 ] txdata [ 0 ] txdata [ 0 ] pd25 tdm1f- rsync tdm1f- rsync txdata [ 4 ] txdata [ 4 ] pe10 tdm1h- txd [ 0 ] rmii8- enet8 _ txd [ 0 ] rxaddr [ 2 ] smi8- enet8 _ txd [ 0 ] pe11 tdm1h- tsync rmi8- enet8 _ txd [ 1 ] rxaddr [ 4 ] smi8- enet8 _ syn c pe16 tdm1h- rxd [ 0 ] rmii8- enet8 _ rxd [ 0 ] txaddr [ 2 ] smi8- enet8 _ rxd [ 0 ] pe23 tdm1h- rsync txaddr [ 4 ] pe14 smi6- enet6_rxd[0] rmii8- enet8_tx_en rxaddr[3] smi6- enet6_rxd[0] pe17 smi6- enet6_txd[0 rmii8- enet8_rxd[1] txaddr[3] smi6- enet6_txd[0 pe22 smi6-enet6_sync rmii8- enet8_rx_dv rxaddr[5] smi6-enet6_sync pe13 rxaddr[0]
interfaces qe interface hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 71 pq pin 16tdm, 2rgmii, 1rmii, usb 11tdm, 8rmii, usb 5tdm, 4rgmii, atm multidevice multiphy usb 5tdm, 2rgmii pos multidevice multiphy pe21 tdm2h- rsync tdm2h- rsync txaddr [ 1 ] txaddr [ 1 ] pe12 tdm2h- tsync tdm2h- tsync txaddr [ 5 ] txaddr [ 5 ] pe15 tdm2h- rxd [ 0 ] tdm2h- rxd [ 0 ] rxaddr [ 1 ] rxaddr [ 1 ] pe20 tdm2h- txd [ 0 ] tdm2h- txd [ 0 ] txaddr [ 0 ] txaddr [ 0 ] pe19 txclav[1] txclav[1] pe18 rxclav[1] rxclav[1] pe31 tdm1b- tsync tdm1b- tsync tdm1b- tsync tdm1b- tsync pf0 tdm1b- rxd [ 0 ] tdm1b- rxd [ 0 ] tdm1b- rxd [ 0 ] tdm1b- rxd [ 0 ] pf1 tdm1b- txd [ 0 ] tdm1b- txd [ 0 ] tdm1b- txd [ 0 ] tdm1b- txd [ 0 ] pf2 tdm1b- rsync tdm1b- rsync tdm1b- rsync tdm1b- rsync pf3 *usb_oe *usb_oe *usb_oe *usb_oe pf4 usb_tp usb_tp usb_tp usb_tp pf5 usb_tn usb_tn usb_tn usb_tn pf6 usb_rp usb_rp usb_rp usb_rp pf7 usb_rxd usb_rxd usb_rxd usb_rxd pf8 usb_rn usb_rn usb_rn usb_rn pf15 tdm2a- tsync tdm2a- tsync tdm2a- tsync pos- tmod pf16 tdm2a- txd [ 0 ] tdm2a- txd [ 0 ] tdm2a- txd [ 0 ] pos- rmod pf17 tdm2a- rxd [ 0 ] tdm2a- rxd [ 0 ] tdm2a- rxd [ 0 ] pos- stp a pf18 tdm2a- rsync tdm2a- rsync tdm2a- rsync pos- reo p pf19 tdm1e- tsync tdm1e- tsync tdm1e- tsync pos- teop pf20 tdm1e- txd [ 0 ] tdm1e- txd [ 0 ] tdm1e- txd [ 0 ] pos- ter r pf21 tdm1e- rxd [ 0 ] tdm1e- rxd [ 0 ] tdm1e- rxd [ 0 ] pos- rer r pf22 tdm1e- rsync tdm1e- rsync tdm1e- rsync pos- rval pc8 ucc1-rxclk clk9 pc20 ucc1-gtxclk clk21 pc11 ucc1,3-in125 clk12 pc9 ucc3-rxclk clk10 pc25 ucc3-gtxclk clk26 pc3 ucc2-rxclk clk4 pc2 ucc2-gtxclk clk3 pc16 ucc2,4-in125 clk17 pc17 ucc4-rxclk clk18 pc24 ucc4-gtxclk clk25 pc15 rmii1-8 clk16 pc4 usb_clk clk5 pc18 upc-rxclk clk19 pc12 upc-txclk clk13 pc0 tdm-si1-tx-rx-a,b,c,d clk1 pc 22 tdm-si1-rx-tx- e,f,g,h clk23 pc 13 tdm-si2-rx-tx- a,b,c,d clk14 pc 26 tdm-si2-rx-tx- e,f,g,h clk27 pe27 spi1_spimosi spi1_spimosi pe28 spi1_spimiso spi1_spimiso pe29 spi1_spiclk spi1_spiclk pe30 spi_enable spi_enable pf9 uart1_sout uart1_sout pf10 uart1_cts_b uart1_cts_b pf11 uart1_rts_b uart1_rts_b pf12 uart1_sin uart1_sin pc 30 spi2- mdc pc 31 spi2- mdio
MPC8569E-MDS-PB hardware user guide, ver. 1.0 72 freescale semiconductor interfaces qe interface table 6-19 lists qe clock distributions for the application scenarios found in table 6-18, ?qe functions? table 6-19. qe clock distributions 6.8.3 riser connectors pb riser connectors, incl uding qe and local bus pins, provide fu ll access to both the mpc8569e qe and local bus signals. pq pi n 16tdm , 2rgmii , 1rmii , usb 11tdm , 8rmii , usb pc8 ucc1-rxclk clk9 pc20 ucc1-gtxclk clk21 pc11 ucc1,3-in125 clk12 pc9 ucc3-rxclk clk10 pc25 ucc3-gtxclk clk26 pc3 ucc2-rxclk clk4 pc2 ucc2-gtxclk clk3 pc16 ucc2,4-in125 clk17 pc17 ucc4-rxclk clk18 pc24 ucc4-gtxclk clk25 pc15 rmii1-8 clk16 pc18 upc-rxclk clk19 pc12 upc-txclk clk13 pc0 tdm-si1-tx-rx-a,b,c,d clk1 pc22 tdm-si1-rx-tx-e,f,g,h clk23 pc13 tdm-si2-rx-tx-a,b,c,d clk14 pc26 tdm-si2-rx-tx-e,f,g,h clk27
memory maps mpc8569e pb memory map hardware user guide, ver. 1.0 MPC8569E-MDS-PB freescale semiconductor 73 chapter 7: memory maps 7.1 mpc8569e pb memory map the memory map has not been finalized. access to mpc8569e memory slaves is cont rolled by the mpc8569e memory controller. table 7-1 is only a recommended memory map; it is a "soft" ma p device. users are free to move addresses around the map. table 7-1. MPC8569E-MDS-PB memory map (wit h nor flash as boot source ) address range block a llocation port size 00000000 - 1fffffff ddr3/ddr3 memory controller memc1 (512mb) 32 00000000 - 3fffffff memc1 (integrated mode) 1gb 64 20000000 - 3fffffff memc2 (512mb) 32 40000000 - 7fffffff reserved 1gb 80000000 - 9fffffff srio1 outbound window (512 mb) x4 lane a0000000 - bfffffff srio2 outbound window (512 mb) x4 lane c0000000 - dfffffff pex outbound window (512 mb) x4 lane e0000000 - e00fffff mpc8569 internal map int ernal memory register space (1 mb) 32 e0100000 - e03fffff reserved for future mpc8569 derivatives (3 mb) - e0400000 - e047ffff l2sram 1mb e0480000 - f7ffffff reserved 400mb f8000000 - f8007fff bcsr on cs1 altera (32kb) 8 f8008000 - f800ffff cs4 pib (32kb) 8 f8010000 - f8017fff cs5 pib (32kb) 8 fa018000 - ffffffff reserved 100mb fc000000 - fdffffff nand flash on cs3/ cs0 samsung: k9f5608u0d-pcb0 (32mb) 8 fe000000 - ffffffff nor flash on cs0/cs 3 spansion: s29gl256n11tfiv2o (32mb) 8
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