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may 1997 ML4411 * /ML4411a ** sensorless spindle motor controller the ML4411a includes a comparator on the p3 output to prevent cross-conduction. features back-emf commutation provides maximum torque for minimum ?pin-up?time for spindle motors accurate, jitter-free phase locked motor speed feedback output linear or pwm motor current control easy microcontroller interface for optimized start-up sequencing and speed control power fail detect circuit with delayed braking drives external n-channel fets and p-channel fets back-emf comparator detects motor rotation after power fail for fast re-lock after brownout * this product is obsolete ** this product is end of life as of august 1, 2000 general description the ML4411 provides complete commutation for delta or wye wound brushless dc (bldc) motors without the need for signals from hall effect sensors. this ic senses the back emf of the three motor windings (no neutral required) to determine the proper commutation phase angle using phase lock loop techniques. this technique will commutate virtually any 3-phase bldc motor and is insensitive to pwm noise and motor snubbing. the ML4411 is architecturally similar to the ml4410 but with improved braking and brown-out recovery circuitry. included in the ML4411 is the circuitry necessary for a hard disk drive microcontroller driven control loop. the ML4411 controls motor current with either a constant off-time pwm or linear current control driven by the microcontroller. braking and power fail are also included in the ML4411. the timing of the start-up sequencing is determined by the micro, allowing the system to be optimized for a wide range of motors and inertial loads. the ML4411 modulates the gates of external n-channel power mosfets to regulate the motor current. the ic drives p-channel mosfets directly. block diagram bldc motor power drivers gate drive logic and control back-emf sampler vco linear or pwm current control power fail detect rc c vco vco/tach out reset enable e/a brake dis pwr i cmd i limit pwr fail +5 vcc gnd c ota c os i sense c brk 3 n1-3 3 p1-3 vcc2 ph3 ph2 ph1 6 patented i ramp 20 14 15 16 21 18 26 8 28 27 17 19 25 22 23 24 4 7 12 13 6 1 rev. 1.0 10/10/2000
ML4411/ML4411a 2 rev. 1.0 10/10/2000 pin configuration 1 gnd signal and power ground 2 p1 drives the external p-channel transistor driving motor ph1 3 p2 drives the external p-channel transistor driving motor ph2 4v cc2 12v power and power for the braking function 5 p3 drives the external p-channel transistor driving motor ph3 6c ota compensation capacitor for linear motor current amplifier loop 7c brk capacitor which stores energy to charge n-channel mosfets for braking with power off. 8 dis pwr a logic 0 on this pin turns off the n and p outputs and causes the tach comparator output to appear on tach out 9-11 n1, n2 n3 drives the external n-channel mosfets for ph1, ph2, ph3 12 i sense motor current sense input 13 c os timing capacitor for fixed off-time pwm current control 14 c vco timing capacitor for vco 15 vco/tach logic output from vco or tach out comparator 16 reset input which holds vco off and sets the ic to the reset condition 17 pwr fail a ??output indicates 5v or 12v is under-voltage. this is an open collector output with a 4.5k ? pull-up to +5v 18 enable e/a a ??logic input enables the error amplifier and closes the back-emf feedback loop 19 +5v 5v power supply input 20 rc vco loop filter components 21 i ramp current into this pin sets the initial acceleration rate of the vco during start-up 22 ph1 motor terminal 1 23 ph2 motor terminal 2 24 ph3 motor terminal 3 25 v cc 12v power supply. terminal which is sensed for power fail 26 brake a ??activates the braking circuit 27 i limit sets the threshold for the pwm comparator 28 i cmd current command for linear current amplifier pin name function pin name function pin description ML4411 28-pin soic (s28w) gnd p1 p2 vcc2 p3 c ota c brk dis pwr n1 n2 n3 i sense c os c vco i cmd i limit brake vcc ph3 ph2 ph1 i ramp rc +5v enable e/a pwr fail reset vco/tach out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 top view
ML4411/ML4411a rev. 1.0 10/10/2000 3 electrical characteristics unless otherwise specified, t a = operating temperature range, v cc = v cc2 = 12v, r sense = 1 ? , c ota = c vco = 0.01 f, c os = 0.02 f parameter conditions min typ max units oscillator (vco) section (v pin16 = 5v) frequency vs. v pin 20 1v v pin20 10v 300 hz/v frequency v vco = 6v 1450 1800 2150 hz v vco = 0.5v 70 140 210 hz reset voltage at c vco mode = 0 125 250 mv sampling amplifier (note 1) v rc state r 125 250 mv i rc v pin18 = 0v, r ramp = 39k ? 70 100 130 a v pin18 = 5v, state a, v ph2 = 4v 30 50 90 a v pin18 = 5v, state a, v ph2 = 6v ?3 2 13 a v pin18 = 5v, state a, v ph2 = 8v ?0 ?0 ?0 a v pin21 r pin21 = 39k ? to +5v 1.0 1.1 1.20 v motor current control section i sense gain v pin27 = 5v, 0v v pin28 2.5v 4.5 5 5.5 v/v one shot off time 12 25 33 s i cmd transconductance gain 0.19 mmho i cmd , i lim bias current v in = 0 0 ?00 ?00 na power fail detection circuit 12v threshold 9.1 9.8 10.5 v hysteresis 150 mv 5v threshold 3.8 4.25 4.5 v hysteresis 70 mv logic inputs voltage high (v ih )2v voltage low (v il ) 0.8 v current high (i ih )v in = 2.7v ?0 1 10 a current low (i il )v in = 0.4v ?00 ?50 ?00 a absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied. supply voltage (pins 4, 25) ........................................ 14v output current (pins 2, 3, 5, 9,10,11) ................ 150ma logic inputs (pins 16, 17, 18, 25) ..................... ?.3 to 7v junction temperature ............................................. 150 c storage temperature range ..................... ?5 c to 150 c lead temperature (soldering 10 sec.) ..................... 150 c thermal resistance ( ja ) ...................................... 60 c/w operating conditions temperature range ....................................... 0 c to 70 c vcc voltage +12v (pin 25) ............................ 12v 10% +5v (pin 19) ................................................. 5v 10% i(ramp) current (pin 21) ................................ 0 to 100 a i control voltage range (pins 27, 28) ................. 0v to 7v
ML4411/ML4411a 4 rev. 1.0 10/10/2000 electrical characteristics (continued) parameter conditions min typ max units braking circuit (v pin17 = 0v) brake active threshold 0.8 1.2 1.6 v pin 26 bias current v pin26 = 0v 0.3 1 a n-channel leakage v cc , v cc2 = 0v 0 0.06 10 na v pin17 = 0v, v n = 4v c brk current v cc , v cc2 = 0v, v pin26 = 3v 20 85 a v pin7 = 6v outputs (i cmd = i limit = 2.5v) i p low v p = 0.8v 5 7 19.5 ma v p = 0.4v 2 4 ma v p high i p = ?0 av cc ?0.4 v p3 comparator threshold v cc2 ?1.6 v cc2 ?0.8 v v n high v pin12 = 0v v cc2 ?3.2 10 v cc ?1.2 v v n low i n = 1ma 0.2 0.7 v logic low (v ol )i out = 0.4ma 0.5 v vco/tach v oh i out = ?00 a 2.4 v power fail v oh i out = ?0 av pin19 ?0.2 v pin19 ?0.1 v pin19 v supply currents (n and p outputs open) 5v current 34ma v cc current 38 50 ma v cc2 current ML4411 2 3 ma v cc2 current ML4411a 2.6 3.75 ma note 1. for explanation of states, see figure 5 and table 1.
ML4411/ML4411a rev. 1.0 10/10/2000 5 maximum voltage at any ph input does not exceed vcc. neutral 0 60 120 180 240 0 300 figure 2. typical motor phase waveform with back-emf superimposed (ideal commutation) vco and phase detector calculations the vco should be set so that at the maximum frequency of operation (the running speed of the motor) the vco control voltage will be no higher than vcc min ?1v. the vco maximum frequency will be: f poles rpm max = 005 . where poles is the number of poles on the motor and rpm is the maximum motor speed in revolutions per functional description the ML4411 provides closed-loop commutation for 3-phase brushless motors. to accomplish this task, a vco, integrating back-emf sampling error amplifier and sequencer form a phase-locked loop, locking the vco to the back-emf of the motor. the ic also contains circuitry to control motor current with either linear or constant off- time pwm modes. braking and power fail detection functions are also provided on chip. the ML4411 is designed to drive external power transistors (n-channel sinking transistors and pnp sourcing transistors) directly. start-up sequencing and motor speed control are accomplished by a microcontroller. speed sensing is accomplished by monitoring the output of the vco, which will be a signal which is phased-locked to the commutation frequency of the motor. back-emf sensing and commutator the ML4411 contains a patented back-emf sensing circuit which samples the phase which is not energized (shaded area in figure 2) to determine whether to increase or decrease the commutator (vco) frequency. a late commutation causes the error amplifier to charge the filter (rc) on pin 20, increasing the vco input while early commutation causes pin 20 discharge. analog speed control loops can use pin 20 as a speed feedback voltage. the input impedance of the three ph inputs is about 8k ? to gnd. when operating with a higher voltage motor, the ph inputs should be divided down in voltage so that the figure 1. back emkf sensing block diagram neutral simulator a + b + c 6 a b c multiplexer r c1 c2 vco commutation logic sign changer b a ? + i(pin 21) + loop filter i rc = va ? vb 8k rc vco /tach out + ? dis pwr 8k 8k rotation sense
ML4411/ML4411a 6 rev. 1.0 10/10/2000 minute. the minimum vco gain derived from the specification table (using the minimum fvco at v vco = 6v) is: k c vco min vco () . = ? 242 10 6 assuming that the v vco(max) = 9.5v, then c f vco max = ? 95 242 10 6 .. or c poles rpm f vco = 460 024681012 3000 2500 2000 1500 1000 500 0 0.01 f 0.02 f frequency (hz) v vco (volts) figure 3. vco output frequency vs. v vco (pin 20) figure 4 shows the transfer function of the phase lock loop with the phase detector formed from the sampled phase through the gm amplifier with the loop filtered formed by r, c1, and c2. the impedance of the loop filter is zs cs s s rc lead lag () () () = + + 1 1 figure 4. back emf phase lock loop components where the lead and lag frequencies are set by: lead rc = 1 2 lag cc rc c = + 12 12 start-up sequencing when the motor is initially at rest, it is generating no back-emf. because a back-emf signal is required for closed loop commutation, the motor must be started ?pen-loop?until a velocity sufficient to generate some back-emf is attained (around 100 rpm). the following steps are a typical procedure for starting a motor which is at rest. step 1: the ic is held in reset (state r) with full power applied to the windings (see figure 6). this aligns the rotor to a position which is 30 (electrical) before the center of the first commutation state. step 2: reset is released, and a fixed current is input to pin 21 and appears as a current on pin 20, and will ramp the vco input voltage, accelerating the motor at a fixed rate. step 3: when the motor speed reaches about 100 rpm, the back emf loop can be closed by pulling pin 18 high. reset/ align p1, p3, n2 on open-loop (stepping) closed loop vco frequency 0 reset enable e/a figure 6. typical start-up sequence. using this technique, some reverse rotation is possible. the maximum amount of reverse rotation is 360/n, where n is the number of poles. for an 8 pole motor, 45 reverse rotation is possible. for quick recovery following a momentary power failure, the following steps can be taken: pin pin pin i limit step 16 18 21 i cmd 1 0 0 fixed i max 2 1 0 fixed i max 3110 i max table 2. start-up sequence. r c1 c2 vco ? + z rc rc f out k vco (hz/v) gm = 1.25 x 10 ? 4 sampled phase
ML4411/ML4411a rev. 1.0 10/10/2000 7 outputs input state n1 n2 n3 p1 p2 p3 sampling r or 0 off on off on off on n/a a off off on on off off ph2 b off off on off on off ph1 c on off off off on off ph3 d on off off off off on ph2 e off on off off off on ph1 f off on off on off off ph3 table 1. commutation states. r reset 0a b c d e f a 4.3 v c vco 2.3 v vco out state figure 5. commutation timing and sequencing. adjusting open loop step rate i ramp should be set so that the vcos frequency ramp during ?pen loop stepping?phase of motor starting is less than the motors acceleration rate. in other words, the motor must be able to keep up with the vcos ramp rate in open loop stepping mode. the vcos input voltage (v pin 20 ) ramp rate is given by: dv dt i cc vco ramp + 12 since fk v vco vco vco = k c vco max vco () = ? 410 6 then combining the 3 equations i ramp can be calculated from the desired maximum open loop stepping rate the motor can follow. i df dt ccc ramp vco vco < + ? () 12 6 410 step 1a: the ic is held in reset (state r) with i cmd low and dis pwr low. the micro processor monitors the vco/tach out pin to determine if a signal is present. if a signal is present, the frequency is determined (by measuring the period). if a signal is not present, proceed to the routine described above for starting a motor which is a rest. step 2a: release reset and dis pwr. apply a current to pin 21 and monitor the vco/tach out pin for vco frequency. step 3a: when the vco frequency approaches 6 x the motor frequency (or where the motor frequency has decelerated to by coasting during the time the vco frequency was ramping up) the back emf loop can be closed by pulling pin 18 high and motor current brought up with i cmd or i limit .
ML4411/ML4411a 8 rev. 1.0 10/10/2000 the motor will start more consistently and tolerate a wider variation in open loop step rate if there is some damping on the motor (such as head drag) during the open loop modes. the tolerance of the open loop step vco acceleration df dt vco ? ? ? ? ? ? depends on the tolerances of k vco , i ramp , c1, c2, and c vco . for more optimum spin up times, these variables can be digitally ?alibrated?out by the microprocessor using the following procedure: 1. reset the ic by holding pin 16 low for at least 5 s. 2. go into open loop step mode with no current on the motor and measure the difference between the first two complete vco periods with the pwm signal at 50% duty cycle: enable e/a = (see below) i cmd = 0v pwm out = 50% i(ramp) vco/tach out pwm out in microp ML4411 figure 7. auto-calibration of open-loop step rate. 3. compute a correction factor to adjust i ramp current by changing the pwm duty cycle from the micro (d.c.) dc new f desired f measured vco vco ..( ) % () () = 50 ? ? 4. use new computed duty cycle for open loop stepping mode and proceed with a normal start-up sequence. if this auto calibration is used enable e/a can be tied permanently high, eliminating a line from the micro. since there is offset associated with the phase detector error amp (e/a), more current than is being injected by i ramp may be taken out of pin 20 if the offset is positive (into pin 20) if the error amp were enabled during the open loop stepping mode. in that case, v vco would not rise and the motor would not step properly. the effect of e/a offset can also be canceled out by the auto calibration algorithm described above allowing the e/a to be permanently enabled. a sc v ota = ? 1 875 10 4 . ? pwm and linear current control to facilitate speed control, the ML4411 includes two current control loops ?linear and pwm (figure 9). the linear control loop senses the motor current on the i sense terminal through r sense . an internal current sense amplifiers (a2) output modulates the gates of the 3 n- channel mosfets when ota out is tied to ota in, or can modulate a single mosfet gate tied to ota out. when operated in this mode, ota in is tied to 12v, and n1-n3 are saturated switches. this method produces the lowest current ripple at the expense of an extra mosfet. the linear current control modulates the gates of the external mosfet drivers. amplifier a2 is a transconductance amplifier which amplifies the difference between i cmd and i sense . the transconductance gain of a2 is: g m = ? 1 875 10 4 . the current loop is compensated by c ota which forms a pole given by p ota c = ? 9 375 10 4 . this time constant should be fast enough so that the current loop settles in less than 10% of t vco at the highest motor speed to avoid torque ripple to v th mismatch of the n-channel mosfets. the i sense input pin should be kept below 1v. if i sense goes above 1v, a bias current of about ?00 a will flow out of pin 12 and the n outputs will be inhibited. bringing i sense below 0.7v removes the bias current to its normal level. for this reason, the noise filter resistor on the i sense pin (1k ? on figure 10) should be less than 1.5k ? . the noise filter time constant should be great enough to filter the leading edge current spike when the n-fets turn on but small enough to avoid excessive phase shift in the i sense signal. output drivers the motors source drivers (p1 thru p3) are open-collector npns with internal 16k ? pull-up resistors. n3is inhibited until p3 is within 1.4v (typ) of v cc2 on the ML4411a. drivers n1 through n3 are totem-pole outputs capable of sourcing and sinking 10ma. switching noise in the external mosfets can be reduced by adding resistance in series with the gates.
ML4411/ML4411a rev. 1.0 10/10/2000 9 braking as shown in figure 9, the braking circuit pulls the n- channel mosfet gates high when brake falls below a 1.4v threshold. after a power failure, c dly is discharged slowly through r dly providing a delay for retract to occur before the braking circuit is activated. the n-channel buffer (b1) tri-states when the brake pin reaches 2.1v to ensure that no charge from c brk is lost through the pull- down transistor in b1. to brake the motor with external signals, first disable power by pulling pin 8 low, then pull pin 26 below 1.4v using an open drain (or diode isolated) output. the bias current for the braking circuits comes from vcc2. when the n-channel mosfets turn on, no additional power is generated for vcc2 (motor back-emf rectified through out the mosfet body diodes). after vcc2 drops below 4v, q2 turns off. continued braking relies on the c gs of the n-channel mosfets to sustain the mosfet gate enhancement voltage. 0 0.01 0.02 0.03 0.04 0.05 60 50 40 30 20 10 0 t off (s) c os figure 8. i limit output off-time vs. c os . p3 only ? + vcc2 ? 3v comm. logic 26 8 27 28 12 r dly brake c dly 1.4v ? + a4 a6 vcc2 dis pwr commutation logic uvlo i limit i cmd i sense ? + a3 ? + a2 a1 a v = 5 q one shot q2 vcc vcc2 7 p1 . . . p3 n1 . . . n3 r sense vin 13 6 c os c ota c brk b1 vcc 2.1v ? + a5 vcc2 dis pwr vcc2 16k power fail 4.5k 17 +5 uvlo q1 1k tri- st. figure 9. current control, output drive and braking circuits.
ML4411/ML4411a 10 rev. 1.0 10/10/2000 applications figure 10 shows a typical application of the ML4411 in a hard disk drive spindle control. although the timing necessary to start the motor in most applications would be generated by a microcontroller, fig. 11 shows a simple ?ne shot?start-up timing approach. speed control can be accomplished either by: 1. sensing the vco out frequency with a microcontroller and adjusting i cmd via an analog output form the micro (pwm dac). 2. using analog circuitry for speed control. (fig. 12). output stage hints in the circuit in figure 10, q1, q2, and q3 are irfr9024 or equivalent. q4, q5, and q6 are irfr024 or equivalent. new mosfet packaging technology such as the little foot ? series may decrease the pc board space. these packages, however have much lower thermal inertia and dissipation capabilities than the larger packages, and care should be taken not to exceed their rated current and junction temperature. since the output section in a full bridge application consists of three half-h switches, cross-conduction can occur. cross-conduction is the condition where an n-fet and p-fet in the same phase of the bridge conduct simultaneously. this could happen under two conditions (see figure 13): i cmd i limit brake vcc ph3 ph2 ph1 i ramp rc +5v enable e/a pwr fail reset vco/tach out gnd p1 p2 vcc2 p3 c ota c brk dis pwr n1 n2 n3 i sense c os c vco i command +5 1m +12 +5 510k 0.22 +5 5k 5k 0.5 q6 q3 0.1 10 q2 q5 q1 q4 vcc2 1n5819 0.1 10 +12v to vcc 510 0.01 0.22 0.02 0.01 enable error amp reset (from micro) power fail to micro vco out disable power 100pf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +12 510 510 1k 1k 1k figure 10. ML4411 typical application
ML4411/ML4411a rev. 1.0 10/10/2000 11 +5v d1 to ML4411 pin 16 r2 r1 ic1 ic1 ic1 to ML4411 pin 18 d2 c2 1/6 1/6 1/6 ML4411 pin 17 c1 figure 11. analog start-up circuit to ML4411 pin 28 r3 ? + a1 ? + a1 c3 r4 +12v r5 r6 to ML4411 pin 20 symbol value a1 lm358 ic1 74hc14 d1, d2 in4148 r1 1m ? r2 1m ? r3 100k ? symbol value r4 100k ? r5 50k ? r6 50k ? c1 3.3 f c2 3.3 f c3 0.47 f figure 12. analog speed control in condition 2 above, the p-channel mosfet is pulled up inside the ML4411 with a 16k ? resistor. if the current through c(cgp) is greater than v th 16k when the n-fet turns on, the p-fet could turn on simultaneously, causing cross-conduction. adding r1 as shown in figure 14 eliminates this. the size of r1 will depend on the fall time of the phase voltage, and the size of the c(dgp). d1 may be needed for high power applications to limit the negative current pulled (through c(dgn)) out of the substrate diode in the ML4411 when p-fet turns off. p n d1 c(dgn) c(dgp) rg(p) rg(n) r1 vcc2 figure 14. causes of cross-conduction adding a series damping resistor to the n-fet gate (rgn) will slow the fall time. the damping resistor should be low enough to: avoid turning on the n-channel gate when the pnp turns on via the same mechanism outlined in condition 2 above not severely increase the switching losses in the n-fet unipolar operation unipolar mode offers the potential advantage of lower motor drive cost by only requiring the use of 3 transistors to drive the motor. the ML4411 will operate in unipolar mode (figure 15) provided the following precautions are taken: 1. the ic supplies should not exceed 12v + 10%. 2. the phase pins on the ic should not exceed the supply voltage. vcc2 1k p 5 4 inhibit n3 q2 + ? a6 ML4411a only p3 16k figure 13. alternate cross-conduction prevention for ML4411a 1. when transitioning from mode 0 to mode a (see table 1) p3 goes from on to off at the same time n3 goes from off to on. if the p3 turns off slowly and n3 turns on quickly, cross-conduction may occur. this condition has been prevented inside the ic on the ML4411a through the addition of comparator a6 on the p3 output (figure 9). this comparator may cause an oscillation when the n3 switches on due to the capacitive coupling effect described below pulling the p3 pin below vcc2-1.4v. to avoid this, use the circuit in figure 13. 2. when the mosfet in the same phase switches on gate current flows due to capacitive coupling of current through the mosfets drain to gate capacitance. this could cause the device that was off to be turned on.
ML4411/ML4411a 12 rev. 1.0 10/10/2000 i cmd i limit brake vcc ph3 ph2 ph1 i ramp rc +5v enable e/a pwr fail reset vco/tach out gnd p1 p2 vcc2 p3 c ota c brk dis pwr n1 n2 n3 i sense c os c vco 0.01 1.2k 0.5 ? +v +v 10k 10k 10k +5 +12 +5 +5 +12 + ? +12 3.3k 10k 1m +5 +5 1m 2.2 c dly +12 0.01 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.02 figure 15. ML4411 unipolar drive application in unipolar operation, the motor? windings must be allowed to drive freely to: v (max) = v supply (max) + v emf (max) therefore, there can be no diodes to clamp the inductive energy to v supply . this energy must be clamped, however, to avoid an over-voltage condition on the mosfets and other components. typically, a v clamp voltage is created to provide the clamping voltage. the inductive energy may either be dissipated (figure 16) or alternately efficiently regenerated back to the system supply (figure 17). the circuit in figure 15 is designed to minimize the external components necessary, at some compromise to performance. the 3 resistors from the motor phase windings to the ph inputs work with the ML4411? 8k ? internal resistance to ground to divide the motor? phase voltage down, providing input signals that do not exceed 12v. v clamp = +24v 12v battery c1 0.1 +12v to vcc and vcc2 +12v 5v reg 12v ldo 0.1 1000 10 0.1 +5v figure 16. dissipative clamping technique this circuit uses analog speed regulation. the 1m ? resistor from pin 20 to the speed regulation op amp provides the function of injecting current into the vco loop filter for the open loop stepping phase of start-up operation. the ?ne shot?circuitry to time the reset is replaced by a diode and rc delay from the rising edge or the powerfail signal. the error amplifier is left enabled continuously since at low speeds its current contribution is negligible. the current injected into the loop filter must be greater than the leakage current from the phase detector amplifier for the motor to start reliably. v clamp = +24v 5v reg 12v ldo 0.1 d1 l1 12v battery 50% duty cycle figure 17. non-dissipative clamping technique
ML4411/ML4411a rev. 1.0 10/10/2000 13 q2 +v q3 p ML4411 +12v q1 figure 19. high voltage translation using ?omposite pnp power transistor q2 +v p ML4411 q3 q1 figure 20. high voltage translation with npn darlington figure 18. high voltage translation using pnp power transistor q1 +v q3 p ML4411 +12v higher voltage motor drive to drive a higher voltage motor, the same precautions regarding ML4411 voltage limitations as were outlined for unipolar drive above should be followed. figures 14?6 provide several methods of translating the ML4411? p outputs to drive a higher voltage.
ML4411/ML4411a 14 rev. 1.0 10/10/2000 ordering information part number temperature range package ML4411cs (obsolete) 0 c to 70 c 28-pin wide soic (s28w) ML4411acs (end of life) 0 c to 70 c 28-pin wide soic (s28w) seating plane 0.291 - 0.301 (7.39 - 7.65) pin 1 id 0.398 - 0.412 (10.11 - 10.47) 0.699 - 0.713 (17.75 - 18.11) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.022 - 0.042 (0.56 - 1.07) 0.095 - 0.107 (2.41 - 2.72) 0.005 - 0.013 (0.13 - 0.33) 0.090 - 0.094 (2.28 - 2.39) 28 0.009 - 0.013 (0.22 - 0.33) 0 o - 8 o 1 0.024 - 0.034 (0.61 - 0.86) (4 places) package: s28 28-pin soic physical dimensions inches (millimeters ) life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ?2000 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

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