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ds05-11408-3e fujitsu semiconductor data sheet memory cmos 2 512 k 16 bit / 2 256 k 32 bit single data rate i / f fcram tm (extended temp. version) consumer/embedded application specific memory for sip mb81es171625/173225-15-x n description the fujitsu mb81es171625/173225 is a fast cycle random access memory (fcram*) containing 16,777,216 bit memory cells accessible in a 2 512k 16 bit / 2 256k 32 bit format. the mb81es171625/173225 features a fully synchronous operation referenced to a positive edge clock same as that of sdram operation, whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexist- ence. the mb81es171625/173225 is utilized using a fujitsu advanced fcram core technology and designed for low power consumption and low voltage operation than regular synchronous dram (sdram). the mb81es171625/173225 is dedicated for sip (system in a package), and ideally suited for various embedded/ consumer applications including digital avs, and image processing where a large band width and low power consumption memory is needed. * : fcram is a trademark of fujitsu limited, japan. n product lineup parameter mb81es171625/173225-15-x clock frequency (max) 66.7 mhz burst mode cycle time (min) cl = 130 ns cl = 215 ns access time from clock (max) cl = 1 27 ns cl = 2 12 ns xras cycle time (min) 75 ns operating current (max) (i dd1 ) 30 ma power down mode current (max) (i dd2p ) 1 ma self-refresh current (max) (i dd6 ) 5 ma
mb81es171625/173225-15-x 2 n features ? fcram core with single data rate sdram interface ? 512 k word 16 bit 2 bank or 256 k word 32 bit 2 bank organization ? single + 1.8 v supply 0.15 v tolerance ?cmos i/o interface ? programmable burst type, burst length, and cas latency burst type : sequential mode, interleave mode burst length : 1, 2, 4, 8, full column (64 : 16 bit, 32 : 32 bit) cas latency mb81es171625/173225-15-x cl = 1 (min t ck = 30 ns, max 33.3 mhz) cl = 2 (min t ck = 15 ns, max 66.7 mhz) ? 2 k refresh cycles every 4 ms ? auto- and self-refresh ? cke power down mode ? output enable and input data mask ? burst stop command at full column burst ? burst read/write ? 66.7 mhz clock frequency
mb81es171625/173225-15-x 3 n pad layout mb81es171625 pa d dse bme tbst dqc - - - - - - - - - - v ss v dd v ss v dd dq 8 dq 9 dq 10 dq 11 v ddq v ssq dq 12 dq 13 dq 14 dq 15 - dqm 1 a 12 a 11 ba a 10 /ap a 9 a 8 a 7 a 6 clk cke v ssq s16 v ddq xcs xras xcas xwe a 5 a 4 a 3 a 2 a 1 a 0 dqm 0 - dq 7 dq 6 dq 5 dq 4 v ssq v ddq dq 3 dq 2 dq 1 dq 0 v dd v ss v dd v ss - - - - - - - - - - - - - - - pad no.84 pa d n o. 1
mb81es171625/173225-15-x 4 mb81es173225 pa d dse bme tbst dqc dq 16 dq 17 dq 18 dq 19 v ddq v ssq dq 20 dq 21 dq 22 dq 23 v ss v dd v ss v dd dq 24 dq 25 dq 26 dq 27 v ddq v ssq dq 28 dq 29 dq 30 dq 31 dqm 2 dqm 3 a 12 a 11 ba a 10 /ap a 9 a 8 a 7 a 6 clk cke v ssq s32 v ddq xcs xras xcas xwe a 5 a 4 a 3 a 2 a 1 a 0 dqm 1 dqm 0 dq 15 dq 14 dq 13 dq 12 v ssq v ddq dq 11 dq 10 dq 9 dq 8 v dd v ss v dd v ss dq 7 dq 6 dq 5 dq 4 v ssq v ddq dq 3 dq 2 dq 1 dq 0 - - - - - pad no.84 pa d n o. 1
mb81es171625/173225-15-x 5 n pad descriptions mb81es171625 mb81es173225 symbol function vdd, vddq supply voltage vss, vssq ground dq 15 to dq 0 data i/o dqm 1 to dqm 0 dq mask xwe write enable xcas column address strobe xras row address strobe xcs chip select ba bank select ap auto precharge enable a 12 to a 0 address input row : a 12 to a 0 column : a 5 to a 0 cke clock enable clk clock input tbst bist control bme burn in enable dse disable dqc bist output s16 16 select symbol function vdd, vddq supply voltage vss, vssq ground dq 31 to dq 0 data i/o dqm 3 to dqm 0 dq mask xwe write enable xcas column address strobe xras row address strobe xcs chip select ba bank select ap auto precharge enable a 12 to a 0 address input row : a 12 to a 0 column : a 4 to a 0 cke clock enable clk clock input tbst bist control bme burn in enable dse disable dqc bist output s32 32 select
mb81es171625/173225-15-x 6 n block diagram mb81es171625 xras xcas xwe a 12 ,a 11 ,a 9 to a 0 , a 10 /ap i/o vdd vss/vssq vddq xras xcas dqm 1 to dqm 0 dq 15 to dq 0 ba xwe clk bme xcs s16 dse cke tbst dqc 16 6 13 bank-1 command decoder clock buffer address buffer/ register & bank select i/o data buffer/ register mode register fcram core (8,192 64 16) col. addr. bank-0 row addr. to each block control signal latch bist column address counter
mb81es171625/173225-15-x 7 mb81es173225 xras xcas xwe a 12 ,a 11 ,a 9 to a 0 , a 10 /ap i/o vdd vss/vssq vddq clk bme xcs xras xcas s32 xwe dse cke dqm 3 to dqm 0 dq 31 to dq 0 ba tbst dqc 32 5 13 bank-1 command decoder clock buffer address buffer/ register & bank select i/o data buffer/ register mode register fcram core (8,192 32 32) col. addr. bank-0 row addr. to each block control signal latch bist column address counter
mb81es171625/173225-15-x 8 n functional truth table 1. command truth table v = valid, l = logic low, h = logic high, x = either l or h, n = state at current clock cycle, n - 1 = state at 1 clock cycle before n. *1: nop and desl commands have the same effect on the part. at desl command (xcs = h) , all input signal are ignored, but hold the internal state. nop command (xcs = l, xras = xcas = xwe = h) is no effect on device operation and the internal state continue. *2: bst command is effective on every burst length. (bl = 1, 2, 4, 8, full column) *3: read, reada, writ and writa commands should be issued only after the corresponding bank has been activated (actv command) . refer to n state diagram. *4: actv command should be issued only after the corresponding bank has been precharged (pre or pall command) . *5: required after power up. refer to 17. power-up- initialization in n functional description. *6: mrs command should be issued only after all banks have been precharged (pre or pall command) and dq is in high-z. refer to n state diagram. notes: all commands assumes no csus command on previous rising edge of clock. all commands are assumed to be valid state transitions. all inputs are latched on the rising edge of the clock. tbst,bme and dse should be held low. s16 should be held v ih , and s32 should be held v il . function com- mand cke xcs xras xcas xwe ba a 10 / ap a 12 to a 6 a5 a 4 to a 0 n-1 n device deselect * 1 desl h x h x x x x x x x x no operation * 1 nop h x l h h h x x x x x burst stop* 2 bst h x l h h l x x x x x read * 3 x16 read hx l h l h v l x v v x32 h x l h l h v l x x v read with auto-precharge * 3 x16 reada hx l h l h v h x v v x32 h x l h l h v h x x v write * 3 x16 writ hx l h l l v l x v v x32 h x l h l l v l x x v write with auto-precharge * 3 x16 writa hx l h l l v h x v v x32 h x l h l l v h x x v bank active * 4 actv h x l l h h v v v v v precharge single bank * 5 pre h x l l h l v l x x x precharge all banks * 5 pall h x l l h l x h x x x mode register set * 5, * 6 mrs h x l l l l l l v v v
mb81es171625/173225-15-x 9 2. dqm truth table v = valid, l = logic low, h = logic high, x = either l or h, n = state at current clock cycle, n - 1 = state at 1 clock cycle before n. notes : mb81es171625; dqm 0 and dqm 1 control dq 7 to dq 0 and dq 15 to dq 8 , respectively. mb81es173225; dqm 0 , dqm 1 , dqm 2 and dqm 3 control dq 7 to dq 0 , dq 15 to dq 8 , dq 23 to dq 16 , and dq 31 to dq 24 , respectively. all commands assume no csus command on previous rising edge of clock. all commands are assumed to be valid state transition. all inputs are latched on the rising edge of clock. tbst, bme and dse should be held low. s16 should be held v ih , and s32 should be held v il . 3. cke truth table v = valid, l = logic low, h = logic high, x = either l or h, n = state at current clock cycle, n - 1 = state at 1 clock cycle before n. *1 : csus command requires that at least one bank is active. refer to n state diagram. *2 : ref and self commands should be issued only after all banks have been precharged (pre or pall command). refer to n state diagram. *3 : self and pd commands should be issued only after the last read data have been appeared on dq. *4 : cke should be held high during t refc . notes: tbst,bme and dse should be held low. s16 should be held v ih , and s32 should be held v il . all commands assume no csus command on previous rising edge of clock. all commands assumed to be valid state transition. all inputs are latched on the rising edge of clock. function command cke dqm n-1 n data input/output enable enbl h x l data input/output disable mask h x h current state function com- mand cke xcs xras xcas xwe ba a 10 / ap a 12 , a 11 , a 9 to a 0 n-1 n bank active clock suspend mode entry * 1 csus h l x x x x x x x any (except idle) clock suspend continue * 1 ? ll x x x x x x x clock suspend clock suspend mode exit ? lh x x x x x x x idle auto-refresh command * 2 ref h h l l l h x x x idle self-refresh entry * 2, * 3 self h l l l l h x x x self refresh self-refresh exit * 4 selfx lh l h h h x x x lh h x x x x x x idle power down entry * 3 pd hl l h h h x x x hl h x x x x x x power down power down exit ? lh l h h h x x x lh h x x x x x x
mb81es171625/173225-15-x 10 4. operation command table (applicable to single bank) (continued) current state xcs xras xcas xwe addr command function idle h x x x x desl nop lh hh x nop l h h l x bst nop * 1 l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa l l h h ba, ra actv bank active after t rcd l l h l ba, ap pre nop l l h l ap pall nop * 1 l l l h x ref/self auto-refresh or self-refresh * 3, * 5 l l l l mode mrs mode register set (idle after t rsc ) * 3, * 6 bank active h x x x x desl nop lh hh x nop l h h l x bst l h l h ba, ca, ap read/reada begin read; determine ap l h l l ba, ca, ap writ/writa begin write; determine ap l l h h ba, ra actv illegal * 2 l l h l ba, ap pre precharge l l h l ap pall precharge * 1 l l l h x ref/self illegal l l l l mode mrs read h x x x x desl continue burst to end ? bank active lh hh x nop l h h l x bst burst stop ? bank active l h l h ba, ca, ap read/reada terminate burst, new read; determine ap l h l l ba, ca, ap writ/writa terminate burst, start write; determine ap * 4 l l h h ba, ra actv illegal * 2 l l h l ba, ap pre terminate burst, precharge ? idle l l h l ap pall terminate burst, precharge ? idle * 1 l l l h x ref/self illegal l l l l mode mrs
mb81es171625/173225-15-x 11 (continued) current state xcs xras xcas xwe addr command function write hxxx x desl continue burst to end ? bank active lh h h x nop l h h l x bst burst stop ? bank active l h l h ba, ca, ap read/reada terminate burst, start read; determine ap * 4 l h l l ba, ca, ap writ/writa terminate burst, new write; determine ap l l h h ba, ra actv illegal * 2 l l h l ba, ap pre terminate burst, precharge ? idle l l h l ap pall terminate burst, precharge ? idle * 1 l l l h x ref/self illegal llll mode mrs read with auto- precharge hxxx x desl continue burst to end ? precharge ? idle lh h h x nop l h h l x bst illegal l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa l l h h ba, ra actv l l h l ba, ap pre l l h l ap pall illegal l l l h x ref/self llll mode mrs write with auto- precharge hxxx x desl continue burst to end ? precharge ? idle lh h h x nop l h h l x bst illegal l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa l l h h ba, ra actv l l h l ba, ap pre l l h l ap pall illegal l l l h x ref/self llll mode mrs
mb81es171625/173225-15-x 12 (continued) current state xcs xras xcas xwe addr command function precharging h x x x x desl idle after t rp lh h h x nop lh h l x bst l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa ll h hba, ra actv l l h l ba, ap pre nop * 7 l l h l ap pall nop * 1 ll l h x ref/self illegal ll l l mode mrs bank activating h x x x x desl bank active after t rcd lh h h x nop l h h l x bst bank active after t rcd * 1 l h l h ba, ca, ap read/reada illegal * 2 l h l l ba, ca, ap writ/writa ll h hba, ra actv l l h l ba, ap pre l l h l ap pall illegal ll l h x ref/self ll l l mode mrs refreshing h x x x x desl idle after t refc lh h h x nop lh h l x bst illegal lh l x x read/reada/ writ/writa ll h x x actv/ pre/pall ll l x x ref/self/ mrs
mb81es171625/173225-15-x 13 (continued) abbreviations l = logic low, h = logic high, x = either l or h ra = row address ba = bank address ca = column address ap = auto precharge *1: entry may affect other bank. *2: illegal to the bank in specified state; entry may be legal to the bank specified by ba, depending on the state of that bank. *3: illegal if any bank is not idle. *4: must satisfy bus contention, bus turn around, and/or write recovery requirements. refer to 11. read interrupted by write (example @ cl = 2, bl = 4) and 12. write to read timing (example @ cl = 1, bl = 4) in n timing diagrams. *5: self command should be issued only after the last read data has been appeared on dq. *6: mrs command should be issued only when all dq are in high-z. *7: nop in precharging or idle state. pre may affect to the bank specified ba and ap. notes: tbst,bme and dse should be held low. s16 should be held v ih , and s32 should be held v il . all entries in 4. operation command table assume that cke was high during the proceeding clock cycle and the current clock cycle. illegal means that the device operation and/or data-integrity are not guaranteed. if used, power up sequence will be asserted after power shut down. all commands assume no csus command on previous rising edge of clock. all commands are assumed to be valid state transitions. all inputs are latched on the rising edge of the clock. current state xcs xras xcas xwe addr command function mode register setting hxxx x desl idle after t rsc lhhh x nop l h h l x bst illegal lhlx x read/reada/ writ/writa llxx x actv/pre/ pall/ref/self/ mrs
mb81es171625/173225-15-x 14 5. command truth table for cke (continued) current state cke xcs xras xcas xwe addr function (n-1) (n) self- refresh h x x x x x x invalid lhhx x x x exit self-refresh (self-refresh recovery ? idle after t refc ) lhlh h h x lhlh h l x illegal lhlh l x x lhl l x x x l l x x x x x maintain self-refresh self- refresh recovery l x x x x x x invalid hhh x x x x idle after t refc hhl h h h x hhl h h l x illegal hhl h l x x hhl l x x x h l x x x x x illegal * 1 power down h x x x x x x invalid lhhx x x x exit power down mode ? idle lhlh h h x l l x x x x x maintain power down mode lhl l x x x illegal lhlh l x x lhlh h l x all banks idle hhh x x x v refer to 4. operation command table. hhl h x x v hhl l h x v h h l l l h x auto-refresh h h l l l l v refer to 4. operation command table. hlhx x x x power down hllh h h x hllh h l x illegal hllh l x x hll l h x x h l l l l h x self-refresh * 2 h l l l l l x illegal l x x x x x x invalid
mb81es171625/173225-15-x 15 (continued) v = valid, l = logic low, h = logic high, x = either l or h *1: cke should be held high for t refc period. *2: self command should be issued only after the last data has been appeared on dq. notes: tbst,bme and dse should be held low. s16 should be held v ih , and s32 should be held v il . all entries in command truth table for cke are specified at cke (n) state and cke input from cke (n - 1) to cke (n) state must satisfy the corresponding setup and hold time for cke. current state cke xcs xras xcas xwe addr function (n-1) (n) bank active bank activating read/write h h x x x x x refer to 4. operation command table. h l x x x x x begin clock suspend next cycle lxx x x x x invalid clock suspend hxx x x x x l h x x x x x exit clock suspend next cycle l l x x x x x maintain clock suspend any state other than listed above l x x x x x x invalid h h x x x x x refer to 4. operation command table. h l x x x x x illegal
mb81es171625/173225-15-x 16 n functional description 1. sdr i/f fcram basic function three major differences between sdr i/f fcrams and conventional drams are : synchronized operation, burst mode, and mode register. the synchronized operation is the fundamental difference. sdr i/f fcram uses a clock input for synchroni- zation, while dram is basically asynchronous memory although it has been using two clocks, xras and xcas. each operation of dram is determined by their timing phase differences while each operation of sdr i/f fcram is determined by commands and all operations are referenced to a rising edge of a clock. the burst mode is a very high speed access mode utilizing an internal column address generator. once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. the mode registe r is to configure sdr i/f fcram operation and function into desired system conditions. n mode register table shows how sdr i/f fcram can be configured for system requirements by mode register programming. the program to the mode resister should be excuted after all banks are precharged. 2. fcram tm mb81es171625/173225 utilizes fcram core technology. fcram is an acronym for fast cycle random access memory and provides very fast random cycle time, low latency and low power consumption than regular drams. 3. clock (clk) and clock enable (cke) all input and output signals of sdr i/f fcram use register type buffers. clk is used as a trigger for the register and internal burst counter increment. all inputs are latched by a rising edge of clk. all outputs are validated by a rising edge of clk. cke is a high active clock enable signal. when cke = low is latched at a clock input during active cycle, the next clock will be internally masked. during idle state (all banks have been precharged) , the power down mode (standby) is entered with cke = low and this will make extremely low standby current. 4. chip select (xcs) xcs enables all command inputs, xras, xcas, xwe and address inputs. when xcs is high, command signals are negated but internal operations such as a burst cycle will not be suspended. if such a control isnt needed, xcs can be tied to ground level. 5. command input ( xras , xcas and xwe) unlike a conventional dram, xras, xcas and xwe do not directly imply sdr i/f fcram operations, such as row address strobe by xras. instead, each combination of xras, xcas, and xwe input in conjunction with xcs input at the rising edge of the clk determines sdr i/f fcram operations. refer to n functional truth table. 6. address input (a 12 to a 0 ) address input selects an arbitrary location of each memory cell matrix, 524,288 ( 16 bit) or 262,144 ( 32 bit) . a total of 19 ( 16 bit) or 18 ( 32 bit) address input signals are required to decode 13 bit row addresses and 6 bit ( 16 bit) or 5 bit ( 32 bit) column addresses matrix. sdr i/f fcram adopts an address multiplexer in order to reduce the pin count of the address line. at a bank active command (actv) , 13 bit row addresses are initially latched and the remainder of 6 bit ( 16 bit) or 5 bit ( 32 bit) column addresses are then latched by a column address strobe command of either a read command (read or reada) or a write command (writ or writa) . a 10 selects read or reada, writ or writa and pre or pall.
mb81es171625/173225-15-x 17 7. bank select (ba) this sdr i/f fcram has two banks. bank selection by ba occurs at bank active command (actv) followed by read (read or reada) , write (writ or writa) , and precharge commands (pre or pall) . 8. data inputs and outputs (dq 15 to dq 0 /dq 31 to dq 0 ) input data is latched and written into the memory at the clock following the write command input. data output is obtained by the following conditions followed by a read command input : t rac ; from the bank active command when t rcd (min) is satisfied. (this parameter is reference only.) t cac ; from the read command when t rcd is greater than t rcd (min) at cl = 1. t ac ; from the rising edge of clock after t rac and t cac . the polarity of the output data is identical to that of input data. data is valid between access time (determined by the three conditions above) and the next positive clock edge (t oh ) . refer to n ac characteristics. 9. data i/o mask (dqm 1 to dqm 0 /dqm 3 to dqm 0 ) dqm is an active high enable input and has an output disable and input mask function. during burst cycle and when dqm = high is latched by a clock, input is masked at the same clock and output will be masked at cl later while internal burst counter will increment by one or will go to the next stage depending on the burst type. 10. burst mode operation the burst mode provides faster memory access. the burst mode is implemented by keeping the same row address and by automatically strobing column address. access time and cycle time of burst mode is specified as t cac /t ac and t ck , respectively. the internal column address counter operation is determined by a mode register which defines burst type and the burst count length of 1, 2, 4, 8 bits of boundary or full column. in order to terminate or move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required : (1) burst type the burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. the sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns + 1 to the previous (or initial) address until reaching the end of boundary address and then wraps around to the least significant address ( = 0) . the interleave mode is a scrambled decoding scheme for a 0 through a 2 . if the first access of column address is even (0) , the next address will be odd (1) , or vice-versa. (2) burst mode termination and method of next stage set current stage next stage method (assert the following command) burst read burst read read command burst read burst write 1st step mask command (normally 3 clock cycles) 2nd step write command after l owd burst write burst write write command burst write burst read read command burst read precharge precharge command burst write precharge precharge command
mb81es171625/173225-15-x 18 (3) counter operation of sequential mode and lnterleave mode 11. full column burst and burst stop command (bst) the full column burst is an option of burst length and available only at sequential mode of burst type. this full column burst mode is repeatedly access to the same row. if burst mode reaches the end of column address, then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read (read) /write (writ) , precharge (pre) , or burst stop (bst) commands. the selection of auto-precharge option is illegal during the full column burst operation. bst command is applicable to terminate the burst operation. if bst command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to bank active. when a read mode is interrupted by bst command, the output will be in high-z. for the detailed rule, please refer to 8. read interrupted by burst stop (example @ bl = full column) in n timing diagrams. when a write mode is interrupted by bst command, the data to be applied at the same time with bst command will be ignored. 12. precharge and precharge option (pre, pall) sdr i/f fcram memory core is the same as a conventional drams, requiring precharge and refresh opera- tions. precharge rewrites the bit line and reset the internal row address line and is executed by the precharge command (pre) . with the precharge command, sdr i/f fcram will automatically be in standby state after precharge time (t rp ) . the precharged bank is selected by combination of ap and ba when the precharge command is asserted. if ap = high, all banks are precharged regardless of ba (pall) . if ap = low, a bank to be selected by ba is precharged (pre) . the auto-precharge enters precharge mode at the end of burst mode of read or write without the precharge command assertion. this auto precharge is entered by ap = high when a read or write command is asserted. refer to n functional truth table. burst length starting column address sequential mode interleave mode a 2 a 1 a 0 2 xx0 0 - 10 - 1 xx1 1 - 01 - 0 4 x00 0 - 1 - 2 - 30 - 1 - 2 - 3 x01 1 - 2 - 3 - 01 - 0 - 3 - 2 x10 2 - 3 - 0 - 12 - 3 - 0 - 1 x11 3 - 0 - 1 - 23 - 2 - 1 - 0 8 0000 - 1 - 2 - 3 - 4 - 5 - 6 - 70 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0011 - 2 - 3 - 4 - 5 - 6 - 7 - 01 - 0 - 3 - 2 - 5 - 4 - 7 - 6 0102 - 3 - 4 - 5 - 6 - 7 - 0 - 12 - 3 - 0 - 1 - 6 - 7 - 4 - 5 0113 - 4 - 5 - 6 - 7 - 0 - 1 - 23 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1004 - 5 - 6 - 7 - 0 - 1 - 2 - 34 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1015 - 6 - 7 - 0 - 1 - 2 - 3 - 45 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1106 - 7 - 0 - 1 - 2 - 3 - 4 - 56 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1117 - 0 - 1 - 2 - 3 - 4 - 5 - 67 - 6 - 5 - 4 - 3 - 2 - 1 - 0
mb81es171625/173225-15-x 19 13. auto-refresh (ref) auto-refresh uses the internal refresh address counter. sdr i/f fcram auto-refresh command (ref) generates the precharge command internally. all banks of sdr i/f fcram should be precharged prior to the auto-refresh command. the auto-refresh command should also be asserted every 1.95 m s or a total 2048 refresh commands within a 4 ms period. 14. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh function until cancelled by selfx. self-refresh is entered by applying an auto-refresh command in conjunction with cke = low (self) . once sdr i/f fcram enters the self-refresh mode, all inputs except for cke will be dont care (either logic high or low level state) and outputs will be in high-z state. during a self-refresh mode, cke = low should be maintained. self command should be issued only after the last read data has been appeared on dq. note : when the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1 ms prior to the self-refresh mode entry. 15. self-refresh exit (selfx) to exit the self-refresh mode, apply minimum t si after cke brought high, and then the no operation command (nop) or the deselect command (desl) should be asserted within one t refc period. cke should be held high within one t refc period after t si . refer to 16. self-refresh entry and exit timing in n timing diagrams for the detail. it is recommended to assert an auto-refresh command just after the t refc period to avoid the violation of refresh period. note : when the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1 ms after the self-refresh exit. 16. mode register set (mrs) the mode register of sdr i/f fcram provides a variety of operations. the register consists of 3 operation fields; burst length, burst type, and cas latency. refer to n mode register table. the mode register can be programmed by the mode register set command (mrs) . each field is set by the address line. once a mode register is programmed, the contents of the register will be held until re-programmed by another mrs command (or part loses power) . mrs command should be issued only when dq is in high-z. the condition of the mode register is undefined after the power-up stage. it is required to set each field after initialization of sdr i/f fcram. refer to 17. power-up initialization. 17. power-up initialization sdr i/f fcram internal condition after power-up will be undefined. it is required to follow the following power on sequence to execute read or write operation. 1. apply the power and start the clock. attempt to maintain either nop or desl command at the input. 2. maintain stable power, stable clock, and nop condition for a minimum of 500 m s. 3. precharge all banks by precharge (pre) or precharge all command (pall) . 4. assert minimum of 2 auto-refresh commands (ref) . 5. program the mode register by mode register set command (mrs) . in addition, it is recommended that dqm and cke track v dd to insure that output is in high-z state. the mode register set command (mrs) can be set before 2 auto-refresh commands (ref) . it is possible to excute 5 before 4.
mb81es171625/173225-15-x 20 n state diagram (simplified for single bank operation state diagram) mode register set self refresh idle read suspend bank active auto refresh power down bank active suspend write write suspend power on precharge read write with auto precharge read with auto precharge writ read read writ bst bst mrs self selfx ref actv cke cke\(csus) cke read writ reada writa reada cke writa pre or pall pre or pa l l power applied definition of allows manual input automatic sequence writa reada pre or pa l l pre or pa l l cke\(pd) read suspend cke write suspend cke cke\(csus) cke\(csus) cke\(csus) cke\(csus) note: cke\ means cke goes low-level from high-level. cke
mb81es171625/173225-15-x 21 n bank operation command table minimum clock latency or delay time for single bank operation *1: assume all banks are in idle state. *2: assume output is in high-z state. *3: assume t ras (min) is satisfied. *4: assume no i/o conflict. *5: assume the last data has been appeared on dq. second command (same bank) mrs actv read reada writ writa pre pall ref self bst first command mrs t rsc t rsc t rsc t rsc t rsc t rsc t rsc actv t rcd t rcd t rcd t rcd t ras t ras 1 read 11 * 4 1 * 4 1 * 3 1 * 3 1 1 reada * 1, * 2 bl + t rp * 1 bl + t rp * 3 bl + t rp * 3 bl + t rp * 1 bl + t rp * 1 bl + t rp * 1 bl + t rp writ t wr t wr 11 * 3 t dpl * 3 t dpl 1 writa * 1, * 2 bl-1 + t dal * 1 bl-1 + t dal * 3 bl-1 + t dal * 3 bl-1 + t dal * 1 bl-1 + t dal * 1 bl-1 + t dal * 1 bl-1 + t dal pre * 1, * 2 t rp t rp 1 * 3 1 * 1 t rp * 1, * 5 t rp 1 pa l l * 2 t rp t rp 11t rp * 5 t rp 1 ref t refc t refc t refc t refc t refc t refc t refc selfx t refc t refc t refc t refc t refc t refc t refc illegal command.
mb81es171625/173225-15-x 22 minimum clock latency or delay time for multi bank operation *1: assume all banks are in idle state. *2: assume output is in high-z state. *3: t rrd (min) of other bank (the second command will be asserted) is satisfied. *4: assume other bank is in active, read or write state. *5: assume t ras (min) is satisfied. *6: assume other banks are not in reada/writa state. *7: assume the last data has been appeared on dq. *8: assume no i/o conflict. second command ( other bank ) mrs actv * 4 read * 4 reada * 4 writ * 4 writa pre pall ref self bst first command mrs t rsc t rsc t rsc t rsc t rsc t rsc t rsc actv * 1 t rrd * 6 1 * 6 1 * 6 1 * 6 1 * 5, * 6 1 * 6 t ras 1 read * 1, * 3 1 11 * 8 1 * 8 1 * 5 1 * 5 1 1 reada * 1, * 2 bl + t rp * 1, * 3 1 * 5 1 * 5 1 * 5, * 8 1 * 5, * 8 1 * 5 1 * 5 bl + t rp * 1 bl + t rp * 1 bl + t rp * 1 bl + t rp writ * 1, * 3 1 1111 * 5 1 * 5 t dpl 1 writa * 1, * 2 bl-1 + t dal * 1, * 3 1 * 5 1 * 5 1 * 5 1 * 5 1 * 5 1 * 5 bl-1 + t dal * 1 bl-1 + t dal * 1 bl-1 + t dal * 1 bl-1 + t dal pre * 1, * 2 t rp * 1, * 3 1 * 6 1 * 6 1 * 6 1 * 6 1 * 5, * 6 1 * 6 1 * 1 t rp * 1, * 7 t rp 1 pa l l * 2 t rp t rp 11t rp * 7 t rp 1 ref t refc t refc t refc t refc t refc t refc t refc selfx t refc t refc t refc t refc t refc t refc t refc illegal command.
mb81es171625/173225-15-x 23 n mode register table mode register set ba a 12 a 11 a 10 a 9 a 8 * 2 a 7 * 2 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address 0 or 1 0 0 cl bt bl mode register *1: bl = 1 and full column are not applicable to the interleave mode. *2: a 7 and a 8 = 1 are reserved for vender test. a 6 a 5 a 4 cas latency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 reserved 1 2 reserved reserved reserved reserved reserved a 2 a 1 a 0 burst length bt = = = = 0 bt = = = = 1 * 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 reserved reserved reserved full column reserved 2 4 8 reserved reserved reserved reserved a 3 burst type 0 1 sequential interleave
mb81es171625/173225-15-x 24 n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions (referenced to vss) *1 : all voltages are referenced to v ss . *4 : the maximum junction temperature of fcram (tj) should not be more than + 125 c. tj is represented by the power consumption of fcram (p fcram ) and logic lsi(p d ),the thermal resistance of the package( q ja),and the maximum ambient temperature of the sip(t a max). tj m ax[ c] = t a max[ c] + q ja[ c/w] s pmax[w] s p m ax[w] = p fcra m + p d warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max voltage of v cc supply relative to v ss v dd , v ddq - 0.5 + 3.0 v voltage at any pin relative to v ss v in , v out - 0.5 + 3.0 v short circuit output current i out - 13 + 13 ma storage temperature t stg - 55 + 125 c parameter symbol value unit min typ max supply voltage* 1 v dd , v ddq 1.65 1.8 1.95 v v ss , v ssq 000v input high voltage * 2 v ih v ddq - 0.4 ? v ddq + 0.3 v input low voltage * 3 v il - 0.3 ? 0.4 v ambient temperature t a - 40 ?+ 85 c junction temperature* 4 tj - 40 ?+ 125 c 3.0 v v ih v il v ih (min) -1.5 v v il v ih v il (max) 50% of pulse amplitude pulse width 5 ns 50% of pulse amplitude pulse width 5 ns *3 : undershoot limit: v il (min) = v ss C1.5 v for pulse width 5 ns acceptable, pulse width measured at 50% of pulse amplitude. *2 : overshoot limit: v ih (max) = 3.0 v for pulse width 5 ns acceptable, pulse width measured at 50% of pulse amplitude.
mb81es171625/173225-15-x 25 n capacitance (f = 1 mhz, t a = + 25 c) parameter symbol value unit min typ max input capacitance, except for clk c in1 2.0 ? 5.0 pf input capacitance for clk c in2 2.0 ? 5.0 pf i/o capacitance c i / o 2.0 ? 5.0 pf
mb81es171625/173225-15-x 26 n dc characteristics (at recommended operating conditions unless otherwise noted.) (continued) parameter symbol condition value unit min max output high voltage v oh(dc) i oh = - 2 ma v ddq - 0.2 ? v output low voltage v ol(dc) i ol = 2 ma ? 0.2 v input leakage current (any input) i li 0 v v in v ddq ; all other pins not under test = 0 v - 55 m a output leakage current i lo 0 v v in v ddq ; data out disabled - 55 m a operating current (average power supply current) i dd1 burst length = 1, t rc = min for bl = 1, t ck = min, one bank active, output pin open, addresses changed up to one time during t ck (min), 0 v v in v il max, v ih min v in v ddq ? 30 ma power supply current (precharge standby current) i dd2p cke = 0 v, all banks idle, t ck = min, power down mode, v il = 0 v, v ih = v ddq ? 1ma i dd2ps cke = 0 v, all banks idle, clk = v ddq or 0 v, power down mode, v il = 0 v, v ih = v ddq ? 1ma i dd2n cke = v ddq , all banks idle, t ck = min, nop command only, input signals (except to cmd) are changed one time during 30 ns, v il = 0 v, v ih = v ddq ? 4ma i dd2ns cke = v ddq , all banks idle, clk = v ddq or 0 v, input signal are stable, v il = 0 v, v ih = v ddq ? 1ma
mb81es171625/173225-15-x 27 (continued) notes: all voltages are referenced to v ss and v ssq. dc characteristics are measured after following 17. power-up initialization procedure in n functional description. i dd depends on output termination, load conditions, clock rate, number of address and/or command change within certain period. the specified values are obtained with the output open. parameter symbol condition value unit min max power supply current (active standby current) i dd3p cke = 0 v, any bank active, t ck = min, v il = 0 v, v ih = v ddq ? 1ma i dd3ps cke = 0 v, any bank active, clk = v ddq or 0 v, v il = 0 v, v ih = v ddq ? 1ma i dd3n cke = v ddq , any bank active, t ck = min, nop command only, input signals (except to cmd) are changed one time during 30 ns, v il = 0 v, v ih = v ddq ? 10 ma i dd3ns cke = v ddq , any bank active, clk = v ddq or 0 v, input signals are stable, v il = 0 v, v ih = v ddq ? 1ma average power supply current (burst mode current) i dd4 t ck = min, burst length = 4, output pin open, all-banks active, gapless data, 0 v v in v il max, v ih min v in v ddq ? 40 ma average power supply current (refresh current #1) i dd5 auto-refresh; t ck = min, t refc = min, 0 v v in v il max, v ih min v in v ddq ? 73 ma average power supply current (refresh current #2) i dd6 self-refresh; clk = v ddq or 0 v, cke= 0 v, 0 v v in v il max, v ih min v in v ddq ? 5ma
mb81es171625/173225-15-x 28 n ac characteristics (1) basic ac characteristics (at recommended operating conditions unless otherwise noted.) *1: if input signal transition time (t t ) is longer than 1 ns; [ (t t / 2) - 0.5] ns should be added to t cac (max) , t ac (max) , t hz (max) and t si (min) spec values, [ (t t / 2) - 0.5] ns should be subtracted from t lz (min) , t hz (min) and t oh (min) spec values, and (t t - 1.0) ns should be added to t ch (min) , t cl (min) , t si (min) , and t hi (min) spec values. *2: this value is for reference only. *3: measured under ac test load circuit shown in (5) measurement condition of ac characteristics (load circuit) . *4: t ac also specifies the access time at burst mode except for first access at cl = 1. *5: specified where output buffer is no longer driven. notes: ac characteristics are measured after following 17. power-up initialization procedure in n functional description. ac characteristics assume t t = 1 ns ,10 pf of capacitive and 50 w of terminated load. refer to (5) measurement condition of ac characteristics (load circuit) 0.9 v is the reference level for measuring timing of input/output signals. transition times are measured between v ih (min) and v il (max) . refer to (6) setup, hold and delay time. parameter symbol value unit min max clock period cl = 1t ck1 30 1000 ns cl = 2t ck2 15 ns clock high time * 1 t ch 6 ? ns clock low time * 1 t cl 6 ? ns input setup time * 1 t si 3 ? ns input hold time except for cke * 1 t hi 2 ? ns xras access time * 2 t rac ? 57 ns xcas access time * 1, * 3 t cac ? 27 ns access time from clock (t ck = min) * 1, * 3, * 4 cl = 1t ac1 ? 27 ns cl = 2t ac2 ? 12 ns output in low-z * 1 t lz 0 ? ns output in high-z * 1, * 5 cl = 1t hz1 2.5 10 ns cl = 2t hz2 2.5 10 ns output hold time * 1, * 3 t oh 2.5 ? ns time between auto-refresh command interval * 2 t refi ? 1.95 m s time between refresh t ref ? 4ms transition time t t 0.5 5 ns
mb81es171625/173225-15-x 29 (2) base values for clock count/latency *: t rc (min) is not sum of t ras (min) and t rp (min) . actual clock count of t rc (l rc ) must satisfy t rc (min) , t ras (min) and t rp (min) . (3) clock count formula note: all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula : clock count equals base value divided by clock period (round up to a whole number) . parameter symbol value unit min max xras cycle time * t rc 75 ? ns xras precharge time t rp 30 ? ns xras active time t ras 45 110000 ns xras to xcas delay time t rcd 30 ? ns write recovery time t wr 15 ? ns xras to xras bank active delay time t rrd 15 ? ns data-in to precharge lead time t dpl 15 ? ns data-in to active/ refresh command period t dal 1cyc + t rp ? ns refresh cycle time t refc 75 ? ns mode resister set cycle time t rsc 45 ? ns clock 3 base value clock period (round up to a whole number)
mb81es171625/173225-15-x 30 (4) latency - fixed values (the latency values on these parameters are fixed regardless of clock period.) (5) measurement condition of ac characteristics (load circuit) parameter symbol value unit cke to clock disable cke 1 cycle dqm to output in high-z cl = 1 dqz1 1 cycle cl = 2 dqz2 2 cycle dqm to input data delay dqd 0 cycle last output to write command delay owd 2 cycle write command to input data delay dwd 0 cycle precharge to output in high-z delay cl = 1 roh1 1 cycle cl = 2 roh2 2 cycle burst stop command to output in high-z delay cl = 1 bsh1 1 cycle cl = 2 bsh2 2 cycle xcas to xcas delay (min) ccd 1 cycle xcas bank delay (min) cbd 1 cycle r 1 = 50 w 0.9 v c l = 10 pf output
mb81es171625/173225-15-x 31 (6) setup, hold and delay time (7) delay time for power down exit v oh v ol 0.9 v 0.9 v 1.4 v 1.4 v 0.4 v 0.4 v 0.9 v t ck t ch t si t hi t cac , t ac1 or t ac2 t lz t hz1 or t hz2 t oh t cl clk output input (control, addr. & data) valid valid notes: reference level of input/output signal is 0.9 v. access time is measured at 0.9 v. ac characteristics are also measured in this condition. clk cke command t si 1 clock (min) nop actv h or l h or l
mb81es171625/173225-15-x 32 (8) pulse width (9) access time t rc , t rp , t ras , t rcd , t wr , t refi , t refc , t dpl , t dal , t rsc , t rrd clk input (control) command command notes : these parameters are a limit value of the rising edge of the clock from one command input to the next input. measurement reference voltage is 0.9 v. : invalid clk xras xcas dq (output) t ac t rcd t rac t ac t ac 1 clock at cl = 2 q (valid) q (valid) q (valid) t cac
mb81es171625/173225-15-x 33 n timing diagrams 1. clock enable - read and write suspend (@ bl = 4) 2. clock enable - power down entry and exit cke (1 clock) cke (1 clock) clk cke clk (internal) dq (read) dq (write) d1 d2 not written not written d3 d4 q1 q2 (no change) (no change) q3 q4 * 1 * 1 * 2 * 2 * 2 * 3 * 3 * 2 t si t hi t si t hi t si t hi *1: the latency of cke ( cke ) is one clock. *2: during the read mode, burst counter will not be increased/decreased at the next clock of csus command. output data remains the same data. *3: during the write mode, data at the next clock of csus command is ignored. csus command csus command clk cke command t si 1 clock (min) t ref (max) nop pd (nop) h or l nop actv * 3 * 2 * 1 *1: the precharge command (pre or pall) should be asserted if any bank is active and in the burst mode. *2: the nop command should be asserted in conjunction with cke. *3: the actv command can be latched after t si + 1 clock (min) .
mb81es171625/173225-15-x 34 3. column address to column address input delay 4. different bank address input delay clk xras xcas address t rcd (min) ccd ccd ccd (1 clock) row address column address column address column address column address column address ccd note : xcas to xcas delay ( ccd ) can be one or more clock period. address clk xras xcas ba t rcd (min) or more t rcd (min) t rrd (min) cbd (1 clock) cbd bank 1 bank 0 bank 1 bank 1 bank 0 bank 0 row address row address column address column address column address column address note : xcas bank delay ( cbd ) can be one or more clock period.
mb81es171625/173225-15-x 35 5. dqm - input mask and output disable ( @ cl = = = = 2, bl = = = = 4 ) 6. precharge timing ( applied to the same bank ) clk dqm (@ read) dq (@ read) dqm (@ write) dq (@ write) d1 q1 q2 dqz2 q4 d4 d3 masked high-z end of burst end of burst dqd (same clock) clk command actv pre t ras (min) note : pre means pre or pall.
mb81es171625/173225-15-x 36 7. read interrupted by precharge ( example @ cl = = = = 2 , bl = = = = 4 ) high-z clk command command command command dq dq dq dq pre roh2 (2 clocks) no effect (end of burst) q1 q2 q3 q4 high-z high-z pre pre pre q1 roh2 (2 clocks) q1 q2 roh2 (2 clocks) q2 q3 q1 note : in case of cl = 1, the roh is 1 clock. in case of cl = 2, the roh is 2 clocks. pre means pre or pall.
mb81es171625/173225-15-x 37 8. read interrupted by burst stop ( example @ bl = = = = full column ) 9. write interrupted by burst stop (example @ bl = 2) bst q n q n - 2 q n - 1 bst q n q n - 2 q n - 1 q n + 1 bsh2 (2 clocks) bsh1 (1 clock) clk command (cl = 1) command (cl = 2) dq dq high-z high-z bst command clk command dq last d n masked by bst
mb81es171625/173225-15-x 38 10. write interrupted by precharge 11. read interrupted by write ( example @ cl = = = = 2 , bl = = = = 4 ) clk command dq pre actv t dpl (min) d n - 1 last d n masked by precharge t rp (min) note : the precharge command (pre) should be issued only after the t dpl of final data input is satisfied. pre means pre or pall. clk command dqm dq read writ dqz2 (2 clocks) owd (2 clocks) dwd (same clock) q 1 masked d 1 d 2 * 1 * 2 * 3 *1: the first dqm makes high-impedance state (high-z) between the last output and the first input data. *2: the second dqm makes internal output data mask to avoid bus contention. *3: the third dqm in illustrated above also makes internal output data mask. if burst read ends (the final data output) at or after the second clock of burst write, this third dqm is required to avoid internal bus contention.
mb81es171625/173225-15-x 39 12. write to read timing ( example @ cl = = = = 1 , bl = = = = 4 ) 13. read with auto - precharge ( example @ cl = = = = 2 , bl = = = = 2 applied to same bank ) clk command dqm dq writ read d1 d2 d3 masked by read q3 q2 q1 t wr (min) t ac1 t ac1 t cac (max) t ac1 notes: read command should be issued after t wr of the final data input is satisfied. the write data after read command is masked by read command. actv clk command dq dqm bl + t rp * actv reada q1 q2 nop or desl *: the next actv command should be issued after bl + t rp from reada command.
mb81es171625/173225-15-x 40 14. write with auto - precharge ( example @ cl = = = = 2 , bl = = = = 2 applied to same bank ) 15. auto - refresh timing actv clk command dq dqm t dal (min) (bl - 1) + t dal * actv writa d1 d2 nop or desl *: the next command should be issued after (bl - 1) + t dal from writa command. notes: if the final data is masked by dqm, the precharge does not start at the clock of the final data input. once the auto precharge command is asserted, no new command within the same bank can be issued. the auto-precharge command can not be invoked at full column burst operation. ref * 1 ref nop * 2 nop * 2 t refc (min) t refc (min) nop * 2 nop * 2 command * 3 clk command ba h or l ba h or l *1: all banks should be precharged prior to the first auto-refresh command (ref) . *2: either nop or desl command should be asserted within t refc period while auto-refresh mode. *3: any activation command such as actv or mrs commands other than ref command should be asserted after t refc from the last ref command. note: bank select is ignored at the ref command. the refresh address and bank select are selected by the internal refresh counter.
mb81es171625/173225-15-x 41 16. self-refresh entry and exit timing 17. mode register set timing nop * 1 self selfx * 2 h or l nop * 3 command t si (min) t si t refc (min) * 4 clk cke command *1: the precharge command (pre or pall) should be asserted if any bank is active prior to the self-refresh entry command (self) . *2: the self-refresh exit command (selfx) is latched after t si . *3: either nop or desl command can be used during t refc period. *4: cke should be held high for at least one t refc period after t si . entry exit actv mrs nop or desl row address mode t rsc (min) clk command address note : the mode register set command (mrs) should be asserted only after all banks have been precharged and dq is in high-z.
mb81es171625/173225-15-x 42 n ordering information part number configuration shipping form remarks MB81ES171625-15WFKT-X 512 k word 16 bit 2 bank wafer mb81es173225-15wfkt-x 256 k word 32 bit 2 bank wafer
mb81es171625/173225-15-x fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0306 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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