View HM511664CTT-7_1965073.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hm511664c series 1m fp dram (64-kword 16-bit) 256 refresh ade-203-627a (z) rev. 1.0 dec. 20, 1997 description the hitachi hm511664c series is a cmos dynamic ram organized 65,536-word 16-bit. hm511664c series has realized higher density, higher performance and various functions by employing 0.8 m m cmos process technology and some new cmos circuit design technologies. the hm511664c series offers fast page mode as a high speed access mode. multiplexed address input permits the hm511664c to be packaged in standard 400-mil 40-pin plastic soj and standard 400-mil 44-pin plastic tsopii. features single 5 v supply: 5 v 10% access time: 60 ns/70 ns/80 ns (max) power dissipation ? active mode: 660 mw/ 633 mw/495 mw (max) ? standby mode: 11 mw (max) fast page mode capability refresh cycles ? 256 refresh cycles: 4 ms 2 variations of refresh ? ras -only refresh ? cas -before- ras refresh 2 we -byte control
hm511664c series 2 ordering information type no. access time package hm511664cj-6 hm511664cj-7 hm511664cj-8 60 ns 70 ns 80 ns 400-mil 40-pin plastic soj (cp-40d) hm511664ctt-6 HM511664CTT-7 hm511664ctt-8 60 ns 70 ns 80 ns 400-mil 44-pin plastic tsopii (ttp-44/40da) pin arrangement v cc i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 nc v cc uwe lwe ras a0 a1 a2 a3 a4 v cc v cc i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 nc v cc uwe lwe ras a0 a1 a2 a3 a4 v cc v ss i/o16 i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 nc v ss cas oe nc nc nc a7 a6 a5 v ss v ss i/o16 i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 nc v ss cas oe nc nc nc a7 a6 a5 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (top view) 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 (top view) hm511664cj series hm511664ctt series
hm511664c series 3 pin description pin name function a0 to a7 address input row address a0 to a7 refresh address a0 to a7 column address a0 to a7 i/o1 to i/o16 data-in/data-out ras row address strobe cas column address strobe uwe , lwe read/write enable oe output enable v cc power supply v ss ground nc no connection block diagram ? ? ? ? ? ? a0 a1 to a7 timing and control ras uwe lwe cas oe column address buffers row address buffers i/o buffers i/o1 to i/o16 column decoder row decoder 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array 64k array
hm511664c series 4 operation table the hm511664c series has the following 10 operation modes. 1. read cycle 2. early write cycle 3. delayed write cycle 4. read-modify-write cycle 5. ras -only refresh cycle 6. cas -before- ras refresh cycle 7. fast page mode read cycle 8. fast page mode early write cycle 9. fast page mode delayed write cycle 10. fast page mode read-modify-write cycle inputs ras cas uwe lwe output operation h h d d open standby h l h h valid standby l l h h valid read cycle lll *2 l *2 open early write cycle lll *2 l *2 undefined delayed write cycle l l h to l h to l valid read-modify-write cycle l h d d open ras -only refresh cycle h to l l d d open cas -before- ras refresh cycle l h to l h h valid fast page mode read cycle l h to l l *2 l *2 open fast page mode early write cycle l h to l l *2 l *2 undefined fast page mode delayed write cycle l h to l h to l h to l valid fast page mode read modify-write cycle notes: 1. h: high (inactive) l: low (active) d: h or l 2. t wcs 3 0 ns early write cycle t wcs < 0 ns delayed write cycle 3. mode is determined by the or function of the uwe and lwe . (mode is set by the earliest of uwe and lwe active edge and reset by the latest of uwe and lwe inactive edge.) however write operation and output high-z control are done independently by each uwe , lwe .
hm511664c series 5 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C1.0 to +7.0 v supply voltage relative to v ss v cc C1.0 to +7.0 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit notes supply voltage v ss 000v2 v cc 4.5 5.0 5.5 v 1, 2 input high voltage v ih 2.4 6.5 v 1 input low voltage (i/o pin) v il C0.5 0.8 v 1 (others) v il C1.0 0.8 v 1 notes: 1. all voltage referred to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
hm511664c series 6 dc characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) * 4 hm511664c -6 -7 -8 parameter symbol min max min max min max unit test conditions operating current* 1, * 2 i cc1 120 115 90 ma ras cycling cas cycling, t rc = min standby current i cc2 2 2 2 ma ttl interface ras , cas = v ih dout = high-z 1 1 1 ma cmos interface ras , cas , uwe , lwe , oe 3 v cc C 0.2 v dout = high-z ras -only refresh current* 2 i cc3 120 115 90 ma t rc = min standby current* 1 i cc5 5 5 5 ma ras = v ih , cas = v il , dout = enable cas -before- ras refresh current* 2 i cc6 120 115 90 ma t rc = min fast page mode current* 1, * 3 i cc7 120 115 90 ma t pc = min input leakage current i li C10 10 C10 10 C10 10 m a 0 v vin 6.5 v output leakage current i lo C10 10 C10 10 C10 10 m a 0 v vout 6.5 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc 2.4 v cc v high iout = C2.5 ma output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 2.1 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed twice or less while ras = v il . 3. address can be changed twice or less while cas = v ih . 4. all the v cc pins should be supplied with the same voltage. and all the v ss pins should be supplied with the same voltage.
hm511664c series 7 capacitance (ta = +25 c, v cc = 5 v 10%) parameter symbol typ max unit notes input capacitance (address) c i1 5 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-in, data-out) c i/o 10 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout. ac characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v)* 1, * 14, * 15, * 17, * 18 test conditions input rise and fall time : 5 ns input levels: v il = 0 v, v ih = 3.0 v input timing reference levels : 0.8 v, 2.4 v output load : 1 ttl gate + c l (50 pf) (including scope and jig)
hm511664c series 8 read, write, read-modify-write and refresh cycles (common parameters) hm511664c -6 -7 -8 parameter symbol min max min max min max unit notes random read or write cycle time t rc 105 125 145 ns ras precharge time t rp 40 50 60 ns ras pulse width t ras 60 10000 70 10000 80 10000 ns 23 cas pulse width t cas 15 10000 20 10000 20 10000 ns 22, 24 row address setup time t asr 000ns row address hold time t rah 10 10 10 ns column address setup time t asc 000ns column address hold time t cah 15 15 15 ns ras to cas delay time t rcd 20 45 20 50 20 60 ns 8 ras to column address delay time t rad 15 30 15 35 15 40 ns 9 ras hold time t rsh 15 20 20 ns cas hold time t csh 60 70 80 ns 25 cas to ras precharge time t crp 10 10 10 ns oe to din delay time t odd 15 15 15 ns oe delay time from din t dzo 000ns cas setup time from din t dzc 000ns transition time (rise and fall) t t 350350350ns7 refresh period t ref 4 4 4 ms
hm511664c series 9 read cycle hm511664c -6 -7 -8 parameter symbol min max min max min max unit notes access time from ras t rac 60 70 80 ns 2, 3 access time from cas t cac 15 20 20 ns 3, 4, 13 access time from address t aa 30 35 40 ns 3, 5, 13 access time from oe t oac 15 20 20 ns22 read command setup time t rcs 0 0 0 ns20 read command hold time to cas t rch 0 0 0 ns 16, 19 read command hold time to ras t rrh 0 0 0 ns 16, 19 column address to ras lead time t ral 30 35 40 ns output buffer turn-off time t off1 015015015ns6 output buffer turn-off time to oe t off2 015015015ns6 cas to din delay time t cdd 15 15 15 ns write cycle hm511664c -6 -7 -8 parameter symbol min max min max min max unit notes write command setup time t wcs 0 0 0 ns 10, 19 write command hold time t wch 10 13 15 ns 20 write command pulse width t wp 10 13 15 ns 21 write command to ras lead time t rwl 20 20 20 ns 21 write command to cas lead time t cwl 10 13 15 ns 21 data-in setup time t ds 0 0 0 ns 11, 21 data-in hold time t dh 10 13 15 ns 11, 21 cas to oe delay time t cod 0 0 0 ns22
hm511664c series 10 read-modify-write cycle hm511664c -6 -7 -8 parameter symbol min max min max min max unit notes read-modify-write cycle time t rwc 135 165 185 ns ras to we delay time t rwd 77 90 102 ns 10, 19 cas to we delay time t cwd 32 38 42 ns 10, 19 column address to we delay time t awd 47 55 62 ns 10, 19 oe hold time from we t oeh 15 18 20 ns 21 refresh cycle hm511664c -6 -7 -8 parameter symbol min max min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 10 10 ns cas hold time (cbr refresh cycle) t chr 10 10 10 ns ras precharge to cas hold time t rpc 10 10 10 ns cas precharge time in normal mode t cpn 10 10 10 ns fast page mode cycle hm511664c -6 -7 -8 parameter symbol min max min max min max unit notes fast page mode cycle time t pc 40 45 50 ns fast page mode cas precharge time t cp 10 10 10 ns fast page mode ras pulse width t rasc 60 100000 70 100000 80 100000 ns 12 access time from cas precharge t acp 35 40 45 ns 3, 13 ras hold time from cas precharge t rhcp 35 40 45 ns
hm511664c series 11 fast page mode read-modify-write cycle hm511664c -6 -7 -8 parameter symbol min max min max min max unit notes fast page mode read-modify-write cycle time t pcm 80 95 100 ns fast page mode read-modify-write cycle cas precharge to we delay time t cpw 52 60 67 ns 10, 21 notes: 1. ac measurements assume t t = 5 ns. 2. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 3. measured with a load circuit equivalent to 1 ttl loads and 50 pf. 4. assumes that t rcd 3 t rcd (max) and t rad t rad (max). 5. assumes that t rcd t rcd (max) and t rad 3 t rad (max). 6. t off1 (max), t off2 (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 8. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only, if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 9. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only, if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 10. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only: if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. these parameters are referred to cas leading edge in an early write cycle and to we leading edge in a delayed write or a read-modify-write cycle. 12. t rasc defines ras pulse width in fast page mode cycles. 13. access time is determined by the longest among t aa , t cac and t acp . 14. an initial pause of 100 m s is required after power up followed by a minimum of eight initialization cycles ( ras -only refresh cycle or cas -before- ras refresh cycle). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles is required. 15. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 16. either t rch or t rrh must be satisfied for a read cycle. 17.when both uwe and lwe go low at the same time, all 16-bits data are written into the device. uwe and lwe cannot be staggered within the same write/read cycles. 18. all the v cc and v ss pins shall be supplied with the same voltages. 19. t rch , t rrh , t wcs , t rwd , t cwd and t awd are determined by the earlier falling edge of uwe and lwe . 20. t wch and t rcs are determined by the later rising edge of uwe or lwe . 21. t wp , t rwl , t cwl , t oeh , t ds , t dh and t cpw should be satisfied by both uwe and lwe .
hm511664c series 12 22. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 23. t ras (min) = t rwd (min) + t rwl (min) + t t in read-modify-write cycle. 24. t cas (min) = t cwd (min) + t cwl (min) + t t in read-modify-write cycle. 25. t csh (min) can be achieved when t rcd t csh (min) C t cas (min) 26. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il . notes concerning 2 we control please do not separate the uwe / lwe operation timing intentionally. however skew between uwe / lwe are allowed under the following conditions . (1) each of the uwe / lwe should satisfy the timing specifications individually. (2) different operation mode for upper/lower byte is not allowed; such as following. ras cas lwe uwe delayed write early write
hm511664c series 13 timing waveforms* 26 read cycle ras address dout t ras t rc t rp t csh t rcd t rsh t cas t ral t cah t rad t t asr rah t asc t rcs t rch t rrh t cac t off1 t aa t rac t t t crp row column din oe high-z dzc t high-z dzo t t oac t cdd t off2 t odd dout cas uwe lwe
hm511664c series 14 early write cycle ras address din dout t ras t rp t rc t csh t crp t rcd t rsh t cas t t t cah t asc t rah t asr row column t wcs t ds t dh din high-z t wch cas uwe lwe
hm511664c series 15 delayed write cycle address ras din dout t ras t rc t rp t csh t crp t rcd t rsh t cas t asr t rah t asc t cah row column t rcs t wp t rwl t cwl t ds t dh din t odd t off2 t t * do not enable dout during delayed write cycle. oe t dzc t dzo t oeh t cod *invalid dout high-z cas uwe lwe
hm511664c series 16 read-modify-write cycle din dout address ras t rwc t rp t ras t cas t crp t t t rcd t rad t asr t rah t cah t asc row column t cwd t rcs t awd t rwd t wp t cwl t rwl t ds t dh din t odd t aa t off2 t oeh t rac oe t dzo t oac high-z t dzc t cac dout high-z cas uwe lwe
hm511664c series 17 ras -only refresh cycle ras address dout t rc t ras t rp t t t crp t rpc t crp t asr t rah row high-z cas
hm511664c series 18 cas -before- ras refresh cycle ras address dout t rc t rc t rp t ras t rp t ras t rp t rpc t t t cpn t csr t chr t cpn t csr t rpc t chr t crp t off1 high-z cas
hm511664c series 19 fast page mode read cycle ras address din dout high-z t rasc t rp t t t csh t pc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t cah row column column column t rac t rch t rrh t aa t cdd t odd high-z t rcs t rch t rcs t dzc t rcs t cdd oe t rhcp t rad t ral dout t cdd t odd t dzo t off2 t oac t oac t odd t dzo dzc t t off2 t oac t off1 t aa t cac t acp t dzo t acp t aa t cac t off1 t off1 t cac t high-z high-z t dzc t asc t rch off2 dout dout cas uwe lwe
hm511664c series 20 fast page mode early write cycle ras address din dout t rasc t rp t t t csh t pc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah row column column column t ds t dh t ds t dh t ds t dh din din din high-z t wcs t wch t wch t wcs t wcs t wch cas uwe lwe
hm511664c series 21 fast page mode delayed write cycle din address ras dout t rasc t rp t t t csh t pc t rsh t cas t rcd t cp t cas t cp t cas t crp t asr t rah t asc t cah t asc t cah t asc t cah row column t wp t rcs t rcs t cwl t t cwl t cwl t t ds t dh t ds t ds t dh din din din oe t odd t oeh t dh high-z t wp t rcs rwl wp column column cas uwe lwe
hm511664c series 22 fast page mode read-modify-write cycle din dout address ras t rasc t t cp t pcm t t tt rcd cas t cas t cas t t cp t rad t asr t asc t t t rah t t cah t t cpw t t cpw t cwl t rwd t awd t awd t awd t cwd t t cwd t cwd t rcs t wp t t wp t ds t t dh t t ds t dzc t dh t odd t dh t cac t dzo t oeh t oeh t oeh t aa t din din din t rp t rwl t oac t odd t off2 t t odd t dzo t off2 t t t dzo aa t oe dout dout dout t cah t ds column column column row rac cwl high-z cac acp wp cwl cac t crp asc acp cah t asc rcs high-z high-z oac t dzc dzc rcs oac t off2 high-z cas uwe lwe
hm511664c series 23 package dimension hm511664cj series (cp-40d) 9.40 0.25 1 20 0.10 0.43 0.10 3.50 0.26 + 0.31 ?0.14 2.30 21 40 26.16 max 25.80 0.74 10.16 0.13 11.18 0.13 1.30 max 1.27 + 0.25 ?0.17 0.80 hitachi code jedec eiaj weight (reference value) cp-40d conforms 1.73 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension
hm511664c series 24 package dimension (cont.) hm511664ctt series (ttp-44/40da) 0.13 m 0.10 44 23 122 18.41 18.81 max 0.30 0.10 1.20 max 10.16 0.13 0.05 11.76 0.20 0.50 0.10 0 ?5 1.005 max 0.17 0.05 10 13 32 35 0.80 2.40 0.80 hitachi code jedec eiaj weight (reference value) ttp-44/40da conforms ? 0.43 g 0.25 0.05 0.125 0.04 unit: mm dimension including the plating thickness base material dimension
hm511664c series 25 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm511664c series 26 revision record rev. date contents of modification drawn by approved by 0.0 sep. 10, 1996 initial issue i. ogiwara s. suzuki 0.1 dec. 20, 1996 correct errors of ac characteristics t t (min): 2/2/2 ns to 3/3/3 ns deletion of note 23 t. oono s. suzuki 1.0 dec. 20, 1997 change of subtitle

▲Up To Search▲

Price & Availability of HM511664CTT-7

	To Download HM511664CTT-7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .