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dual interface for flat panel displays ad9882a rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features analog interfa c e 140 msps m a ximum conversi on rate programmable analog bandwidth 0.5 v to 1.0 v a n alog input ra nge 500 ps p-p pll clock jitter at 1 40 msps 3.3 v power supply full s y nc processing midscale clamping 4:2:2 output format mode digital interf ace dvi 1.0 compatible interface 112 mh z opera t ion high skew tole rance of 1 fu ll i n put clock sync detect for hot plugging supports high bandwidth digi tal content protection applic ati o ns rgb graphics processing lcd monitors and projectors plasma display panels scan converter microdisplays digital t v func tio n a l block di agram a/d clamp r ain g ain b ain sogin hsync sync processing and clock generation filt vsync scl sda a 0 r x0+ r x0 ? r x1+ r x1 ? r x2+ r x2 ? r xc+ r xc ? r term ddcscl ddcsda mcl mda 8 a/d clamp 8 a/d clamp 8 analog interface muxes datack hsout vsout sogout 8 ref r out g out b out r out g out b out r out g out b out datack de hsync vsync datack hsout csout sogout de refbypass 8 8 dvi receiver hdcp 8 8 8 ad9882a serial register and power management digital interface 05123- 001 fi g u r e 1 . general description the ad9882 a o f f e rs desig n ers th e f l exib il i t y o f a n a n alog in t e r - face an d a d i g i t a l visua l in t e r f a c e (d vi) r e cei v er in teg r a t e d o n a s i ng l e ch i p . al s o incl u d e d is sup p or t for hig h b a ndw i dt h dig i t a l co n t en t p r o t ectio n (h d c p ) . analog int e rf ac e the ad9882 a is a co m p lete , 8-b i t, 140 ms ps m o n o li t h ic a n a l og in ter f ace o p t i mi ze d fo r ca p t ur in g rgb g r a p hics sig n a l s f r o m p e rs o n al c o m p u t ers and wo rks t a t io n s . i t s 140 ms ps en co de r a te c a p a b i l i ty and f u l l p o w e r a n a l o g b a nd w i d t h o f 30 0 mh z s u p-p o r t s r e s o l u tio n s u p to sx ga (1280 1024 a t 75 h z ). the a n alog in t e r f ace in c l udes a 140 mh z tr i p le ad c wi th in t e r n al 1.25 v r e f e r e n c e , a p h as e-lo c k e d lo o p ( p ll), p r og ra m- ma b l e ga i n , o f fs et, an d clam p c o n t r o l . the us er p r o v ides onl y a 3.3 v p o w e r s u p p l y , a n alog in p u t, an d h s y n c. thr e e-sta t e cm os o u t p u t s ca n be p o w e r e d f r o m 2.2 v t o 3.3 v . the ad9882 a s o n -c hi p p ll g e n e ra t e s a p i xe l clo c k f r o m h s y n c . pi x e l cl o c k output f r e q u e nc i e s r a nge f r om 1 2 m h z to 140 mh z. p ll c l o c k ji t t e r is ty p i cal l y 500 ps p-p a t 140 ms ps. the ad9882 a als o o f f e rs f u l l s y n c p r o c es s i n g f o r co m p osi t e sy n c and sy n c -on-g r e e n (so g ) a p plic a t io n s . digital interface the ad9882 a co n t a i n s a d v i 1.0 co m p a t i b le recei v er an d s u p p o r ts dis p la y r e s o l u tio n s u p t o sx ga (1280 1024 a t 60 h z ). the r e cei v er fe a t ur es an i n t r a p a i r s k e w t o lera n c e o f u p to one f u l l cl o c k c y cl e. w i t h t h e i n cl usi o n o f hd cp , di spla y s can n o w r e cei v e en cr yp t e d video co n t en t. the ad9882a al lo ws f o r a u th en tic a - t i on of a v i d e o r e c e ive r , d e c r y p t i on of e n c o d e d d a t a a t t h e r e ce i v e r , a n d r e n e w a b i li t y o f tha t a u t h e n t i ca ti o n d u rin g tra n s- missio n, as sp e c if ie d b y t h e hd cp v1.0 p r o t o c ol. i t a l s o has h i g h to l e r a nc e of no nc om pl i a n t h d c p s o u r c e s . f a b r ica t ed in an ad van c e d cmos p r o c es s, t h e ad9882a is p r o v ided in a s p ace-s a ving, 100-lead l q fp s u r f ace-m o u n t plast i c p a ck a g e a nd is sp e c if ie d o v er t h e 0 c t o 70c t e m p era t ur e ra ng e . i t is a v ai lab l e in a pb -f r e e p a cka g e.
ad9882a rev. 0 | page 2 of 40 table of contents specifications ............................................................................................3 absolute maximum ratings ..................................................................6 explanation of test levels ..................................................................6 esd caution ........................................................................................6 pin configuration and function descriptions ....................................7 pin descriptions of shared pins between analog and digital interfaces ..............................................................................................8 serial port (2-wire) ............................................................................8 data outputs ........................................................................................8 pin function detail: analog interface .............................................9 power supply .....................................................................................10 theory of operation: interface detection .........................................12 active interface detection and selection .......................................12 power management ..........................................................................12 theory of operation and design guide: analog interface .............13 general description ..........................................................................13 input signal handling ......................................................................13 hsync and vsync inputs ..................................................................13 serial control port ............................................................................13 output signal handling ...................................................................13 clamping ............................................................................................13 gain and offset control ...................................................................14 sync-on-green (sog) ......................................................................15 clock generation ..............................................................................15 timing: analog interface .....................................................................17 timing diagrams ..............................................................................18 theory of operation: digital interface ...............................................19 digital interface pin descriptions ..................................................19 capturing the encoded data ...........................................................20 data frames .......................................................................................20 special characters .............................................................................20 channel resynchronization .............................................................20 data decoder .....................................................................................20 hdcp ..................................................................................................20 general timing diagrams: digital interface .................................22 timing mode diagrams: digital interface ....................................22 2-wire serial register map ..................................................................23 2-wire serial control register detail .................................................26 chip identification ............................................................................26 pll divider control .........................................................................26 clamp timing ....................................................................................27 hsync output pulse width ..............................................................27 input gain ..........................................................................................27 input offset ........................................................................................27 2-wire serial control port ...............................................................32 sync processing engine ........................................................................35 sync slicer ...........................................................................................35 sync separator ...................................................................................35 pcb layout recommendations ...........................................................36 analog interface inputs ....................................................................36 digital interface inputs .....................................................................36 power supply bypassing ...................................................................36 pll ......................................................................................................37 outputs: data and clocks ................................................................37 digital inputs .....................................................................................37 volt age r e fe re nc e ..............................................................................37 outline dimensions ..............................................................................38 ordering guide ..................................................................................38 revision history 10/04revision 0: initial version
ad9882a rev. 0 | page 3 of 40 specifications v d = 3.3 v, v dd = 3.3 v, adc clock = maximum conversion rate, unless otherwise noted. table 1. analog interface electrical characteristics ad9882akstz-100 ad9882akstz-140 parameter temp test level min typ max min typ max unit resolution 8 8 bits dc accuracy differential nonlinearity 25c i 0.5 +1.25/C1.0 0.5 +1.35/C1.0 lsb full vi +1.35/C1.0 +1.45/C1.0 lsb integral nonlinearity 25c i 0.5 1.85 0.5 2.0 lsb full vi 2.0 2.3 lsb no missing codes full vi guaranteed guaranteed analog input input voltage range minimum full vi 0.5 0.5 v p-p maximum full vi 1.0 1.0 v p-p gain tempco 25c v 100 100 ppm/c input bias current full iv 1 1 a input full-scale matching full vi 1.5 8.0 1.5 8.0 % fs offset adjustment range full vi 45 49 56 45 49 56 % fs reference output output voltage full vi 1.25 1.25 v temperature coefficient full v 50 50 ppm/c switching performance 1 maximum conversion rate full vi 100 140 msps minimum conversion rate full iv 10 10 msps clock to data skew, t skew full iv C0.5 +2.0 C0.5 +2.0 ns serial port timing t buff full vi 4.7 4.7 s t stah full vi 4.0 4.0 s t dho full vi 250 250 ns t dal full vi 4.7 4.7 s t dah full vi 4.0 4.0 s t dsu full vi 250 250 ns t stasu full vi 4.7 4.7 s t stosu full vi 4.0 4.0 s hsync input frequency full iv 15 110 15 110 khz maximum pll clock rate full vi 100 140 mhz minimum pll clock rate full iv 12 12 mhz pll jitter 25c iv 500 700 2 500 700 2 ps p-p full iv 1000 2 1000 2 ps p-p sampling phase tempco full iv 15 15 ps/c digital inputs input voltage, high (v ih ) full vi 2.6 2.6 v input voltage, low (v il ) full vi 0.8 0.8 v input current, high (i ih ) full iv C1.0 C1.0 a input current, low (i il ) full iv 1.0 1.0 a input capacitance 25c v 3 3 pf digital outputs 1 output voltage, high (v oh ) full iv v dd C 0.1 v dd C 0.1 v output voltage, low (v ol ) full iv 0.4 0.4 v duty cycle, datack full iv 45 50 55 45 50 55 %
ad9882a rev. 0 | page 4 of 40 ad9882akstz-100 ad9882akstz-140 parameter temp test level min typ max min typ max unit output coding binary binary power supply 1 v d supply voltage full iv 3.15 3.3 3.45 3.15 3.3 3.45 v v dd supply voltage full iv 2.2 3.3 3.45 2.2 3.3 3.45 v p vd supply voltage full iv 3.15 3.3 3.45 3.15 3.3 3.45 v i d supply current (v d ) 25c v 162 181 ma i dd supply current (v dd ) 3 25c v 47 63 ma ipv d supply current (pv d ) 25c v 19 21 ma total supply current full vi 228 237 265 274 ma power-down supply current full vi 30 35 30 35 ma dynamic performance analog bandwidth, full power 25c v 300 300 mhz signal-to-noise ratio (snr) 25c v 44 43 db f in = 2.3 mhz crosstalk full v 55 55 dbc thermal characteristics ja junction-to-ambient 4 v 43 43 c/w 1 drive strength = 11. 2 vco range = 10, charge pump current = 110, pll divider = 1693. 3 datack load = 15 pf, data load = 5 pf. 4 simulated typical performance with pa ckage mounted to a 4-layer board. vd = 3.3 v, vdd = 3.3 v, clock = maximum, unless otherwise noted. table 2. digital interface electrical characteristics ad9882akstz parameter conditions temp test level min typ max unit resolution 8 bits dc digital i/o specifications high level input voltage (v ih ) full vi 2.6 v low level input voltage (v il ) full vi 0.8 v high level output voltage (v oh ) full iv 2.4 v low level output voltage (v ol ) full iv 0.4 v output leakage current (i ol ) high impedance full iv C10 +10 a dc specifications output high drive output drive = high full v 11 ma (i ohd )(v out = v oh ) output drive = medium full v 8 ma output drive = low full v 5 ma output low drive output drive = high full v C7 ma (i old )(v out = v ol ) output drive = medium full v C6 ma output drive = low full v C5 ma datack high drive output drive = high full v 28 ma (v ohc )(v out = v oh ) output drive = medium full v 14 ma output drive = low full v 7 ma datack low drive output drive = high full v C15 ma (v olc )(v out = v ol ) output drive = medium full v C9 ma output drive = low full v C7 ma differential input voltage single-ended amplitude full iv 75 800 mv
ad9882a rev. 0 | page 5 of 40 ad9882akstz parameter conditions temp test level min typ max unit power supply v d supply voltage full iv 3.15 3.3 3.45 v v dd supply voltage full iv 2.2 3.3 3.45 v pv d supply voltage full iv 3.15 3.3 3.45 v i d supply current (typical pattern) 1 25c v 237 ma i dd supply current (typical pattern) 1, 2 25c v 25 ma ipv d supply current (typical pattern) 1 25c v 57 ma total supply current with hdcp (typical pattern) 1, 2 full iv 340 367 ma i d supply current (worst-case pattern) 3 25c v 247 ma i dd supply current (worst-case pattern) 2, 3 25c v 61 ma ipv d supply current (worst-case pattern) 3 25c v 57 ma total supply current with hdcp (worst-case pattern) 2, 3 full iv 385 420 ma power-down supply current (i pd ) full vi 30 35 ma ac specifications intrapair (+ to C) differential input skew (t dps ) full iv 360 ps channel-to-channel differential input skew (t ccs ) full iv 1 clock period low-to-high transition time for data (d lht ) output drive = high, c l = 10 pf full iv 2.2 ns output drive = medium, c l = 7 pf full iv 2.5 ns output drive = low, c l = 5 pf full iv 3.2 ns low-to-high transition time for datack (d lht ) output drive = high, c l = 10 pf full iv 1.0 ns output drive = medium, c l = 7 pf full iv 1.6 ns output drive = low, c l = 5 pf full iv 2.1 ns high-to-low transition time for data (d hlt ) output drive = high, c l = 10 pf full iv 2.2 ns output drive = medium, c l = 7 pf full iv 1.9 ns output drive = low, c l = 5 pf full iv 1.7 ns high-to-low transition time for datack (d hlt ) output drive = high, c l = 10 pf full iv 1.0 ns output drive = medium, c l = 7 pf full iv 1.0 ns output drive = low, c l = 5 pf full iv 1.4 ns clock -to- data skew, 4 t skew full iv C0.5 +2.0 ns duty cycle, datack 4 full iv 40 46 50 % datack frequency (f cip ) full vi 25 112 mhz 1 the typical pattern contains a gray scale area. output drive = high. 2 datack load = 10 pf, data load = 10 pf. 3 the worst-case pattern contains a black and white checkerboard pattern. output drive = high. 4 drive strength = 11.
ad9882a rev. 0 | page 6 of 4 0 absolute maximum ra tings table 3. p a r a m e t e r r a t i n g v d 3.6 v v dd 3.6 v analog inputs v d to 0.0 v v ref v d to 0.0 v digital inputs 5 v to 0.0 v digital output c u rrent 20 ma operating temperature C25c to +85c storage temperature C65c to +150c maximum junction temperature 150c maximum case temperature 150c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xi m u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or an y ot he r co ndi t i on s o u tsi d e o f t h o s e i ndi ca te d i n t h e op e r a t io n s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ngs fo r ex ten d e d p e r i o d s m a y a f f e c t de vi ce rel i abi l it y . expl ana t ion of test levels i. 100% p r o d uc t i o n t e st ed . ii. 100% p r o d uc t i o n t e st ed a t 25c a nd s a m p le t e s t ed a t sp e c if ie d t e m p e r a t ur es. iii. s a m p l e te ste d on ly . iv. p a r a me te r i s g u ar an te e d b y d e s i g n an d ch ar a c te r i z a t i on te st i n g . v. p a ra m e t e r is a typ i cal val u e o n ly . vi. 100% p r o d uc t i o n t e st ed a t 25c; gua r a n t e ed b y desig n and ch ar a c te r i z a t i on te st i n g . esd c a ution esd (electrostatic discharge) sensitive device. ele c trostatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although this product features proprietar y esd protection circuitry, permanent damage may occur on devices subjected to high energy electro s tatic discha rge s . therefore, pro p er esd precautions are recommended to avoid perform a nce degradatio n or los s of functionality.
ad9882a rev. 0 | page 7 of 4 0 pin conf igura t ion and fu nction descriptions ad9882a top view (not to scale) v dd re d<0 > re d<1 > re d<2 > re d<3 > re d<4 > re d<5 > re d<6 > re d<7 > gnd v dd sogout hs out vsou t de datack gnd v dd mda mcl vsyn c h syn c sd a sc l a0 gnd v d r term v d v d gnd r x0 ? r x0 + gnd r x1 ? r x1 + gnd r x2 ? r x2 + gnd r xc + r xc ? v d pv d gnd pv d gnd filt pv d gnd 1 gnd green<7> green<6> green<5> green<4> green<3> green<2> green<1> green<0> v dd gnd blue<7> blue<6> blue<5> blue<4> blue<3> blue<2> blue<1> blue<0> v dd gnd ctl 0 ctl 1 ctl 2 ctl 3 gnd midbypass refbypass v d gnd r ain v d gnd v d gnd g ain sogin v d gnd v d gnd b ain v d gnd v d gnd ddcsda ddcscl pv d gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 05123-002 pin 1 indicator f i g u re 2. 10 0-l e ad l qfp pin conf ig ur a t ion ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin type mnemonic function value pin n u m b e r i n t e r f a c e analog video inputs r ain analog input for converter r 0.0 v to 1.0 v 70 analog g ain analog input for converter g 0.0 v to 1.0 v 65 analog b ain analog input for converter b 0.0 v to 1.0 v 59 analog external sync/c lock hsync horizont al sync input 3.3 v cmos 79 analog vsync vertical sync input 3.3 v cmos 80 analog sogin input for sync-on-green 0.0 v to 1.0 v 64 analog sync outputs hsout hsync output clock (phase-aligned with datack) 3.3 v cmos 88 both vsout vsync output clock 3.3 v cmos 87 both s o g o u t s y n c - o n - g r e e n slicer output 3.3 v cmos 89 analog r e f e r e n c e s r e f b y p a s s internal re ference bypass 1.25 v 73 analog midbypass internal midscal e voltage bypas s 74 analog pll filter filt connection for external filter c o mponents for internal pll 4 8 a n a l o g power supply v d analog power s u pply 3.15 v to 3.45 v both v dd output power supply 2.2 v to 3.6 v both p v d pll power supply 3.15 v to 3.45 v both gnd g r o u n d 0 v b o t h serial port control sda serial po rt data i/o 3.3 v cmos 78 both scl serial port data clock (100 khz maximum) 3.3 v cmos 77 both a0 serial port addr ess input 3.3 v cmos 76 both
ad9882a rev. 0 | page 8 of 40 pin type mnemonic function value pin number interface data outputs red [7:0 ] outputs of converter red, bit 7 is the msb 3.3 v cmos 92C99 both green [7:0] outputs of converter green, bit 7 is the msb 3.3 v cmos 2C9 both blue [7:0] outputs of converter bue, bit 7 is the msb 3.3 v cmos 12C19 both data clock output datack data output clock for th e analog and digital interface 3.3 v cmos 85 both r x0+ digital input channel 0 true 33 digital digital video data inputs r x0C digital input channel 0 complement 32 digital r x1+ digital input channel 1 true 36 digital r x1C digital input channel 1 complement 35 digital r x2+ digital input channel 2 true 39 digital r x2C digital input channel 2 complement 38 digital r xc+ digital data clock true 41 digital digital video clock inputs r xcC digital data clock complement 42 digital data enable de data enable 3.3 v cmos 86 digital control bits ctl [0:3] decoded cont rol bits 3.3 v cmos 22C25 digital rterm r term sets internal termination resistance 28 digital hdcp ddcscl hdcp slave serial port data clock 3.3 v cmos 53 digital ddcsda hdcp slave serial port data i/o 3.3 v cmos 54 digital mcl hdcp master serial port data clock 3.3 v cmos 81 digital mda hdcp master serial port data i/o 3.3 v cmos 82 digital pin descriptions of shared pins between analog and digital interfaces hsouthorizontal sync output a reconstructed and phase-aligned version of the video hsync. the polarity of this output can be controlled via a serial bus bit. in analog interface mode, the placement and duration are variable. in digital interface mode, the placement and duration are set by the graphics transmitter. vsoutvertical sync output the separated vsync from a composite signal or a direct pass- through of the vsync input. the polarity of this output can be controlled via a serial bus bit. the placement and duration in all modes is set by the graphics transmitter. serial port (2-wire) sdaserial port data i/o sclserial port data clock a0serial port address input for a full description of the 2-wire serial register, refer to the 2-wire serial control register detail section. data outputs reddata output, red channel greendata output, green channel bluedata output, blue channel the main data outputs. bit 7 is the msb. these outputs are shared between the two interfaces and behave in accordance with the active interface. refer to the analog interface and digital interface sections. datackdata output clock just like the data outputs, the data clock output is shared between the two interfaces. it behaves differently depending on which interface is active. refer to the datackdata output clock section to determine how this pin behaves. .
ad9882a rev. 0 | page 9 of 40 table 5. analog interface pin list pin type mnemonic function value pin number analog video inputs r ain analog input for converter r 0.0 v to 1.0 v 70 g ain analog input for converter g 0.0 v to 1.0 v 65 b ain analog input for converter b 0.0 v to 1.0 v 59 external sync/clock hsync horizo ntal sync input 3.3 v cmos 79 vsync vertical sync input 3.3 v cmos 80 sogin sync-on-green input 0.0 v to 1.0 v 64 sync outputs hsout hsync output (phase-aligned with datack) 3.3 v cmos 88 vsout vsync output 3.3 v cmos 87 sogout composite sync 3.3 v cmos 89 voltage reference clamp voltages refby pass internal reference bypass 1.25 v 73 midbypass internal midscale voltage bypass 74 pll filter filt connection for external filter components for internal pll 48 power supply v d main power supply 3.15 v to 3.45 v pv d pll power supply (nominally 3.3 v) 3.15 v to 3.45 v v dd output power supply 2.2 v to 3.6 v gnd ground 0 v pin function detail: analog interface inputs r ain analog input for red channel g ain analog input for green channel b ain analog input for blue channel high impedance inputs that accept the red, green, and blue channel graphics signals, respectively. for rgb, the three channels are identical and can be used for any colors, but colors are assigned for convenient reference. for proper 4:2:2 formatting in a ypbpr application, the y must be connected to the g ain input, the pb must be connected to the b ain input, and the pr must be connected to the r ain input. they accommodate input signals ranging from 0.5 v to 1.0 v full scale. signals should be ac-coupled to these pins to support clamp operation. hsynchorizontal sync input this input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. the logic sense of this pin is controlled by serial register bit 0x10, bit 6 (hsync polarity). only the leading edge of hsync is used by the pll; the trailing edge is used for clamp timing. when hsync polarity = 0, the falling edge of hsync is used. when hsync polarity = 1, the rising edge is active. the input includes a schmitt trigger for noise immunity, with a nominal input threshold of 1.5 v. electrostatic discharge (esd) protection diodes conduct heavily if this pin is driven more than 0.5 v above the maximum tolerance voltage (3.3 v) or more than 0.5 v below ground. vsyncvertical sync input this is the input for vertical sync. soginsync-on-green input this input is provided to assist with processing signals with embedded sync, typically on the green channel. the pin is connected to a high speed comparator with an internally generated threshold, which is set by the value of register 0x0f, bits 7 to 3. when connected to an ac-coupled graphics signal with embedded sync, it produces a noninverting digital output on sogout. when not used, this input should be left unconnected. for more details on this function and how it should be configured, refer to the sync-on-green (sog) section. sogoutsync-on-green slicer output this pin can be programmed to produce either the output from the sync-on-green slicer comparator or an unprocessed but delayed version of the hsync input. see figure 20, the sync processing block diagram, to view how this pin is connected. note that the output from this pin is the composite sync without additional processing from the ad9882a.
ad9882a rev. 0 | page 10 of 40 filtexternal filter connection for proper operation, the pixel clock generator pll requires an external filter. connect the filter as shown in figure 8 to this pin. for optimal performance, minimize noise and parasitics on this node. refbypassinternal reference bypass bypass for the internal 1.25 v band gap reference. it should be connected to ground through a 0.1 f capacitor. the absolute accuracy of this reference is 4%, and the temp- erature coefficient is 50 ppm, which is adequate for most ad9882a applications. if higher accuracy is required, an external reference can be employed instead. midbypassmidscale voltage reference bypass bypass for the internal midscale voltage reference. it should be connected to ground through a 0.1 f capacitor. the exact voltage varies with the gain setting of the red channel. hsouthorizontal sync output a reconstructed and phase-aligned version of the hsync input. the duration of hsync can be programmed only on the analog interface, not the digital. datackdata output clock the data clock output signal is used to clock the output data and hsout into external logic. it is produced by the internal clock generator and is synchronous with the internal pixel sampling clock. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the data bits, datack, and hsout outputs are all moved, so the timing relationship among the signals is maintained. vsoutvertical sync output the separated vsync from a composite signal or a direct pass- through of the vsync input. the polarity of this output can be controlled via register 0x10, bit 2. the placement and duration in all modes is set by the graphics transmitter. reddata output, red channel greendata output, green channel bluedata output, blue channel these are the main data outputs. bit 7 is the msb. the delay from pixel sampling time to output is fixed. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the datack and hsout outputs are also moved, so the timing relationship among the signals is maintained. see the timing diagrams section for more information. power supply v d main power supply these pins supply power to the main elements of the circuit. they should be as quiet as possible. v dd digital output power supply a large number of output pins (up to 25) switching at high speed (up to 140 mhz) generates a lot of power supply transi- ents. these supply pins are identified separately from the v d pins, so special care must be taken to minimize output noise transferred into the sensitive analog circuitry. if the ad9882a is interfacing with lower voltage logic, v dd can be connected to a lower supply voltage (as low as 2.2 v) for compatibility. pv d clock generator power supply the most sensitive portion of the ad9882a is the clock gener- ation circuitry. these pins provide power to the clock pll and help the user design for optimal performance. the designer should provide noise-free power to these pins. gndground the ground return for all circuitry on-chip. it is recommended that the ad9882a be assembled on a single solid ground plane, with careful attention to ground current paths.
ad9882a rev. 0 | page 11 of 40 table 6. interface selection controls aio (0xf bit 2) analog interface detect digital interface detect ais (0x0f, bit 1) active interface description 0 analog force the analog interface active. 1 x x 1 digital force the digital interface active. 0 x none neither interface was detected. both interfaces are powered down. 0 1 x digital the digital interface was detected. power down the analog interface. 1 0 x analog the analog interface was detected. power down the digital interface. 1 1 0 analog both interfaces were detected. the analog interface gets priority. 0 1 digital both interfaces were detected. the digital interface gets priority. table 7. power-down modes, 4:2:2 and 4:4:4 format descriptions mode power- down 1 analog interface detect 2 digital interface detect 3 active interface override active interface select 4:2:2 formatting data sheet signals powered on soft power-down (seek mode) 1 0 0 0 x x serial bus, digital interface clock detect, analog interface clock detect, sog digital interface on 1 0 1 0 x x serial bus; digital interface and analog interface activity detect; sog, band gap reference; red, green, and blue outputs analog interface on 4:4:4 format 1 1 0 0 x 0 serial bus; analog interface and digital interface clock detect; sog, band gap reference; red, green, and blue outputs analog interface on 4:2:2 format 1 1 0 0 x 1 serial bus; analog interface and digital interface clock detect; sog, band gap reference; red and green outputs only serial bus arbitrated interface 1 1 1 1 0 0 same as the analog interface in 4:4:4 mode serial bus arbitrated interface 1 1 1 1 0 1 same as the analog interface in 4:2:2 mode serial bus arbitrated interface 1 1 1 1 1 x same as digital interface mode override to analog interface 1 1 x 1 0 0 same as the analog interface 4:4:4 mode override to analog interface 1 1 x 1 0 1 same as the analog interface 4:2:2 mode override to digital interface 1 x 1 1 1 x same as digital interface mode absolute power- down 0 x x x x x serial bus 1 power-down is controlled via bit 1 in serial bus register 0x14. 2 analog interface detect is determined by oring bits 7, 6, and 5 in serial bus register 0x15. 3 digital interface detect is determined by bit 4 in serial bus register 0x15.
ad9882a rev. 0 | page 12 of 40 theory of operation: interface detection active interface detection and selection the ad9882a includes circuitry to detect whether an interface is active or not (see table 6). for detecting the analog interface, the circuitry monitors the presence of hsync, vsync, and sync-on-green. the result of the detection circuitry can be read from the 2-wire serial interface bus at address 0x15, bits 7, 5, and 6, respectively. if one of these sync signals disappears, the maximum time it takes for the circuitry to detect it is 100 ms. for detecting the digital interface, there are two stages of detection. the first stage searches for the presence of the digital interface clock. the circuitry for detecting the digital interface clock is active even when the digital interface is powered down. the result of this detection stage can be read from the 2-wire serial interface bus at address 0x15, bit 4. if the clock disap- pears, the maximum time it takes for the circuitry to detect it is 100 ms. once a digital interface clock is detected, the digital interface is powered up and the second stage of detection begins. during the second stage, the circuitry searches for 32 consecutive des. once 32 des are found, the detection process is complete. there is an override for the automatic interface selection. it is the aio (active interface override) bit, register 0x0f, bit 2. when the aio bit is set to logic 0, the automatic circuitry is used. when the aio bit is set to logic 1, the ais (active interface select) bit (register 0x0f, bit 1) is used to determine the active interface rather than the automatic circuitry. power management the ad9882a is a dual interface device with shared outputs. only one interface can be used at a time. for this reason, the chip automatically powers down the unused interface. when the analog interface is being used, most of the digital interface circuitry is powered down, and vice versa. this helps to mini- mize the ad9882a total power dissipation. in addition, if neither interface has activity on it, the chip powers down both interfaces. the ad9882a uses the activity detect circuits, the active interface bits in serial register 0x15, the active interface override bits in register 0x0f, bits 2 and 1, and the power-down bit in register 0x14, bit 1, to determine the correct power state. in a given power mode, not all circuitry in the inactive interface is powered down completely. when the digital interface is active, the band gap reference hsync, vsync, and sog detect circuitry remain powered-up. when the analog interface is active, the digital interface clock detect circuit is not powered-down. table 7 summarizes how the ad9882a determines which power mode to be in and which circuitry is powered on/off in each of these modes. the power-down command has priority, then the active interface override, and then the automatic circuitry.
ad9882a rev. 0 | page 13 of 40 theor y of opera tion and design guide: analog interf ace gener a l description the ad9882 a is a f u l l y in t e g r a t ed s o l u tion f o r ca p t ur in g a n alog rgb sig n a l s a nd d i g i t i zi n g t h e m fo r displa y on f l a t p a nel m o ni- t o r s o r p r o j ect o r s . t h e devi ce i s i d eal f o r i m p l em en tin g a co m - pute r i n te r f a c e f o r h d t v monitors or a s t h e f r on t e n d to h i g h p e r f o r ma n c e vi de o s c an con v er t e rs. i m ple m e n t e d i n a hig h p e r f o r ma n c e cmos p r o c es s, t h e i n t e r - face can c a p t ur e sig n als wi th p i xe l ra t e s o f u p t o 140 mh z. the ad9882 a in c l udes al l n e ces s a r y in p u t b u f f er in g, sig n al dc r e sto r a t io n (cl a m p ing), o f fs et a nd ga in ( b r i g h t n ess and co n t r a st) ad j u st m e n t , pixel clo c k ge n e r a t i o n , s a m p l i n g ph as e co n t r o l, an d o u t p u t d a ta f o rm a t ti n g . a l l c o n t r o l s a r e p r o g r a m m a b l e v i a a 2-w i r e s e r i al i n ter f ace . f u l l in te g r a t io n o f t h es e s e n s i t i v e a n alog f u n c tio n s mak e s th e syst em desig n s t ra ig h t fo r w a r d a nd les s s e n s i t i v e t o t h e ph ysical and e l e c t r ical e n vir o nm e n t. w i t h a typ i cal p o w e r dis s i p a t ion o f o n l y 875 mw an d an o p er - a t in g t e m p era t u r e ra n g e o f 0c t o 70c, t h e de v i ce r e q u ir es n o s p eci a l en v i r o nm en tal co n s i d e r a t i o n s . inpu t sig n al handli ng the ad9882 a has thr e e hig h im p e dan c e a n al og in p u t p i n s f o r t h e r e d , g r e e n, and b l ue chan n e l s . t h e y wi l l acc o mm o d a t e sig n als ra n g in g f r o m 0.5 v t o 1.0 v p-p . sig n a l s a r e typ i c a l l y b r o u g h t o n to t h e i n ter f ace b o a r d v i a a d v i-i conne c t or , a 15-p i n d conn e c to r , o r bnc co nne c t o r s. the ad9882 a sh o u ld be lo ca t e d as c l os e as p r ac tical t o the in p u t co nn e c t o r . s i g n als sh o u ld be r o u t e d v i a ma t c h e d- i m p e d a n c e tra c e s (n o r m a ll y 75 ?) t o th e i c i n p u t p i n s . a t tha t p o in t, t h e sig n al sh o u ld be r e sis t i v e l y t e r m ina t e d (75 ? to t h e s i g n a l g r o u nd r e t u r n ) a n d ca p a ci t i vely cou p le d to t h e ad9882a in p u ts thr o ug h 47 nf ca p a ci t o rs. th es e c a p a ci t o rs f o r m p a r t o f th e dc r e s t o r a t io n c i r c ui t (s e e f i gure 9). i n an id e a l w o rl d o f p e r f e c t l y ma tch e d im p e dances, t h e b e st pe rf o r m a n c e c a n be o b ta i n ed w i t h th e w i d e s t po s s i b l e s i gn al ba ndwid th. th e wide band wid t h in p u ts o f t h e ad9882a (300 mh z) can trac k t h e in p u t sig n al co n t in uous l y as i t mo v e s f r om one pi x e l l e vel to t h e ne x t an d d i g i t i z e t h e pi x e l d u r i ng a lo n g , f l a t pixe l t i m e . i n man y sys t em s, h o we v e r , t h er e a r e misma t ch es, r e f l e c t i o n s, an d n o is e , w h ich ca n res u l t i n exces s i v e r i ng i n g a n d d i st or t i on of t h e i n put w a ve f o r m . t h i s m a ke s it m o r e dif f i c u l t to es t a b l ish a s a m p lin g phas e t h a t p r o v ides g o o d ima g e q u ali t y . i t has be e n sh o w n tha t a smal l ind u c t o r in s e r i es wi t h t h e i n p u t i s ef fe c t i v e in r o l l in g o f f t h e in p u t b a ndwi d t h s l i g h t l y a n d p r o v id i n g a hi gh q u ali t y si gn al o v er a w i d e r ra n g e o f co n d i t io n s . u s in g a f a ir -r i t e #2508051217z0 hig h s p ee d sig n al c h i p bead ind u c t o r in t h e cir c ui t o f f i gur e 9 g i v e s g o o d r e su l t s in m o st a p plic a t io n s . 05123-003 rgb input r ain g ain b ain 47nf 75 ? f i gure 3. a n alog in put inter f ac e cir c u i t h s yn c a n d v s yn c i n p u t s the ad9882 a r e cei v es a h o r i zon t al sy n c sig n al a nd us es i t t o gen e r a te t h e pixel clo c k and clam p t i m i ng. t h is ca n b e e i t h er a syn c sig n a l dir e c t l y f r o m th e g r a p hics s o ur ce o r a p r ep r o ces s e d t t l o r cmos le v e l sig n al . the h s y n c in p u t i n cl udes a s c hmi t t t r ig g e r b u f f er a n d is ca p a b l e o f hand lin g sig n als wi t h lo n g r i s e tim e s, wi th s u p e r i o r n o is e im m u n i t y . i n ty p i c a l pc- b as e d g r a p h i c s y st em s, t h e sy n c sig n als a r e sim p l y t t l l e v e l dr iv er s, fe e d in g uns h ie lde d wir e s in t h e m o ni t o r c a ble . a s such, n o ter m ina t io n is r e q u ir e d . serial c o ntr o l port the s e r i al con t r o l p o r t is desig n ed f o r 3.3 v log i c. i f t h er e a r e 5 v dr i v ers o n t h e b u s, t h es e pi n s sh o u ld b e p r o t e c t e d w i t h 150 ? s e r i es r e sis t o r s p l ace d b e tw een t h e p u l l -u p r e sis t o r s a n d th e i n p u t p i n s . outpu t sig n al ha ndl i ng the d i g i t a l o u t p u t s a r e desig n e d a nd sp e c if ie d to o p er a t e f r o m a 3.3 v p o w e r s u p p l y (v dd ). t h e y ca n also w o r k wi th a v dd as lo w as 2.5 v f o r co m p a t i b ili t y wi t h o t h e r 2.5 v log i c. cl amping rgb cla m ping t o p r o p erl y dig i t i ze t h e i n comi n g sig n al , t h e dc o f fs et o f t h e in p u t m u s t b e ad j u s t e d t o f i t t h e ra n g e o f t h e o n - b o a r d ad cs. m o s t g r a p hics s y s t em s p r o d uc e r g b sig n als wi t h b l ac k a t g r o u n d and w h i t e a t a p p r o x ima t e l y 0.75 v . h o w e v e r , if sy n c sig n als a r e em b e dde d i n t h e g r a p hics, t h e sy n c t i p is o f t e n a t g r o u n d , and blac k is a t 300 mv ; whi t e wil l be a p p r o x ima t e l y 1.0 v . s o m e comm on r g b l i ne a m p l if ier bo xes us e emi t t e r - fol l o w er b u f f ers to spli t sig n a l s a nd i n cr e a s e dr ive ca p a b i l i ty . this in tr o d uces a 700 mv dc o f fs et t o t h e sig n a l , which is r e m o v e d b y c l am p i ng f o r p r o p er ca p t ur e b y the ad9882a. the k e y t o cla m p i n g is t o i d en t i f y a p o r t io n (t im e) o f t h e sig n a l w h en t h e g r a p hics sys t em is k n o w n t o b e p r o d ucin g black. or ig ina t in g f r o m cr t di spl a y s , t h e e l e c t r o n b e a m is bla n k e d b y s e ndi n g a b l ack le vel d u r i n g h o r i zon t a l r e t r ac e to p r e v en t dist urb i n g t h e ima g e . m o s t g r a p hics sys t em s ma in tain this fo r m a t o f s e ndi n g a black l e vel b e tw e e n ac t i ve vid e o li n e s.
ad9882a rev. 0 | page 14 of 40 an o f fs et is t h e n i n t r o d uce d , w h ich r e su l t s in t h e ad c p r o d ucin g a bla c k o u t p u t (c o d e 0x00) w h e n t h e k n o w n black in p u t is p r es en t. the o f fs et t h en r e ma in s i n plac e w h en ot h e r sig n a l le vels a r e p r o c ess e d, a nd t h e e n t i r e sig n a l is shif te d to e l im in a t e o f fs et er r o rs. i n sys t e m s wi t h em be dde d sy n c , a b l ack e r - than-b lack sig n al (h syn c ) is p r o d uced b r ief l y t o sig n al t h e c r t t h a t i t is tim e t o b e g i n a re t r a c e. f o r o b v i ou s re a s ons , it i s i m p o r t an t to a v oi d cl am pi ng o n t h e t i p of h s y n c . for tu n a t e ly , t h e r e i s v i r t u a l l y al w a ys a pe ri o d f o ll o w i n g h s yn c c a ll ed th e ba c k po r c h , in wh ic h a go o d black r e fer e n c e is p r o v i d e d . t h is is t h e t i m e w h en cl am pi ng s h ou l d b e d o ne. the clam p t i mi n g is es t a b l i s h e d b y t h e ad988 2a in t e r n al cl am p t i mi n g g e n e ra t o r . the clam p placem e n t r e g i s t er (0x05) is p r og ra mm e d wi th t h e n u m b er o f p i xe l tim e s tha t sh o u ld p a ss af te r t h e t r a i l i ng e d ge of h s y n c b e fore cl am pi ng st ar t s . a s e c o n d r e g i s t er (c la m p d u ra tion, 0x06) s e ts t h e d u ra t i on o f the c l am p . th e s e a r e b o t h 8-b i t val u es, p r o v i d ing co n s ider a b le f l exi b i l i t y i n cl am p ge ne r a t i o n . t h e c l a m p t i m i ng i s re fe re nc e d to t h e t r ai l i n g edg e o f h s yn c, bec a us e t h e back p o r c h (blac k ref e r e n c e) al wa ys fol l o w s h s yn c. a g o o d sta r tin g p o in t fo r es ta bl is hing c l am p i n g is t o s e t t h e clam p place m en t to 0x08 (p r o vidi n g eig h t p i xe l p e r i o d s fo r th e g r a p hics sig n al t o s t a b ilize a f t e r syn c ) an d s e t t h e c l a m p d u ra t i o n t o 0x14 (g i v in g th e clam p 20 p i xe l p e r i o d s t o re e s t a bl i s h t h e b l a c k re f e re nc e ) . the val u e o f t h e ext e r n al in p u t co u p lin g c a p a ci t o r a f fe c t s t h e p e r f o r ma n c e o f t h e clam p . i f t h e val u e is t o o smal l , t h er e can b e an am pl it u d e ch ange d u r i ng a h o r i z o n t a l l i ne t i me ( b e t we e n cl am pi ng i n te r v a l s ) . i f t h e c a p a c i tor i s to o l a rge, t h e n it t a ke s e x c e ss ively l o ng for t h e cl am p t o re c o ve r f r om a l a rge change i n inco ming sig n a l o f fs et. the r e co mmende d va l u e (47 nf ) r e su l t s in r e co v e r y f r o m a st ep er r o r o f 100 mv t o wi t h in on e-half ls b in 30 lin e s , using a c l am p d u r a tio n o f 20 p i xe l p e r i o d s o n a 75 h z s x ga s i g n al . yuv clamping yuv sig n als a r e s l ig h t l y dif f er en t f r o m r g b sig n als in tha t t h e dc r e f e r e n c e le ve l (b lack le ve l in r g b sig n als) is a t t h e mid p o i n t o f th e u a n d v v i deo . f o r th ese si gn als, i t mi gh t be n e ces s a r y t o cla m p t o t h e mi ds cale ran g e o f t h e ad c ra n g e ( 0 x80) ra t h er t h a n t h e b o t t om o f t h e ad c ra n g e (0x00). c l a m pin g to mi ds ca le r a t h er t h a n g r o u nd can b e ac co m p lish e d b y s e t t i n g t h e cl a m p s e le c t b i ts i n t h e s e r i al b u s r e g i s t er . e a ch o f th e th r e e co n v er t e r s h a s i t s o w n s e lecti o n b i t , s o th a t t h ey ca n be cla m p e d to ei t h er mids c a le o r g r o u n d i n de p e nden t ly . t h es e b i ts a r e lo ca t e d in reg i s t er 0x11 a nd a r e b i ts 4 t o 6. the mids cal e r e fer e n c e v o l t a g e t h a t e a ch ad c clam ps t o is p r o v ide d o n t h e midbyp ass p i n (pin 74). t h is p i n sh o u l d b e b y p a ss e d t o g r o u n d wi th a 0 . 1 f ca p a ci t o r (ev e n if mids cal e c l a m p i n g is n o t re qu i r e d ) . gain a n d o ffse t c o nt rol the ad9882 a ca n ac co mm o d a t e in p u t sig n als wi th in p u ts ra n g in g f r o m 0. 5 v t o 1.0 v f u l l s c ale . th e f u l l -s cale ra n g e is s e t in t h r e e 8 - b i t r e g i st ers (r e d ga in , g r e e n ga in, and b l ue ga i n ). a co de o f 0 es t a b l ish e s a minim u m in p u t ra n g e o f 0.5 v ; a co de o f 255 co r r es p o n d s wi th the maxim u m ra n g e o f 1.0 v . n o t e tha t in cr e a s i n g t h e g a in s e t t in g r e su lts in an i m a g e w i t h less co n t rast. the o f fs et co n t rol shif ts t h e e n t i r e in p u t ra n g e , resu l t in g in a cha n g e i n ima g e b r ig h t n e s s . thr e e 7-b i t r e g i s t e r s (r e d o f fs et, g r e e n o f fs et, a nd b l ue o f fs et) p r o v i d e i ndep e n d en t s e t t in gs fo r e a ch chan nel. the o f fs et co n t rols p r o v ide a 6 3 ls b ad j u s t m e n t ra n g e . this ra n g e is co nne c t e d wi t h t h e f u l l -s cal e ra n g e , s o if t h e i n p u t ra n g e is do u b le d (f r o m 0.5 v t o 1.0 v), t h e o f fs et s t ep s i ze is als o do ub le d (f r o m 2 mv p e r step to 4 mv p e r step ). f i gur e 4 i l l u st r a tes t h e i n ter a c t i o n o f ga in and o f fs et co n t r o ls. t h e m a g n itu d e of an l s b i n of f s e t a d j u st me n t i s prop or t i on a l to th e full -sc a le ra n g e , so c h a n gin g th e full -sc a le ra n g e al so cha n g e s t h e o f fs et. th e cha n g e i s minimal if t h e o f fs et s e t t in g is n e a r mids cale . w h en cha n g i n g t h e o f fs et, t h e f u l l -s cale ran g e i s n o t a f fe c t e d , b u t t h e f u l l -s c a le l e v e l is shif t e d b y t h e s a m e a m o u n t as t h e zer o -s cale l e v e l . 05123-004 1. 0 v 0. 5 v 0. 0 v inp u t range gain 0x00 0xff offset = 0 x3f o f f s e t =0 x 7 f o f f s e t = 0 x 0 0 o f f s e t = 0 x 3 f o f f s e t = 0 x 7 f o f f s e t = 0 x 0 0 f i g u re 4. g a in and o f f s et cont r o l
ad9882a rev. 0 | page 15 of 40 sy nc- o n- g r een (sog ) the sy n c -on-g r e e n i n p u t op era t es in tw o st eps. f i rs t, i t s e ts a bas e l i n e c l a m p l e v e l o f f o f th e inco min g video sig n al wi t h a ne g a t i ve p e a k d e te c t or . s e c o nd, i t s e t s t h e s y nc t r i g ge r l e vel (n o m inal l y 150 mv abo v e t h e nega ti v e p e a k ). th e exac t tr ig g e r le vel is v a r i ab le a nd can b e p r o g r a mm e d vi a re g i ster 0x 0f , b i ts 7 t o 3. th e syn c -on-g r een in p u t m u s t be ac -co u p l ed t o t h e g r e e n a n a l o g in p u t t h r o ug h i t s o w n c a p a ci to r a s sho w n in f i gur e 5. th e va l u e o f th e ca p a c i t o r m u s t be 1 nf 20%. i f sy n c - o n -g r e en is n o t us e d , t h is co n n e c t i o n is n o t r e quir e d an d so gin sh o u l d be lef t u n co nn e c t e d . n o t e tha t t h e sy n c -o n- gr ee n s i gn al i s al w a ys n e g a ti v e po l a ri t y . s e e th e s y n c p r oc e s s i n g en gin e sec t io n fo r f u r t h e r in f o rma t io n. 05123-005 g ain sogin 1nf r ain 47nf b ain 47nf 47nf f i g u re 5. t y pic a l cl amp conf ig ur at i o n cl ock gen e r a tion a p h as e-lo ck ed lo o p (p ll) is em p l o y ed t o g e nera t e t h e p i xe l clo c k. th e h s y n c i n p u t p r o v ides a r e fer e n c e f r e q uen c y fo r t h e p l l . a v o l t a g e c o n t r o ll ed osc i lla t o r (v co ) g e n e ra t e s a m u c h hig h er p i xe l c l o c k f r eq uen c y . this p i xe l c l o c k is divided b y t h e p ll di vide val u e (reg ist e rs 0x01 a nd 0x02) a n d p h as e co m- p a r e d w i t h t h e h s yn c i n p u t. a n y er r o r is us e d t o s h if t t h e v c o f r eq ue n c y a n d m a i n ta in l o c k b e t w een t h e t w o s i gn al s . the st ab i l i t y o f t h is clo c k is a ve r y im p o r t a n t ele m e n t i n p r o v i d - i n g t h e cl e a re s t an d mo st st abl e i m age . d u r i ng e a ch pi xel t i me, t h er e is a p e r i o d d u r i n g w h ich t h e sig n a l is sl e w in g f r o m t h e old p i xe l a m pl i t u d e a nd s e t t l i n g a t i t s ne w v a l u e . then t h er e is a tim e w h en t h e in p u t v o l t a g e is sta b le , bef o r e the sig n al m u s t s l e w t o a n e w va l u e (f igur e 6). th e ra t i o o f t h e s l e w in g t i m e t o t h e s t a b le t i m e i s a fu n c ti o n o f th e b a n d w i d th o f t h e gr a p h i c s d a c and t h e ban d wid t h o f t h e t r a n smis sio n syst em (c a b le and t e r m in a t io n). i t is a l s o a f u n c t i o n o f t h e o v era l l p i xe l ra te . c l e a rl y , if t h e dyna mic cha r ac ter i s t ics o f t h e sys t em r e main f i x e d, t h e n t h e s l e w i n g a n d s e tt l i ng t i m e i s l i k e w i s e f i x e d. t h i s tim e m u st b e s u b t rac t e d f r o m t h e t o tal p i xe l p e r i o d , le a v in g t h e s t a b le p e r i o d . a t hig h er p i xe l f r e q uen c ies, t h e to tal c y c l e tim e is shor te r , and t h e st abl e pixel t i me b e c o me s s h or te r as wel l . 05123-006 pixel clock invalid sample times f i g u re 6. pix e l s a m p ling ti mes an y j i t t e r in t h e clo c k r e d u ces t h e p r e c isio n w i t h w h ich t h e s a m p ling t i m e c a n b e de ter m i n e d an d m u st a l s o b e sub t r a c t e d f r o m th e s t a b le p i xe l tim e . c o n s iderab le car e has b e e n t a k e n i n t h e des i g n o f t h e ad9882a s c l o c k g e nera tion circ ui t t o minimize ji t t er . a s indica t e d in f i g u r e 7, th e c l o c k ji t t er o f t h e ad9882a is les s th a n 6% o f th e t o tal p i x e l t i m e in all o p e r a t i n g m o d e s, m a k i n g n e g l ig i b le t h e r e d u c t io n in t h e v a lid s a m p li n g t i m e d u e t o ji t t er . 10 8 6 4 2 0 25.1 31.5 36.0 40.0 50.0 56.2 65.0 75.0 78.7 85.5 94.5 108.0 135.0 05123-007 pixel clock frequency (mhz) p i x e l clo ck j i tte r (p-p) (% ) f i g u re 7. pix e l c l oc k jit t e r v s . f r equen c y the p ll cha r ac t e r i s t ics a r e de t e r m ine d b y t h e l o o p f i l t er desig n , t h e p ll cha r g e p u m p c u r r en t, and t h e v c o ra ng e s e t t ing. the lo o p f i l t er desig n is i l l u st r a te d i n f i gur e 8. re c o mm e nde d s e t t in gs o f v c o ra n g e a nd cha r g e p u m p c u r r en t fo r vesa st anda r d displ a y m o des a r e li ste d i n t a b l e 10. 05123-008 c p 0.0082 f c z 0.082 f r z 2.74k ? filt pv d f i g u re 8. pll l oop f ilt er d e t a i l
ad9882a rev. 0 | page 16 of 40 four programmable registers are provided to optimize the performance of the pll. these registers are 1. the 12-bit divisor register (registers 0x01 and 0x02). the input hsync frequencies range from 15 khz to 110 khz. the pll multiplies the frequency of the hsync signal, producing pixel clock frequencies in the range of 12 mhz to 140 mhz. the divisor register controls the exact multiplication factor. this register can be set to any value between 221 and 4095. the divide ratio that is actually used is the programmed divide ratio plus one. 2. the 2-bit vco range register (register 0x03, bits 6 and 7). to improve the noise performance of the ad9882a, the vco operating frequency range is divided into three overlapping regions. the vco range register sets this operating range. the frequency ranges for the lowest and highest regions are shown in table 8. 3. the 3-bit charge pump current register (register 0x03, bits 3 to 5). this register allows the current that drives the low-pass loop filter to be varied. the possible current values are listed in table 9. 4. the 5-bit phase adjust register (register 0x04, bits 3 to 7). the phase of the generated sampling clock can be shifted to locate an optimum sampling point within a clock cycle. the phase adjust register provides 32 phase-shift steps of 11.25 each. the hsync signal with an identical phase shift is available through the hsout pin. table 8. vco frequency ranges pv1 pv0 pixel clock range (mhz) 0 0 12C41 0 1 41C82 1 0 82C140 table 9. charge pump current/control bits ip2 ip1 ip0 current (a) 0 0 0 50 0 0 1 100 0 1 0 150 0 1 1 250 1 0 0 350 1 0 1 500 1 1 0 750 1 1 1 1500 the coast function allows the pll to continue to run at the same frequency, in the absence of the incoming hsync signal or during disturbances in hsync (such as equalization pulses). this can be used during the vertical sync period, or any other time that the hsync signal is unavailable. also, the polarity of the hsync signal can be set through the hsync polarity bit (register 0x10, bit 6). if not using automatic polarity detection, the hsync polarity bit should be set to match the polarity of the hsync input signal. table 10. recommended vco range and charge pump current settings for standard display formats standard refresh resolution horizontal rate (hz) frequency (khz) pixel rate (mhz) vcornge current vga 640 480 60 31.500 25.175 00 101 72 37.700 31.500 00 101 75 37.500 31.500 00 101 85 43.300 36.000 00 110 svga 800 600 56 35.100 36.000 00 101 60 37.900 40.000 00 110 72 48.100 50.000 01 101 75 46.900 49.500 01 101 85 53.700 56.250 01 101 xga 1024 768 60 48.400 65.000 01 101 70 56.500 75.000 01 110 75 60.000 78.750 01 110 80 64.000 85.500 10 101 85 68.300 94.500 10 101 sxga 1280 1024 60 64.000 108.000 10 101 75 80.000 135.000 10 110 tv modes 480i 60 15.750 13.500 00 001 480p 60 31.470 27.000 00 100 720p 60 45.000 74.500 01 101 1080i 60 33.750 74.500 01 101
ad9882a rev. 0 | page 17 of 40 timing: analog interf ace the fol l o w in g t i min g dia g ra ms s h o w t h e op era t io n o f t h e ad9882a. th e o u t p u t da t a c l o c k sig n al is cr ea ted s o tha t i t s r i sin g e d ge a l wa y s o c c u rs b e tw e e n da t a t r a n si t i o n s a nd can b e u s e d to l a tc h t h e out p ut da t a e x te r n a l ly . t per t dcycle t skew datack data hsout t skew 05123-009 fi g u r e 9 . o u t p u t t i m i n g hsync timing h o r i zon t al sy n c (h syn c ) is p r o c es s e d in t h e ad9882a t o e l im in a t e am b i g u i t y i n t h e t i m i n g o f t h e l e ad ing e d ge wi t h r e sp e c t t o t h e phas e- dela ye d pi xel clo c k an d d a t a . t h e h s y n c in p u t is us e d as a r e fer e n c e t o gen e ra t e t h e pixel s a m p ling clo c k . the s a m p l i n g phas e can b e ad j u s t e d , wi t h r e sp e c t t o h s yn c, t h r o ug h a f u l l 3 60 in 32 st eps v i a t h e phas e ad j u s t r e g i s t er (reg ist e r 0x04) t o o p timize t h e p i xe l s a m p l i n g t i me . dis p la y sys t em s us e h s y n c t o al ig n m e m o r y a n d dis p l a y wr i t e c y cles, s o i t is im p o r t a n t to ha v e a sta b le t i min g r e l a tio n shi p betw een h s yn c o u t p u t ( h so ut ) a nd da ta c l o c k (d a t a c k). thr e e thin gs ha p p en t o h o r i zo n t al sy n c in t h e ad9882a. f i rs t, t h e p o la r i ty o f h s yn c i n p u t is det e r m i n e d and t h er efo r e has a k n ow n output p o l a r i t y . t h e k n ow n output p o l a r i t y c a n b e p r og ra mm ed ei t h er ac ti ve hig h o r ac ti v e lo w ( r eg is t e r 0x10, bi t 5). s e con d , hsou t is a l ig ne d wi t h d a t a c k an d d a t a output s . t h i r d, t h e d u r a t i on of h s ou t ( i n pi x e l cl o c k s ) i s s e t via reg i s t er 0x07. hso u t is t h e syn c sig n al tha t sh o u ld b e us e d t o dr i v e t h e r e st o f t h e dis p l a y sys t em. coast timing i n m o s t com p uter sys t em s, t h e h s yn c sig n al is p r o v ide d co n t i n uo us l y o n a de dic a t e d wire . i n t h es e sys t e m s, t h e co ast f u n c t i o n i s unn e cess a r y a nd sh o u ld b e di s a b l e d usin g reg i st er 0x11, b i ts 1 t o 3. i n s o me sys t ems, h o we v e r , h s y n c is dis t urbe d d u r i n g t h e v e r t i- cal sy n c p e r i o d (vsyn c ). i n o t her cas e s, h s y n c p u ls es dis a p p e a r . i n o t h e r sys t ems, s u c h as t h os e tha t em p l o y co m p osi t e sy n c (csyn c ) sig n als o r em be dde d sy n c -on-g r e e n (s o g ), h s yn c i n c l u d e s e q u a l i z a t i on pu l s e s or ot he r d i stor t i on s d u r i ng v s y n c . t o a v o i d u p set t in g t h e c l o c k g e n e ra t o r d u r i n g vsyn c, i t is im p o r t an t t o ig n o r e t h es e dist o r t i o n s. i f t h e p i xe l clo c k p ll s e e s ext r a n e o us p u ls es, i t a t tem p ts to lo ck t o t h is n e w f r e q uen c y a nd has cha n g e d f r e q uen c y b y t h e e nd o f t h e vsy n c p e r i o d . i t t h en tak e s a f e w lin e s o f co rr ect h s yn c ti m i n g t o r e co v e r a t t h e beg i nnin g o f a new f r a m e , r e s u l t in g in a t e a r ing o f th e ima g e a t th e t o p o f th e d i s p la y . the co ast f u n c t i o n is p r o v i d e d to e l im ina t e t h is p r ob lem. i t is an i n te r n a l ly ge ne r a te d s i g n a l , c r e a te d b y t h e s y nc pro c e s s i ng en g i n e t h a t dis a b l es t h e p ll in pu t a nd al lo ws t h e clo c k t o f r e e - r u n a t i t s t h en-c ur r e n t f r eq uen c y . th e p l l can f r ee-r un f o r s e v e ra l l i n e s wi t h o u t s i g n if ican t f r e q uen c y dr if t.
ad9882a rev. 0 | page 18 of 40 timing dia g r a ms 05123-010 rgbin hsync pxck hs adcck datack dataout hsout variable duration d0 d1 d2 d3 d4 d5 d6 d7 p0 p1 p2 p3 p4 p5 p6 p7 5-pipe delay f i g u re 10. 4: 4: 4 m o de (f or r g b and y p bp r) rgbin hsync pxck hs adcck datac k gouta y0 y1 y2 y3 y4 y5 y6 y7 routa pb0 pr0 pb2 pr2 pb4 pr4 pb6 pr6 p0 p1 p2 p3 p4 p5 p6 p7 5-pipe delay 05123-011 hsout variable duration f i g u re 11. 4: 4: 2 m o de (f or yp bpr o n ly )
ad9882a rev. 0 | page 19 of 40 theory of operation: digital interface table 11. digital interface pin list pin type mnemonic function value pin number r x0+ digital input channel 0 true 33 digital video data inputs r x0C digital input channel 0 complement 32 r x1+ digital input channel 1 true 36 r x1C digital input channel 1 complement 35 r x2+ digital input channel 2 true 39 r x2C digital input channel 2 complement 38 r xc+ digital data clock true 41 digital video clock inputs r xcC digital data clock complement 42 termination control r term control pin for setting the internal termination resistance 28 outputs de data enable 3.3 v cmos 86 hsout hsync output 3.3 v cmos 88 vsout vsync output 3.3 v cmos 87 ctl0, ctl1, ctl2, ctl3 decoded control bit outputs 3.3 v cmos 22C25 hdcp ddcscl hdcp slave serial port data clock 3.3 v cmos 53 ddcsda hdcp slave serial port data i/o 3.3 v cmos 54 mcl hdcp master serial port data clock 3.3 v cmos 81 mda hdcp master serial port data i/o 3.3 v cmos 82 power supply v d main power supply 3.15 v to 3.45 v pv d pll power supply 3.15 v to 3.45 v v dd output power supply 2.2 v to 3.6 v gnd ground supply 0 v digital interface pin descriptions digital data inputs r x0+ positive differential input data (channel 0) r x0C negative differential input data (channel 0) r x1+ positive differential input data (channel 1) r x1C negative differential input data (channel 1) r x2+ positive differential input data (channel 2) r x2C negative differential input data (channel 2) these six pins receive three pairs of differential, low voltage swing input pixel data from a dvi transmitter. digital clock inputs r xc+ positive differential input clock r xcC negative differential input clock these two pins receive the differential, low voltage swing input pixel clock from a dvi transmitter. termination control r term internal termination set pin this pin is used to set the termination resistance for all of the digital interface high speed inputs. to set, place a resistor of value equal to 10 the desired input termination resistance between this pin (pin 28) and ground supply. typically, the value of this resistor should be 500 ?. outputs dedata enable output this pin outputs the state of data enable (de). the ad9882a decodes de from the incoming stream of data. the de signal is high during active video and is low while there is no active video. ddcsclhdcp slave serial port data clock used for communicating with the hdcp-enabled dvi transmitter. ddcsdahdcp slave serial port i/o for use in communicating with the hdcp-enabled dvi transmitter.
ad9882a rev. 0 | page 20 of 40 mclhdcp master serial port data clock connects to the eeprom for reading the encrypted hdcp keys. mdahdcp master serial port data i/o connects to the eeprom for reading the encrypted hdcp keys. ctldigital control outputs these pins output the control signals for the red and green channels. ctl0 and ctl1 correspond to the red channels input, while ctl2 and ctl3 correspond to the green channels input. power supply v d main power supply it should be as quiet as possible. pv d pll power supply it should be as quiet as possible. v dd outputs power supply the power for the data and clock outputs. it can run at 3.3 v or 2.5 v. gndground the ground return for all circuitry on the device. it is recom- mended that the application circuit board have a single, solid ground plane. capturing the encoded data the first step in recovering the encoded data is to capture the raw data. to accomplish this, the ad9882a employs a high speed phase-locked loop (pll) to generate clocks capable of over sampling the data at the correct frequency. the data capture circuitry continuously monitors the incoming data during horizontal and vertical blanking times (when de is low) and selects the best sampling phase for each data channel independently. the phase information is stored and used until the next blanking period (one video line). data frames the digital interface data is captured in groups of 10 bits each, which are called data frames. during the active data period, each frame is made up of the nine encoded video data bits and one dc-balancing bit. the data capture block receives this data serially but outputs each frame in parallel 10-bit words. special characters during periods of horizontal or vertical blanking time (when de is low), the digital transmitter transmits special characters. the ad9882a receives these characters and uses them to set the video frame boundaries and the phase recovery loop for each channel. there are four special characters that can be received. they are used to identify the top, bottom, left side, and right side of each video frame. the data receiver can differentiate these special characters from active data because the special characters have a different number of transitions per data frame. channel resynchronization the purpose of the channel resynchronization block is to resynchronize the three data channels to a single internal data clock. coming into this block, all three data channels can be on different phases of the 3 oversampling pll clock (0, 120, and 240). this block can resynchronize the channels from a worst- case skew of one full input period (8.93 ns at 112 mhz). data decoder the data decoder receives frames of data and sync signals from the data capture block (in 10-bit parallel words) and decodes them into groups of eight rgb bits, two control bits, and a data enable bit (de). hdcp the ad9882a contains all the circuitry necessary for decryption of a high bandwidth digital content protection encoded dvi video stream. a typical hdcp implementation is shown in figure 12. several features of the ad9882a make this possible and add functionality to ease the implementation of hdcp. the basic components of hdcp are included in the ad9882a. a slave serial bus connects to the ddc clock and ddc data pins on the dvi connector to allow the hdcp-enabled dvi transmitter to coordinate the hdcp algorithm with the ad9882a. a second serial port (mda/mcl) allows the ad9882a to read the hdcp keys and key selection vector (ksv) stored in an external serial eeprom. when transmitting encrypted video, the dvi transmitter enables hdcp through the ddc port. the ad9882a then decodes the dvi stream using information provided by the transmitter, hdcp keys, and ksv. the ad9882a allows the mda and mcl pins to be three- stated using the mda/mcl three-state bit (register 0x1b, bit 7) in the configuration registers. the three-state feature allows the eeprom to be programmed in-circuit. the mda/mcl port must be three-stated before attempting to program the eeprom using an external master. the keys will be stored in an i 2 c? compatible 3.3 v serial eeprom of at least 512 bytes in size. the eeprom should have a device address of 0xa0. proprietary software licensed from analog devices encrypts the keys and creates properly formatted eeprom images for use in a production environment. encrypting the keys helps maintain
ad9882a rev. 0 | page 21 of 40 th e co n f i d en tiali t y o f t h e h d cp k e ys a s r e q u i r ed b y th e hd cp v . 1.0 s p ecif ica t ion. the ad9882a inc l u d es ha r d wa r e f o r d e cr yp ti n g t h e k e ys i n th e ext e r n al eep r o m. ad i p r o v i d es a r o yal t y-f r e e lice n s e fo r t h e p r o p r i et a r y s o f t wa r e n e e d ed b y c u s t om ers t o en cr yp t th e keys b e tw e e n t h e ad9882 a a nd t h e eep r o m o n l y a f t e r c u s t om ers p r o v i d e e v i de n c e o f a co m p let e d hd cp ado p t e r s lic e n s e a g r e e m en t a nd sig n ad i s s o f t w a re l i c e n s e ag re e m e n t . t h e a d opte r s l i c e n s e ag re e m e n t i s ma in t a i n e d b y dig i t a l c o n t e n t pr o t e c t i o n , llc , a nd can b e do wn lo ade d f r o m w w w . dig i t a l - c p .co m . t o o b t a in adi s s o f t w a re l i c e n s e ag re e m e n t , c o n t a c t t h e d i sp l a y e l e c t r on i c s pro d u c t l i ne d i re c t ly b y s e nd i n g an e m ai l to f l a t p a ne l_a p ps@a nalog.com. 05123- 012 ddc clock dvi connector ddc data dvi-vcc scl sda eeprom 3.3v 5k ? pull-up resistors 150 ? series resistor 10k ? pull-up resistor ddc scl ddc sda ad9882a mcl mda 3.3v s d 3.3v 5k ? pull-up resistors f i gure 1 2 . h d c p i m pl em ent a ti on usi n g the ad98 82 a
ad9882a rev. 0 | page 22 of 40 gener a l timing dia g r a ms: digit a l interf a c e 05123-013 rx0 rx1 rx2 v diff = 0v v diff = 0v t ccs f i gure 1 3 . di g i ta l o u tput r i se and f a l l t i m e s 05123-014 t cip , r cip t cil , r cil t cih , r cih f i gure 1 4 . clo c k c y cl e hi gh/l o w tim e s 05123-015 rx0 rx1 rx2 v diff = 0v v diff = 0v t ccs f i gure 15. channe l-to - c hann el sk ew t i ming timing mode dia g r a ms: digit a l interf a c e 05123-016 internal odclk datack de first pixel tst second pixel third pixel fourth pixel dataout f i g u re 16. dv i cl k i n ver t = 1 (r eg is t e r 14, bit 4) 05123-017 first pixel second pixel third pixel fourth pixel internal odclk datack de dataout tst f i g u re 17. dv i cl k i n ver t = 0 (r eg is t e r 14, bit 4)
ad9882a rev. 0 | page 23 of 40 2-wire serial register map the ad9882a is initialized and controlled by a set of registers that determines the operating modes. an external controller is employed to write and read the control registers through the 2-wire serial interface port. table 12. control register map hexadecimal address read and write or read only bit default value register name function 0x00 ro 7C0 chip revisions an 8-bit register that represents the silicon level. 0x01 r/w 7C0 0110 1001 pll div msb this register is for bits [11:4] of the pll divider. larger values mean the pll operates at a faster rate. this register should be loaded first whenever a change is needed. (this will give the pll more time to lock.) 1 0x02 r/w 7C4 1101 **** pll div lsb bits [3:0] lsbs of the pll divide r word. links to pll msb to make a 12-bit register. 1 0x03 r/w 7C6 01** **** vco range selects vco frequency range. 5C3 **00 1*** charge pump varies the current that drives the pll loop filter. 0x04 r/w 7C3 1000 0*** phase adjust adc clock phase adjustment. larg er values mean more delay (1 lsb = t/32). 0x05 r/w 7C0 0000 1000 clamp placement places the clamp signal an integer number of clock periods after the trailing edge of hsync. 0x06 r/w 7C0 0001 0100 clamp duration number of clock periods that the clamp signal is actively clamping. 0x07 r/w 7C0 0010 0000 hsync output pulse width sets the number of pixel clocks that hsout will remain active. 0x08 r/w 7C0 1000 0000 red gain controls the adc input range (con trast) of the red channel. larger values give less contrast. 0x09 r/w 7C0 1000 0000 green gain controls the adc input range (con trast) of the green channel. larger values give less contrast. 0x0a r/w 7C0 1000 0000 blue gain controls the adc input range (con trast) of the blue channel. larger values give less contrast. 0x0b r/w 7C1 1000 000* red offset controls the dc offset (brightness) of the red channel. larger values decrease brightness. 0x0c r/w 7C1 1000 000* green offset controls the dc offset (brightness) of the green channel. larger values decrease brightness. 0x0d r/w 7C1 1000 000* blue offset controls the dc offset (brightn ess) of the blue channel. larger values decrease brightness. 0x0e r/w 7C0 0010 0000 sync separator threshold sets how many pixel clocks to co unt before toggling high or low. this should be set to some nu mber greater than the maximum hsync or equalization pulsewidth. 0x0f r/w 7C3 0111 1*** sync-on-green threshold sets the voltage level of the sy nc-on-green slicers comparator. 2 **** *0** active interface override 0 = no override. 1 = user overrides, interface set by 0x0f, bit 1. 1 **** **0* active interface select 0 = analog interface active. 1 = digital interface active. this interface is selected only if regi ster 0x0f, bit 2 is set to 1, or if both interfaces are active. 0x10 r/w 7 0*** **** hsync polarity override 0 = polarity determined by chip. 1 = polarity set by 0x10, bit 6. 6 *1** **** input hsync polarity 0 = active low polarity. 1 = active high polarity. 5 **0* **** output hsync polarity 0 = active high sync signal. 1 = active low sync signal.
ad9882a rev. 0 | page 24 of 40 hexadecimal address read and write or read only bit default value register name function 4 ***0 **** active hsync override 0 = no override. 1 = user overrides, analog hsync set by 0x10, bit 3. 3 **** 0*** active hsync select 0 = analog hsync from the hsync input pin. 1 = analog hsync from sog. this bi t is used if register 0x10, bit 4 is set to 1 or if both syncs are active. 2 **** *0** output vsync polarity 0 = invert. 1 = not inverted. 1 **** **0* active vsync override 0 = no override. 1 = user overrides, analog vsync set by 0x10, bit 0. 0 **** ***0 active vsync select 0 = analog vsync from the vsync input pin. 1 = analog vsync from sync separator. 0x11 r/w 7 0*** **** clamp function 0 = clamping with internal clamp. 1 = clamping disabled. 6 *0** **** red clamp select 0 = clamp to ground. 1 = clamp to midscale for red channel. 5 **0* **** green clamp select 0 = clamp to ground. 1 = clamp to midscale for green channel. 4 ***0 **** blue clamp select 0 = clamp to ground. 1 = clamp to midscale for blue channel. 3 **** 1*** coast select 0 = disabled coast. 1 = coasting with internally generated coast signal. 2 **** *0** coast polarity override 0 = coast polarity determined by the chip. 1 = coast polarity set by 0x11, bit 1. this bit must be set to 1 to disable coast. 1 **** **1* input coast polarity 0 = active low coast signal. 1 = active high coast signal. this bit must be set to 1 to disable coast. 0x12 r/w 7C0 0000 0000 precoast number of hsync pe riods that coast goes active prior to vsync. 0x13 r/w 7C0 0000 0000 postcoast number of hsync periods before coast goes inactive following vsync. 0x14 r/w 7C6 11** **** output drive select selects among high, medium, and low output drive strength. 5 **1* **** programmable bandwidth 0 = low bandwidth of 10 mhz. 1 = high bandwidth of 300 mhz. 4 ***0 **** dvi clock invert 0 = dvi data clock output not inverted. 1 = dvi data clock output inverted. for digital interface only. 3 **** 0*** dvi pdo three- state 0 = normal outputs. 1 = high impedance outputs. 2 **** *0** hdcp address address bit 0 = 0 for hdcp slave port. address bit 1 = 1 for hdcp slave port. 1 **** **1* power-down 0 = full chip power-down. 0 **** ***0 enable 4:2:2 0 = 4:4:4 mode. 1 = 4:2:2 mode. 0x15 ro 7 analog hsync active 0 = hsync not detected. 1 = hsync detected. 6 analog sog active 0 = sync signal not detected on green channel. 1 = sync signal detected on green channel. 5 analog vsync active 0 = vsync not detected. 1 = vsync detected. 4 dvi active 0 = digital interface clock not detected. 1 = digital interface clock detected. 3 active interface 0 = analog interface active. 1 = dvi interface active.
ad9882a rev. 0 | page 25 of 40 hexadecimal address read and write or read only bit default value register name function 0x16 ro 7 active hsync 0 = hsync from the hsync input pin. 1 = hsync from the sog input. 6 hsync polarity detected 0 = active low polarity detected. 1 = active high polarity detected. 5 active vsync 0 = vsync from the vsync input pin. 1 = vsync from sog. 4 vsync polarity detected 0 = active high polarity detected. 1 = active low polarity detected. 3 coast polarity detected 0 = active low polarity detected. 1 = active high polarity detected. this function works only with internal coast. 2 hdcp keys detected 0 = not detected. 1 = detected. 0x17 r/w 7C0 0000 0000 test register must be set to 1000 0000 for proper operation. 0x18 r/w 7C0 0000 000x test register must be set to 1100 000x for proper operation. 0x19 r/w 7C0 0000 010x test register must be set to 0111 110x for proper operation. 0x1a r/w 7C0 0011 1111 test register must be set to default for proper operation. 0x1b r/w 7 1*** **** mda and mcl 0 = mda and mcl three-stated. 1 = mda and mcl not three-stated. 6C0 *111 0000 test register must be set to *110 0111 for proper operation. 0x1c r/w 7C1 0000 111* test register must be set to default for proper operation. 0 **** ***1 rxc connect 0 = rx clock lines disconnected. 1 = rx clock lines connected. 0x1d ro 7C0 test register reserved for future use. 0x1e ro 7C0 test register reserved for future use. 1 the ad9882a updates the pll divi de ratio only when the lsbs are written to register 0x02.
ad9882a rev. 0 | page 26 of 40 2-wire serial control register detail chip identification 0x00 7C0 chip revision an 8-bit register that represents the silicon revision. pll divider control 0x01 7C0 pll divide ratio msbs the eight most significant bits of the 12-bit pll divide ratio plldiv. (the operational divide ratio is plldiv + 1.) the pll derives a pixel clock from the incoming hsync signal. the pixel clock frequency is then divided by an integer value, such that the output is phase-locked to hsync. this plldiv value determines the number of pixel times (pixels plus hori- zontal blanking overhead) per line. this is typically 20% to 30% more than the number of active pixels in the display. the 12-bit value of the pll divider supports divide ratios from 221 to 4095. the higher the value loaded in this register, the higher the resulting clock frequency with respect to a fixed hsync frequency. vesa has established some standard timing specifications that can assist in determining the value for plldiv as a function of the horizontal and vertical display resolution and frame rate (see table 10). however, many computer systems do not con- form precisely to the recommendations, and these numbers should be used only as a guide. the display system manu- facturer should provide automatic or manual means for optimizing plldiv. an incorrectly set plldiv usually produces one or more vertical noise bars on the display. the greater the error, the greater the number of bars produced. the power-up default value of plldiv is 1693 (plldivm = 0x69, plldivl = 0xdx). the ad9882a updates the full divide ratio only when the lsbs are changed. writing to this register by itself does not trigger an update. 0x02 7C4 pll divide ratio lsbs the four least significant bits of the 12-bit pll divide ratio plldiv. the operational divide ratio is plldiv + 1. the power-up default value of plldiv is 1693 (plldivm = 0x69, plldivl = 0xdx). the ad9882a updates the full divide ratio only when this register is written. 0x03 7C6 vco range select two bits that establish the operating range of the clock generator. vcornge must be set to correspond with the desired operating frequency (incoming pixel rate). the pll vco gives the best jitter performance while operating at high frequencies. for this reason, to output low pixel rates and still get good jitter performance, the pll vco actually operates at a higher frequency but then divides down the clock rate afterward. table 13 shows the pixel rates for each vco range setting. the pll output divisor is automatically selected with the vco range setting. table 13. vco ranges vcornge pixel rate range 00 12C41 01 41C82 10 82C140 the power-up default value is vcornge = 01. 0x03 5C3 current charge pump current three bits that establish the current driving the loop filter in the clock generator. table 14. charge pump currents charge pump current (a) 000 50 001 100 010 150 011 250 100 350 101 500 110 750 111 1500 charge pump must be set to correspond with the desired operating frequency (incoming pixel rate). see table 10 for the charge pump current for each register setting. the power-up default value for current is 001. 0x04 7C3 phase adjust a 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. each step represents an 11.25 shift in sampling phase. the power-up default phase adjust value is 0x10.
ad9882a rev. 0 | page 27 of 40 clamp timing 0x05 7C0 clamp placement an 8-bit register that sets the position of the internally generated clamp. when clamp function (register 0x11, bit 7) is 0, a clamp signal is generated internally at a position established by the clamp placement and for a duration set by the clamp duration. clamping is started (clamp placement) an integral number of pixel periods after the trailing edge of hsync. the clamp placement can be programmed to any value from 1 to 255. the clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between hsync and the image. when clamp function is 1, this register is ignored. 0x06 7C0 clamp duration an 8-bit register that sets the duration of the internally generated clamp. for the best results, the clamp duration should be set to include the majority of the black-reference signal time that follows the hsync signal trailing edge. insufficient clamping time can pro- duce brightness changes at the top of the screen and a slow recovery from large changes in the average picture level (apl) or brightness. when clamp function is 1, this register is ignored. hsync output pulse width 0x07 7C0 hsync output pulse width an 8-bit register that sets the duration of the hsync output pulse. the leading edge of the hsync output is triggered by the internally generated, phase-adjusted pll feedback clock. the ad9882a then counts a number of pixel clocks equal to the value in this register minus one. this triggers the trailing edge of the hsync output, which is also phase-adjusted. input gain 0x08 7C0 red gain red gain an 8-bit word that sets the gain of the red channel. the ad9882a can accommodate input signals with a full-scale range of between 0.5 v and 1.0 v p-p. setting red gain to 255 corresponds to an input range of 1.0 v. a red gain of 0 establishes an input range of 0.5 v. note that increasing red gain results in the picture having less contrast (the input signal uses fewer of the available converter codes). see figure 4. 0x09 7C0 green gain green gain an 8-bit word that sets the gain of the green channel. see red gain (0x08). 0x0a 7C0 blue gain blue gain an 8-bit word that sets the gain of the blue channel. see red gain (0x08). input offset 0x0b 7C1 red channel offset adjust a 7-bit offset binary word that sets the dc offset of the red chan- nel. one lsb of offset adjustment equals approximately one lsb change in the adc offset. therefore, the absolute magnitude of the offset adjustment scales as the gain of the channel changes. a nominal setting of 64 results in the channel nominally clamp- ing the back porch (during the clamping interval) to code 00. an offset setting of 127 results in the channel clamping to code 63 of the adc. an offset setting of 0 clamps to code C64 (off the bottom of the range). increasing the value of the red offset decreases the brightness of the channel. 0x0c 7C1 green cha nnel offset adjust a 7-bit offset binary word that sets the dc offset of the green channel. see the 0x0b 7C1 red channel offset adjust. 0x0d 7C1 blue channel offset adjust a 7-bit offset binary word that sets the dc offset of the blue channel. 0x0b 7C1 red channel offset adjust. 0x0e 7C0 sync separator threshold this register is used to set the responsiveness of the sync separator. it sets how many internal 5 mhz clock periods the sync separator must count to before toggling high or low. it works like a low-pass filter to ignore hsync pulses in order to extract the vsync signal. this register should be set to some number greater than the maximum hsync pulse width. note that the sync separator threshold uses an internal dedicated clock with a frequency of approximately 5 mhz. the default for this register is 0x20. 0x0f 7C3 sync-on-green slicer threshold this register allows the comparator threshold of the sync-on- green slicer to be adjusted. this register adjusts it in steps of 10 mv, with the minimum setting equaling 10 mv and the maximum setting equaling 330 mv. the default setting is 15 decimal and corresponds to a threshold value of 170 mv. 0x0f 2 aio active interface override this bit is used to override the automatic interface selection (bit 3 in register 0x15). to override, set this bit to logic 1. when overriding, the active interface is set via bit 1 in this register. table 15. active interface override settings aio result 0 autodetermines the active interface. 1 override; bit 1 determines the active interface. the default for this register is 0.
ad9882a rev. 0 | page 28 of 40 0x0f 1 ais active interface select this bit is used under two conditions. it is used to select the active interface when the override bit is set (register 0x0f, bit 2). alternatively, it is used to determine the active interface when not overriding but both interfaces are detected. table 16. active interface select settings ais result 0 analog interface 1 digital interface the default for this register is 0. 0x10 7 hsync input polarity override this register is used to overri de the internal circuitry that determines the polarity of the hsync signal going into the pll. table 17. hsync input polarity override settings override bit result 0 hsync polarity determined by chip. 1 hsync polarity determined by register 0x10, bit 6. the default for hsync polarity override is 0. (polarity determined by chip.) 0x10 6 hspol hsync input polarity a bit that must be set to indicate the polarity of the hsync signal that is applied to the pll hsync input. table 18. hsync input polarity settings hspol function 0 active low 1 active high active low means the leading edge of the hsync pulse is negative-going. all pll timing is based on the leading edge of hsync, which is the falling edge. the rising edge is used to time the internal clamping. active high means the leading edge of the hsync pulse is positive-going. this means that pll timing is based on the leading edge of hsync, which is now the rising edge. the device operates if this bit is set incorrectly, but the internally generated clamp position, as established by clamp placement (register 0x05), is not placed as expected, which might generate clamping errors. the power-up default value for hspol is 1. 0x10 5 hsync output polarity this bit determines the polarity of the hsync output and the sog output. table 19 shows the effect of this option. sync indicates the logic state of the sync pulse. table 19. hsync output polarity settings setting sync 0 logic 1 (positive polarity) 1 logic 0 (negative polarity) the default setting for this register is 0. 0x10 4 active hsync override this bit is used to override the automatic hsync selection. to override, set this bit to logic 1. when overriding, the active hsync is set via bit 3 in this register. table 20. active hsync override settings override result 0 autodetermines the active hsync. 1 override; bit 3 determines the active hsync. the default for this register is 0. 0x10 3 active hsync select this bit is used under two conditions. it is used to select the active hsync when the override bit is set (bit 4). alternatively, it is used to determine the active hsync when not overriding, but both hsyncs are detected. table 21. active hsync select settings select result 0 hsync input 1 sync-on-green input the default for this register is 0. 0x10 2 vsync output polarity this bit determines the polarity of the vsync output. table 22 shows the effect of this option. sync indicates the logic state of the sync pulse. table 22. vsync output polarity settings setting sync 1 not inverted 0 inverted the default setting for this register is 0. 0x10 1 active vsync override this bit is used to override the automatic vsync selection. to override, set this bit to logic 1. when overriding, the active interface is set via bit 0 in this register.
ad9882a rev. 0 | page 29 of 40 table 23. active vsync override settings override result 0 autodetermines the active vsync 1 override; bit 0 determines the active vsync. the default for this register is 0. 0x10 0 active vsync select this bit is used to select the active vsync when the override bit is set (bit 1). table 24. active vsync select settings select result 0 vsync input 1 sync separator output the default for this register is 0. 0x11 7 clamp function this bit enables/disables clamping. table 25. clamp input signal source settings clamp function function 0 internally generated clamp enabled 1 clamping disabled 0 enables the clamp timing circuitry controlled by clamp placement and clamp duration. the clamp position and duration is counted from the trailing edge of hsync. 1 disables clamping. the three channels are clamped when the clamp signal is active. power-up default value for clamp function is 0. 0x11 6 red clamp select a bit that determines whether the red channel is clamped to ground or to midscale. for rgb video, all three channels are referenced to ground. for ypbpr, the y channel is referenced to ground, but the pbpr channels are referenced to midscale. clamping to midscale clamps to pin 74. table 26. red clamp select settings clamp function 0 clamp to ground 1 clamp to midscale (pin 74) the default setting for this register is 0. 0x11 5 green clamp select this bit determines whether the green channel is clamped to ground or to midscale. table 27. green clamp select settings clamp function 0 clamp to ground 1 clamp to midscale (pin 74) the default setting for this register is 0. 0x11 4 blue clamp select this bit determines whether the blue channel is clamped to ground or to midscale. table 28. blue clamp select settings clamp function 0 clamp to ground 1 clamp to midscale (pin 74) the default setting for this register is 0. 0x11 3 coast select this bit is used to enable or disable the coast signal. if coast is enabled, the additional decision of using the vsync input pin or the output from the sync separator needs to be made (register 0x10, bits 1, 0). to disable coast, the user must set register 0x11, bit 2 to 1 and register 0x11, bit 1 to 1. table 29. coast enable settings select result 0 coast disabled 1 internally genera ted coast signal the default for this register is 1. 0x11 2 coast input polarity override this register is used to overri de the internal circuitry that determines the polarity of the coast signal going into the pll. when disabling coast, register 11, bit 2 must be set to 1 and register 0x11, bit 1 must be set to 1. this register works only when coast is disabled. it does not work with internal coast. table 30. coast input polarity override settings override bit result 0 coast polarity determined by chip 1 coast polarity determined by user the default for coast polarity override is 0.
ad9882a rev. 0 | page 30 of 40 0x11 1 coast input polarity this bit indicates the polarity of the coast signal that is applied to the pll coast input. this register can be used only when coast is disabled and register 0x11, bit 2 is set to 1. table 31. coast input polarity settings cstpol function 0 active low 1 active high the power-up default value is cstpol = 1. 0x12 7C0 precoast this register allows the coast signal to be applied prior to the vsync signal. this is necessary in cases where pre-equalization pulses are present. this register defines the number of edges that are filtered before vsync on a composite sync. the default is 0. 0x13 7C0 postcoast this register allows the coast signal to be applied following the vsync signal. this is necessary in cases where postequalization pulses are present. the step size for this control is one hsync period. this register defines the number of edges that are filtered after vsync on a composite sync. the default is 0. 0x14 7C6 output drive these two bits select the drive strength for the high speed digital outputs (all data output and clock output pins). higher drive strength results in faster rise/fall times, and in general makes it easier to capture data. lower drive strength results in slower rise/fall times and helps reduce emi and digitally generated power supply noise. table 32. output drive strength settings bit 7 bit 6 result 1 x high drive strength 0 1 medium drive strength 0 0 low drive strength the default for this register is 11, high drive strength. this option works on both the analog and digital interfaces. 0x14 5 programmable analog bandwidth these bits select the analog bandwidth. table 33. analog bandwidth control bit 5 analog bandwidth 0 10 mhz 1 300 mhz 0x14 4 clk inv data output clock invert a control bit for the inversion of the output data clock (pin 85). this function works only for the digital interface. when not inverted, data is output on the falling edge of the data clock. see the timing diagrams sections, figure 14 and figure 15, to see how this affects timing. table 34. clock output invert settings clk inv function 0 not inverted 1 inverted the default for this register is 0 (not inverted). 0x14 3 pdo power-down outputs this bit is used to put the outputs in a high impedance mode. this applies to the 24 data output pins, hsout, vsout, and de pins. table 35. power-down output settings pdo function 0 normal operation 1 three-state the default for this register is 0. (this option works on both the analog and digital interfaces.) 0x14 2 hdcp address this bit is used to set the hdcp slave port address. table 36. hdcp address settings address bit result 0 0 for hdcp slave port 1 1 for hdcp slave port the default for this register is 0. 0x14 1 pwrdn this bit is used to control chip power-down. see the power management section for details about which blocks are actually powered down. table 37. power-down settings select result 0 power-down 1 normal operation the default for this register is 1.
ad9882a rev. 0 | page 31 of 40 0x14 0 4:2:2 output mode select this bit configures the output data in 4:2:2 mode. this mode can be used to reduce the number of data lines used from 24 to 16 for applications using ypbpr graphics signals. a timing diagram for this mode is shown in figure 17. recommended input and output configurations are shown in table 39. in 4:2:2 mode, the red and blue channels can be interchanged to help satisfy board layout or timing requirements, but the green channel must be configured for y. table 38. 4:2:2 output mode select select output mode 0 4:4:4 1 4:2:2 table 39. 4:2:2 input/output configuration channel input connection output format red pr pb/pr green y y blue pr high impedance 0x15 7 hsync detect this bit is used to indicate when activity is detected on the hsync input pin (pin 79). if hsync is held high or low, activity is not detected. table 40. hsync detection results detect function 0 no activity detected 1 activity detected figure 20 shows where this function is implemented. 0x15 6 sync-on-green detect this bit is used to indicate when sync activity is detected on the sync-on-green input pin (pin 64). table 41. sync-on-green detection results detect function 0 no activity detected 1 activity detected figure 20 shows where this function is implemented. note that if no sync signal is presented on the green video input, normal video might still trigger activity. 0x15 5 vsync detect this bit is used to indicate when activity is detected on the vsync input pin (pin 80). if vsync is held high or low, activity is not detected. table 42. vsync detection results detect function 0 no activity detected 1 activity detected figure 20 shows where this function is implemented. 0x15 4 digital interface clock detect this bit is used to indicate when activity is detected on the digital interface clock input. table 43. digital interface clock detection results detect function 0 no activity detected 1 activity detected figure 20 shows where this function is implemented. 0x15 3 active interface this bit is used to indicate which interface should be active, analog or digital. it checks for activity on the analog interface and for activity on the digital interface, then determines which should be active according to table 44. specifically, analog interface detection is determined by oring bits 7, 6, and 5 in this register. digital interface detection is determined by bit 4 in this register. if both interfaces are detected, the user can determine which has priority via bit 1 in register 0x0f. the user can override this function via bit 2 in register 0x0f. if the override bit is set to logic 1, then this bit will be forced to the same state as bit 1 in register 0x0f. table 44. active interface results bits 7, 6, or 5 (analog detection) bit 4 (digital detection) override ai 0 0 0 soft power- down (seek mode) 0 1 0 1 1 0 0 0 1 1 0 bit 1 in 0x0f x x 1 bit 1 in 0x0f ai = 0 means analog interface. ai = 1 means digital interface. the override bit is in register 0x0f, bit 2. 0x16 7 ahs active hsync this bit indicates which hsync input source is being used by the pll (hsync input or sync-on-green). bits 6 and 7 in register 0x15 determine which source is used. if both hsync and sog are detected, the user can determine which has priority via bit 3 in register 0x10. the user can override this function via bit 4 in register 0x10. if the override bit is set to logic 1, then this bit will be forced to the same state as bit 3 in register 0x10.
ad9882a rev. 0 | page 32 of 40 table 45. active hsync results hsync detect register 0x15,bit 7 sog detect register 0x,10 bit 4 override register 0x,15 bit 6 ahs register 0x16,bit 7 0 0 0 bit 3 in 0x10 0 1 0 1 1 0 0 0 1 1 0 bit 3 in 0x10 x x 1 bit 3 in 0x10 ahs = 0 means use the hsync pin input for hsync. ahs = 1 means use the sog pin input for hsync. the override bit is in register 0x10, bit 4. 0x16 6 detected hsync input polarity status this bit reports the status of the hsync input polarity detection circuit. it can be used to determine the polarity of the hsync input. the detection circuits location is shown figure 20. table 46. detected hsync input polarity status hsync polarity status result 0 hsync polarity is negative/active low. 1 hsync polarity is positive/active high. 0x16 5 avs active vsync this bit indicates which vsync source is being used for the analog interface, the vsync input or output from the sync separator. if the override bit (0x10, bit 1) is set to logic 1, then this bit will be forced to the same state as bit 0 in register 0x10. table 47. active vsync results vsync detect register 0x16 bit 5 override register 0x10 bit 1 avs 0 0 0 1 0 1 x 1 bit 0 in 0x10 avs = 0 means vsync input. avs = 1 means sync separator. the override bit is in register 0x10, bit 1. 0x16 4 detected vsync output polarity status this bit reports the status of the vsync output polarity detection circuit. it can be used to determine the polarity of the vsync output. the detection circuits location is shown in figure 20. table 48. detected vsync input polarity status vsync polarity status result 0 vsync polarity is active high. 1 vsync polarity is active low. 0x16 3 detected coast polarity status this bit reports the status of the coast input polarity detection circuit. the detection circuits location is shown in figure 20. this bit applies only to the internal coast and does not apply when coast is disabled. table 49. detected coast input polarity status hsync polarity status result 0 coast polarity is negative/active low. 1 coast polarity is positive/active high. 0x16 2 key read verification this bit reports wherever hdcp keys are detected. table 50. key read verification detect function 0 not detected 1 detected 0x1b 7 mda an d mcl three-state the mda and mcl three-state feature allows the eeprom to be programmed in-circuit. the mda/mcl port must be three- stated before attempting to program the eeprom using an external master. the keys are stored in an i 2 c compatible 3.3 v serial eeprom of at least 512 bytes. the eeprom should have a device address of 0xa0. 0x1c 0 rxc connect the rxc (dvi differential clock pair) can be disconnected via software if the hdcp specified hot plug detect does not work to resynchronize the hdcp transmitter engine. to use this function, write this bit to 0 (0 xr1c to 0x0e) then back to 1 (0xr1c to 0x0f). this signals to the dvi transmitter to restart the hdcp protocol. it is recommended that the user perform this toggle of the bit whenever switching from analog to digital inputs. table 51. dvi clock connect set function 0 rxc lines disconnected (open). 1 rxc lines connected internally. 2-wire serial control port a 2-wire serial control interface is provided. two ad9882a devices can be connected to the 2-wire serial interface, with each device having a unique address. the 2-wire serial interface comprises a clock (scl) and a bidirectional data (sda) pin. the analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. when the serial interface is not active, the logic levels on scl and sda are pulled high by external pull-up resistors. data received or transmitted on the sda line must be stable for the duration of the positive-going scl pulse. data on sda must
ad9882a rev. 0 | page 33 of 40 cha n g e o n l y w h en scl is lo w . i f s d a chan g e s s t a t e w h i l e s c l is hig h , t h e s e r i a l i n t e r f ac e in t e r p r e ts t h a t ac t i on a s a st a r t o r st o p seq u en c e . the f i v e co m p on e n ts t o s e r i al b u s o p era t io n a r e ? st ar t s i g n a l ? sla v e addr es s b y t e ? b a s e r e g i st er addr es s b y t e ? da t a b y te t o r e ad o r wr i t e ? stop s i g n a l w h en t h e ser i al i n t e rface i s i n acti v e (scl a n d s d a a r e hi g h ), co mm un ic a t io ns a r e ini t i a te d b y s e nding a st a r t sig n a l . t h e st ar t si gn al i s a hi gh-t o- lo w tra n si ti on o n s d a while scl is hig h . t h i s si gn al aler t s all s l a v e d d e vices th a t a d a t a t r a n sf er seq u en ce is co ming. the f i rst ei g h t b i ts o f da t a t r a n sfer r e d a f t e r a st ar t sig n a l co m- p r is e a 7- b i t sl a v e addr ess (t he f i rst s e ve n b i ts) and a sing le r / w b i t (t he eig h t h b i t). th e r/ w b i t i ndic a tes t h e d i r e c t io n o f d a t a t r a n sfer : r e ad f r o m (1) o r wr i t e t o (0) t h e sl a v e de vic e . i f t h e tra n smi t t e d sla ve addr ess ma t c hes th e addr es s o f th e de vic e (s et b y t h e s t a t e o f t h e sa in p u t p i n list e d in t a ble 52), t h e ad9882a ac k n o w ledg es b y b r in g i n g s d a lo w o n t h e nin t h scl p u ls e . i f t h e addr ess e s do n o t ma t c h, t h e ad9882a do es not a c k n o w l e d g e. table 52. serial port addresse s bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 a6 (msb ) a 5 a 4 a 3 a 2 a 1 a0 (lsb) 1 0 0 1 1 0 0 1 0 0 1 1 0 1 da ta transfe r v i a se ria l interfac e f o r eac h b y t e o f da ta r e ad o r wr i t t e n, the ms b is th e f i rst b i t o f th e s e q u en c e . i f th e ad9882 a do es n o t ac k n o w l e dg e t h e mas t er de vice d u r i n g a wr i t e s e q u ence , t h e s d a r e ma ins hig h s o t h e mas t er can g e n- era t e a s t o p sig n al . i f t h e mas t er de vice do es n o t ac kno w le dg e t h e ad9882a d u r i n g a r e ad s e q u en ce, t h e ad9882a in ter p r e ts this as end o f da t a . the s d a r e ma in s hig h s o t h e mast er ca n g e n e r a t e a s t o p sig n a l . w r i t in g da t a t o s p ecif ic co n t r o l r e g i s t ers o f the ad9882a r e q u ir es t h a t t h e 8-b i t addr es s o f t h e con t r o l r e g i s t er o f in t e r e st b e wr i t t e n a f t e r t h e s l a v e addr es s has b e e n es t a blis h e d . this co n t r o l r e g i s t er addr es s is t h e b a s e addr es s fo r s u bs e q u e n t wr i t e o p era t io n s . th e b a s e addr es s a u t o in cr emen t s b y o n e fo r e a ch b y te of da t a w r it te n af te r t h e d a t a b y te i n te nde d for t h e b a s e addr es s. i f t h er e a r e m o r e b y t e s t r a n sfer r e d t h a n t h er e a r e a v a i l - a b le ad dr ess e s, t h e a ddr ess do es n o t i n cr em e n t a nd r e ma ins a t i t s max i m u m va l u e o f 0x1e. an y bas e addr es s hig h er tha n 0x1e do es n o t p r o d u c e a n ack n o w le dg e sig n al . da t a is r e ad f r o m t h e con t r o l r e g i s t ers o f the ad9882a in a simi la r mann er . re adin g r e q u ires tw o da t a t r a n sfer o p era t io n s : ? the b a s e addr ess m u s t b e wr i t t e n w i t h t h e r / w bi t of t h e s l a v e addr es s b y t e lo w t o s e t u p a s e q u e n t i al r e ad o p era t io n. ? re adin g (t h e r/ w b i t o f t h e s l a v e addr es s b y t e hig h ) b e g i n s a t t h e p r e v io u sly est a b l ish e d b a s e ad dr ess. t h e addr ess o f th e r e ad r e gi s t e r a u t o in cr em en t s a f t e r ea c h b y t e i s tra n sf e r r e d . t o t e r m ina t e a read/wr i t e s e q u en ce t o the ad9 882a, a st o p sig n al m u s t be s e n t . a s t o p sig n al co m p r i s e s a lo w-t o -hig h tra n si ti o n o f s d a wh ile sc l i s h i gh. th e t i m i n g f o r th e r e ad/wr i t e is sho w n in f i gur e 1 8 , a nd a typ i c a l b y t e tra n sf er is sh ow n i n fi g u re 1 9 . a r e pea t ed s t a r t s i gn al occur s w h en t h e m a s t e r d e v i ce d r i v in g t h e s e r i a l i n t e r f ace genera t e s a st a r t sig n a l wi t h o u t f i rst ge n e r - a t in g a s t o p s i g n al t o t e r m ina t e t h e c u r r en t co mm unica t io n. this is us ed t o c h a n g e t h e m o de o f co mm unica t io n (r ead , wr i t e) b e tw e e n t h e s l a v e a nd mast er w i t h o u t r e l e asin g t h e s e r i al in t e r f ace li n e s . sda scl t dho t dsu t stasu t stah t buff t dal t dah t stosu 05123-018 f i gure 18. s e ri al p o r t r e ad/wri te t i mi ng bit 7 sd a scl ack bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05123-019 f i g u re 19. s e ri al int e r f ace , t y pic a l b y te t r ans f er
ad9882a rev. 0 | page 34 of 40 serial interface read/write examples example 1. write to one control register ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? stop signal example 2. write to four consecutive control registers ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? data byte to (base address + 1) ? data byte to (base address + 2) ? data byte to (base address + 3) ? stop signal example 3. read from one control register ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? stop signal example 4. read from four consecutive control registers ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? data byte from (base address + 1) ? data byte from (base address + 2) ? data byte from (base address + 3) ? stop signal table 53. control of the sync block muxes via the serial register mux number(s) serial bus control bit control bit state result 1 and 2 0x10: bit 3 0 pass hsync 1 pass sync-on-green 3 0x10: bit 0 0 pass vsync 1 pass sync separator signal 4, 5, and 6 0x0f: bit 1 0 pass analog interface signals 1 pass digital interface signals
ad9882a rev. 0 | page 35 of 40 sync processing engine sy nc slice r this s e c t io n de s c r i b e s t h e b a sic o p era t ion o f t h e sy n c p r o c es sin g en g i n e (s e e f i gur e 2 0 ). the p u r p os e o f t h e sy n c s l icer i s t o ext r ac t t h e syn c sig n a l f r o m th e gr een gra p hi c s c h a n n e l . a syn c s i gnal i s n o t p r e s e n t o n all g r a p hics sys t ems (o nl y th os e wi th sy n c -on-g r e e n ). th e sy n c sig n al is ext r ac te d f r o m t h e g r e e n cha n ne l i n a tw o-st ep p r o c ess. 1. so g in p u t is cl a m p e d t o i t s n e ga t i v e p e a k ( t y p ica l ly 0.3 v b e lo w t h e b l ack le vel). 2. the sig n al g o es t o a co m p a r a t o r wi t h a va r i a b le t r ig g e r le v e l , n o minal l y 0.15 v a b o v e t h e clam p e d le ve l . the o u t p u t sig n al is typ i c a l l y a co m p osi t e sy n c sig n al co n t a i nin g bo t h h s yn c an d vsy n c. sy nc sep a r a t o r a syn c s e p a ra t o r ext r ac ts t h e v s yn c sig n a l f r o m a com p osi t e syn c sig n a l . i t do es t h is t h r o ug h a lo w - p a s s f i l t er -li k e o r in teg r a t o r -l i k e op era t ion. i t w o rks o n t h e ide a t h a t t h e vs y n c si gn al s t a y s a c ti v e f o r a m u c h lo n g e r tim e th a n t h e h s yn c si gn a l . s o , i t r e je c t s an y sig n al sh o r t e r tha n a t h r e sh old val u e , which is s o me w h er e b e t w e e n an h s yn c p u ls e wi d t h and a vsy n c p u ls e wi d t h. the sy n c s e p a ra t o r o n the ad9 882a is a n 8-b i t dig i tal co u n t e r wi t h a 5 mhz cl o c k. i t w o rk s i ndep e nden t ly o f t h e p o la r i ty o f t h e co m p osi t e s y n c sig n al . p o lar i t i es a r e de t e r m i n e d e l s e w h ere o n t h e chi p . the co un t e r co u n t s u p w h en h s y n c p u ls es a r e p r es en t. but si nce h s yn c p u ls es a r e r e la t i v e l y sho r t in w i d t h, t h e co un t e r r e ach e s o n l y a val u e o f n b e fo r e t h e p u ls e en ds . i t t h en st ar t s c o u n t i ng d o w n , e v e n tu a l l y re a c h i ng 0 b e fore t h e ne x t h s yn c p u ls e a r r i v e s. th e sp e c if i c val u e o f n va r i es fo r dif f er en t video m o des, b u t is al wa ys les s tha n 255. f o r exa m p l e , wi th a 1 m s wid t h h s y n c, t h e co un t e r o n l y r e ac h e s 5 ( 1 s/200 n s = 5). w h en vsy n c is p r es en t o n t h e c o m p osi t e sy nc, t h e co un t e r als o co un ts up . h o we v e r , b e ca us e t h e vsy n c sig n al i s m u ch lo n g er , i t co un ts t o a hig h er n u m b er , m. f o r m o s t v i de o m o des, m is a t leas t 255. s o , vs yn c c a n be det e c t ed o n t h e co m p osi t e sy n c s i g n a l b y d e te c t i n g w h e n t h e c o u n te r c o u n t s to h i g h e r t h a n n. the sp e c if ic coun t t h a t t r ig gers det e c t io n (t) can b e p r og ra m- me d t h rou g h t h e s e r i a l re g i ste r ( 0 x 0 e ) . on ce vsy n c has be e n de t e c t e d , a simi la r p r o c ess det e c t s w h e n i t go e s i n a c t i v e . a t de te c t i o n, t h e c o u n te r f i rst re s e t s to 0 , t h e n s t a r ts co un t i n g u p w h en vsy n c g o es a w a y . i n a wa y simila r t o t h e p r e v i o u s cas e , i t det e c t s t h e a b s e n c e o f vsy n c w h en t h e c o u n te r re a c he s t h e t h re s h o l d c o u n t ( t ) . i n t h i s w a y , it re j e c t s n o is e and/o r s e r r a t io n p u ls es. o n ce vsy n c is de ter m i n e d to b e ab s e n t , t h e c o u n te r re s e t s to 0 an d b e g i ns t h e c y cl e ag ai n . 05123-020 sog hsync in hsync out pixel clock hsync out pll ad9882a clock generator vsync in activity detect activity detect sync stripper comp sync negative peak clamp sync separator integrator vsync 1/s activity detect mux 2 mux 1 mux 4 mux 5 mux 3 polarity detect polarity detect hsync coast sog out vsync out de mux 6 hsync vsync de dvi f i gure 20. s y nc pr oc essing b l ock d i agr a m
ad9882a rev. 0 | page 36 of 40 pcb layout recommendations the ad9882a is a high precision, high speed analog device. to derive the maximum performance from the part, it is important to have a well laid out board. the following is a guide for designing a board using the ad9882a. analog interface inputs using the following layout techniques on the graphics inputs is extremely important. minimize the trace length running into the graphics inputs. this is accomplished by placing the ad9882a as close as possible to the graphics vga connector. long input trace lengths are undesirable because they will pick up more noise from the board and other external sources. place the 75 ? termination resistors (see figure 9) as close to the ad9882a chip as possible. any additional trace length between the termination resistors and the input of the ad9882a increases the magnitude of reflections, which corrupts the graphics signal. use 75 ? matched impedance traces. trace impedances other than 75 ? also increase the chance of reflections. the ad9882a has a very high input bandwidth (300 mhz). while this is desirable for acquiring a high resolution pc graphics signal with fast edges, it means that it captures any high frequency noise present. therefore, it is important to reduce the amount of noise that gets coupled to the inputs. avoid running any digital traces near the analog inputs. due to the high bandwidth of the ad9882a, sometimes low- pass filtering the analog inputs can help to reduce noise. (for many applications, filtering is unnecessary.) experiments have shown that placing a series ferrite bead prior to the 75 ? termination resistor is helpful in filtering out excess noise. specifically, the part used was the #2508051217z0 from fair- rite, but different applications may work best with different bead values. alternatively, placing a 100 ? to 120 ? resistor between the 75 ? termination resistor and the input coupling capacitor can also be beneficial. digital interface inputs many of the same techniques that are recommended for the analog interface inputs should also be used for the digital interface inputs. it is important to minimize trace lengths, then make the input trace impedances match the input termination (typically 50 ?). each differential input pair (r x0+ , r x0C , r xc+ , r xcC , and so on) should be routed together using 50 ? strip line routing techniques and should be kept as short as possible. no other components, such as clamping diodes, should be placed on these inputs. every effort should be made to route these signals on a single layer (component layer) with no vias. power supply bypassing bypassing each power supply pin with a 0.1 f capacitor is recommended. the exception is when two or more supply pins are adjacent to each other. for these groupings of powers/ grounds, it is necessary to have one bypass capacitor. the fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. also, avoid placing the capacitor on the side of the pc board opposite the ad9882a, as that interposes resistive vias in the path. the bypass capacitors should be physically located between the power plane and the power pin. current should flow from the power plane ->to the capacitor ->to the power pin. do not make the power connection between the capacitor and the power pin. placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. it is particularly important to maintain low noise and good stability of pv d (the clock generator supply). abrupt changes in pv d can result in similarly abrupt changes in sampling clock phase and frequency. this can be avoided by careful attention to regulation, filtering, and bypassing. it is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (v d and pv d ). some graphic controllers use levels of power when active (during active picture time) that are substantially different from those used when they are idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. this can be mitigated by regulating the analog supply, or at least pv d , from a different, cleaner, power source (for example, from a 12 v supply). using a single ground plane for the entire board is also recom- mended. experience has repeatedly shown that the noise performance is the same or better with a single ground plane. using multiple ground planes can be detrimental, because each separate ground plane is smaller than one common ground plane, and can result in long ground loops. in some cases, using separate ground planes is unavoidable. when they must be used, it is recommended that at least a single ground plane be placed under the ad9882a. the location of the split should be at the receiver of the digital outputs. in this case, it is even more important to place components wisely, because the current loops are much longer (current takes the path of least resistance). the following is an example of a current loop: power plane -> ad9882a -> digital output trace -> digital data receiver -> digital ground plane -> analog ground plane.
ad9882a rev. 0 | page 37 of 40 pll place the pll loop filter components as close to the filt pin as possible. do not place any digital or other high frequency traces near these components. use the values suggested in the data sheet with 10% or smaller tolerances. outputs: data and clocks try to minimize the trace length that the digital outputs have to drive. longer traces have higher capacitance and require more current, which causes more internal digital noise. shorter traces reduce the possibility of reflections. adding a series resistor with a value of 22 ? to 100 ? can suppress reflections, reduce emi, and reduce the current spikes inside of the ad9882a. however, if 50 ? traces are used on the pcb, the data output should not need these resistors. a 22 ? resistor on the datack output should provide good impedance matching that can reduce reflections. if emi or current spiking is a concern, use a lower drive strength setting by adjusting register 0x14. if series resistors are used, place them as close as possible to the ad9882a pins but avoid adding vias or extra length to the output trace to get the resistors closer. if possible, limit the capacitance that each of the digital outputs drives to less than 10 pf by keeping traces short and connecting the outputs to only one device. loading the outputs with excessive capacitance increases the current transients inside the ad9882a, creating more digital noise on its power supplies. digital inputs the digital inputs on the ad9882a were designed to work with 3.3 v signals, but are tolerant of 5.0 v signals. no extra components need to be added, if 5.0 v logic is used. any noise that gets onto the hsync input trace adds jitter to the system. therefore, minimize the trace length and do not run any digital or other high frequency traces near it. voltage reference bypass with a 0.1 f capacitor. place as close as possible to the ad9882a pin. make the ground connection as short as possible.
ad9882a rev. 0 | page 38 of 40 outline dimensions top view (pins down) 1 25 26 51 50 75 76 100 14.00 bsc sq 0.50 bsc 0.27 0.22 0.17 1.60 max seating plane 12 typ 0.75 0.60 0.45 view a 16.00 bsc sq 12.00 ref 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 pin 1 compliant to jedec standards ms-026bed f i g u re 21. 1 00-l e a d q u ad flat p a ck [l qfp ] (st - 10 0) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package option ad9882akstz- 100 1 0c to 70c st-100 ad9882akstz- 140 1 0c to 70c st-100 a d 9 8 8 2 a / p c b e v a l u a t i o n k i t 1 z = pb-free part.
ad9882a rev. 0 | page 39 of 40 notes
ad9882a rev. 0 | page 40 of 40 notes pur c has e o f licen s ed i 2 c c o m p one n t s of a n a l o g d e v i c e s or on e of it s su bl i c e n s e d ass o c i a t e d c o m p an i e s c o n v e y s a l i c e n s e f o r t h e p u r c haser un d e r th e phili p s i 2 c p a t e n t r i g h ts to us e t h es e co m p o n e n ts in an i 2 c sys t em, p r o v i d e d t h a t t h e sys t em co nfo r m s to t h e i 2 c s t a nda rd s p e c if ica t io n as d e f i ne d b y phi l i p s. ? 200 4 a n a l og d e v i ce s, i n c . al l rig h ts r e s e r v e d . t r ad em a r k s a n d r e g i st e r e d tr ad em a r k s a r e t h e p r op e r t y of t h e i r re sp e c tive ow ne r s . d05123-0 - 10/0 4 (0)

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