? summit microelectronics, inc. 2000 ? 300 orchard city drive, suite 131 campbell, ca 95008 phone 408- 378-6461 fax 408-378-6586 www.summitmicro.com 1 characteristics subject to change without notice summit microelectronics, inc. 2035 3.0 5/10/00 SMP9517 features digitally controlled electronic potentiometer ? 7-bit digital-to-analog converter (dac) ? independent reference inputs ? differential non-linearity of 0.5lsb max ? integral non-linearity of 1lsb max v out value in eeprom for power-on recall ? equivalent to 128-step potentiometer unity gain op amp drives up to 1ma simple trimming adjustment ? debounced pushbutton interface low noise operation ?clickless? transitions between dac steps no mechanical wear-out problem ? 1,000,000 stores (typical) ? 100 year data retention operation from 2.7v to 5.5v supply low power: 1mw max at 5v nonvolatile dacpot? electronic potentiometer with debounced push button interface overview the SMP9517 dacpot trimmer is an 7-bit nonvolatile dac designed to replace mechanical potentiometers. the SMP9517 includes a unity-gain amplifier to buffer the dac output and enables v out to swing from rail to rail. the dacpot trimmer operates over a supply voltage range of 2.7v to 5.5v. the SMP9517?s simple pushbutton input provides an ideal interface for operator adjusted equipment. this interface allows for quick and easy adjustment of even the most sophisticated systems. the SMP9517 is a pin-compatible performance upgrade for other industry nonvolatile potentiometers. for higher resolution applications the pin-compatible s9518 pro- vides 256 steps with the same pushbutton interface. both the SMP9517 and the s9518 provide ?clickless? transitions of v out . functional block diagram dwn# v dd 8 2 v out 5 7-bit e 2 prom vl 6 vh 3 7-bit data register debounce circuit & write control logic 7-bit dac up# 1 str# 7 gnd 4 2035 t bd 3.0
2 SMP9517 summit microelectronics, inc. 2035 3.0 5/10/00 analog section the SMP9517 is an 7-bit, voltage output digital-to-analog converter (dac). the dac consists of a resistor network that converts 7-bit digital values into equivalent analog output voltages in proportion to the applied reference voltage. reference inputs the voltage differential between the v l and v h inputs sets the full-scale output voltage range. v l must be equal to or greater than ground (a positive voltage). v h must be greater than v l and less than or equal to v dd . see specifications for guaranteed operating limits. output buffer amplifier the voltage output is from a precision unity-gain follower that provides a rail-to-rail output swing. digital interface the interface provides simple pushbutton control of an up/down counter that drives the dac. the dac output is a ratiometric voltage output. up# is an active low pushbutton input. an internal pull-up resistor, with nominal value of 50k ? ?
SMP9517 3 summit microelectronics, inc. 2035 3.0 5/10/00 there are five main blocks to the SMP9517: an 7-bit eeprom memory; input debounce circuits, control logic, and 7-bit counter; 7-bit data register; decode section and resistor ladder (dac); and the buffer amplifier. the input control section operates just like an up/down counter. the output of this counter is fed to the data register and then decoded to activate one of 127 electronic switches connected to the resistor ladder. the ladder is comprised of 128 resistors of equal value connected in series. at the bottom of the ladder and at the junctions of the resistors there are electronic switches that transfer the voltage at each point to the buffer amplifier and then to the output. the SMP9517 is designed to interface directly to two pushbutton switches that effectively move the potentiom- eter wiper up or down. the up# and dwn# inputs, respectively, increment or decrement the 7-bit counter. the data input to the dac is decoded to select one of the 128 wiper positions along the resistive ladder. the wiper increment input up# and the wiper decrement input dwn# are connected to internal pull-ups so that they normally remain high. when pulled low by an external pushbutton switch or a logic low level input, the wiper will be switched to the next adjacent tap position. internal debounce circuitry prevents inadvertent switching of the wiper position if up# or dwn# remain low for less than 30ms (typical). each of the buttons can be pushed either once for a single increment/decrement or held low continuously for multiple increments/decrements. the number of increments/dec- rements of the wiper position depends on how long the button is pushed. when making a continuous push, after the first second, the increment/decrement speed in- creases. for the first second the device will be in the slow scan mode. then, if the button is held for longer than one second, the device will go into the fast scan mode. as soon as the button is released the SMP9517 will return to a standby condition. the dac, whether set to 00 hex or ff hex , acts like its mechanical equivalent and does not move beyond the last position. that is, the counter does not wrap around when clocked up to ff hex or down to 00 hex . autostore the value of the counter is stored in eeprom memory whenever the chip senses a power-down of v dd while str# is enabled (held low). when power is restored the contents of the memory are recalled and the counter reset to the last value stored. if autostore is to be imple- mented, str# is typically hard wired to gnd. if str# is held high during power-up and then taken low the wiper will not respond to the up# or dwn# inputs until str# is brought high and the store is complete. see figure 1. manual (pushbutton) store when str# is not enabled (held high) a pushbutton switch may be used to pull str# low and released to perform a manual store of the wiper position in eeprom memory. see figure 2. effect of v dd removal the resistor ladder, connected between v h and v l , does not change value when v dd is removed. however, the buffer amplifier no longer functions, and consequently a high impedance appears at the v out pin. figure 2: typical circuit with str store pin controlled by push button switch figure 1: typical circuit with str store pin used in autostore mode device operation up# dwn# v h gnd v dd str# v l v out 8 7 6 5 1 2 3 4 v dd 3.3f 2035 t fig01 3.0 up# dwn# v h gnd v dd str# v l v out 8 7 6 5 1 2 3 4 v dd 20k 2035 t fig02 3.0
4 SMP9517 summit microelectronics, inc. 2035 3.0 5/10/00 absolute maximum ratings temperature under bias ? 55 c to 125 c storage temperature ? 65 c to 150 c voltage on pins with reference to gnd: analog inputs ? 0.5v to v dd +0.5v digital inputs ? 0.5v to v dd +0.5v analog outputs ? 0.5v to v dd +0.5v digital outputs ? 0.5v to v dd +0.5v lead solder temperature (10s) 300 c comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operation sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. recommended operating conditions n o i t i d n o c. n i m. x a m e r u t a r e p m e tc o 0 4 ? c o 5 8 v d d v 7 . 2v 5 . 5 2035 table02 3.0
SMP9517 5 summit microelectronics, inc. 2035 3.0 5/10/00 reliability characteristics 2035 table03 3.0 symbol parameter conditions min. typ. max. units accuracy inl integral non-linearity i load = 100a, 0.5 1 lsb dnl differential non-linearity i load = 100a, 0.1 0.5 lsb guaranteed but not tested references v h v refh input voltage v refl v dd v v l v refl input voltage gnd v refh v r in v refh to v refl resistance 38k tcr in temperature coefficient v refh to v refl 600 ppm/ c of r in analog g efs full-scale gain error data = ff hex 1 lsb output v out zs zero-scale output voltage data = 00 hex 020mv tcv out v out temperature v dd = 5, i load = 50a, coefficient v refh = 5v, v refl = 0v 50 v/ c guaranteed but not tested i l amplifier output load current -200 1000 a r out amplifier output resistance i load = 100a v dd = 5v 10 v dd = 3v 20 psrr power supply rejection i load = 10a 1 lsb/v e n amplifier output noise f = 1khz, v dd = 5v 90 nv/ h z thd total harmonic distortion v in = 1v rms , f = 1khz 0.08 % bw bandwidth ? 3db v in = 100mv rms 300 khz dac dc electrical characteristics v dd = 2.7v to 5.5v, v refh = v dd , v refl = 0v, t a = ? 40 c to 85 c, unless specified otherwise 2017 pgm t3.4 l o b m y sr e t e m a r a p. n i m. x a mt i n u v p a z y t i l i b i t p e c s u s d s e0 0 0 2v i h t l p u h c t a l0 0 1a m t r d n o a i t n e t e r a t a d0 0 1s r a e y n d n e e c n a r u d n e0 0 0 , 0 0 0 , 1s e r o t s
6 SMP9517 summit microelectronics, inc. 2035 3.0 5/10/00 2017 pgm t5.1 dc electrical characteristics v dd = 2.7v to 5.5v, v h = v dd , v l = 0v, unless otherwise specified notes: 1. i dd is the supply current drawn while the eeprom is being updated. i dd does not include the current that flows through the reference resistor chain. 2. up# and dwn# have internal pull-up resistors of approximately 50k . when the input is pulled to ground the resulting output current will be v dd /50k y . limits symbol parameter min. typ. max. units f gap time between two separate push button events 0 s t db debounce time 30 60 ms t s slow after debounce to wiper change on a slow mode 100 250 375 ms t s fast wiper change on a fast mode 25 50 75 ms t pu power-up to wiper stable 500 s t r v dd v dd power-up rate 0.2 50 mv/s t asto autostore cycle time (note 3) 4 2 ms v asth autostore threshold voltage (note 3) 4.6 5.5 v t asend autostore cycle end voltage 3.5 v ac operating characteristics v dd = 4.5v to 5.5v 2017 pgm t6.0 symbol parameter conditions min max units i dd supply current str# = 1.2 ma during store (note 1) i sb supply standby current 200 a i ih input leakage current v in = v dd 10 a i il input leakage current (note 2) v in = 0v -100 a v ih high level input voltage 2 v dd v v il low level input voltage 0 0.8 v notes: 3. t asto and v asth are characterized and periodically sampled, but not 100% tested.
SMP9517 7 summit microelectronics, inc. 2035 3.0 5/10/00 figure 3. autostore cycle timing diagram store time 5 time (ms) 2017 ill5.0 t asto v asend v asth v dd volts (v) autostore cycle in progress notes: v asth = autostore threshold voltage v asend = autostore cycle end voltage t asto = autostore cycle time figure 4. slow mode timing 2017 ill6.0 up v out t db t gap 1lsb step figure 5. fast mode timing 2017 ill7.0 t db t s fast t s slow 1 second v out up 1lsb step
8 SMP9517 summit microelectronics, inc. 2035 3.0 5/10/00 notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect it s safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives writte n assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2000 summit microelectronics, inc. 8 pin soic (type s) package jedec (150 mil body width) ordering information .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45 .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) typ. .275 (6.99) typ. .030 (.762) typ. 8 places .050 (1.27) typ. .050 (1.270) typ. 8 places .157 (4.00) .150 (3.80) .196 (5.00) 1 .189 (4.80) footprint 8pn jedec soic ill.2 SMP9517 s base part number package s=8-pin soic 2035 tree 3.0
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