product brief t el 408.919.4 1 1 1 fax 408.919.4122 www.zoran.com 10/02-ldi zorans FRAME-IT-1 video deinterlacer is a silicon-efficient, high-performance intellectual property core for video ic designs requiring progressive video output. FRAME-IT-1 is based on zorans extensive experience delivering high quality, high volume video ics to major consumer products manufacturers worldwide. FRAME-IT-1 employs a robust motion detection and an intelligent interpolation algorithm in a easily implemented, fully synchronous design. 3:2 pulldown, 2:2 pulldown, and bad edit detection enable superior dein- terlacing of source material orginally from film. proven in silicon, the FRAME-IT-1 video deinterlacer greatly reduces the risk and time involved when integrating the video deinterlacing function into an ic. expensive, discrete components can be elimi- nated from system designs. FRAME-IT-1 is designed into zoran's v addis? family of dvd decoders, which are in mass production and are used in brand name consumer products worldwide. vip-ii demonstration system the vip-ii is an fpga demonstration system for zoran's ip core products. the vip-ii accepts composite video, s-video and compo- nent video inputs and with its user friendly gui, enables customers to thoroughly evaluate the performance of zoran's ip core products. fea tures ? "i to p" converter ? converts interlaced video to progressive output video ? robust motion detection based algorithm ? weaves still areas of the image ? advanced interpolation for moving areas of the image ? 3:2 and 2:2 pulldown detection for film modes ? bad edit detection ? silicon efficient design ? requires only a single clock input from 20 to 30 mhz ? fully synchronous design ? process technology independent "softcore" zoran corporation 3112 scott boulevard santa clara, ca 95054-3317 FRAME-IT-1-pb-1.0 FRAME-IT-1 tm v ideo deinterlacer intellectual property core solutions on a chip for enjoying the digital life style integrated circuit applications ? lcd controllers ? lcd-tv ? pdp-tv ? projector tv systems ? progressive output crt-tv ? any ic requiring progressive video output description deliverables ? compilable verilog source code ? bit-accurate, cycle-accurate c++ model ? synopsis synthesis scripts ? test input files ? documentation ? vip-ii fpga demonstration system available ? interlaced video input line buffers optional line buffers field buffer control field buffers input control motion detector gradient detector adaptive bob- w eave output control de in te rla ce d v id e o output FRAME-IT-1 video deinterlacer fr ame-it-1 video deinterlacer block diagram
product brief FRAME-IT-1 tm v ideo deinterlacer intellectual property core solutions on a chip for enjoying the digital life style ext_clk ext_reset_1 reg_addr[7:0] reg_rd_wtn reg_rdy reg_wt_data[7:0] clk clk_x2 (optional)* reset_1 enable (optional) ? hactive_in vactive_in field proscan240 repeat_first_field no_time_advance ? y_prev_in[7:0] c_prev_in[7:0] y_curr_in[7:0] c_curr_in[7:0] y_next_in[7:0] c_next_in[7:0] c_curr_lbuf_a_rdata[7:0] c_curr_lbuf_b_rdata[7:0] c_miss_lbuf_rdata[7:0] k_prev_lbuf_rdata[7:0] m_top_lbuf_rdata[7:0] k_prev_fbuf_rdata[7:0] y_prev_lbuf_a_rdata[7:0] y_prev_lbuf_b-rdata[7:0] y_curr_lbuf_a_rdata[7:0] y_curr_lbuf_b_rdata[7:0] y_next_lbuf_a_rdata[7:0] y_next_lbuf_rdata[7:0] FRAME-IT-1 v ideo deinterlacer pinout euired or doule-ate utut euired or naled flo eered or future e reac rerdrd rerddata actieout actieout toout ctoout otout cotout clurrt clurt reluren reluen reluren reluen reludata currluren currluen currluren currluen currludata netluren netluen netluren netluen netludata ccurrluren ccurrluen ccurrluren ccurrluen ccurrludata cmiluren cmiluen cmiludata relurrt reluren relurt reluen reludata mtolurrt mtoluren mtolurt mtoluen mtoludata reurrt reuren reurt reuen reudata ddmu fr ame-it-1 video deinterlacer oical pinout oran vaddi and frame-it are trademar or reitered trademar o oran ororation ll oter trademar are roert o teir reectie oner FRAME-IT-1-p-1 1-di f or more inormation contact oran anta lara oice or te oice nearet ou anada oran oronto a 1 ueen t at uite oronto ntario 1 anada el 1 - fa 1 - ina oran ina ice uite lectronic cience ec uildin entral ennan d enen uandon 11 p ina e l ---1 fa --- on on oran ia paciic td nit - e at cean enter o cience ueum oad oloon on on e l --- fa --- irael oran icroelectronic td danced ecnolo tr p o aia 1 irael e l --- fa --1-1 a an oran aan ice -- ooni inato-u oo 1- aan e l 1---1 fa 1---1 orea oran orea ice donu uildin - oido-don ounduno-u eoul orea 1-1 e l --1-1 fa --1- aian oran aian ice f-1 o ane 1 eiuan d eiu 11 a iei aian el --- fa ---
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